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drm/i915: fix ironlake CRTC enable/disable
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_display.c
blob29ecaa0b1344aa8ed20634eb54edeee5382331e9
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static inline u32 /* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device *dev)
347 {
348 struct drm_i915_private *dev_priv = dev->dev_private;
349 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
350 }
351
352 static const intel_limit_t intel_limits_i8xx_dvo = {
353 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
354 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
355 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
356 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
357 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
358 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
359 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
360 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
361 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
362 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
363 .find_pll = intel_find_best_PLL,
364 };
365
366 static const intel_limit_t intel_limits_i8xx_lvds = {
367 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
368 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
369 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
370 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
371 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
372 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
373 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
374 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
375 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
376 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
377 .find_pll = intel_find_best_PLL,
378 };
379
380 static const intel_limit_t intel_limits_i9xx_sdvo = {
381 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
382 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
383 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
384 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
385 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
386 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
387 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
388 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
389 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
390 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
391 .find_pll = intel_find_best_PLL,
392 };
393
394 static const intel_limit_t intel_limits_i9xx_lvds = {
395 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
396 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
397 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
398 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
399 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
400 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
401 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
402 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
403 /* The single-channel range is 25-112Mhz, and dual-channel
404 * is 80-224Mhz. Prefer single channel as much as possible.
405 */
406 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
407 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
408 .find_pll = intel_find_best_PLL,
409 };
410
411 /* below parameter and function is for G4X Chipset Family*/
412 static const intel_limit_t intel_limits_g4x_sdvo = {
413 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
414 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
415 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
416 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
417 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
418 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
419 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
420 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
421 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
422 .p2_slow = G4X_P2_SDVO_SLOW,
423 .p2_fast = G4X_P2_SDVO_FAST
424 },
425 .find_pll = intel_g4x_find_best_PLL,
426 };
427
428 static const intel_limit_t intel_limits_g4x_hdmi = {
429 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
430 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
431 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
432 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
433 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
434 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
435 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
436 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
437 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
438 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
439 .p2_fast = G4X_P2_HDMI_DAC_FAST
440 },
441 .find_pll = intel_g4x_find_best_PLL,
442 };
443
444 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
445 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
446 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
447 .vco = { .min = G4X_VCO_MIN,
448 .max = G4X_VCO_MAX },
449 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
450 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
451 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
452 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
453 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
454 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
455 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
456 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
457 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
458 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
459 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
460 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
461 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
462 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
463 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
464 },
465 .find_pll = intel_g4x_find_best_PLL,
466 };
467
468 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
469 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
470 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
471 .vco = { .min = G4X_VCO_MIN,
472 .max = G4X_VCO_MAX },
473 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
474 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
475 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
476 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
477 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
478 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
479 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
480 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
481 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
482 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
483 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
484 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
485 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
486 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
487 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
488 },
489 .find_pll = intel_g4x_find_best_PLL,
490 };
491
492 static const intel_limit_t intel_limits_g4x_display_port = {
493 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
494 .max = G4X_DOT_DISPLAY_PORT_MAX },
495 .vco = { .min = G4X_VCO_MIN,
496 .max = G4X_VCO_MAX},
497 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
498 .max = G4X_N_DISPLAY_PORT_MAX },
499 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
500 .max = G4X_M_DISPLAY_PORT_MAX },
501 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
502 .max = G4X_M1_DISPLAY_PORT_MAX },
503 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
504 .max = G4X_M2_DISPLAY_PORT_MAX },
505 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
506 .max = G4X_P_DISPLAY_PORT_MAX },
507 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
508 .max = G4X_P1_DISPLAY_PORT_MAX},
509 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
510 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
511 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
512 .find_pll = intel_find_pll_g4x_dp,
513 };
514
515 static const intel_limit_t intel_limits_pineview_sdvo = {
516 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
517 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
518 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
519 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
520 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
521 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
522 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
523 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
524 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
525 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
526 .find_pll = intel_find_best_PLL,
527 };
528
529 static const intel_limit_t intel_limits_pineview_lvds = {
530 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
531 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
532 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
533 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
534 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
535 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
536 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
537 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
538 /* Pineview only supports single-channel mode. */
539 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
540 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
541 .find_pll = intel_find_best_PLL,
542 };
543
544 static const intel_limit_t intel_limits_ironlake_dac = {
545 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
546 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
547 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
548 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
549 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
550 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
551 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
552 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
553 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
554 .p2_slow = IRONLAKE_DAC_P2_SLOW,
555 .p2_fast = IRONLAKE_DAC_P2_FAST },
556 .find_pll = intel_g4x_find_best_PLL,
557 };
558
559 static const intel_limit_t intel_limits_ironlake_single_lvds = {
560 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
561 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
562 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
563 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
564 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
565 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
566 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
567 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
568 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
569 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
570 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
571 .find_pll = intel_g4x_find_best_PLL,
572 };
573
574 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
575 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
576 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
577 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
578 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
579 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
580 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
581 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
582 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
583 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
584 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
585 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
586 .find_pll = intel_g4x_find_best_PLL,
587 };
588
589 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
590 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
591 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
592 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
593 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
594 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
595 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
596 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
597 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
598 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
599 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
600 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
601 .find_pll = intel_g4x_find_best_PLL,
602 };
603
604 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
605 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
606 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
607 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
608 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
609 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
610 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
611 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
612 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
613 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
614 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
615 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
616 .find_pll = intel_g4x_find_best_PLL,
617 };
618
619 static const intel_limit_t intel_limits_ironlake_display_port = {
620 .dot = { .min = IRONLAKE_DOT_MIN,
621 .max = IRONLAKE_DOT_MAX },
622 .vco = { .min = IRONLAKE_VCO_MIN,
623 .max = IRONLAKE_VCO_MAX},
624 .n = { .min = IRONLAKE_DP_N_MIN,
625 .max = IRONLAKE_DP_N_MAX },
626 .m = { .min = IRONLAKE_DP_M_MIN,
627 .max = IRONLAKE_DP_M_MAX },
628 .m1 = { .min = IRONLAKE_M1_MIN,
629 .max = IRONLAKE_M1_MAX },
630 .m2 = { .min = IRONLAKE_M2_MIN,
631 .max = IRONLAKE_M2_MAX },
632 .p = { .min = IRONLAKE_DP_P_MIN,
633 .max = IRONLAKE_DP_P_MAX },
634 .p1 = { .min = IRONLAKE_DP_P1_MIN,
635 .max = IRONLAKE_DP_P1_MAX},
636 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
637 .p2_slow = IRONLAKE_DP_P2_SLOW,
638 .p2_fast = IRONLAKE_DP_P2_FAST },
639 .find_pll = intel_find_pll_ironlake_dp,
640 };
641
642 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
643 {
644 struct drm_device *dev = crtc->dev;
645 struct drm_i915_private *dev_priv = dev->dev_private;
646 const intel_limit_t *limit;
647 int refclk = 120;
648
649 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
650 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
651 refclk = 100;
652
653 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
654 LVDS_CLKB_POWER_UP) {
655 /* LVDS dual channel */
656 if (refclk == 100)
657 limit = &intel_limits_ironlake_dual_lvds_100m;
658 else
659 limit = &intel_limits_ironlake_dual_lvds;
660 } else {
661 if (refclk == 100)
662 limit = &intel_limits_ironlake_single_lvds_100m;
663 else
664 limit = &intel_limits_ironlake_single_lvds;
665 }
666 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
667 HAS_eDP)
668 limit = &intel_limits_ironlake_display_port;
669 else
670 limit = &intel_limits_ironlake_dac;
671
672 return limit;
673 }
674
675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
676 {
677 struct drm_device *dev = crtc->dev;
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 const intel_limit_t *limit;
680
681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
682 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
683 LVDS_CLKB_POWER_UP)
684 /* LVDS with dual channel */
685 limit = &intel_limits_g4x_dual_channel_lvds;
686 else
687 /* LVDS with dual channel */
688 limit = &intel_limits_g4x_single_channel_lvds;
689 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
690 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
691 limit = &intel_limits_g4x_hdmi;
692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
693 limit = &intel_limits_g4x_sdvo;
694 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
695 limit = &intel_limits_g4x_display_port;
696 } else /* The option is for other outputs */
697 limit = &intel_limits_i9xx_sdvo;
698
699 return limit;
700 }
701
702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
703 {
704 struct drm_device *dev = crtc->dev;
705 const intel_limit_t *limit;
706
707 if (HAS_PCH_SPLIT(dev))
708 limit = intel_ironlake_limit(crtc);
709 else if (IS_G4X(dev)) {
710 limit = intel_g4x_limit(crtc);
711 } else if (IS_PINEVIEW(dev)) {
712 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
713 limit = &intel_limits_pineview_lvds;
714 else
715 limit = &intel_limits_pineview_sdvo;
716 } else if (!IS_GEN2(dev)) {
717 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
718 limit = &intel_limits_i9xx_lvds;
719 else
720 limit = &intel_limits_i9xx_sdvo;
721 } else {
722 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
723 limit = &intel_limits_i8xx_lvds;
724 else
725 limit = &intel_limits_i8xx_dvo;
726 }
727 return limit;
728 }
729
730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
731 static void pineview_clock(int refclk, intel_clock_t *clock)
732 {
733 clock->m = clock->m2 + 2;
734 clock->p = clock->p1 * clock->p2;
735 clock->vco = refclk * clock->m / clock->n;
736 clock->dot = clock->vco / clock->p;
737 }
738
739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
740 {
741 if (IS_PINEVIEW(dev)) {
742 pineview_clock(refclk, clock);
743 return;
744 }
745 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
746 clock->p = clock->p1 * clock->p2;
747 clock->vco = refclk * clock->m / (clock->n + 2);
748 clock->dot = clock->vco / clock->p;
749 }
750
751 /**
752 * Returns whether any output on the specified pipe is of the specified type
753 */
754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
755 {
756 struct drm_device *dev = crtc->dev;
757 struct drm_mode_config *mode_config = &dev->mode_config;
758 struct intel_encoder *encoder;
759
760 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
761 if (encoder->base.crtc == crtc && encoder->type == type)
762 return true;
763
764 return false;
765 }
766
767 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
768 /**
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
771 */
772
773 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
774 {
775 const intel_limit_t *limit = intel_limit (crtc);
776 struct drm_device *dev = crtc->dev;
777
778 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
779 INTELPllInvalid ("p1 out of range\n");
780 if (clock->p < limit->p.min || limit->p.max < clock->p)
781 INTELPllInvalid ("p out of range\n");
782 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
783 INTELPllInvalid ("m2 out of range\n");
784 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
785 INTELPllInvalid ("m1 out of range\n");
786 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
787 INTELPllInvalid ("m1 <= m2\n");
788 if (clock->m < limit->m.min || limit->m.max < clock->m)
789 INTELPllInvalid ("m out of range\n");
790 if (clock->n < limit->n.min || limit->n.max < clock->n)
791 INTELPllInvalid ("n out of range\n");
792 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
793 INTELPllInvalid ("vco out of range\n");
794 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
795 * connector, etc., rather than just a single range.
796 */
797 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
798 INTELPllInvalid ("dot out of range\n");
799
800 return true;
801 }
802
803 static bool
804 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
805 int target, int refclk, intel_clock_t *best_clock)
806
807 {
808 struct drm_device *dev = crtc->dev;
809 struct drm_i915_private *dev_priv = dev->dev_private;
810 intel_clock_t clock;
811 int err = target;
812
813 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
814 (I915_READ(LVDS)) != 0) {
815 /*
816 * For LVDS, if the panel is on, just rely on its current
817 * settings for dual-channel. We haven't figured out how to
818 * reliably set up different single/dual channel state, if we
819 * even can.
820 */
821 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
822 LVDS_CLKB_POWER_UP)
823 clock.p2 = limit->p2.p2_fast;
824 else
825 clock.p2 = limit->p2.p2_slow;
826 } else {
827 if (target < limit->p2.dot_limit)
828 clock.p2 = limit->p2.p2_slow;
829 else
830 clock.p2 = limit->p2.p2_fast;
831 }
832
833 memset (best_clock, 0, sizeof (*best_clock));
834
835 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
836 clock.m1++) {
837 for (clock.m2 = limit->m2.min;
838 clock.m2 <= limit->m2.max; clock.m2++) {
839 /* m1 is always 0 in Pineview */
840 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
841 break;
842 for (clock.n = limit->n.min;
843 clock.n <= limit->n.max; clock.n++) {
844 for (clock.p1 = limit->p1.min;
845 clock.p1 <= limit->p1.max; clock.p1++) {
846 int this_err;
847
848 intel_clock(dev, refclk, &clock);
849
850 if (!intel_PLL_is_valid(crtc, &clock))
851 continue;
852
853 this_err = abs(clock.dot - target);
854 if (this_err < err) {
855 *best_clock = clock;
856 err = this_err;
857 }
858 }
859 }
860 }
861 }
862
863 return (err != target);
864 }
865
866 static bool
867 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
868 int target, int refclk, intel_clock_t *best_clock)
869 {
870 struct drm_device *dev = crtc->dev;
871 struct drm_i915_private *dev_priv = dev->dev_private;
872 intel_clock_t clock;
873 int max_n;
874 bool found;
875 /* approximately equals target * 0.00585 */
876 int err_most = (target >> 8) + (target >> 9);
877 found = false;
878
879 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
880 int lvds_reg;
881
882 if (HAS_PCH_SPLIT(dev))
883 lvds_reg = PCH_LVDS;
884 else
885 lvds_reg = LVDS;
886 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
887 LVDS_CLKB_POWER_UP)
888 clock.p2 = limit->p2.p2_fast;
889 else
890 clock.p2 = limit->p2.p2_slow;
891 } else {
892 if (target < limit->p2.dot_limit)
893 clock.p2 = limit->p2.p2_slow;
894 else
895 clock.p2 = limit->p2.p2_fast;
896 }
897
898 memset(best_clock, 0, sizeof(*best_clock));
899 max_n = limit->n.max;
900 /* based on hardware requirement, prefer smaller n to precision */
901 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
902 /* based on hardware requirement, prefere larger m1,m2 */
903 for (clock.m1 = limit->m1.max;
904 clock.m1 >= limit->m1.min; clock.m1--) {
905 for (clock.m2 = limit->m2.max;
906 clock.m2 >= limit->m2.min; clock.m2--) {
907 for (clock.p1 = limit->p1.max;
908 clock.p1 >= limit->p1.min; clock.p1--) {
909 int this_err;
910
911 intel_clock(dev, refclk, &clock);
912 if (!intel_PLL_is_valid(crtc, &clock))
913 continue;
914 this_err = abs(clock.dot - target) ;
915 if (this_err < err_most) {
916 *best_clock = clock;
917 err_most = this_err;
918 max_n = clock.n;
919 found = true;
920 }
921 }
922 }
923 }
924 }
925 return found;
926 }
927
928 static bool
929 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
930 int target, int refclk, intel_clock_t *best_clock)
931 {
932 struct drm_device *dev = crtc->dev;
933 intel_clock_t clock;
934
935 if (target < 200000) {
936 clock.n = 1;
937 clock.p1 = 2;
938 clock.p2 = 10;
939 clock.m1 = 12;
940 clock.m2 = 9;
941 } else {
942 clock.n = 2;
943 clock.p1 = 1;
944 clock.p2 = 10;
945 clock.m1 = 14;
946 clock.m2 = 8;
947 }
948 intel_clock(dev, refclk, &clock);
949 memcpy(best_clock, &clock, sizeof(intel_clock_t));
950 return true;
951 }
952
953 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
954 static bool
955 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
956 int target, int refclk, intel_clock_t *best_clock)
957 {
958 intel_clock_t clock;
959 if (target < 200000) {
960 clock.p1 = 2;
961 clock.p2 = 10;
962 clock.n = 2;
963 clock.m1 = 23;
964 clock.m2 = 8;
965 } else {
966 clock.p1 = 1;
967 clock.p2 = 10;
968 clock.n = 1;
969 clock.m1 = 14;
970 clock.m2 = 2;
971 }
972 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
973 clock.p = (clock.p1 * clock.p2);
974 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
975 clock.vco = 0;
976 memcpy(best_clock, &clock, sizeof(intel_clock_t));
977 return true;
978 }
979
980 /**
981 * intel_wait_for_vblank - wait for vblank on a given pipe
982 * @dev: drm device
983 * @pipe: pipe to wait for
984 *
985 * Wait for vblank to occur on a given pipe. Needed for various bits of
986 * mode setting code.
987 */
988 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
989 {
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
992
993 /* Clear existing vblank status. Note this will clear any other
994 * sticky status fields as well.
995 *
996 * This races with i915_driver_irq_handler() with the result
997 * that either function could miss a vblank event. Here it is not
998 * fatal, as we will either wait upon the next vblank interrupt or
999 * timeout. Generally speaking intel_wait_for_vblank() is only
1000 * called during modeset at which time the GPU should be idle and
1001 * should *not* be performing page flips and thus not waiting on
1002 * vblanks...
1003 * Currently, the result of us stealing a vblank from the irq
1004 * handler is that a single frame will be skipped during swapbuffers.
1005 */
1006 I915_WRITE(pipestat_reg,
1007 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1008
1009 /* Wait for vblank interrupt bit to set */
1010 if (wait_for(I915_READ(pipestat_reg) &
1011 PIPE_VBLANK_INTERRUPT_STATUS,
1012 50))
1013 DRM_DEBUG_KMS("vblank wait timed out\n");
1014 }
1015
1016 /*
1017 * intel_wait_for_pipe_off - wait for pipe to turn off
1018 * @dev: drm device
1019 * @pipe: pipe to wait for
1020 *
1021 * After disabling a pipe, we can't wait for vblank in the usual way,
1022 * spinning on the vblank interrupt status bit, since we won't actually
1023 * see an interrupt when the pipe is disabled.
1024 *
1025 * On Gen4 and above:
1026 * wait for the pipe register state bit to turn off
1027 *
1028 * Otherwise:
1029 * wait for the display line value to settle (it usually
1030 * ends up stopping at the start of the next frame).
1031 *
1032 */
1033 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1034 {
1035 struct drm_i915_private *dev_priv = dev->dev_private;
1036
1037 if (INTEL_INFO(dev)->gen >= 4) {
1038 int reg = PIPECONF(pipe);
1039
1040 /* Wait for the Pipe State to go off */
1041 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1042 100))
1043 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1044 } else {
1045 u32 last_line;
1046 int reg = PIPEDSL(pipe);
1047 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1048
1049 /* Wait for the display line to settle */
1050 do {
1051 last_line = I915_READ(reg) & DSL_LINEMASK;
1052 mdelay(5);
1053 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1054 time_after(timeout, jiffies));
1055 if (time_after(jiffies, timeout))
1056 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1057 }
1058 }
1059
1060 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1061 {
1062 struct drm_device *dev = crtc->dev;
1063 struct drm_i915_private *dev_priv = dev->dev_private;
1064 struct drm_framebuffer *fb = crtc->fb;
1065 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1066 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068 int plane, i;
1069 u32 fbc_ctl, fbc_ctl2;
1070
1071 if (fb->pitch == dev_priv->cfb_pitch &&
1072 obj_priv->fence_reg == dev_priv->cfb_fence &&
1073 intel_crtc->plane == dev_priv->cfb_plane &&
1074 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1075 return;
1076
1077 i8xx_disable_fbc(dev);
1078
1079 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1080
1081 if (fb->pitch < dev_priv->cfb_pitch)
1082 dev_priv->cfb_pitch = fb->pitch;
1083
1084 /* FBC_CTL wants 64B units */
1085 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1086 dev_priv->cfb_fence = obj_priv->fence_reg;
1087 dev_priv->cfb_plane = intel_crtc->plane;
1088 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1089
1090 /* Clear old tags */
1091 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1092 I915_WRITE(FBC_TAG + (i * 4), 0);
1093
1094 /* Set it up... */
1095 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1096 if (obj_priv->tiling_mode != I915_TILING_NONE)
1097 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1098 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1099 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1100
1101 /* enable it... */
1102 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1103 if (IS_I945GM(dev))
1104 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1105 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1106 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1107 if (obj_priv->tiling_mode != I915_TILING_NONE)
1108 fbc_ctl |= dev_priv->cfb_fence;
1109 I915_WRITE(FBC_CONTROL, fbc_ctl);
1110
1111 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1112 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1113 }
1114
1115 void i8xx_disable_fbc(struct drm_device *dev)
1116 {
1117 struct drm_i915_private *dev_priv = dev->dev_private;
1118 u32 fbc_ctl;
1119
1120 /* Disable compression */
1121 fbc_ctl = I915_READ(FBC_CONTROL);
1122 if ((fbc_ctl & FBC_CTL_EN) == 0)
1123 return;
1124
1125 fbc_ctl &= ~FBC_CTL_EN;
1126 I915_WRITE(FBC_CONTROL, fbc_ctl);
1127
1128 /* Wait for compressing bit to clear */
1129 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1130 DRM_DEBUG_KMS("FBC idle timed out\n");
1131 return;
1132 }
1133
1134 DRM_DEBUG_KMS("disabled FBC\n");
1135 }
1136
1137 static bool i8xx_fbc_enabled(struct drm_device *dev)
1138 {
1139 struct drm_i915_private *dev_priv = dev->dev_private;
1140
1141 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1142 }
1143
1144 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1145 {
1146 struct drm_device *dev = crtc->dev;
1147 struct drm_i915_private *dev_priv = dev->dev_private;
1148 struct drm_framebuffer *fb = crtc->fb;
1149 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1150 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1152 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1153 unsigned long stall_watermark = 200;
1154 u32 dpfc_ctl;
1155
1156 dpfc_ctl = I915_READ(DPFC_CONTROL);
1157 if (dpfc_ctl & DPFC_CTL_EN) {
1158 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1159 dev_priv->cfb_fence == obj_priv->fence_reg &&
1160 dev_priv->cfb_plane == intel_crtc->plane &&
1161 dev_priv->cfb_y == crtc->y)
1162 return;
1163
1164 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1165 POSTING_READ(DPFC_CONTROL);
1166 intel_wait_for_vblank(dev, intel_crtc->pipe);
1167 }
1168
1169 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1170 dev_priv->cfb_fence = obj_priv->fence_reg;
1171 dev_priv->cfb_plane = intel_crtc->plane;
1172 dev_priv->cfb_y = crtc->y;
1173
1174 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1175 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1176 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1177 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1178 } else {
1179 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1180 }
1181
1182 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1183 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1184 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1185 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1186
1187 /* enable it... */
1188 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1189
1190 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1191 }
1192
1193 void g4x_disable_fbc(struct drm_device *dev)
1194 {
1195 struct drm_i915_private *dev_priv = dev->dev_private;
1196 u32 dpfc_ctl;
1197
1198 /* Disable compression */
1199 dpfc_ctl = I915_READ(DPFC_CONTROL);
1200 if (dpfc_ctl & DPFC_CTL_EN) {
1201 dpfc_ctl &= ~DPFC_CTL_EN;
1202 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1203
1204 DRM_DEBUG_KMS("disabled FBC\n");
1205 }
1206 }
1207
1208 static bool g4x_fbc_enabled(struct drm_device *dev)
1209 {
1210 struct drm_i915_private *dev_priv = dev->dev_private;
1211
1212 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1213 }
1214
1215 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1216 {
1217 struct drm_device *dev = crtc->dev;
1218 struct drm_i915_private *dev_priv = dev->dev_private;
1219 struct drm_framebuffer *fb = crtc->fb;
1220 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1221 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1223 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1224 unsigned long stall_watermark = 200;
1225 u32 dpfc_ctl;
1226
1227 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1228 if (dpfc_ctl & DPFC_CTL_EN) {
1229 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1230 dev_priv->cfb_fence == obj_priv->fence_reg &&
1231 dev_priv->cfb_plane == intel_crtc->plane &&
1232 dev_priv->cfb_offset == obj_priv->gtt_offset &&
1233 dev_priv->cfb_y == crtc->y)
1234 return;
1235
1236 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1237 POSTING_READ(ILK_DPFC_CONTROL);
1238 intel_wait_for_vblank(dev, intel_crtc->pipe);
1239 }
1240
1241 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1242 dev_priv->cfb_fence = obj_priv->fence_reg;
1243 dev_priv->cfb_plane = intel_crtc->plane;
1244 dev_priv->cfb_offset = obj_priv->gtt_offset;
1245 dev_priv->cfb_y = crtc->y;
1246
1247 dpfc_ctl &= DPFC_RESERVED;
1248 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1249 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1250 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1251 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1252 } else {
1253 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1254 }
1255
1256 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1257 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1258 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1259 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1260 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1261 /* enable it... */
1262 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1263
1264 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1265 }
1266
1267 void ironlake_disable_fbc(struct drm_device *dev)
1268 {
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270 u32 dpfc_ctl;
1271
1272 /* Disable compression */
1273 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1274 if (dpfc_ctl & DPFC_CTL_EN) {
1275 dpfc_ctl &= ~DPFC_CTL_EN;
1276 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1277
1278 DRM_DEBUG_KMS("disabled FBC\n");
1279 }
1280 }
1281
1282 static bool ironlake_fbc_enabled(struct drm_device *dev)
1283 {
1284 struct drm_i915_private *dev_priv = dev->dev_private;
1285
1286 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1287 }
1288
1289 bool intel_fbc_enabled(struct drm_device *dev)
1290 {
1291 struct drm_i915_private *dev_priv = dev->dev_private;
1292
1293 if (!dev_priv->display.fbc_enabled)
1294 return false;
1295
1296 return dev_priv->display.fbc_enabled(dev);
1297 }
1298
1299 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1300 {
1301 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1302
1303 if (!dev_priv->display.enable_fbc)
1304 return;
1305
1306 dev_priv->display.enable_fbc(crtc, interval);
1307 }
1308
1309 void intel_disable_fbc(struct drm_device *dev)
1310 {
1311 struct drm_i915_private *dev_priv = dev->dev_private;
1312
1313 if (!dev_priv->display.disable_fbc)
1314 return;
1315
1316 dev_priv->display.disable_fbc(dev);
1317 }
1318
1319 /**
1320 * intel_update_fbc - enable/disable FBC as needed
1321 * @dev: the drm_device
1322 *
1323 * Set up the framebuffer compression hardware at mode set time. We
1324 * enable it if possible:
1325 * - plane A only (on pre-965)
1326 * - no pixel mulitply/line duplication
1327 * - no alpha buffer discard
1328 * - no dual wide
1329 * - framebuffer <= 2048 in width, 1536 in height
1330 *
1331 * We can't assume that any compression will take place (worst case),
1332 * so the compressed buffer has to be the same size as the uncompressed
1333 * one. It also must reside (along with the line length buffer) in
1334 * stolen memory.
1335 *
1336 * We need to enable/disable FBC on a global basis.
1337 */
1338 static void intel_update_fbc(struct drm_device *dev)
1339 {
1340 struct drm_i915_private *dev_priv = dev->dev_private;
1341 struct drm_crtc *crtc = NULL, *tmp_crtc;
1342 struct intel_crtc *intel_crtc;
1343 struct drm_framebuffer *fb;
1344 struct intel_framebuffer *intel_fb;
1345 struct drm_i915_gem_object *obj_priv;
1346
1347 DRM_DEBUG_KMS("\n");
1348
1349 if (!i915_powersave)
1350 return;
1351
1352 if (!I915_HAS_FBC(dev))
1353 return;
1354
1355 /*
1356 * If FBC is already on, we just have to verify that we can
1357 * keep it that way...
1358 * Need to disable if:
1359 * - more than one pipe is active
1360 * - changing FBC params (stride, fence, mode)
1361 * - new fb is too large to fit in compressed buffer
1362 * - going to an unsupported config (interlace, pixel multiply, etc.)
1363 */
1364 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1365 if (tmp_crtc->enabled) {
1366 if (crtc) {
1367 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1368 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1369 goto out_disable;
1370 }
1371 crtc = tmp_crtc;
1372 }
1373 }
1374
1375 if (!crtc || crtc->fb == NULL) {
1376 DRM_DEBUG_KMS("no output, disabling\n");
1377 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1378 goto out_disable;
1379 }
1380
1381 intel_crtc = to_intel_crtc(crtc);
1382 fb = crtc->fb;
1383 intel_fb = to_intel_framebuffer(fb);
1384 obj_priv = to_intel_bo(intel_fb->obj);
1385
1386 if (intel_fb->obj->size > dev_priv->cfb_size) {
1387 DRM_DEBUG_KMS("framebuffer too large, disabling "
1388 "compression\n");
1389 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1390 goto out_disable;
1391 }
1392 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1393 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1394 DRM_DEBUG_KMS("mode incompatible with compression, "
1395 "disabling\n");
1396 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1397 goto out_disable;
1398 }
1399 if ((crtc->mode.hdisplay > 2048) ||
1400 (crtc->mode.vdisplay > 1536)) {
1401 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1402 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1403 goto out_disable;
1404 }
1405 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1406 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1407 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1408 goto out_disable;
1409 }
1410 if (obj_priv->tiling_mode != I915_TILING_X) {
1411 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1412 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1413 goto out_disable;
1414 }
1415
1416 /* If the kernel debugger is active, always disable compression */
1417 if (in_dbg_master())
1418 goto out_disable;
1419
1420 intel_enable_fbc(crtc, 500);
1421 return;
1422
1423 out_disable:
1424 /* Multiple disables should be harmless */
1425 if (intel_fbc_enabled(dev)) {
1426 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1427 intel_disable_fbc(dev);
1428 }
1429 }
1430
1431 int
1432 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1433 struct drm_gem_object *obj,
1434 bool pipelined)
1435 {
1436 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1437 u32 alignment;
1438 int ret;
1439
1440 switch (obj_priv->tiling_mode) {
1441 case I915_TILING_NONE:
1442 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1443 alignment = 128 * 1024;
1444 else if (INTEL_INFO(dev)->gen >= 4)
1445 alignment = 4 * 1024;
1446 else
1447 alignment = 64 * 1024;
1448 break;
1449 case I915_TILING_X:
1450 /* pin() will align the object as required by fence */
1451 alignment = 0;
1452 break;
1453 case I915_TILING_Y:
1454 /* FIXME: Is this true? */
1455 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1456 return -EINVAL;
1457 default:
1458 BUG();
1459 }
1460
1461 ret = i915_gem_object_pin(obj, alignment);
1462 if (ret)
1463 return ret;
1464
1465 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1466 if (ret)
1467 goto err_unpin;
1468
1469 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1470 * fence, whereas 965+ only requires a fence if using
1471 * framebuffer compression. For simplicity, we always install
1472 * a fence as the cost is not that onerous.
1473 */
1474 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1475 obj_priv->tiling_mode != I915_TILING_NONE) {
1476 ret = i915_gem_object_get_fence_reg(obj, false);
1477 if (ret)
1478 goto err_unpin;
1479 }
1480
1481 return 0;
1482
1483 err_unpin:
1484 i915_gem_object_unpin(obj);
1485 return ret;
1486 }
1487
1488 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1489 static int
1490 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1491 int x, int y, int enter)
1492 {
1493 struct drm_device *dev = crtc->dev;
1494 struct drm_i915_private *dev_priv = dev->dev_private;
1495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1496 struct intel_framebuffer *intel_fb;
1497 struct drm_i915_gem_object *obj_priv;
1498 struct drm_gem_object *obj;
1499 int plane = intel_crtc->plane;
1500 unsigned long Start, Offset;
1501 u32 dspcntr;
1502 u32 reg;
1503
1504 switch (plane) {
1505 case 0:
1506 case 1:
1507 break;
1508 default:
1509 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1510 return -EINVAL;
1511 }
1512
1513 intel_fb = to_intel_framebuffer(fb);
1514 obj = intel_fb->obj;
1515 obj_priv = to_intel_bo(obj);
1516
1517 reg = DSPCNTR(plane);
1518 dspcntr = I915_READ(reg);
1519 /* Mask out pixel format bits in case we change it */
1520 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1521 switch (fb->bits_per_pixel) {
1522 case 8:
1523 dspcntr |= DISPPLANE_8BPP;
1524 break;
1525 case 16:
1526 if (fb->depth == 15)
1527 dspcntr |= DISPPLANE_15_16BPP;
1528 else
1529 dspcntr |= DISPPLANE_16BPP;
1530 break;
1531 case 24:
1532 case 32:
1533 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1534 break;
1535 default:
1536 DRM_ERROR("Unknown color depth\n");
1537 return -EINVAL;
1538 }
1539 if (INTEL_INFO(dev)->gen >= 4) {
1540 if (obj_priv->tiling_mode != I915_TILING_NONE)
1541 dspcntr |= DISPPLANE_TILED;
1542 else
1543 dspcntr &= ~DISPPLANE_TILED;
1544 }
1545
1546 if (HAS_PCH_SPLIT(dev))
1547 /* must disable */
1548 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1549
1550 I915_WRITE(reg, dspcntr);
1551
1552 Start = obj_priv->gtt_offset;
1553 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1554
1555 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1556 Start, Offset, x, y, fb->pitch);
1557 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1558 if (INTEL_INFO(dev)->gen >= 4) {
1559 I915_WRITE(DSPSURF(plane), Start);
1560 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1561 I915_WRITE(DSPADDR(plane), Offset);
1562 } else
1563 I915_WRITE(DSPADDR(plane), Start + Offset);
1564 POSTING_READ(reg);
1565
1566 intel_update_fbc(dev);
1567 intel_increase_pllclock(crtc);
1568
1569 return 0;
1570 }
1571
1572 static int
1573 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1574 struct drm_framebuffer *old_fb)
1575 {
1576 struct drm_device *dev = crtc->dev;
1577 struct drm_i915_master_private *master_priv;
1578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1579 int ret;
1580
1581 /* no fb bound */
1582 if (!crtc->fb) {
1583 DRM_DEBUG_KMS("No FB bound\n");
1584 return 0;
1585 }
1586
1587 switch (intel_crtc->plane) {
1588 case 0:
1589 case 1:
1590 break;
1591 default:
1592 return -EINVAL;
1593 }
1594
1595 mutex_lock(&dev->struct_mutex);
1596 ret = intel_pin_and_fence_fb_obj(dev,
1597 to_intel_framebuffer(crtc->fb)->obj,
1598 false);
1599 if (ret != 0) {
1600 mutex_unlock(&dev->struct_mutex);
1601 return ret;
1602 }
1603
1604 if (old_fb) {
1605 struct drm_i915_private *dev_priv = dev->dev_private;
1606 struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1607 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1608
1609 wait_event(dev_priv->pending_flip_queue,
1610 atomic_read(&obj_priv->pending_flip) == 0);
1611 }
1612
1613 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, 0);
1614 if (ret) {
1615 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1616 mutex_unlock(&dev->struct_mutex);
1617 return ret;
1618 }
1619
1620 if (old_fb)
1621 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1622
1623 mutex_unlock(&dev->struct_mutex);
1624
1625 if (!dev->primary->master)
1626 return 0;
1627
1628 master_priv = dev->primary->master->driver_priv;
1629 if (!master_priv->sarea_priv)
1630 return 0;
1631
1632 if (intel_crtc->pipe) {
1633 master_priv->sarea_priv->pipeB_x = x;
1634 master_priv->sarea_priv->pipeB_y = y;
1635 } else {
1636 master_priv->sarea_priv->pipeA_x = x;
1637 master_priv->sarea_priv->pipeA_y = y;
1638 }
1639
1640 return 0;
1641 }
1642
1643 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1644 {
1645 struct drm_device *dev = crtc->dev;
1646 struct drm_i915_private *dev_priv = dev->dev_private;
1647 u32 dpa_ctl;
1648
1649 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1650 dpa_ctl = I915_READ(DP_A);
1651 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1652
1653 if (clock < 200000) {
1654 u32 temp;
1655 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1656 /* workaround for 160Mhz:
1657 1) program 0x4600c bits 15:0 = 0x8124
1658 2) program 0x46010 bit 0 = 1
1659 3) program 0x46034 bit 24 = 1
1660 4) program 0x64000 bit 14 = 1
1661 */
1662 temp = I915_READ(0x4600c);
1663 temp &= 0xffff0000;
1664 I915_WRITE(0x4600c, temp | 0x8124);
1665
1666 temp = I915_READ(0x46010);
1667 I915_WRITE(0x46010, temp | 1);
1668
1669 temp = I915_READ(0x46034);
1670 I915_WRITE(0x46034, temp | (1 << 24));
1671 } else {
1672 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1673 }
1674 I915_WRITE(DP_A, dpa_ctl);
1675
1676 POSTING_READ(DP_A);
1677 udelay(500);
1678 }
1679
1680 /* The FDI link training functions for ILK/Ibexpeak. */
1681 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1682 {
1683 struct drm_device *dev = crtc->dev;
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1686 int pipe = intel_crtc->pipe;
1687 u32 reg, temp, tries;
1688
1689 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1690 for train result */
1691 reg = FDI_RX_IMR(pipe);
1692 temp = I915_READ(reg);
1693 temp &= ~FDI_RX_SYMBOL_LOCK;
1694 temp &= ~FDI_RX_BIT_LOCK;
1695 I915_WRITE(reg, temp);
1696 I915_READ(reg);
1697 udelay(150);
1698
1699 /* enable CPU FDI TX and PCH FDI RX */
1700 reg = FDI_TX_CTL(pipe);
1701 temp = I915_READ(reg);
1702 temp &= ~(7 << 19);
1703 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1704 temp &= ~FDI_LINK_TRAIN_NONE;
1705 temp |= FDI_LINK_TRAIN_PATTERN_1;
1706 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1707
1708 reg = FDI_RX_CTL(pipe);
1709 temp = I915_READ(reg);
1710 temp &= ~FDI_LINK_TRAIN_NONE;
1711 temp |= FDI_LINK_TRAIN_PATTERN_1;
1712 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1713
1714 POSTING_READ(reg);
1715 udelay(150);
1716
1717 /* Ironlake workaround, enable clock pointer after FDI enable*/
1718 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1719
1720 reg = FDI_RX_IIR(pipe);
1721 for (tries = 0; tries < 5; tries++) {
1722 temp = I915_READ(reg);
1723 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1724
1725 if ((temp & FDI_RX_BIT_LOCK)) {
1726 DRM_DEBUG_KMS("FDI train 1 done.\n");
1727 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1728 break;
1729 }
1730 }
1731 if (tries == 5)
1732 DRM_ERROR("FDI train 1 fail!\n");
1733
1734 /* Train 2 */
1735 reg = FDI_TX_CTL(pipe);
1736 temp = I915_READ(reg);
1737 temp &= ~FDI_LINK_TRAIN_NONE;
1738 temp |= FDI_LINK_TRAIN_PATTERN_2;
1739 I915_WRITE(reg, temp);
1740
1741 reg = FDI_RX_CTL(pipe);
1742 temp = I915_READ(reg);
1743 temp &= ~FDI_LINK_TRAIN_NONE;
1744 temp |= FDI_LINK_TRAIN_PATTERN_2;
1745 I915_WRITE(reg, temp);
1746
1747 POSTING_READ(reg);
1748 udelay(150);
1749
1750 reg = FDI_RX_IIR(pipe);
1751 for (tries = 0; tries < 5; tries++) {
1752 temp = I915_READ(reg);
1753 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1754
1755 if (temp & FDI_RX_SYMBOL_LOCK) {
1756 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1757 DRM_DEBUG_KMS("FDI train 2 done.\n");
1758 break;
1759 }
1760 }
1761 if (tries == 5)
1762 DRM_ERROR("FDI train 2 fail!\n");
1763
1764 DRM_DEBUG_KMS("FDI train done\n");
1765
1766 /* enable normal train */
1767 reg = FDI_TX_CTL(pipe);
1768 temp = I915_READ(reg);
1769 temp &= ~FDI_LINK_TRAIN_NONE;
1770 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1771 I915_WRITE(reg, temp);
1772
1773 reg = FDI_RX_CTL(pipe);
1774 temp = I915_READ(reg);
1775 if (HAS_PCH_CPT(dev)) {
1776 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1777 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1778 } else {
1779 temp &= ~FDI_LINK_TRAIN_NONE;
1780 temp |= FDI_LINK_TRAIN_NONE;
1781 }
1782 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1783
1784 /* wait one idle pattern time */
1785 POSTING_READ(reg);
1786 udelay(1000);
1787 }
1788
1789 static const int const snb_b_fdi_train_param [] = {
1790 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1791 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1792 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1793 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1794 };
1795
1796 /* The FDI link training functions for SNB/Cougarpoint. */
1797 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1798 {
1799 struct drm_device *dev = crtc->dev;
1800 struct drm_i915_private *dev_priv = dev->dev_private;
1801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1802 int pipe = intel_crtc->pipe;
1803 u32 reg, temp, i;
1804
1805 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1806 for train result */
1807 reg = FDI_RX_IMR(pipe);
1808 temp = I915_READ(reg);
1809 temp &= ~FDI_RX_SYMBOL_LOCK;
1810 temp &= ~FDI_RX_BIT_LOCK;
1811 I915_WRITE(reg, temp);
1812
1813 POSTING_READ(reg);
1814 udelay(150);
1815
1816 /* enable CPU FDI TX and PCH FDI RX */
1817 reg = FDI_TX_CTL(pipe);
1818 temp = I915_READ(reg);
1819 temp &= ~(7 << 19);
1820 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1821 temp &= ~FDI_LINK_TRAIN_NONE;
1822 temp |= FDI_LINK_TRAIN_PATTERN_1;
1823 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1824 /* SNB-B */
1825 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1826 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1827
1828 reg = FDI_RX_CTL(pipe);
1829 temp = I915_READ(reg);
1830 if (HAS_PCH_CPT(dev)) {
1831 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1832 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1833 } else {
1834 temp &= ~FDI_LINK_TRAIN_NONE;
1835 temp |= FDI_LINK_TRAIN_PATTERN_1;
1836 }
1837 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1838
1839 POSTING_READ(reg);
1840 udelay(150);
1841
1842 for (i = 0; i < 4; i++ ) {
1843 reg = FDI_TX_CTL(pipe);
1844 temp = I915_READ(reg);
1845 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1846 temp |= snb_b_fdi_train_param[i];
1847 I915_WRITE(reg, temp);
1848
1849 POSTING_READ(reg);
1850 udelay(500);
1851
1852 reg = FDI_RX_IIR(pipe);
1853 temp = I915_READ(reg);
1854 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1855
1856 if (temp & FDI_RX_BIT_LOCK) {
1857 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1858 DRM_DEBUG_KMS("FDI train 1 done.\n");
1859 break;
1860 }
1861 }
1862 if (i == 4)
1863 DRM_ERROR("FDI train 1 fail!\n");
1864
1865 /* Train 2 */
1866 reg = FDI_TX_CTL(pipe);
1867 temp = I915_READ(reg);
1868 temp &= ~FDI_LINK_TRAIN_NONE;
1869 temp |= FDI_LINK_TRAIN_PATTERN_2;
1870 if (IS_GEN6(dev)) {
1871 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1872 /* SNB-B */
1873 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1874 }
1875 I915_WRITE(reg, temp);
1876
1877 reg = FDI_RX_CTL(pipe);
1878 temp = I915_READ(reg);
1879 if (HAS_PCH_CPT(dev)) {
1880 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1881 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1882 } else {
1883 temp &= ~FDI_LINK_TRAIN_NONE;
1884 temp |= FDI_LINK_TRAIN_PATTERN_2;
1885 }
1886 I915_WRITE(reg, temp);
1887
1888 POSTING_READ(reg);
1889 udelay(150);
1890
1891 for (i = 0; i < 4; i++ ) {
1892 reg = FDI_TX_CTL(pipe);
1893 temp = I915_READ(reg);
1894 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1895 temp |= snb_b_fdi_train_param[i];
1896 I915_WRITE(reg, temp);
1897
1898 POSTING_READ(reg);
1899 udelay(500);
1900
1901 reg = FDI_RX_IIR(pipe);
1902 temp = I915_READ(reg);
1903 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1904
1905 if (temp & FDI_RX_SYMBOL_LOCK) {
1906 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1907 DRM_DEBUG_KMS("FDI train 2 done.\n");
1908 break;
1909 }
1910 }
1911 if (i == 4)
1912 DRM_ERROR("FDI train 2 fail!\n");
1913
1914 DRM_DEBUG_KMS("FDI train done.\n");
1915 }
1916
1917 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1918 {
1919 struct drm_device *dev = crtc->dev;
1920 struct drm_i915_private *dev_priv = dev->dev_private;
1921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1922 int pipe = intel_crtc->pipe;
1923 u32 reg, temp;
1924
1925 /* Write the TU size bits so error detection works */
1926 I915_WRITE(FDI_RX_TUSIZE1(pipe),
1927 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1928
1929 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1930 reg = FDI_RX_CTL(pipe);
1931 temp = I915_READ(reg);
1932 temp &= ~((0x7 << 19) | (0x7 << 16));
1933 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1934 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1935 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1936
1937 POSTING_READ(reg);
1938 udelay(200);
1939
1940 /* Switch from Rawclk to PCDclk */
1941 temp = I915_READ(reg);
1942 I915_WRITE(reg, temp | FDI_PCDCLK);
1943
1944 POSTING_READ(reg);
1945 udelay(200);
1946
1947 /* Enable CPU FDI TX PLL, always on for Ironlake */
1948 reg = FDI_TX_CTL(pipe);
1949 temp = I915_READ(reg);
1950 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1951 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1952
1953 POSTING_READ(reg);
1954 udelay(100);
1955 }
1956 }
1957
1958 static void intel_flush_display_plane(struct drm_device *dev,
1959 int plane)
1960 {
1961 struct drm_i915_private *dev_priv = dev->dev_private;
1962 u32 reg = DSPADDR(plane);
1963 I915_WRITE(reg, I915_READ(reg));
1964 }
1965
1966 /*
1967 * When we disable a pipe, we need to clear any pending scanline wait events
1968 * to avoid hanging the ring, which we assume we are waiting on.
1969 */
1970 static void intel_clear_scanline_wait(struct drm_device *dev)
1971 {
1972 struct drm_i915_private *dev_priv = dev->dev_private;
1973 u32 tmp;
1974
1975 if (IS_GEN2(dev))
1976 /* Can't break the hang on i8xx */
1977 return;
1978
1979 tmp = I915_READ(PRB0_CTL);
1980 if (tmp & RING_WAIT) {
1981 I915_WRITE(PRB0_CTL, tmp);
1982 POSTING_READ(PRB0_CTL);
1983 }
1984 }
1985
1986 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
1987 {
1988 struct drm_i915_gem_object *obj_priv;
1989 struct drm_i915_private *dev_priv;
1990
1991 if (crtc->fb == NULL)
1992 return;
1993
1994 obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj);
1995 dev_priv = crtc->dev->dev_private;
1996 wait_event(dev_priv->pending_flip_queue,
1997 atomic_read(&obj_priv->pending_flip) == 0);
1998 }
1999
2000 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2001 {
2002 struct drm_device *dev = crtc->dev;
2003 struct drm_i915_private *dev_priv = dev->dev_private;
2004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2005 int pipe = intel_crtc->pipe;
2006 int plane = intel_crtc->plane;
2007 u32 reg, temp;
2008
2009 if (intel_crtc->active)
2010 return;
2011
2012 intel_crtc->active = true;
2013 intel_update_watermarks(dev);
2014
2015 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2016 temp = I915_READ(PCH_LVDS);
2017 if ((temp & LVDS_PORT_EN) == 0)
2018 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2019 }
2020
2021 ironlake_fdi_enable(crtc);
2022
2023 /* Enable panel fitting for LVDS */
2024 if (dev_priv->pch_pf_size &&
2025 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2026 /* Force use of hard-coded filter coefficients
2027 * as some pre-programmed values are broken,
2028 * e.g. x201.
2029 */
2030 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2031 PF_ENABLE | PF_FILTER_MED_3x3);
2032 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2033 dev_priv->pch_pf_pos);
2034 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2035 dev_priv->pch_pf_size);
2036 }
2037
2038 /* Enable CPU pipe */
2039 reg = PIPECONF(pipe);
2040 temp = I915_READ(reg);
2041 if ((temp & PIPECONF_ENABLE) == 0) {
2042 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2043 POSTING_READ(reg);
2044 intel_wait_for_vblank(dev, intel_crtc->pipe);
2045 }
2046
2047 /* configure and enable CPU plane */
2048 reg = DSPCNTR(plane);
2049 temp = I915_READ(reg);
2050 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2051 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2052 intel_flush_display_plane(dev, plane);
2053 }
2054
2055 /* For PCH output, training FDI link */
2056 if (IS_GEN6(dev))
2057 gen6_fdi_link_train(crtc);
2058 else
2059 ironlake_fdi_link_train(crtc);
2060
2061 /* enable PCH DPLL */
2062 reg = PCH_DPLL(pipe);
2063 temp = I915_READ(reg);
2064 if ((temp & DPLL_VCO_ENABLE) == 0) {
2065 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2066 POSTING_READ(reg);
2067 udelay(200);
2068 }
2069
2070 if (HAS_PCH_CPT(dev)) {
2071 /* Be sure PCH DPLL SEL is set */
2072 temp = I915_READ(PCH_DPLL_SEL);
2073 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2074 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2075 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2076 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2077 I915_WRITE(PCH_DPLL_SEL, temp);
2078 }
2079
2080 /* set transcoder timing */
2081 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2082 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2083 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2084
2085 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2086 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2087 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2088
2089 /* For PCH DP, enable TRANS_DP_CTL */
2090 if (HAS_PCH_CPT(dev) &&
2091 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2092 reg = TRANS_DP_CTL(pipe);
2093 temp = I915_READ(reg);
2094 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2095 TRANS_DP_SYNC_MASK);
2096 temp |= (TRANS_DP_OUTPUT_ENABLE |
2097 TRANS_DP_ENH_FRAMING);
2098
2099 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2100 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2101 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2102 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2103
2104 switch (intel_trans_dp_port_sel(crtc)) {
2105 case PCH_DP_B:
2106 temp |= TRANS_DP_PORT_SEL_B;
2107 break;
2108 case PCH_DP_C:
2109 temp |= TRANS_DP_PORT_SEL_C;
2110 break;
2111 case PCH_DP_D:
2112 temp |= TRANS_DP_PORT_SEL_D;
2113 break;
2114 default:
2115 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2116 temp |= TRANS_DP_PORT_SEL_B;
2117 break;
2118 }
2119
2120 I915_WRITE(reg, temp);
2121 }
2122
2123 /* enable PCH transcoder */
2124 reg = TRANSCONF(pipe);
2125 temp = I915_READ(reg);
2126 /*
2127 * make the BPC in transcoder be consistent with
2128 * that in pipeconf reg.
2129 */
2130 temp &= ~PIPE_BPC_MASK;
2131 temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2132 I915_WRITE(reg, temp | TRANS_ENABLE);
2133 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2134 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2135
2136 intel_crtc_load_lut(crtc);
2137 intel_update_fbc(dev);
2138 intel_crtc_update_cursor(crtc, true);
2139 }
2140
2141 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2142 {
2143 struct drm_device *dev = crtc->dev;
2144 struct drm_i915_private *dev_priv = dev->dev_private;
2145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2146 int pipe = intel_crtc->pipe;
2147 int plane = intel_crtc->plane;
2148 u32 reg, temp;
2149
2150 if (!intel_crtc->active)
2151 return;
2152
2153 intel_crtc_wait_for_pending_flips(crtc);
2154 drm_vblank_off(dev, pipe);
2155 intel_crtc_update_cursor(crtc, false);
2156
2157 /* Disable display plane */
2158 reg = DSPCNTR(plane);
2159 temp = I915_READ(reg);
2160 if (temp & DISPLAY_PLANE_ENABLE) {
2161 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2162 intel_flush_display_plane(dev, plane);
2163 }
2164
2165 if (dev_priv->cfb_plane == plane &&
2166 dev_priv->display.disable_fbc)
2167 dev_priv->display.disable_fbc(dev);
2168
2169 /* disable cpu pipe, disable after all planes disabled */
2170 reg = PIPECONF(pipe);
2171 temp = I915_READ(reg);
2172 if (temp & PIPECONF_ENABLE) {
2173 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2174 POSTING_READ(reg);
2175 /* wait for cpu pipe off, pipe state */
2176 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2177 }
2178
2179 /* Disable PF */
2180 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2181 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2182
2183 /* disable CPU FDI tx and PCH FDI rx */
2184 reg = FDI_TX_CTL(pipe);
2185 temp = I915_READ(reg);
2186 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2187 POSTING_READ(reg);
2188
2189 reg = FDI_RX_CTL(pipe);
2190 temp = I915_READ(reg);
2191 temp &= ~(0x7 << 16);
2192 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2193 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2194
2195 POSTING_READ(reg);
2196 udelay(100);
2197
2198 /* Ironlake workaround, disable clock pointer after downing FDI */
2199 I915_WRITE(FDI_RX_CHICKEN(pipe),
2200 I915_READ(FDI_RX_CHICKEN(pipe) &
2201 ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2202
2203 /* still set train pattern 1 */
2204 reg = FDI_TX_CTL(pipe);
2205 temp = I915_READ(reg);
2206 temp &= ~FDI_LINK_TRAIN_NONE;
2207 temp |= FDI_LINK_TRAIN_PATTERN_1;
2208 I915_WRITE(reg, temp);
2209
2210 reg = FDI_RX_CTL(pipe);
2211 temp = I915_READ(reg);
2212 if (HAS_PCH_CPT(dev)) {
2213 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2214 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2215 } else {
2216 temp &= ~FDI_LINK_TRAIN_NONE;
2217 temp |= FDI_LINK_TRAIN_PATTERN_1;
2218 }
2219 /* BPC in FDI rx is consistent with that in PIPECONF */
2220 temp &= ~(0x07 << 16);
2221 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2222 I915_WRITE(reg, temp);
2223
2224 POSTING_READ(reg);
2225 udelay(100);
2226
2227 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2228 temp = I915_READ(PCH_LVDS);
2229 if (temp & LVDS_PORT_EN) {
2230 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2231 POSTING_READ(PCH_LVDS);
2232 udelay(100);
2233 }
2234 }
2235
2236 /* disable PCH transcoder */
2237 reg = TRANSCONF(plane);
2238 temp = I915_READ(reg);
2239 if (temp & TRANS_ENABLE) {
2240 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2241 /* wait for PCH transcoder off, transcoder state */
2242 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2243 DRM_ERROR("failed to disable transcoder\n");
2244 }
2245
2246 if (HAS_PCH_CPT(dev)) {
2247 /* disable TRANS_DP_CTL */
2248 reg = TRANS_DP_CTL(pipe);
2249 temp = I915_READ(reg);
2250 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2251 I915_WRITE(reg, temp);
2252
2253 /* disable DPLL_SEL */
2254 temp = I915_READ(PCH_DPLL_SEL);
2255 if (pipe == 0)
2256 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2257 else
2258 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2259 I915_WRITE(PCH_DPLL_SEL, temp);
2260 }
2261
2262 /* disable PCH DPLL */
2263 reg = PCH_DPLL(pipe);
2264 temp = I915_READ(reg);
2265 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2266
2267 /* Switch from PCDclk to Rawclk */
2268 reg = FDI_RX_CTL(pipe);
2269 temp = I915_READ(reg);
2270 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2271
2272 /* Disable CPU FDI TX PLL */
2273 reg = FDI_TX_CTL(pipe);
2274 temp = I915_READ(reg);
2275 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2276
2277 POSTING_READ(reg);
2278 udelay(100);
2279
2280 reg = FDI_RX_CTL(pipe);
2281 temp = I915_READ(reg);
2282 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2283
2284 /* Wait for the clocks to turn off. */
2285 POSTING_READ(reg);
2286 udelay(100);
2287
2288 intel_crtc->active = false;
2289 intel_update_watermarks(dev);
2290 intel_update_fbc(dev);
2291 intel_clear_scanline_wait(dev);
2292 }
2293
2294 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2295 {
2296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2297 int pipe = intel_crtc->pipe;
2298 int plane = intel_crtc->plane;
2299
2300 /* XXX: When our outputs are all unaware of DPMS modes other than off
2301 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2302 */
2303 switch (mode) {
2304 case DRM_MODE_DPMS_ON:
2305 case DRM_MODE_DPMS_STANDBY:
2306 case DRM_MODE_DPMS_SUSPEND:
2307 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2308 ironlake_crtc_enable(crtc);
2309 break;
2310
2311 case DRM_MODE_DPMS_OFF:
2312 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2313 ironlake_crtc_disable(crtc);
2314 break;
2315 }
2316 }
2317
2318 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2319 {
2320 if (!enable && intel_crtc->overlay) {
2321 struct drm_device *dev = intel_crtc->base.dev;
2322
2323 mutex_lock(&dev->struct_mutex);
2324 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2325 mutex_unlock(&dev->struct_mutex);
2326 }
2327
2328 /* Let userspace switch the overlay on again. In most cases userspace
2329 * has to recompute where to put it anyway.
2330 */
2331 }
2332
2333 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2334 {
2335 struct drm_device *dev = crtc->dev;
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2338 int pipe = intel_crtc->pipe;
2339 int plane = intel_crtc->plane;
2340 u32 reg, temp;
2341
2342 if (intel_crtc->active)
2343 return;
2344
2345 intel_crtc->active = true;
2346 intel_update_watermarks(dev);
2347
2348 /* Enable the DPLL */
2349 reg = DPLL(pipe);
2350 temp = I915_READ(reg);
2351 if ((temp & DPLL_VCO_ENABLE) == 0) {
2352 I915_WRITE(reg, temp);
2353
2354 /* Wait for the clocks to stabilize. */
2355 POSTING_READ(reg);
2356 udelay(150);
2357
2358 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2359
2360 /* Wait for the clocks to stabilize. */
2361 POSTING_READ(reg);
2362 udelay(150);
2363
2364 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2365
2366 /* Wait for the clocks to stabilize. */
2367 POSTING_READ(reg);
2368 udelay(150);
2369 }
2370
2371 /* Enable the pipe */
2372 reg = PIPECONF(pipe);
2373 temp = I915_READ(reg);
2374 if ((temp & PIPECONF_ENABLE) == 0)
2375 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2376
2377 /* Enable the plane */
2378 reg = DSPCNTR(plane);
2379 temp = I915_READ(reg);
2380 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2381 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2382 intel_flush_display_plane(dev, plane);
2383 }
2384
2385 intel_crtc_load_lut(crtc);
2386 intel_update_fbc(dev);
2387
2388 /* Give the overlay scaler a chance to enable if it's on this pipe */
2389 intel_crtc_dpms_overlay(intel_crtc, true);
2390 intel_crtc_update_cursor(crtc, true);
2391 }
2392
2393 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2394 {
2395 struct drm_device *dev = crtc->dev;
2396 struct drm_i915_private *dev_priv = dev->dev_private;
2397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2398 int pipe = intel_crtc->pipe;
2399 int plane = intel_crtc->plane;
2400 u32 reg, temp;
2401
2402 if (!intel_crtc->active)
2403 return;
2404
2405 /* Give the overlay scaler a chance to disable if it's on this pipe */
2406 intel_crtc_wait_for_pending_flips(crtc);
2407 drm_vblank_off(dev, pipe);
2408 intel_crtc_dpms_overlay(intel_crtc, false);
2409 intel_crtc_update_cursor(crtc, false);
2410
2411 if (dev_priv->cfb_plane == plane &&
2412 dev_priv->display.disable_fbc)
2413 dev_priv->display.disable_fbc(dev);
2414
2415 /* Disable display plane */
2416 reg = DSPCNTR(plane);
2417 temp = I915_READ(reg);
2418 if (temp & DISPLAY_PLANE_ENABLE) {
2419 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2420 /* Flush the plane changes */
2421 intel_flush_display_plane(dev, plane);
2422
2423 /* Wait for vblank for the disable to take effect */
2424 if (IS_GEN2(dev))
2425 intel_wait_for_vblank(dev, pipe);
2426 }
2427
2428 /* Don't disable pipe A or pipe A PLLs if needed */
2429 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2430 goto done;
2431
2432 /* Next, disable display pipes */
2433 reg = PIPECONF(pipe);
2434 temp = I915_READ(reg);
2435 if (temp & PIPECONF_ENABLE) {
2436 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2437
2438 /* Wait for the pipe to turn off */
2439 POSTING_READ(reg);
2440 intel_wait_for_pipe_off(dev, pipe);
2441 }
2442
2443 reg = DPLL(pipe);
2444 temp = I915_READ(reg);
2445 if (temp & DPLL_VCO_ENABLE) {
2446 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2447
2448 /* Wait for the clocks to turn off. */
2449 POSTING_READ(reg);
2450 udelay(150);
2451 }
2452
2453 done:
2454 intel_crtc->active = false;
2455 intel_update_fbc(dev);
2456 intel_update_watermarks(dev);
2457 intel_clear_scanline_wait(dev);
2458 }
2459
2460 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2461 {
2462 /* XXX: When our outputs are all unaware of DPMS modes other than off
2463 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2464 */
2465 switch (mode) {
2466 case DRM_MODE_DPMS_ON:
2467 case DRM_MODE_DPMS_STANDBY:
2468 case DRM_MODE_DPMS_SUSPEND:
2469 i9xx_crtc_enable(crtc);
2470 break;
2471 case DRM_MODE_DPMS_OFF:
2472 i9xx_crtc_disable(crtc);
2473 break;
2474 }
2475 }
2476
2477 /**
2478 * Sets the power management mode of the pipe and plane.
2479 */
2480 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2481 {
2482 struct drm_device *dev = crtc->dev;
2483 struct drm_i915_private *dev_priv = dev->dev_private;
2484 struct drm_i915_master_private *master_priv;
2485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2486 int pipe = intel_crtc->pipe;
2487 bool enabled;
2488
2489 if (intel_crtc->dpms_mode == mode)
2490 return;
2491
2492 intel_crtc->dpms_mode = mode;
2493
2494 dev_priv->display.dpms(crtc, mode);
2495
2496 if (!dev->primary->master)
2497 return;
2498
2499 master_priv = dev->primary->master->driver_priv;
2500 if (!master_priv->sarea_priv)
2501 return;
2502
2503 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2504
2505 switch (pipe) {
2506 case 0:
2507 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2508 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2509 break;
2510 case 1:
2511 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2512 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2513 break;
2514 default:
2515 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2516 break;
2517 }
2518 }
2519
2520 static void intel_crtc_disable(struct drm_crtc *crtc)
2521 {
2522 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2523 struct drm_device *dev = crtc->dev;
2524
2525 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2526
2527 if (crtc->fb) {
2528 mutex_lock(&dev->struct_mutex);
2529 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2530 mutex_unlock(&dev->struct_mutex);
2531 }
2532 }
2533
2534 /* Prepare for a mode set.
2535 *
2536 * Note we could be a lot smarter here. We need to figure out which outputs
2537 * will be enabled, which disabled (in short, how the config will changes)
2538 * and perform the minimum necessary steps to accomplish that, e.g. updating
2539 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2540 * panel fitting is in the proper state, etc.
2541 */
2542 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2543 {
2544 i9xx_crtc_disable(crtc);
2545 }
2546
2547 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2548 {
2549 i9xx_crtc_enable(crtc);
2550 }
2551
2552 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2553 {
2554 ironlake_crtc_disable(crtc);
2555 }
2556
2557 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2558 {
2559 ironlake_crtc_enable(crtc);
2560 }
2561
2562 void intel_encoder_prepare (struct drm_encoder *encoder)
2563 {
2564 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2565 /* lvds has its own version of prepare see intel_lvds_prepare */
2566 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2567 }
2568
2569 void intel_encoder_commit (struct drm_encoder *encoder)
2570 {
2571 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2572 /* lvds has its own version of commit see intel_lvds_commit */
2573 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2574 }
2575
2576 void intel_encoder_destroy(struct drm_encoder *encoder)
2577 {
2578 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2579
2580 drm_encoder_cleanup(encoder);
2581 kfree(intel_encoder);
2582 }
2583
2584 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2585 struct drm_display_mode *mode,
2586 struct drm_display_mode *adjusted_mode)
2587 {
2588 struct drm_device *dev = crtc->dev;
2589
2590 if (HAS_PCH_SPLIT(dev)) {
2591 /* FDI link clock is fixed at 2.7G */
2592 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2593 return false;
2594 }
2595
2596 /* XXX some encoders set the crtcinfo, others don't.
2597 * Obviously we need some form of conflict resolution here...
2598 */
2599 if (adjusted_mode->crtc_htotal == 0)
2600 drm_mode_set_crtcinfo(adjusted_mode, 0);
2601
2602 return true;
2603 }
2604
2605 static int i945_get_display_clock_speed(struct drm_device *dev)
2606 {
2607 return 400000;
2608 }
2609
2610 static int i915_get_display_clock_speed(struct drm_device *dev)
2611 {
2612 return 333000;
2613 }
2614
2615 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2616 {
2617 return 200000;
2618 }
2619
2620 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2621 {
2622 u16 gcfgc = 0;
2623
2624 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2625
2626 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2627 return 133000;
2628 else {
2629 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2630 case GC_DISPLAY_CLOCK_333_MHZ:
2631 return 333000;
2632 default:
2633 case GC_DISPLAY_CLOCK_190_200_MHZ:
2634 return 190000;
2635 }
2636 }
2637 }
2638
2639 static int i865_get_display_clock_speed(struct drm_device *dev)
2640 {
2641 return 266000;
2642 }
2643
2644 static int i855_get_display_clock_speed(struct drm_device *dev)
2645 {
2646 u16 hpllcc = 0;
2647 /* Assume that the hardware is in the high speed state. This
2648 * should be the default.
2649 */
2650 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2651 case GC_CLOCK_133_200:
2652 case GC_CLOCK_100_200:
2653 return 200000;
2654 case GC_CLOCK_166_250:
2655 return 250000;
2656 case GC_CLOCK_100_133:
2657 return 133000;
2658 }
2659
2660 /* Shouldn't happen */
2661 return 0;
2662 }
2663
2664 static int i830_get_display_clock_speed(struct drm_device *dev)
2665 {
2666 return 133000;
2667 }
2668
2669 struct fdi_m_n {
2670 u32 tu;
2671 u32 gmch_m;
2672 u32 gmch_n;
2673 u32 link_m;
2674 u32 link_n;
2675 };
2676
2677 static void
2678 fdi_reduce_ratio(u32 *num, u32 *den)
2679 {
2680 while (*num > 0xffffff || *den > 0xffffff) {
2681 *num >>= 1;
2682 *den >>= 1;
2683 }
2684 }
2685
2686 #define DATA_N 0x800000
2687 #define LINK_N 0x80000
2688
2689 static void
2690 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2691 int link_clock, struct fdi_m_n *m_n)
2692 {
2693 u64 temp;
2694
2695 m_n->tu = 64; /* default size */
2696
2697 temp = (u64) DATA_N * pixel_clock;
2698 temp = div_u64(temp, link_clock);
2699 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2700 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2701 m_n->gmch_n = DATA_N;
2702 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2703
2704 temp = (u64) LINK_N * pixel_clock;
2705 m_n->link_m = div_u64(temp, link_clock);
2706 m_n->link_n = LINK_N;
2707 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2708 }
2709
2710
2711 struct intel_watermark_params {
2712 unsigned long fifo_size;
2713 unsigned long max_wm;
2714 unsigned long default_wm;
2715 unsigned long guard_size;
2716 unsigned long cacheline_size;
2717 };
2718
2719 /* Pineview has different values for various configs */
2720 static struct intel_watermark_params pineview_display_wm = {
2721 PINEVIEW_DISPLAY_FIFO,
2722 PINEVIEW_MAX_WM,
2723 PINEVIEW_DFT_WM,
2724 PINEVIEW_GUARD_WM,
2725 PINEVIEW_FIFO_LINE_SIZE
2726 };
2727 static struct intel_watermark_params pineview_display_hplloff_wm = {
2728 PINEVIEW_DISPLAY_FIFO,
2729 PINEVIEW_MAX_WM,
2730 PINEVIEW_DFT_HPLLOFF_WM,
2731 PINEVIEW_GUARD_WM,
2732 PINEVIEW_FIFO_LINE_SIZE
2733 };
2734 static struct intel_watermark_params pineview_cursor_wm = {
2735 PINEVIEW_CURSOR_FIFO,
2736 PINEVIEW_CURSOR_MAX_WM,
2737 PINEVIEW_CURSOR_DFT_WM,
2738 PINEVIEW_CURSOR_GUARD_WM,
2739 PINEVIEW_FIFO_LINE_SIZE,
2740 };
2741 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2742 PINEVIEW_CURSOR_FIFO,
2743 PINEVIEW_CURSOR_MAX_WM,
2744 PINEVIEW_CURSOR_DFT_WM,
2745 PINEVIEW_CURSOR_GUARD_WM,
2746 PINEVIEW_FIFO_LINE_SIZE
2747 };
2748 static struct intel_watermark_params g4x_wm_info = {
2749 G4X_FIFO_SIZE,
2750 G4X_MAX_WM,
2751 G4X_MAX_WM,
2752 2,
2753 G4X_FIFO_LINE_SIZE,
2754 };
2755 static struct intel_watermark_params g4x_cursor_wm_info = {
2756 I965_CURSOR_FIFO,
2757 I965_CURSOR_MAX_WM,
2758 I965_CURSOR_DFT_WM,
2759 2,
2760 G4X_FIFO_LINE_SIZE,
2761 };
2762 static struct intel_watermark_params i965_cursor_wm_info = {
2763 I965_CURSOR_FIFO,
2764 I965_CURSOR_MAX_WM,
2765 I965_CURSOR_DFT_WM,
2766 2,
2767 I915_FIFO_LINE_SIZE,
2768 };
2769 static struct intel_watermark_params i945_wm_info = {
2770 I945_FIFO_SIZE,
2771 I915_MAX_WM,
2772 1,
2773 2,
2774 I915_FIFO_LINE_SIZE
2775 };
2776 static struct intel_watermark_params i915_wm_info = {
2777 I915_FIFO_SIZE,
2778 I915_MAX_WM,
2779 1,
2780 2,
2781 I915_FIFO_LINE_SIZE
2782 };
2783 static struct intel_watermark_params i855_wm_info = {
2784 I855GM_FIFO_SIZE,
2785 I915_MAX_WM,
2786 1,
2787 2,
2788 I830_FIFO_LINE_SIZE
2789 };
2790 static struct intel_watermark_params i830_wm_info = {
2791 I830_FIFO_SIZE,
2792 I915_MAX_WM,
2793 1,
2794 2,
2795 I830_FIFO_LINE_SIZE
2796 };
2797
2798 static struct intel_watermark_params ironlake_display_wm_info = {
2799 ILK_DISPLAY_FIFO,
2800 ILK_DISPLAY_MAXWM,
2801 ILK_DISPLAY_DFTWM,
2802 2,
2803 ILK_FIFO_LINE_SIZE
2804 };
2805
2806 static struct intel_watermark_params ironlake_cursor_wm_info = {
2807 ILK_CURSOR_FIFO,
2808 ILK_CURSOR_MAXWM,
2809 ILK_CURSOR_DFTWM,
2810 2,
2811 ILK_FIFO_LINE_SIZE
2812 };
2813
2814 static struct intel_watermark_params ironlake_display_srwm_info = {
2815 ILK_DISPLAY_SR_FIFO,
2816 ILK_DISPLAY_MAX_SRWM,
2817 ILK_DISPLAY_DFT_SRWM,
2818 2,
2819 ILK_FIFO_LINE_SIZE
2820 };
2821
2822 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2823 ILK_CURSOR_SR_FIFO,
2824 ILK_CURSOR_MAX_SRWM,
2825 ILK_CURSOR_DFT_SRWM,
2826 2,
2827 ILK_FIFO_LINE_SIZE
2828 };
2829
2830 /**
2831 * intel_calculate_wm - calculate watermark level
2832 * @clock_in_khz: pixel clock
2833 * @wm: chip FIFO params
2834 * @pixel_size: display pixel size
2835 * @latency_ns: memory latency for the platform
2836 *
2837 * Calculate the watermark level (the level at which the display plane will
2838 * start fetching from memory again). Each chip has a different display
2839 * FIFO size and allocation, so the caller needs to figure that out and pass
2840 * in the correct intel_watermark_params structure.
2841 *
2842 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2843 * on the pixel size. When it reaches the watermark level, it'll start
2844 * fetching FIFO line sized based chunks from memory until the FIFO fills
2845 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2846 * will occur, and a display engine hang could result.
2847 */
2848 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2849 struct intel_watermark_params *wm,
2850 int pixel_size,
2851 unsigned long latency_ns)
2852 {
2853 long entries_required, wm_size;
2854
2855 /*
2856 * Note: we need to make sure we don't overflow for various clock &
2857 * latency values.
2858 * clocks go from a few thousand to several hundred thousand.
2859 * latency is usually a few thousand
2860 */
2861 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2862 1000;
2863 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2864
2865 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2866
2867 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2868
2869 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2870
2871 /* Don't promote wm_size to unsigned... */
2872 if (wm_size > (long)wm->max_wm)
2873 wm_size = wm->max_wm;
2874 if (wm_size <= 0)
2875 wm_size = wm->default_wm;
2876 return wm_size;
2877 }
2878
2879 struct cxsr_latency {
2880 int is_desktop;
2881 int is_ddr3;
2882 unsigned long fsb_freq;
2883 unsigned long mem_freq;
2884 unsigned long display_sr;
2885 unsigned long display_hpll_disable;
2886 unsigned long cursor_sr;
2887 unsigned long cursor_hpll_disable;
2888 };
2889
2890 static const struct cxsr_latency cxsr_latency_table[] = {
2891 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2892 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2893 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2894 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2895 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2896
2897 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2898 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2899 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2900 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2901 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2902
2903 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2904 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2905 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2906 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2907 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2908
2909 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2910 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2911 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2912 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2913 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2914
2915 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2916 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2917 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2918 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2919 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2920
2921 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2922 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2923 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2924 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2925 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2926 };
2927
2928 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2929 int is_ddr3,
2930 int fsb,
2931 int mem)
2932 {
2933 const struct cxsr_latency *latency;
2934 int i;
2935
2936 if (fsb == 0 || mem == 0)
2937 return NULL;
2938
2939 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2940 latency = &cxsr_latency_table[i];
2941 if (is_desktop == latency->is_desktop &&
2942 is_ddr3 == latency->is_ddr3 &&
2943 fsb == latency->fsb_freq && mem == latency->mem_freq)
2944 return latency;
2945 }
2946
2947 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2948
2949 return NULL;
2950 }
2951
2952 static void pineview_disable_cxsr(struct drm_device *dev)
2953 {
2954 struct drm_i915_private *dev_priv = dev->dev_private;
2955
2956 /* deactivate cxsr */
2957 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2958 }
2959
2960 /*
2961 * Latency for FIFO fetches is dependent on several factors:
2962 * - memory configuration (speed, channels)
2963 * - chipset
2964 * - current MCH state
2965 * It can be fairly high in some situations, so here we assume a fairly
2966 * pessimal value. It's a tradeoff between extra memory fetches (if we
2967 * set this value too high, the FIFO will fetch frequently to stay full)
2968 * and power consumption (set it too low to save power and we might see
2969 * FIFO underruns and display "flicker").
2970 *
2971 * A value of 5us seems to be a good balance; safe for very low end
2972 * platforms but not overly aggressive on lower latency configs.
2973 */
2974 static const int latency_ns = 5000;
2975
2976 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2977 {
2978 struct drm_i915_private *dev_priv = dev->dev_private;
2979 uint32_t dsparb = I915_READ(DSPARB);
2980 int size;
2981
2982 size = dsparb & 0x7f;
2983 if (plane)
2984 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2985
2986 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2987 plane ? "B" : "A", size);
2988
2989 return size;
2990 }
2991
2992 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2993 {
2994 struct drm_i915_private *dev_priv = dev->dev_private;
2995 uint32_t dsparb = I915_READ(DSPARB);
2996 int size;
2997
2998 size = dsparb & 0x1ff;
2999 if (plane)
3000 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3001 size >>= 1; /* Convert to cachelines */
3002
3003 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3004 plane ? "B" : "A", size);
3005
3006 return size;
3007 }
3008
3009 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3010 {
3011 struct drm_i915_private *dev_priv = dev->dev_private;
3012 uint32_t dsparb = I915_READ(DSPARB);
3013 int size;
3014
3015 size = dsparb & 0x7f;
3016 size >>= 2; /* Convert to cachelines */
3017
3018 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3019 plane ? "B" : "A",
3020 size);
3021
3022 return size;
3023 }
3024
3025 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3026 {
3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 uint32_t dsparb = I915_READ(DSPARB);
3029 int size;
3030
3031 size = dsparb & 0x7f;
3032 size >>= 1; /* Convert to cachelines */
3033
3034 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3035 plane ? "B" : "A", size);
3036
3037 return size;
3038 }
3039
3040 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3041 int planeb_clock, int sr_hdisplay, int unused,
3042 int pixel_size)
3043 {
3044 struct drm_i915_private *dev_priv = dev->dev_private;
3045 const struct cxsr_latency *latency;
3046 u32 reg;
3047 unsigned long wm;
3048 int sr_clock;
3049
3050 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3051 dev_priv->fsb_freq, dev_priv->mem_freq);
3052 if (!latency) {
3053 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3054 pineview_disable_cxsr(dev);
3055 return;
3056 }
3057
3058 if (!planea_clock || !planeb_clock) {
3059 sr_clock = planea_clock ? planea_clock : planeb_clock;
3060
3061 /* Display SR */
3062 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3063 pixel_size, latency->display_sr);
3064 reg = I915_READ(DSPFW1);
3065 reg &= ~DSPFW_SR_MASK;
3066 reg |= wm << DSPFW_SR_SHIFT;
3067 I915_WRITE(DSPFW1, reg);
3068 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3069
3070 /* cursor SR */
3071 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3072 pixel_size, latency->cursor_sr);
3073 reg = I915_READ(DSPFW3);
3074 reg &= ~DSPFW_CURSOR_SR_MASK;
3075 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3076 I915_WRITE(DSPFW3, reg);
3077
3078 /* Display HPLL off SR */
3079 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3080 pixel_size, latency->display_hpll_disable);
3081 reg = I915_READ(DSPFW3);
3082 reg &= ~DSPFW_HPLL_SR_MASK;
3083 reg |= wm & DSPFW_HPLL_SR_MASK;
3084 I915_WRITE(DSPFW3, reg);
3085
3086 /* cursor HPLL off SR */
3087 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3088 pixel_size, latency->cursor_hpll_disable);
3089 reg = I915_READ(DSPFW3);
3090 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3091 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3092 I915_WRITE(DSPFW3, reg);
3093 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3094
3095 /* activate cxsr */
3096 I915_WRITE(DSPFW3,
3097 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3098 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3099 } else {
3100 pineview_disable_cxsr(dev);
3101 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3102 }
3103 }
3104
3105 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3106 int planeb_clock, int sr_hdisplay, int sr_htotal,
3107 int pixel_size)
3108 {
3109 struct drm_i915_private *dev_priv = dev->dev_private;
3110 int total_size, cacheline_size;
3111 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3112 struct intel_watermark_params planea_params, planeb_params;
3113 unsigned long line_time_us;
3114 int sr_clock, sr_entries = 0, entries_required;
3115
3116 /* Create copies of the base settings for each pipe */
3117 planea_params = planeb_params = g4x_wm_info;
3118
3119 /* Grab a couple of global values before we overwrite them */
3120 total_size = planea_params.fifo_size;
3121 cacheline_size = planea_params.cacheline_size;
3122
3123 /*
3124 * Note: we need to make sure we don't overflow for various clock &
3125 * latency values.
3126 * clocks go from a few thousand to several hundred thousand.
3127 * latency is usually a few thousand
3128 */
3129 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3130 1000;
3131 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3132 planea_wm = entries_required + planea_params.guard_size;
3133
3134 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3135 1000;
3136 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3137 planeb_wm = entries_required + planeb_params.guard_size;
3138
3139 cursora_wm = cursorb_wm = 16;
3140 cursor_sr = 32;
3141
3142 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3143
3144 /* Calc sr entries for one plane configs */
3145 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3146 /* self-refresh has much higher latency */
3147 static const int sr_latency_ns = 12000;
3148
3149 sr_clock = planea_clock ? planea_clock : planeb_clock;
3150 line_time_us = ((sr_htotal * 1000) / sr_clock);
3151
3152 /* Use ns/us then divide to preserve precision */
3153 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3154 pixel_size * sr_hdisplay;
3155 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3156
3157 entries_required = (((sr_latency_ns / line_time_us) +
3158 1000) / 1000) * pixel_size * 64;
3159 entries_required = DIV_ROUND_UP(entries_required,
3160 g4x_cursor_wm_info.cacheline_size);
3161 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3162
3163 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3164 cursor_sr = g4x_cursor_wm_info.max_wm;
3165 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3166 "cursor %d\n", sr_entries, cursor_sr);
3167
3168 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3169 } else {
3170 /* Turn off self refresh if both pipes are enabled */
3171 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3172 & ~FW_BLC_SELF_EN);
3173 }
3174
3175 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3176 planea_wm, planeb_wm, sr_entries);
3177
3178 planea_wm &= 0x3f;
3179 planeb_wm &= 0x3f;
3180
3181 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3182 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3183 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3184 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3185 (cursora_wm << DSPFW_CURSORA_SHIFT));
3186 /* HPLL off in SR has some issues on G4x... disable it */
3187 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3188 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3189 }
3190
3191 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3192 int planeb_clock, int sr_hdisplay, int sr_htotal,
3193 int pixel_size)
3194 {
3195 struct drm_i915_private *dev_priv = dev->dev_private;
3196 unsigned long line_time_us;
3197 int sr_clock, sr_entries, srwm = 1;
3198 int cursor_sr = 16;
3199
3200 /* Calc sr entries for one plane configs */
3201 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3202 /* self-refresh has much higher latency */
3203 static const int sr_latency_ns = 12000;
3204
3205 sr_clock = planea_clock ? planea_clock : planeb_clock;
3206 line_time_us = ((sr_htotal * 1000) / sr_clock);
3207
3208 /* Use ns/us then divide to preserve precision */
3209 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3210 pixel_size * sr_hdisplay;
3211 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3212 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3213 srwm = I965_FIFO_SIZE - sr_entries;
3214 if (srwm < 0)
3215 srwm = 1;
3216 srwm &= 0x1ff;
3217
3218 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3219 pixel_size * 64;
3220 sr_entries = DIV_ROUND_UP(sr_entries,
3221 i965_cursor_wm_info.cacheline_size);
3222 cursor_sr = i965_cursor_wm_info.fifo_size -
3223 (sr_entries + i965_cursor_wm_info.guard_size);
3224
3225 if (cursor_sr > i965_cursor_wm_info.max_wm)
3226 cursor_sr = i965_cursor_wm_info.max_wm;
3227
3228 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3229 "cursor %d\n", srwm, cursor_sr);
3230
3231 if (IS_CRESTLINE(dev))
3232 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3233 } else {
3234 /* Turn off self refresh if both pipes are enabled */
3235 if (IS_CRESTLINE(dev))
3236 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3237 & ~FW_BLC_SELF_EN);
3238 }
3239
3240 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3241 srwm);
3242
3243 /* 965 has limitations... */
3244 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3245 (8 << 0));
3246 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3247 /* update cursor SR watermark */
3248 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3249 }
3250
3251 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3252 int planeb_clock, int sr_hdisplay, int sr_htotal,
3253 int pixel_size)
3254 {
3255 struct drm_i915_private *dev_priv = dev->dev_private;
3256 uint32_t fwater_lo;
3257 uint32_t fwater_hi;
3258 int total_size, cacheline_size, cwm, srwm = 1;
3259 int planea_wm, planeb_wm;
3260 struct intel_watermark_params planea_params, planeb_params;
3261 unsigned long line_time_us;
3262 int sr_clock, sr_entries = 0;
3263
3264 /* Create copies of the base settings for each pipe */
3265 if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3266 planea_params = planeb_params = i945_wm_info;
3267 else if (!IS_GEN2(dev))
3268 planea_params = planeb_params = i915_wm_info;
3269 else
3270 planea_params = planeb_params = i855_wm_info;
3271
3272 /* Grab a couple of global values before we overwrite them */
3273 total_size = planea_params.fifo_size;
3274 cacheline_size = planea_params.cacheline_size;
3275
3276 /* Update per-plane FIFO sizes */
3277 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3278 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3279
3280 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3281 pixel_size, latency_ns);
3282 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3283 pixel_size, latency_ns);
3284 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3285
3286 /*
3287 * Overlay gets an aggressive default since video jitter is bad.
3288 */
3289 cwm = 2;
3290
3291 /* Calc sr entries for one plane configs */
3292 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3293 (!planea_clock || !planeb_clock)) {
3294 /* self-refresh has much higher latency */
3295 static const int sr_latency_ns = 6000;
3296
3297 sr_clock = planea_clock ? planea_clock : planeb_clock;
3298 line_time_us = ((sr_htotal * 1000) / sr_clock);
3299
3300 /* Use ns/us then divide to preserve precision */
3301 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3302 pixel_size * sr_hdisplay;
3303 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3304 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3305 srwm = total_size - sr_entries;
3306 if (srwm < 0)
3307 srwm = 1;
3308
3309 if (IS_I945G(dev) || IS_I945GM(dev))
3310 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3311 else if (IS_I915GM(dev)) {
3312 /* 915M has a smaller SRWM field */
3313 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3314 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3315 }
3316 } else {
3317 /* Turn off self refresh if both pipes are enabled */
3318 if (IS_I945G(dev) || IS_I945GM(dev)) {
3319 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3320 & ~FW_BLC_SELF_EN);
3321 } else if (IS_I915GM(dev)) {
3322 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3323 }
3324 }
3325
3326 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3327 planea_wm, planeb_wm, cwm, srwm);
3328
3329 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3330 fwater_hi = (cwm & 0x1f);
3331
3332 /* Set request length to 8 cachelines per fetch */
3333 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3334 fwater_hi = fwater_hi | (1 << 8);
3335
3336 I915_WRITE(FW_BLC, fwater_lo);
3337 I915_WRITE(FW_BLC2, fwater_hi);
3338 }
3339
3340 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3341 int unused2, int unused3, int pixel_size)
3342 {
3343 struct drm_i915_private *dev_priv = dev->dev_private;
3344 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3345 int planea_wm;
3346
3347 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3348
3349 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3350 pixel_size, latency_ns);
3351 fwater_lo |= (3<<8) | planea_wm;
3352
3353 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3354
3355 I915_WRITE(FW_BLC, fwater_lo);
3356 }
3357
3358 #define ILK_LP0_PLANE_LATENCY 700
3359 #define ILK_LP0_CURSOR_LATENCY 1300
3360
3361 static bool ironlake_compute_wm0(struct drm_device *dev,
3362 int pipe,
3363 int *plane_wm,
3364 int *cursor_wm)
3365 {
3366 struct drm_crtc *crtc;
3367 int htotal, hdisplay, clock, pixel_size = 0;
3368 int line_time_us, line_count, entries;
3369
3370 crtc = intel_get_crtc_for_pipe(dev, pipe);
3371 if (crtc->fb == NULL || !crtc->enabled)
3372 return false;
3373
3374 htotal = crtc->mode.htotal;
3375 hdisplay = crtc->mode.hdisplay;
3376 clock = crtc->mode.clock;
3377 pixel_size = crtc->fb->bits_per_pixel / 8;
3378
3379 /* Use the small buffer method to calculate plane watermark */
3380 entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3381 entries = DIV_ROUND_UP(entries,
3382 ironlake_display_wm_info.cacheline_size);
3383 *plane_wm = entries + ironlake_display_wm_info.guard_size;
3384 if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3385 *plane_wm = ironlake_display_wm_info.max_wm;
3386
3387 /* Use the large buffer method to calculate cursor watermark */
3388 line_time_us = ((htotal * 1000) / clock);
3389 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3390 entries = line_count * 64 * pixel_size;
3391 entries = DIV_ROUND_UP(entries,
3392 ironlake_cursor_wm_info.cacheline_size);
3393 *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3394 if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3395 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3396
3397 return true;
3398 }
3399
3400 static void ironlake_update_wm(struct drm_device *dev,
3401 int planea_clock, int planeb_clock,
3402 int sr_hdisplay, int sr_htotal,
3403 int pixel_size)
3404 {
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 int plane_wm, cursor_wm, enabled;
3407 int tmp;
3408
3409 enabled = 0;
3410 if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3411 I915_WRITE(WM0_PIPEA_ILK,
3412 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3413 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3414 " plane %d, " "cursor: %d\n",
3415 plane_wm, cursor_wm);
3416 enabled++;
3417 }
3418
3419 if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3420 I915_WRITE(WM0_PIPEB_ILK,
3421 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3422 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3423 " plane %d, cursor: %d\n",
3424 plane_wm, cursor_wm);
3425 enabled++;
3426 }
3427
3428 /*
3429 * Calculate and update the self-refresh watermark only when one
3430 * display plane is used.
3431 */
3432 tmp = 0;
3433 if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3434 unsigned long line_time_us;
3435 int small, large, plane_fbc;
3436 int sr_clock, entries;
3437 int line_count, line_size;
3438 /* Read the self-refresh latency. The unit is 0.5us */
3439 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3440
3441 sr_clock = planea_clock ? planea_clock : planeb_clock;
3442 line_time_us = (sr_htotal * 1000) / sr_clock;
3443
3444 /* Use ns/us then divide to preserve precision */
3445 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3446 / 1000;
3447 line_size = sr_hdisplay * pixel_size;
3448
3449 /* Use the minimum of the small and large buffer method for primary */
3450 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3451 large = line_count * line_size;
3452
3453 entries = DIV_ROUND_UP(min(small, large),
3454 ironlake_display_srwm_info.cacheline_size);
3455
3456 plane_fbc = entries * 64;
3457 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3458
3459 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3460 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3461 plane_wm = ironlake_display_srwm_info.max_wm;
3462
3463 /* calculate the self-refresh watermark for display cursor */
3464 entries = line_count * pixel_size * 64;
3465 entries = DIV_ROUND_UP(entries,
3466 ironlake_cursor_srwm_info.cacheline_size);
3467
3468 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3469 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3470 cursor_wm = ironlake_cursor_srwm_info.max_wm;
3471
3472 /* configure watermark and enable self-refresh */
3473 tmp = (WM1_LP_SR_EN |
3474 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3475 (plane_fbc << WM1_LP_FBC_SHIFT) |
3476 (plane_wm << WM1_LP_SR_SHIFT) |
3477 cursor_wm);
3478 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3479 " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3480 }
3481 I915_WRITE(WM1_LP_ILK, tmp);
3482 /* XXX setup WM2 and WM3 */
3483 }
3484
3485 /**
3486 * intel_update_watermarks - update FIFO watermark values based on current modes
3487 *
3488 * Calculate watermark values for the various WM regs based on current mode
3489 * and plane configuration.
3490 *
3491 * There are several cases to deal with here:
3492 * - normal (i.e. non-self-refresh)
3493 * - self-refresh (SR) mode
3494 * - lines are large relative to FIFO size (buffer can hold up to 2)
3495 * - lines are small relative to FIFO size (buffer can hold more than 2
3496 * lines), so need to account for TLB latency
3497 *
3498 * The normal calculation is:
3499 * watermark = dotclock * bytes per pixel * latency
3500 * where latency is platform & configuration dependent (we assume pessimal
3501 * values here).
3502 *
3503 * The SR calculation is:
3504 * watermark = (trunc(latency/line time)+1) * surface width *
3505 * bytes per pixel
3506 * where
3507 * line time = htotal / dotclock
3508 * surface width = hdisplay for normal plane and 64 for cursor
3509 * and latency is assumed to be high, as above.
3510 *
3511 * The final value programmed to the register should always be rounded up,
3512 * and include an extra 2 entries to account for clock crossings.
3513 *
3514 * We don't use the sprite, so we can ignore that. And on Crestline we have
3515 * to set the non-SR watermarks to 8.
3516 */
3517 static void intel_update_watermarks(struct drm_device *dev)
3518 {
3519 struct drm_i915_private *dev_priv = dev->dev_private;
3520 struct drm_crtc *crtc;
3521 int sr_hdisplay = 0;
3522 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3523 int enabled = 0, pixel_size = 0;
3524 int sr_htotal = 0;
3525
3526 if (!dev_priv->display.update_wm)
3527 return;
3528
3529 /* Get the clock config from both planes */
3530 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3532 if (intel_crtc->active) {
3533 enabled++;
3534 if (intel_crtc->plane == 0) {
3535 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3536 intel_crtc->pipe, crtc->mode.clock);
3537 planea_clock = crtc->mode.clock;
3538 } else {
3539 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3540 intel_crtc->pipe, crtc->mode.clock);
3541 planeb_clock = crtc->mode.clock;
3542 }
3543 sr_hdisplay = crtc->mode.hdisplay;
3544 sr_clock = crtc->mode.clock;
3545 sr_htotal = crtc->mode.htotal;
3546 if (crtc->fb)
3547 pixel_size = crtc->fb->bits_per_pixel / 8;
3548 else
3549 pixel_size = 4; /* by default */
3550 }
3551 }
3552
3553 if (enabled <= 0)
3554 return;
3555
3556 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3557 sr_hdisplay, sr_htotal, pixel_size);
3558 }
3559
3560 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3561 struct drm_display_mode *mode,
3562 struct drm_display_mode *adjusted_mode,
3563 int x, int y,
3564 struct drm_framebuffer *old_fb)
3565 {
3566 struct drm_device *dev = crtc->dev;
3567 struct drm_i915_private *dev_priv = dev->dev_private;
3568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3569 int pipe = intel_crtc->pipe;
3570 int plane = intel_crtc->plane;
3571 u32 fp_reg, dpll_reg;
3572 int refclk, num_connectors = 0;
3573 intel_clock_t clock, reduced_clock;
3574 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3575 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3576 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3577 struct intel_encoder *has_edp_encoder = NULL;
3578 struct drm_mode_config *mode_config = &dev->mode_config;
3579 struct intel_encoder *encoder;
3580 const intel_limit_t *limit;
3581 int ret;
3582 struct fdi_m_n m_n = {0};
3583 u32 reg, temp;
3584 int target_clock;
3585
3586 drm_vblank_pre_modeset(dev, pipe);
3587
3588 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3589 if (encoder->base.crtc != crtc)
3590 continue;
3591
3592 switch (encoder->type) {
3593 case INTEL_OUTPUT_LVDS:
3594 is_lvds = true;
3595 break;
3596 case INTEL_OUTPUT_SDVO:
3597 case INTEL_OUTPUT_HDMI:
3598 is_sdvo = true;
3599 if (encoder->needs_tv_clock)
3600 is_tv = true;
3601 break;
3602 case INTEL_OUTPUT_DVO:
3603 is_dvo = true;
3604 break;
3605 case INTEL_OUTPUT_TVOUT:
3606 is_tv = true;
3607 break;
3608 case INTEL_OUTPUT_ANALOG:
3609 is_crt = true;
3610 break;
3611 case INTEL_OUTPUT_DISPLAYPORT:
3612 is_dp = true;
3613 break;
3614 case INTEL_OUTPUT_EDP:
3615 has_edp_encoder = encoder;
3616 break;
3617 }
3618
3619 num_connectors++;
3620 }
3621
3622 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3623 refclk = dev_priv->lvds_ssc_freq * 1000;
3624 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3625 refclk / 1000);
3626 } else if (!IS_GEN2(dev)) {
3627 refclk = 96000;
3628 if (HAS_PCH_SPLIT(dev) &&
3629 (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
3630 refclk = 120000; /* 120Mhz refclk */
3631 } else {
3632 refclk = 48000;
3633 }
3634
3635 /*
3636 * Returns a set of divisors for the desired target clock with the given
3637 * refclk, or FALSE. The returned values represent the clock equation:
3638 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3639 */
3640 limit = intel_limit(crtc);
3641 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3642 if (!ok) {
3643 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3644 drm_vblank_post_modeset(dev, pipe);
3645 return -EINVAL;
3646 }
3647
3648 /* Ensure that the cursor is valid for the new mode before changing... */
3649 intel_crtc_update_cursor(crtc, true);
3650
3651 if (is_lvds && dev_priv->lvds_downclock_avail) {
3652 has_reduced_clock = limit->find_pll(limit, crtc,
3653 dev_priv->lvds_downclock,
3654 refclk,
3655 &reduced_clock);
3656 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3657 /*
3658 * If the different P is found, it means that we can't
3659 * switch the display clock by using the FP0/FP1.
3660 * In such case we will disable the LVDS downclock
3661 * feature.
3662 */
3663 DRM_DEBUG_KMS("Different P is found for "
3664 "LVDS clock/downclock\n");
3665 has_reduced_clock = 0;
3666 }
3667 }
3668 /* SDVO TV has fixed PLL values depend on its clock range,
3669 this mirrors vbios setting. */
3670 if (is_sdvo && is_tv) {
3671 if (adjusted_mode->clock >= 100000
3672 && adjusted_mode->clock < 140500) {
3673 clock.p1 = 2;
3674 clock.p2 = 10;
3675 clock.n = 3;
3676 clock.m1 = 16;
3677 clock.m2 = 8;
3678 } else if (adjusted_mode->clock >= 140500
3679 && adjusted_mode->clock <= 200000) {
3680 clock.p1 = 1;
3681 clock.p2 = 10;
3682 clock.n = 6;
3683 clock.m1 = 12;
3684 clock.m2 = 8;
3685 }
3686 }
3687
3688 /* FDI link */
3689 if (HAS_PCH_SPLIT(dev)) {
3690 int lane = 0, link_bw, bpp;
3691 /* CPU eDP doesn't require FDI link, so just set DP M/N
3692 according to current link config */
3693 if (has_edp_encoder && !intel_encoder_is_pch_edp(&encoder->base)) {
3694 target_clock = mode->clock;
3695 intel_edp_link_config(has_edp_encoder,
3696 &lane, &link_bw);
3697 } else {
3698 /* [e]DP over FDI requires target mode clock
3699 instead of link clock */
3700 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3701 target_clock = mode->clock;
3702 else
3703 target_clock = adjusted_mode->clock;
3704
3705 /* FDI is a binary signal running at ~2.7GHz, encoding
3706 * each output octet as 10 bits. The actual frequency
3707 * is stored as a divider into a 100MHz clock, and the
3708 * mode pixel clock is stored in units of 1KHz.
3709 * Hence the bw of each lane in terms of the mode signal
3710 * is:
3711 */
3712 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3713 }
3714
3715 /* determine panel color depth */
3716 temp = I915_READ(PIPECONF(pipe));
3717 temp &= ~PIPE_BPC_MASK;
3718 if (is_lvds) {
3719 /* the BPC will be 6 if it is 18-bit LVDS panel */
3720 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3721 temp |= PIPE_8BPC;
3722 else
3723 temp |= PIPE_6BPC;
3724 } else if (has_edp_encoder) {
3725 switch (dev_priv->edp.bpp/3) {
3726 case 8:
3727 temp |= PIPE_8BPC;
3728 break;
3729 case 10:
3730 temp |= PIPE_10BPC;
3731 break;
3732 case 6:
3733 temp |= PIPE_6BPC;
3734 break;
3735 case 12:
3736 temp |= PIPE_12BPC;
3737 break;
3738 }
3739 } else
3740 temp |= PIPE_8BPC;
3741 I915_WRITE(PIPECONF(pipe), temp);
3742
3743 switch (temp & PIPE_BPC_MASK) {
3744 case PIPE_8BPC:
3745 bpp = 24;
3746 break;
3747 case PIPE_10BPC:
3748 bpp = 30;
3749 break;
3750 case PIPE_6BPC:
3751 bpp = 18;
3752 break;
3753 case PIPE_12BPC:
3754 bpp = 36;
3755 break;
3756 default:
3757 DRM_ERROR("unknown pipe bpc value\n");
3758 bpp = 24;
3759 }
3760
3761 if (!lane) {
3762 /*
3763 * Account for spread spectrum to avoid
3764 * oversubscribing the link. Max center spread
3765 * is 2.5%; use 5% for safety's sake.
3766 */
3767 u32 bps = target_clock * bpp * 21 / 20;
3768 lane = bps / (link_bw * 8) + 1;
3769 }
3770
3771 intel_crtc->fdi_lanes = lane;
3772
3773 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3774 }
3775
3776 /* Ironlake: try to setup display ref clock before DPLL
3777 * enabling. This is only under driver's control after
3778 * PCH B stepping, previous chipset stepping should be
3779 * ignoring this setting.
3780 */
3781 if (HAS_PCH_SPLIT(dev)) {
3782 temp = I915_READ(PCH_DREF_CONTROL);
3783 /* Always enable nonspread source */
3784 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3785 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3786 temp &= ~DREF_SSC_SOURCE_MASK;
3787 temp |= DREF_SSC_SOURCE_ENABLE;
3788 I915_WRITE(PCH_DREF_CONTROL, temp);
3789
3790 POSTING_READ(PCH_DREF_CONTROL);
3791 udelay(200);
3792
3793 if (has_edp_encoder) {
3794 if (dev_priv->lvds_use_ssc) {
3795 temp |= DREF_SSC1_ENABLE;
3796 I915_WRITE(PCH_DREF_CONTROL, temp);
3797
3798 POSTING_READ(PCH_DREF_CONTROL);
3799 udelay(200);
3800 }
3801 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3802
3803 /* Enable CPU source on CPU attached eDP */
3804 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3805 if (dev_priv->lvds_use_ssc)
3806 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3807 else
3808 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3809 } else {
3810 /* Enable SSC on PCH eDP if needed */
3811 if (dev_priv->lvds_use_ssc) {
3812 DRM_ERROR("enabling SSC on PCH\n");
3813 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
3814 }
3815 }
3816 I915_WRITE(PCH_DREF_CONTROL, temp);
3817 POSTING_READ(PCH_DREF_CONTROL);
3818 udelay(200);
3819 }
3820 }
3821
3822 if (IS_PINEVIEW(dev)) {
3823 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3824 if (has_reduced_clock)
3825 fp2 = (1 << reduced_clock.n) << 16 |
3826 reduced_clock.m1 << 8 | reduced_clock.m2;
3827 } else {
3828 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3829 if (has_reduced_clock)
3830 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3831 reduced_clock.m2;
3832 }
3833
3834 dpll = 0;
3835 if (!HAS_PCH_SPLIT(dev))
3836 dpll = DPLL_VGA_MODE_DIS;
3837
3838 if (!IS_GEN2(dev)) {
3839 if (is_lvds)
3840 dpll |= DPLLB_MODE_LVDS;
3841 else
3842 dpll |= DPLLB_MODE_DAC_SERIAL;
3843 if (is_sdvo) {
3844 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3845 if (pixel_multiplier > 1) {
3846 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3847 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3848 else if (HAS_PCH_SPLIT(dev))
3849 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3850 }
3851 dpll |= DPLL_DVO_HIGH_SPEED;
3852 }
3853 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3854 dpll |= DPLL_DVO_HIGH_SPEED;
3855
3856 /* compute bitmask from p1 value */
3857 if (IS_PINEVIEW(dev))
3858 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3859 else {
3860 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3861 /* also FPA1 */
3862 if (HAS_PCH_SPLIT(dev))
3863 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3864 if (IS_G4X(dev) && has_reduced_clock)
3865 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3866 }
3867 switch (clock.p2) {
3868 case 5:
3869 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3870 break;
3871 case 7:
3872 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3873 break;
3874 case 10:
3875 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3876 break;
3877 case 14:
3878 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3879 break;
3880 }
3881 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
3882 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3883 } else {
3884 if (is_lvds) {
3885 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3886 } else {
3887 if (clock.p1 == 2)
3888 dpll |= PLL_P1_DIVIDE_BY_TWO;
3889 else
3890 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3891 if (clock.p2 == 4)
3892 dpll |= PLL_P2_DIVIDE_BY_4;
3893 }
3894 }
3895
3896 if (is_sdvo && is_tv)
3897 dpll |= PLL_REF_INPUT_TVCLKINBC;
3898 else if (is_tv)
3899 /* XXX: just matching BIOS for now */
3900 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3901 dpll |= 3;
3902 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3903 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3904 else
3905 dpll |= PLL_REF_INPUT_DREFCLK;
3906
3907 /* setup pipeconf */
3908 pipeconf = I915_READ(PIPECONF(pipe));
3909
3910 /* Set up the display plane register */
3911 dspcntr = DISPPLANE_GAMMA_ENABLE;
3912
3913 /* Ironlake's plane is forced to pipe, bit 24 is to
3914 enable color space conversion */
3915 if (!HAS_PCH_SPLIT(dev)) {
3916 if (pipe == 0)
3917 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3918 else
3919 dspcntr |= DISPPLANE_SEL_PIPE_B;
3920 }
3921
3922 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3923 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3924 * core speed.
3925 *
3926 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3927 * pipe == 0 check?
3928 */
3929 if (mode->clock >
3930 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3931 pipeconf |= PIPECONF_DOUBLE_WIDE;
3932 else
3933 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3934 }
3935
3936 dspcntr |= DISPLAY_PLANE_ENABLE;
3937 pipeconf |= PIPECONF_ENABLE;
3938 dpll |= DPLL_VCO_ENABLE;
3939
3940 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3941 drm_mode_debug_printmodeline(mode);
3942
3943 /* assign to Ironlake registers */
3944 if (HAS_PCH_SPLIT(dev)) {
3945 fp_reg = PCH_FP0(pipe);
3946 dpll_reg = PCH_DPLL(pipe);
3947 } else {
3948 fp_reg = FP0(pipe);
3949 dpll_reg = DPLL(pipe);
3950 }
3951
3952 /* PCH eDP needs FDI, but CPU eDP does not */
3953 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3954 I915_WRITE(fp_reg, fp);
3955 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3956
3957 POSTING_READ(dpll_reg);
3958 udelay(150);
3959 }
3960
3961 /* enable transcoder DPLL */
3962 if (HAS_PCH_CPT(dev)) {
3963 temp = I915_READ(PCH_DPLL_SEL);
3964 if (pipe == 0)
3965 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3966 else
3967 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3968 I915_WRITE(PCH_DPLL_SEL, temp);
3969
3970 POSTING_READ(PCH_DPLL_SEL);
3971 udelay(150);
3972 }
3973
3974 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3975 * This is an exception to the general rule that mode_set doesn't turn
3976 * things on.
3977 */
3978 if (is_lvds) {
3979 reg = LVDS;
3980 if (HAS_PCH_SPLIT(dev))
3981 reg = PCH_LVDS;
3982
3983 temp = I915_READ(reg);
3984 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3985 if (pipe == 1) {
3986 if (HAS_PCH_CPT(dev))
3987 temp |= PORT_TRANS_B_SEL_CPT;
3988 else
3989 temp |= LVDS_PIPEB_SELECT;
3990 } else {
3991 if (HAS_PCH_CPT(dev))
3992 temp &= ~PORT_TRANS_SEL_MASK;
3993 else
3994 temp &= ~LVDS_PIPEB_SELECT;
3995 }
3996 /* set the corresponsding LVDS_BORDER bit */
3997 temp |= dev_priv->lvds_border_bits;
3998 /* Set the B0-B3 data pairs corresponding to whether we're going to
3999 * set the DPLLs for dual-channel mode or not.
4000 */
4001 if (clock.p2 == 7)
4002 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4003 else
4004 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4005
4006 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4007 * appropriately here, but we need to look more thoroughly into how
4008 * panels behave in the two modes.
4009 */
4010 /* set the dithering flag on non-PCH LVDS as needed */
4011 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4012 if (dev_priv->lvds_dither)
4013 temp |= LVDS_ENABLE_DITHER;
4014 else
4015 temp &= ~LVDS_ENABLE_DITHER;
4016 }
4017 I915_WRITE(reg, temp);
4018 }
4019
4020 /* set the dithering flag and clear for anything other than a panel. */
4021 if (HAS_PCH_SPLIT(dev)) {
4022 pipeconf &= ~PIPECONF_DITHER_EN;
4023 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4024 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4025 pipeconf |= PIPECONF_DITHER_EN;
4026 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4027 }
4028 }
4029
4030 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4031 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4032 } else if (HAS_PCH_SPLIT(dev)) {
4033 /* For non-DP output, clear any trans DP clock recovery setting.*/
4034 if (pipe == 0) {
4035 I915_WRITE(TRANSA_DATA_M1, 0);
4036 I915_WRITE(TRANSA_DATA_N1, 0);
4037 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4038 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4039 } else {
4040 I915_WRITE(TRANSB_DATA_M1, 0);
4041 I915_WRITE(TRANSB_DATA_N1, 0);
4042 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4043 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4044 }
4045 }
4046
4047 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4048 I915_WRITE(fp_reg, fp);
4049 I915_WRITE(dpll_reg, dpll);
4050
4051 /* Wait for the clocks to stabilize. */
4052 POSTING_READ(dpll_reg);
4053 udelay(150);
4054
4055 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4056 temp = 0;
4057 if (is_sdvo) {
4058 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4059 if (temp > 1)
4060 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4061 else
4062 temp = 0;
4063 }
4064 I915_WRITE(DPLL_MD(pipe), temp);
4065 } else {
4066 /* write it again -- the BIOS does, after all */
4067 I915_WRITE(dpll_reg, dpll);
4068 }
4069
4070 /* Wait for the clocks to stabilize. */
4071 POSTING_READ(dpll_reg);
4072 udelay(150);
4073 }
4074
4075 intel_crtc->lowfreq_avail = false;
4076 if (is_lvds && has_reduced_clock && i915_powersave) {
4077 I915_WRITE(fp_reg + 4, fp2);
4078 intel_crtc->lowfreq_avail = true;
4079 if (HAS_PIPE_CXSR(dev)) {
4080 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4081 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4082 }
4083 } else {
4084 I915_WRITE(fp_reg + 4, fp);
4085 if (HAS_PIPE_CXSR(dev)) {
4086 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4087 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4088 }
4089 }
4090
4091 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4092 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4093 /* the chip adds 2 halflines automatically */
4094 adjusted_mode->crtc_vdisplay -= 1;
4095 adjusted_mode->crtc_vtotal -= 1;
4096 adjusted_mode->crtc_vblank_start -= 1;
4097 adjusted_mode->crtc_vblank_end -= 1;
4098 adjusted_mode->crtc_vsync_end -= 1;
4099 adjusted_mode->crtc_vsync_start -= 1;
4100 } else
4101 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4102
4103 I915_WRITE(HTOTAL(pipe),
4104 (adjusted_mode->crtc_hdisplay - 1) |
4105 ((adjusted_mode->crtc_htotal - 1) << 16));
4106 I915_WRITE(HBLANK(pipe),
4107 (adjusted_mode->crtc_hblank_start - 1) |
4108 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4109 I915_WRITE(HSYNC(pipe),
4110 (adjusted_mode->crtc_hsync_start - 1) |
4111 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4112
4113 I915_WRITE(VTOTAL(pipe),
4114 (adjusted_mode->crtc_vdisplay - 1) |
4115 ((adjusted_mode->crtc_vtotal - 1) << 16));
4116 I915_WRITE(VBLANK(pipe),
4117 (adjusted_mode->crtc_vblank_start - 1) |
4118 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4119 I915_WRITE(VSYNC(pipe),
4120 (adjusted_mode->crtc_vsync_start - 1) |
4121 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4122
4123 /* pipesrc and dspsize control the size that is scaled from,
4124 * which should always be the user's requested size.
4125 */
4126 if (!HAS_PCH_SPLIT(dev)) {
4127 I915_WRITE(DSPSIZE(plane),
4128 ((mode->vdisplay - 1) << 16) |
4129 (mode->hdisplay - 1));
4130 I915_WRITE(DSPPOS(plane), 0);
4131 }
4132 I915_WRITE(PIPESRC(pipe),
4133 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4134
4135 if (HAS_PCH_SPLIT(dev)) {
4136 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4137 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4138 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4139 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4140
4141 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4142 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4143 } else {
4144 /* enable FDI RX PLL too */
4145 reg = FDI_RX_CTL(pipe);
4146 temp = I915_READ(reg);
4147 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4148
4149 POSTING_READ(reg);
4150 udelay(200);
4151
4152 /* enable FDI TX PLL too */
4153 reg = FDI_TX_CTL(pipe);
4154 temp = I915_READ(reg);
4155 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4156
4157 /* enable FDI RX PCDCLK */
4158 reg = FDI_RX_CTL(pipe);
4159 temp = I915_READ(reg);
4160 I915_WRITE(reg, temp | FDI_PCDCLK);
4161
4162 POSTING_READ(reg);
4163 udelay(200);
4164 }
4165 }
4166
4167 I915_WRITE(PIPECONF(pipe), pipeconf);
4168 POSTING_READ(PIPECONF(pipe));
4169
4170 intel_wait_for_vblank(dev, pipe);
4171
4172 if (IS_IRONLAKE(dev)) {
4173 /* enable address swizzle for tiling buffer */
4174 temp = I915_READ(DISP_ARB_CTL);
4175 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4176 }
4177
4178 I915_WRITE(DSPCNTR(plane), dspcntr);
4179
4180 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4181
4182 intel_update_watermarks(dev);
4183
4184 drm_vblank_post_modeset(dev, pipe);
4185
4186 return ret;
4187 }
4188
4189 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4190 void intel_crtc_load_lut(struct drm_crtc *crtc)
4191 {
4192 struct drm_device *dev = crtc->dev;
4193 struct drm_i915_private *dev_priv = dev->dev_private;
4194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4195 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4196 int i;
4197
4198 /* The clocks have to be on to load the palette. */
4199 if (!crtc->enabled)
4200 return;
4201
4202 /* use legacy palette for Ironlake */
4203 if (HAS_PCH_SPLIT(dev))
4204 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4205 LGC_PALETTE_B;
4206
4207 for (i = 0; i < 256; i++) {
4208 I915_WRITE(palreg + 4 * i,
4209 (intel_crtc->lut_r[i] << 16) |
4210 (intel_crtc->lut_g[i] << 8) |
4211 intel_crtc->lut_b[i]);
4212 }
4213 }
4214
4215 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4216 {
4217 struct drm_device *dev = crtc->dev;
4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4220 bool visible = base != 0;
4221 u32 cntl;
4222
4223 if (intel_crtc->cursor_visible == visible)
4224 return;
4225
4226 cntl = I915_READ(CURACNTR);
4227 if (visible) {
4228 /* On these chipsets we can only modify the base whilst
4229 * the cursor is disabled.
4230 */
4231 I915_WRITE(CURABASE, base);
4232
4233 cntl &= ~(CURSOR_FORMAT_MASK);
4234 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4235 cntl |= CURSOR_ENABLE |
4236 CURSOR_GAMMA_ENABLE |
4237 CURSOR_FORMAT_ARGB;
4238 } else
4239 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4240 I915_WRITE(CURACNTR, cntl);
4241
4242 intel_crtc->cursor_visible = visible;
4243 }
4244
4245 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4246 {
4247 struct drm_device *dev = crtc->dev;
4248 struct drm_i915_private *dev_priv = dev->dev_private;
4249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4250 int pipe = intel_crtc->pipe;
4251 bool visible = base != 0;
4252
4253 if (intel_crtc->cursor_visible != visible) {
4254 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4255 if (base) {
4256 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4257 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4258 cntl |= pipe << 28; /* Connect to correct pipe */
4259 } else {
4260 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4261 cntl |= CURSOR_MODE_DISABLE;
4262 }
4263 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4264
4265 intel_crtc->cursor_visible = visible;
4266 }
4267 /* and commit changes on next vblank */
4268 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4269 }
4270
4271 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4272 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4273 bool on)
4274 {
4275 struct drm_device *dev = crtc->dev;
4276 struct drm_i915_private *dev_priv = dev->dev_private;
4277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4278 int pipe = intel_crtc->pipe;
4279 int x = intel_crtc->cursor_x;
4280 int y = intel_crtc->cursor_y;
4281 u32 base, pos;
4282 bool visible;
4283
4284 pos = 0;
4285
4286 if (on && crtc->enabled && crtc->fb) {
4287 base = intel_crtc->cursor_addr;
4288 if (x > (int) crtc->fb->width)
4289 base = 0;
4290
4291 if (y > (int) crtc->fb->height)
4292 base = 0;
4293 } else
4294 base = 0;
4295
4296 if (x < 0) {
4297 if (x + intel_crtc->cursor_width < 0)
4298 base = 0;
4299
4300 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4301 x = -x;
4302 }
4303 pos |= x << CURSOR_X_SHIFT;
4304
4305 if (y < 0) {
4306 if (y + intel_crtc->cursor_height < 0)
4307 base = 0;
4308
4309 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4310 y = -y;
4311 }
4312 pos |= y << CURSOR_Y_SHIFT;
4313
4314 visible = base != 0;
4315 if (!visible && !intel_crtc->cursor_visible)
4316 return;
4317
4318 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4319 if (IS_845G(dev) || IS_I865G(dev))
4320 i845_update_cursor(crtc, base);
4321 else
4322 i9xx_update_cursor(crtc, base);
4323
4324 if (visible)
4325 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4326 }
4327
4328 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4329 struct drm_file *file_priv,
4330 uint32_t handle,
4331 uint32_t width, uint32_t height)
4332 {
4333 struct drm_device *dev = crtc->dev;
4334 struct drm_i915_private *dev_priv = dev->dev_private;
4335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4336 struct drm_gem_object *bo;
4337 struct drm_i915_gem_object *obj_priv;
4338 uint32_t addr;
4339 int ret;
4340
4341 DRM_DEBUG_KMS("\n");
4342
4343 /* if we want to turn off the cursor ignore width and height */
4344 if (!handle) {
4345 DRM_DEBUG_KMS("cursor off\n");
4346 addr = 0;
4347 bo = NULL;
4348 mutex_lock(&dev->struct_mutex);
4349 goto finish;
4350 }
4351
4352 /* Currently we only support 64x64 cursors */
4353 if (width != 64 || height != 64) {
4354 DRM_ERROR("we currently only support 64x64 cursors\n");
4355 return -EINVAL;
4356 }
4357
4358 bo = drm_gem_object_lookup(dev, file_priv, handle);
4359 if (!bo)
4360 return -ENOENT;
4361
4362 obj_priv = to_intel_bo(bo);
4363
4364 if (bo->size < width * height * 4) {
4365 DRM_ERROR("buffer is to small\n");
4366 ret = -ENOMEM;
4367 goto fail;
4368 }
4369
4370 /* we only need to pin inside GTT if cursor is non-phy */
4371 mutex_lock(&dev->struct_mutex);
4372 if (!dev_priv->info->cursor_needs_physical) {
4373 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4374 if (ret) {
4375 DRM_ERROR("failed to pin cursor bo\n");
4376 goto fail_locked;
4377 }
4378
4379 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4380 if (ret) {
4381 DRM_ERROR("failed to move cursor bo into the GTT\n");
4382 goto fail_unpin;
4383 }
4384
4385 addr = obj_priv->gtt_offset;
4386 } else {
4387 int align = IS_I830(dev) ? 16 * 1024 : 256;
4388 ret = i915_gem_attach_phys_object(dev, bo,
4389 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4390 align);
4391 if (ret) {
4392 DRM_ERROR("failed to attach phys object\n");
4393 goto fail_locked;
4394 }
4395 addr = obj_priv->phys_obj->handle->busaddr;
4396 }
4397
4398 if (IS_GEN2(dev))
4399 I915_WRITE(CURSIZE, (height << 12) | width);
4400
4401 finish:
4402 if (intel_crtc->cursor_bo) {
4403 if (dev_priv->info->cursor_needs_physical) {
4404 if (intel_crtc->cursor_bo != bo)
4405 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4406 } else
4407 i915_gem_object_unpin(intel_crtc->cursor_bo);
4408 drm_gem_object_unreference(intel_crtc->cursor_bo);
4409 }
4410
4411 mutex_unlock(&dev->struct_mutex);
4412
4413 intel_crtc->cursor_addr = addr;
4414 intel_crtc->cursor_bo = bo;
4415 intel_crtc->cursor_width = width;
4416 intel_crtc->cursor_height = height;
4417
4418 intel_crtc_update_cursor(crtc, true);
4419
4420 return 0;
4421 fail_unpin:
4422 i915_gem_object_unpin(bo);
4423 fail_locked:
4424 mutex_unlock(&dev->struct_mutex);
4425 fail:
4426 drm_gem_object_unreference_unlocked(bo);
4427 return ret;
4428 }
4429
4430 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4431 {
4432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4433
4434 intel_crtc->cursor_x = x;
4435 intel_crtc->cursor_y = y;
4436
4437 intel_crtc_update_cursor(crtc, true);
4438
4439 return 0;
4440 }
4441
4442 /** Sets the color ramps on behalf of RandR */
4443 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4444 u16 blue, int regno)
4445 {
4446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4447
4448 intel_crtc->lut_r[regno] = red >> 8;
4449 intel_crtc->lut_g[regno] = green >> 8;
4450 intel_crtc->lut_b[regno] = blue >> 8;
4451 }
4452
4453 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4454 u16 *blue, int regno)
4455 {
4456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4457
4458 *red = intel_crtc->lut_r[regno] << 8;
4459 *green = intel_crtc->lut_g[regno] << 8;
4460 *blue = intel_crtc->lut_b[regno] << 8;
4461 }
4462
4463 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4464 u16 *blue, uint32_t start, uint32_t size)
4465 {
4466 int end = (start + size > 256) ? 256 : start + size, i;
4467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4468
4469 for (i = start; i < end; i++) {
4470 intel_crtc->lut_r[i] = red[i] >> 8;
4471 intel_crtc->lut_g[i] = green[i] >> 8;
4472 intel_crtc->lut_b[i] = blue[i] >> 8;
4473 }
4474
4475 intel_crtc_load_lut(crtc);
4476 }
4477
4478 /**
4479 * Get a pipe with a simple mode set on it for doing load-based monitor
4480 * detection.
4481 *
4482 * It will be up to the load-detect code to adjust the pipe as appropriate for
4483 * its requirements. The pipe will be connected to no other encoders.
4484 *
4485 * Currently this code will only succeed if there is a pipe with no encoders
4486 * configured for it. In the future, it could choose to temporarily disable
4487 * some outputs to free up a pipe for its use.
4488 *
4489 * \return crtc, or NULL if no pipes are available.
4490 */
4491
4492 /* VESA 640x480x72Hz mode to set on the pipe */
4493 static struct drm_display_mode load_detect_mode = {
4494 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4495 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4496 };
4497
4498 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4499 struct drm_connector *connector,
4500 struct drm_display_mode *mode,
4501 int *dpms_mode)
4502 {
4503 struct intel_crtc *intel_crtc;
4504 struct drm_crtc *possible_crtc;
4505 struct drm_crtc *supported_crtc =NULL;
4506 struct drm_encoder *encoder = &intel_encoder->base;
4507 struct drm_crtc *crtc = NULL;
4508 struct drm_device *dev = encoder->dev;
4509 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4510 struct drm_crtc_helper_funcs *crtc_funcs;
4511 int i = -1;
4512
4513 /*
4514 * Algorithm gets a little messy:
4515 * - if the connector already has an assigned crtc, use it (but make
4516 * sure it's on first)
4517 * - try to find the first unused crtc that can drive this connector,
4518 * and use that if we find one
4519 * - if there are no unused crtcs available, try to use the first
4520 * one we found that supports the connector
4521 */
4522
4523 /* See if we already have a CRTC for this connector */
4524 if (encoder->crtc) {
4525 crtc = encoder->crtc;
4526 /* Make sure the crtc and connector are running */
4527 intel_crtc = to_intel_crtc(crtc);
4528 *dpms_mode = intel_crtc->dpms_mode;
4529 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4530 crtc_funcs = crtc->helper_private;
4531 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4532 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4533 }
4534 return crtc;
4535 }
4536
4537 /* Find an unused one (if possible) */
4538 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4539 i++;
4540 if (!(encoder->possible_crtcs & (1 << i)))
4541 continue;
4542 if (!possible_crtc->enabled) {
4543 crtc = possible_crtc;
4544 break;
4545 }
4546 if (!supported_crtc)
4547 supported_crtc = possible_crtc;
4548 }
4549
4550 /*
4551 * If we didn't find an unused CRTC, don't use any.
4552 */
4553 if (!crtc) {
4554 return NULL;
4555 }
4556
4557 encoder->crtc = crtc;
4558 connector->encoder = encoder;
4559 intel_encoder->load_detect_temp = true;
4560
4561 intel_crtc = to_intel_crtc(crtc);
4562 *dpms_mode = intel_crtc->dpms_mode;
4563
4564 if (!crtc->enabled) {
4565 if (!mode)
4566 mode = &load_detect_mode;
4567 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4568 } else {
4569 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4570 crtc_funcs = crtc->helper_private;
4571 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4572 }
4573
4574 /* Add this connector to the crtc */
4575 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4576 encoder_funcs->commit(encoder);
4577 }
4578 /* let the connector get through one full cycle before testing */
4579 intel_wait_for_vblank(dev, intel_crtc->pipe);
4580
4581 return crtc;
4582 }
4583
4584 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4585 struct drm_connector *connector, int dpms_mode)
4586 {
4587 struct drm_encoder *encoder = &intel_encoder->base;
4588 struct drm_device *dev = encoder->dev;
4589 struct drm_crtc *crtc = encoder->crtc;
4590 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4591 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4592
4593 if (intel_encoder->load_detect_temp) {
4594 encoder->crtc = NULL;
4595 connector->encoder = NULL;
4596 intel_encoder->load_detect_temp = false;
4597 crtc->enabled = drm_helper_crtc_in_use(crtc);
4598 drm_helper_disable_unused_functions(dev);
4599 }
4600
4601 /* Switch crtc and encoder back off if necessary */
4602 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4603 if (encoder->crtc == crtc)
4604 encoder_funcs->dpms(encoder, dpms_mode);
4605 crtc_funcs->dpms(crtc, dpms_mode);
4606 }
4607 }
4608
4609 /* Returns the clock of the currently programmed mode of the given pipe. */
4610 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4611 {
4612 struct drm_i915_private *dev_priv = dev->dev_private;
4613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4614 int pipe = intel_crtc->pipe;
4615 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4616 u32 fp;
4617 intel_clock_t clock;
4618
4619 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4620 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4621 else
4622 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4623
4624 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4625 if (IS_PINEVIEW(dev)) {
4626 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4627 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4628 } else {
4629 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4630 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4631 }
4632
4633 if (!IS_GEN2(dev)) {
4634 if (IS_PINEVIEW(dev))
4635 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4636 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4637 else
4638 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4639 DPLL_FPA01_P1_POST_DIV_SHIFT);
4640
4641 switch (dpll & DPLL_MODE_MASK) {
4642 case DPLLB_MODE_DAC_SERIAL:
4643 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4644 5 : 10;
4645 break;
4646 case DPLLB_MODE_LVDS:
4647 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4648 7 : 14;
4649 break;
4650 default:
4651 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4652 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4653 return 0;
4654 }
4655
4656 /* XXX: Handle the 100Mhz refclk */
4657 intel_clock(dev, 96000, &clock);
4658 } else {
4659 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4660
4661 if (is_lvds) {
4662 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4663 DPLL_FPA01_P1_POST_DIV_SHIFT);
4664 clock.p2 = 14;
4665
4666 if ((dpll & PLL_REF_INPUT_MASK) ==
4667 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4668 /* XXX: might not be 66MHz */
4669 intel_clock(dev, 66000, &clock);
4670 } else
4671 intel_clock(dev, 48000, &clock);
4672 } else {
4673 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4674 clock.p1 = 2;
4675 else {
4676 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4677 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4678 }
4679 if (dpll & PLL_P2_DIVIDE_BY_4)
4680 clock.p2 = 4;
4681 else
4682 clock.p2 = 2;
4683
4684 intel_clock(dev, 48000, &clock);
4685 }
4686 }
4687
4688 /* XXX: It would be nice to validate the clocks, but we can't reuse
4689 * i830PllIsValid() because it relies on the xf86_config connector
4690 * configuration being accurate, which it isn't necessarily.
4691 */
4692
4693 return clock.dot;
4694 }
4695
4696 /** Returns the currently programmed mode of the given pipe. */
4697 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4698 struct drm_crtc *crtc)
4699 {
4700 struct drm_i915_private *dev_priv = dev->dev_private;
4701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4702 int pipe = intel_crtc->pipe;
4703 struct drm_display_mode *mode;
4704 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4705 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4706 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4707 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4708
4709 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4710 if (!mode)
4711 return NULL;
4712
4713 mode->clock = intel_crtc_clock_get(dev, crtc);
4714 mode->hdisplay = (htot & 0xffff) + 1;
4715 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4716 mode->hsync_start = (hsync & 0xffff) + 1;
4717 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4718 mode->vdisplay = (vtot & 0xffff) + 1;
4719 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4720 mode->vsync_start = (vsync & 0xffff) + 1;
4721 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4722
4723 drm_mode_set_name(mode);
4724 drm_mode_set_crtcinfo(mode, 0);
4725
4726 return mode;
4727 }
4728
4729 #define GPU_IDLE_TIMEOUT 500 /* ms */
4730
4731 /* When this timer fires, we've been idle for awhile */
4732 static void intel_gpu_idle_timer(unsigned long arg)
4733 {
4734 struct drm_device *dev = (struct drm_device *)arg;
4735 drm_i915_private_t *dev_priv = dev->dev_private;
4736
4737 dev_priv->busy = false;
4738
4739 queue_work(dev_priv->wq, &dev_priv->idle_work);
4740 }
4741
4742 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4743
4744 static void intel_crtc_idle_timer(unsigned long arg)
4745 {
4746 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4747 struct drm_crtc *crtc = &intel_crtc->base;
4748 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4749
4750 intel_crtc->busy = false;
4751
4752 queue_work(dev_priv->wq, &dev_priv->idle_work);
4753 }
4754
4755 static void intel_increase_pllclock(struct drm_crtc *crtc)
4756 {
4757 struct drm_device *dev = crtc->dev;
4758 drm_i915_private_t *dev_priv = dev->dev_private;
4759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4760 int pipe = intel_crtc->pipe;
4761 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4762 int dpll = I915_READ(dpll_reg);
4763
4764 if (HAS_PCH_SPLIT(dev))
4765 return;
4766
4767 if (!dev_priv->lvds_downclock_avail)
4768 return;
4769
4770 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4771 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4772
4773 /* Unlock panel regs */
4774 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4775 PANEL_UNLOCK_REGS);
4776
4777 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4778 I915_WRITE(dpll_reg, dpll);
4779 dpll = I915_READ(dpll_reg);
4780 intel_wait_for_vblank(dev, pipe);
4781 dpll = I915_READ(dpll_reg);
4782 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4783 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4784
4785 /* ...and lock them again */
4786 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4787 }
4788
4789 /* Schedule downclock */
4790 mod_timer(&intel_crtc->idle_timer, jiffies +
4791 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4792 }
4793
4794 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4795 {
4796 struct drm_device *dev = crtc->dev;
4797 drm_i915_private_t *dev_priv = dev->dev_private;
4798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4799 int pipe = intel_crtc->pipe;
4800 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4801 int dpll = I915_READ(dpll_reg);
4802
4803 if (HAS_PCH_SPLIT(dev))
4804 return;
4805
4806 if (!dev_priv->lvds_downclock_avail)
4807 return;
4808
4809 /*
4810 * Since this is called by a timer, we should never get here in
4811 * the manual case.
4812 */
4813 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4814 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4815
4816 /* Unlock panel regs */
4817 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4818 PANEL_UNLOCK_REGS);
4819
4820 dpll |= DISPLAY_RATE_SELECT_FPA1;
4821 I915_WRITE(dpll_reg, dpll);
4822 dpll = I915_READ(dpll_reg);
4823 intel_wait_for_vblank(dev, pipe);
4824 dpll = I915_READ(dpll_reg);
4825 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4826 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4827
4828 /* ...and lock them again */
4829 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4830 }
4831
4832 }
4833
4834 /**
4835 * intel_idle_update - adjust clocks for idleness
4836 * @work: work struct
4837 *
4838 * Either the GPU or display (or both) went idle. Check the busy status
4839 * here and adjust the CRTC and GPU clocks as necessary.
4840 */
4841 static void intel_idle_update(struct work_struct *work)
4842 {
4843 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4844 idle_work);
4845 struct drm_device *dev = dev_priv->dev;
4846 struct drm_crtc *crtc;
4847 struct intel_crtc *intel_crtc;
4848 int enabled = 0;
4849
4850 if (!i915_powersave)
4851 return;
4852
4853 mutex_lock(&dev->struct_mutex);
4854
4855 i915_update_gfx_val(dev_priv);
4856
4857 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4858 /* Skip inactive CRTCs */
4859 if (!crtc->fb)
4860 continue;
4861
4862 enabled++;
4863 intel_crtc = to_intel_crtc(crtc);
4864 if (!intel_crtc->busy)
4865 intel_decrease_pllclock(crtc);
4866 }
4867
4868 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4869 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4870 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4871 }
4872
4873 mutex_unlock(&dev->struct_mutex);
4874 }
4875
4876 /**
4877 * intel_mark_busy - mark the GPU and possibly the display busy
4878 * @dev: drm device
4879 * @obj: object we're operating on
4880 *
4881 * Callers can use this function to indicate that the GPU is busy processing
4882 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4883 * buffer), we'll also mark the display as busy, so we know to increase its
4884 * clock frequency.
4885 */
4886 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4887 {
4888 drm_i915_private_t *dev_priv = dev->dev_private;
4889 struct drm_crtc *crtc = NULL;
4890 struct intel_framebuffer *intel_fb;
4891 struct intel_crtc *intel_crtc;
4892
4893 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4894 return;
4895
4896 if (!dev_priv->busy) {
4897 if (IS_I945G(dev) || IS_I945GM(dev)) {
4898 u32 fw_blc_self;
4899
4900 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4901 fw_blc_self = I915_READ(FW_BLC_SELF);
4902 fw_blc_self &= ~FW_BLC_SELF_EN;
4903 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4904 }
4905 dev_priv->busy = true;
4906 } else
4907 mod_timer(&dev_priv->idle_timer, jiffies +
4908 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4909
4910 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4911 if (!crtc->fb)
4912 continue;
4913
4914 intel_crtc = to_intel_crtc(crtc);
4915 intel_fb = to_intel_framebuffer(crtc->fb);
4916 if (intel_fb->obj == obj) {
4917 if (!intel_crtc->busy) {
4918 if (IS_I945G(dev) || IS_I945GM(dev)) {
4919 u32 fw_blc_self;
4920
4921 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4922 fw_blc_self = I915_READ(FW_BLC_SELF);
4923 fw_blc_self &= ~FW_BLC_SELF_EN;
4924 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4925 }
4926 /* Non-busy -> busy, upclock */
4927 intel_increase_pllclock(crtc);
4928 intel_crtc->busy = true;
4929 } else {
4930 /* Busy -> busy, put off timer */
4931 mod_timer(&intel_crtc->idle_timer, jiffies +
4932 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4933 }
4934 }
4935 }
4936 }
4937
4938 static void intel_crtc_destroy(struct drm_crtc *crtc)
4939 {
4940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4941 struct drm_device *dev = crtc->dev;
4942 struct intel_unpin_work *work;
4943 unsigned long flags;
4944
4945 spin_lock_irqsave(&dev->event_lock, flags);
4946 work = intel_crtc->unpin_work;
4947 intel_crtc->unpin_work = NULL;
4948 spin_unlock_irqrestore(&dev->event_lock, flags);
4949
4950 if (work) {
4951 cancel_work_sync(&work->work);
4952 kfree(work);
4953 }
4954
4955 drm_crtc_cleanup(crtc);
4956
4957 kfree(intel_crtc);
4958 }
4959
4960 static void intel_unpin_work_fn(struct work_struct *__work)
4961 {
4962 struct intel_unpin_work *work =
4963 container_of(__work, struct intel_unpin_work, work);
4964
4965 mutex_lock(&work->dev->struct_mutex);
4966 i915_gem_object_unpin(work->old_fb_obj);
4967 drm_gem_object_unreference(work->pending_flip_obj);
4968 drm_gem_object_unreference(work->old_fb_obj);
4969 mutex_unlock(&work->dev->struct_mutex);
4970 kfree(work);
4971 }
4972
4973 static void do_intel_finish_page_flip(struct drm_device *dev,
4974 struct drm_crtc *crtc)
4975 {
4976 drm_i915_private_t *dev_priv = dev->dev_private;
4977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4978 struct intel_unpin_work *work;
4979 struct drm_i915_gem_object *obj_priv;
4980 struct drm_pending_vblank_event *e;
4981 struct timeval now;
4982 unsigned long flags;
4983
4984 /* Ignore early vblank irqs */
4985 if (intel_crtc == NULL)
4986 return;
4987
4988 spin_lock_irqsave(&dev->event_lock, flags);
4989 work = intel_crtc->unpin_work;
4990 if (work == NULL || !work->pending) {
4991 spin_unlock_irqrestore(&dev->event_lock, flags);
4992 return;
4993 }
4994
4995 intel_crtc->unpin_work = NULL;
4996 drm_vblank_put(dev, intel_crtc->pipe);
4997
4998 if (work->event) {
4999 e = work->event;
5000 do_gettimeofday(&now);
5001 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
5002 e->event.tv_sec = now.tv_sec;
5003 e->event.tv_usec = now.tv_usec;
5004 list_add_tail(&e->base.link,
5005 &e->base.file_priv->event_list);
5006 wake_up_interruptible(&e->base.file_priv->event_wait);
5007 }
5008
5009 spin_unlock_irqrestore(&dev->event_lock, flags);
5010
5011 obj_priv = to_intel_bo(work->pending_flip_obj);
5012
5013 /* Initial scanout buffer will have a 0 pending flip count */
5014 atomic_clear_mask(1 << intel_crtc->plane,
5015 &obj_priv->pending_flip.counter);
5016 if (atomic_read(&obj_priv->pending_flip) == 0)
5017 wake_up(&dev_priv->pending_flip_queue);
5018 schedule_work(&work->work);
5019
5020 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5021 }
5022
5023 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5024 {
5025 drm_i915_private_t *dev_priv = dev->dev_private;
5026 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5027
5028 do_intel_finish_page_flip(dev, crtc);
5029 }
5030
5031 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5032 {
5033 drm_i915_private_t *dev_priv = dev->dev_private;
5034 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5035
5036 do_intel_finish_page_flip(dev, crtc);
5037 }
5038
5039 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5040 {
5041 drm_i915_private_t *dev_priv = dev->dev_private;
5042 struct intel_crtc *intel_crtc =
5043 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5044 unsigned long flags;
5045
5046 spin_lock_irqsave(&dev->event_lock, flags);
5047 if (intel_crtc->unpin_work) {
5048 if ((++intel_crtc->unpin_work->pending) > 1)
5049 DRM_ERROR("Prepared flip multiple times\n");
5050 } else {
5051 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5052 }
5053 spin_unlock_irqrestore(&dev->event_lock, flags);
5054 }
5055
5056 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5057 struct drm_framebuffer *fb,
5058 struct drm_pending_vblank_event *event)
5059 {
5060 struct drm_device *dev = crtc->dev;
5061 struct drm_i915_private *dev_priv = dev->dev_private;
5062 struct intel_framebuffer *intel_fb;
5063 struct drm_i915_gem_object *obj_priv;
5064 struct drm_gem_object *obj;
5065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5066 struct intel_unpin_work *work;
5067 unsigned long flags, offset;
5068 int pipe = intel_crtc->pipe;
5069 u32 pf, pipesrc;
5070 int ret;
5071
5072 work = kzalloc(sizeof *work, GFP_KERNEL);
5073 if (work == NULL)
5074 return -ENOMEM;
5075
5076 work->event = event;
5077 work->dev = crtc->dev;
5078 intel_fb = to_intel_framebuffer(crtc->fb);
5079 work->old_fb_obj = intel_fb->obj;
5080 INIT_WORK(&work->work, intel_unpin_work_fn);
5081
5082 /* We borrow the event spin lock for protecting unpin_work */
5083 spin_lock_irqsave(&dev->event_lock, flags);
5084 if (intel_crtc->unpin_work) {
5085 spin_unlock_irqrestore(&dev->event_lock, flags);
5086 kfree(work);
5087
5088 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5089 return -EBUSY;
5090 }
5091 intel_crtc->unpin_work = work;
5092 spin_unlock_irqrestore(&dev->event_lock, flags);
5093
5094 intel_fb = to_intel_framebuffer(fb);
5095 obj = intel_fb->obj;
5096
5097 mutex_lock(&dev->struct_mutex);
5098 ret = intel_pin_and_fence_fb_obj(dev, obj, true);
5099 if (ret)
5100 goto cleanup_work;
5101
5102 /* Reference the objects for the scheduled work. */
5103 drm_gem_object_reference(work->old_fb_obj);
5104 drm_gem_object_reference(obj);
5105
5106 crtc->fb = fb;
5107
5108 ret = drm_vblank_get(dev, intel_crtc->pipe);
5109 if (ret)
5110 goto cleanup_objs;
5111
5112 obj_priv = to_intel_bo(obj);
5113 atomic_add(1 << intel_crtc->plane, &obj_priv->pending_flip);
5114 work->pending_flip_obj = obj;
5115
5116 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5117 u32 flip_mask;
5118
5119 /* Can't queue multiple flips, so wait for the previous
5120 * one to finish before executing the next.
5121 */
5122 BEGIN_LP_RING(2);
5123 if (intel_crtc->plane)
5124 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5125 else
5126 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5127 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5128 OUT_RING(MI_NOOP);
5129 ADVANCE_LP_RING();
5130 }
5131
5132 work->enable_stall_check = true;
5133
5134 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5135 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5136
5137 BEGIN_LP_RING(4);
5138 switch(INTEL_INFO(dev)->gen) {
5139 case 2:
5140 OUT_RING(MI_DISPLAY_FLIP |
5141 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5142 OUT_RING(fb->pitch);
5143 OUT_RING(obj_priv->gtt_offset + offset);
5144 OUT_RING(MI_NOOP);
5145 break;
5146
5147 case 3:
5148 OUT_RING(MI_DISPLAY_FLIP_I915 |
5149 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5150 OUT_RING(fb->pitch);
5151 OUT_RING(obj_priv->gtt_offset + offset);
5152 OUT_RING(MI_NOOP);
5153 break;
5154
5155 case 4:
5156 case 5:
5157 /* i965+ uses the linear or tiled offsets from the
5158 * Display Registers (which do not change across a page-flip)
5159 * so we need only reprogram the base address.
5160 */
5161 OUT_RING(MI_DISPLAY_FLIP |
5162 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5163 OUT_RING(fb->pitch);
5164 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5165
5166 /* XXX Enabling the panel-fitter across page-flip is so far
5167 * untested on non-native modes, so ignore it for now.
5168 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5169 */
5170 pf = 0;
5171 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5172 OUT_RING(pf | pipesrc);
5173 break;
5174
5175 case 6:
5176 OUT_RING(MI_DISPLAY_FLIP |
5177 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5178 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5179 OUT_RING(obj_priv->gtt_offset);
5180
5181 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5182 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5183 OUT_RING(pf | pipesrc);
5184 break;
5185 }
5186 ADVANCE_LP_RING();
5187
5188 mutex_unlock(&dev->struct_mutex);
5189
5190 trace_i915_flip_request(intel_crtc->plane, obj);
5191
5192 return 0;
5193
5194 cleanup_objs:
5195 drm_gem_object_unreference(work->old_fb_obj);
5196 drm_gem_object_unreference(obj);
5197 cleanup_work:
5198 mutex_unlock(&dev->struct_mutex);
5199
5200 spin_lock_irqsave(&dev->event_lock, flags);
5201 intel_crtc->unpin_work = NULL;
5202 spin_unlock_irqrestore(&dev->event_lock, flags);
5203
5204 kfree(work);
5205
5206 return ret;
5207 }
5208
5209 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5210 .dpms = intel_crtc_dpms,
5211 .mode_fixup = intel_crtc_mode_fixup,
5212 .mode_set = intel_crtc_mode_set,
5213 .mode_set_base = intel_pipe_set_base,
5214 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5215 .load_lut = intel_crtc_load_lut,
5216 .disable = intel_crtc_disable,
5217 };
5218
5219 static const struct drm_crtc_funcs intel_crtc_funcs = {
5220 .cursor_set = intel_crtc_cursor_set,
5221 .cursor_move = intel_crtc_cursor_move,
5222 .gamma_set = intel_crtc_gamma_set,
5223 .set_config = drm_crtc_helper_set_config,
5224 .destroy = intel_crtc_destroy,
5225 .page_flip = intel_crtc_page_flip,
5226 };
5227
5228
5229 static void intel_crtc_init(struct drm_device *dev, int pipe)
5230 {
5231 drm_i915_private_t *dev_priv = dev->dev_private;
5232 struct intel_crtc *intel_crtc;
5233 int i;
5234
5235 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5236 if (intel_crtc == NULL)
5237 return;
5238
5239 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5240
5241 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5242 for (i = 0; i < 256; i++) {
5243 intel_crtc->lut_r[i] = i;
5244 intel_crtc->lut_g[i] = i;
5245 intel_crtc->lut_b[i] = i;
5246 }
5247
5248 /* Swap pipes & planes for FBC on pre-965 */
5249 intel_crtc->pipe = pipe;
5250 intel_crtc->plane = pipe;
5251 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5252 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5253 intel_crtc->plane = !pipe;
5254 }
5255
5256 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5257 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5258 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5259 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5260
5261 intel_crtc->cursor_addr = 0;
5262 intel_crtc->dpms_mode = -1;
5263 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5264
5265 if (HAS_PCH_SPLIT(dev)) {
5266 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5267 intel_helper_funcs.commit = ironlake_crtc_commit;
5268 } else {
5269 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5270 intel_helper_funcs.commit = i9xx_crtc_commit;
5271 }
5272
5273 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5274
5275 intel_crtc->busy = false;
5276
5277 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5278 (unsigned long)intel_crtc);
5279 }
5280
5281 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5282 struct drm_file *file_priv)
5283 {
5284 drm_i915_private_t *dev_priv = dev->dev_private;
5285 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5286 struct drm_mode_object *drmmode_obj;
5287 struct intel_crtc *crtc;
5288
5289 if (!dev_priv) {
5290 DRM_ERROR("called with no initialization\n");
5291 return -EINVAL;
5292 }
5293
5294 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5295 DRM_MODE_OBJECT_CRTC);
5296
5297 if (!drmmode_obj) {
5298 DRM_ERROR("no such CRTC id\n");
5299 return -EINVAL;
5300 }
5301
5302 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5303 pipe_from_crtc_id->pipe = crtc->pipe;
5304
5305 return 0;
5306 }
5307
5308 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5309 {
5310 struct intel_encoder *encoder;
5311 int index_mask = 0;
5312 int entry = 0;
5313
5314 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5315 if (type_mask & encoder->clone_mask)
5316 index_mask |= (1 << entry);
5317 entry++;
5318 }
5319
5320 return index_mask;
5321 }
5322
5323 static void intel_setup_outputs(struct drm_device *dev)
5324 {
5325 struct drm_i915_private *dev_priv = dev->dev_private;
5326 struct intel_encoder *encoder;
5327 bool dpd_is_edp = false;
5328
5329 if (IS_MOBILE(dev) && !IS_I830(dev))
5330 intel_lvds_init(dev);
5331
5332 if (HAS_PCH_SPLIT(dev)) {
5333 dpd_is_edp = intel_dpd_is_edp(dev);
5334
5335 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5336 intel_dp_init(dev, DP_A);
5337
5338 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5339 intel_dp_init(dev, PCH_DP_D);
5340 }
5341
5342 intel_crt_init(dev);
5343
5344 if (HAS_PCH_SPLIT(dev)) {
5345 int found;
5346
5347 if (I915_READ(HDMIB) & PORT_DETECTED) {
5348 /* PCH SDVOB multiplex with HDMIB */
5349 found = intel_sdvo_init(dev, PCH_SDVOB);
5350 if (!found)
5351 intel_hdmi_init(dev, HDMIB);
5352 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5353 intel_dp_init(dev, PCH_DP_B);
5354 }
5355
5356 if (I915_READ(HDMIC) & PORT_DETECTED)
5357 intel_hdmi_init(dev, HDMIC);
5358
5359 if (I915_READ(HDMID) & PORT_DETECTED)
5360 intel_hdmi_init(dev, HDMID);
5361
5362 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5363 intel_dp_init(dev, PCH_DP_C);
5364
5365 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5366 intel_dp_init(dev, PCH_DP_D);
5367
5368 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5369 bool found = false;
5370
5371 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5372 DRM_DEBUG_KMS("probing SDVOB\n");
5373 found = intel_sdvo_init(dev, SDVOB);
5374 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5375 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5376 intel_hdmi_init(dev, SDVOB);
5377 }
5378
5379 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5380 DRM_DEBUG_KMS("probing DP_B\n");
5381 intel_dp_init(dev, DP_B);
5382 }
5383 }
5384
5385 /* Before G4X SDVOC doesn't have its own detect register */
5386
5387 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5388 DRM_DEBUG_KMS("probing SDVOC\n");
5389 found = intel_sdvo_init(dev, SDVOC);
5390 }
5391
5392 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5393
5394 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5395 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5396 intel_hdmi_init(dev, SDVOC);
5397 }
5398 if (SUPPORTS_INTEGRATED_DP(dev)) {
5399 DRM_DEBUG_KMS("probing DP_C\n");
5400 intel_dp_init(dev, DP_C);
5401 }
5402 }
5403
5404 if (SUPPORTS_INTEGRATED_DP(dev) &&
5405 (I915_READ(DP_D) & DP_DETECTED)) {
5406 DRM_DEBUG_KMS("probing DP_D\n");
5407 intel_dp_init(dev, DP_D);
5408 }
5409 } else if (IS_GEN2(dev))
5410 intel_dvo_init(dev);
5411
5412 if (SUPPORTS_TV(dev))
5413 intel_tv_init(dev);
5414
5415 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5416 encoder->base.possible_crtcs = encoder->crtc_mask;
5417 encoder->base.possible_clones =
5418 intel_encoder_clones(dev, encoder->clone_mask);
5419 }
5420 }
5421
5422 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5423 {
5424 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5425
5426 drm_framebuffer_cleanup(fb);
5427 drm_gem_object_unreference_unlocked(intel_fb->obj);
5428
5429 kfree(intel_fb);
5430 }
5431
5432 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5433 struct drm_file *file_priv,
5434 unsigned int *handle)
5435 {
5436 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5437 struct drm_gem_object *object = intel_fb->obj;
5438
5439 return drm_gem_handle_create(file_priv, object, handle);
5440 }
5441
5442 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5443 .destroy = intel_user_framebuffer_destroy,
5444 .create_handle = intel_user_framebuffer_create_handle,
5445 };
5446
5447 int intel_framebuffer_init(struct drm_device *dev,
5448 struct intel_framebuffer *intel_fb,
5449 struct drm_mode_fb_cmd *mode_cmd,
5450 struct drm_gem_object *obj)
5451 {
5452 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5453 int ret;
5454
5455 if (obj_priv->tiling_mode == I915_TILING_Y)
5456 return -EINVAL;
5457
5458 if (mode_cmd->pitch & 63)
5459 return -EINVAL;
5460
5461 switch (mode_cmd->bpp) {
5462 case 8:
5463 case 16:
5464 case 24:
5465 case 32:
5466 break;
5467 default:
5468 return -EINVAL;
5469 }
5470
5471 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5472 if (ret) {
5473 DRM_ERROR("framebuffer init failed %d\n", ret);
5474 return ret;
5475 }
5476
5477 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5478 intel_fb->obj = obj;
5479 return 0;
5480 }
5481
5482 static struct drm_framebuffer *
5483 intel_user_framebuffer_create(struct drm_device *dev,
5484 struct drm_file *filp,
5485 struct drm_mode_fb_cmd *mode_cmd)
5486 {
5487 struct drm_gem_object *obj;
5488 struct intel_framebuffer *intel_fb;
5489 int ret;
5490
5491 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5492 if (!obj)
5493 return ERR_PTR(-ENOENT);
5494
5495 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5496 if (!intel_fb)
5497 return ERR_PTR(-ENOMEM);
5498
5499 ret = intel_framebuffer_init(dev, intel_fb,
5500 mode_cmd, obj);
5501 if (ret) {
5502 drm_gem_object_unreference_unlocked(obj);
5503 kfree(intel_fb);
5504 return ERR_PTR(ret);
5505 }
5506
5507 return &intel_fb->base;
5508 }
5509
5510 static const struct drm_mode_config_funcs intel_mode_funcs = {
5511 .fb_create = intel_user_framebuffer_create,
5512 .output_poll_changed = intel_fb_output_poll_changed,
5513 };
5514
5515 static struct drm_gem_object *
5516 intel_alloc_context_page(struct drm_device *dev)
5517 {
5518 struct drm_gem_object *ctx;
5519 int ret;
5520
5521 ctx = i915_gem_alloc_object(dev, 4096);
5522 if (!ctx) {
5523 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5524 return NULL;
5525 }
5526
5527 mutex_lock(&dev->struct_mutex);
5528 ret = i915_gem_object_pin(ctx, 4096);
5529 if (ret) {
5530 DRM_ERROR("failed to pin power context: %d\n", ret);
5531 goto err_unref;
5532 }
5533
5534 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5535 if (ret) {
5536 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5537 goto err_unpin;
5538 }
5539 mutex_unlock(&dev->struct_mutex);
5540
5541 return ctx;
5542
5543 err_unpin:
5544 i915_gem_object_unpin(ctx);
5545 err_unref:
5546 drm_gem_object_unreference(ctx);
5547 mutex_unlock(&dev->struct_mutex);
5548 return NULL;
5549 }
5550
5551 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5552 {
5553 struct drm_i915_private *dev_priv = dev->dev_private;
5554 u16 rgvswctl;
5555
5556 rgvswctl = I915_READ16(MEMSWCTL);
5557 if (rgvswctl & MEMCTL_CMD_STS) {
5558 DRM_DEBUG("gpu busy, RCS change rejected\n");
5559 return false; /* still busy with another command */
5560 }
5561
5562 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5563 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5564 I915_WRITE16(MEMSWCTL, rgvswctl);
5565 POSTING_READ16(MEMSWCTL);
5566
5567 rgvswctl |= MEMCTL_CMD_STS;
5568 I915_WRITE16(MEMSWCTL, rgvswctl);
5569
5570 return true;
5571 }
5572
5573 void ironlake_enable_drps(struct drm_device *dev)
5574 {
5575 struct drm_i915_private *dev_priv = dev->dev_private;
5576 u32 rgvmodectl = I915_READ(MEMMODECTL);
5577 u8 fmax, fmin, fstart, vstart;
5578
5579 /* Enable temp reporting */
5580 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5581 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5582
5583 /* 100ms RC evaluation intervals */
5584 I915_WRITE(RCUPEI, 100000);
5585 I915_WRITE(RCDNEI, 100000);
5586
5587 /* Set max/min thresholds to 90ms and 80ms respectively */
5588 I915_WRITE(RCBMAXAVG, 90000);
5589 I915_WRITE(RCBMINAVG, 80000);
5590
5591 I915_WRITE(MEMIHYST, 1);
5592
5593 /* Set up min, max, and cur for interrupt handling */
5594 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5595 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5596 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5597 MEMMODE_FSTART_SHIFT;
5598 fstart = fmax;
5599
5600 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5601 PXVFREQ_PX_SHIFT;
5602
5603 dev_priv->fmax = fstart; /* IPS callback will increase this */
5604 dev_priv->fstart = fstart;
5605
5606 dev_priv->max_delay = fmax;
5607 dev_priv->min_delay = fmin;
5608 dev_priv->cur_delay = fstart;
5609
5610 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5611 fstart);
5612
5613 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5614
5615 /*
5616 * Interrupts will be enabled in ironlake_irq_postinstall
5617 */
5618
5619 I915_WRITE(VIDSTART, vstart);
5620 POSTING_READ(VIDSTART);
5621
5622 rgvmodectl |= MEMMODE_SWMODE_EN;
5623 I915_WRITE(MEMMODECTL, rgvmodectl);
5624
5625 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5626 DRM_ERROR("stuck trying to change perf mode\n");
5627 msleep(1);
5628
5629 ironlake_set_drps(dev, fstart);
5630
5631 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5632 I915_READ(0x112e0);
5633 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5634 dev_priv->last_count2 = I915_READ(0x112f4);
5635 getrawmonotonic(&dev_priv->last_time2);
5636 }
5637
5638 void ironlake_disable_drps(struct drm_device *dev)
5639 {
5640 struct drm_i915_private *dev_priv = dev->dev_private;
5641 u16 rgvswctl = I915_READ16(MEMSWCTL);
5642
5643 /* Ack interrupts, disable EFC interrupt */
5644 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5645 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5646 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5647 I915_WRITE(DEIIR, DE_PCU_EVENT);
5648 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5649
5650 /* Go back to the starting frequency */
5651 ironlake_set_drps(dev, dev_priv->fstart);
5652 msleep(1);
5653 rgvswctl |= MEMCTL_CMD_STS;
5654 I915_WRITE(MEMSWCTL, rgvswctl);
5655 msleep(1);
5656
5657 }
5658
5659 static unsigned long intel_pxfreq(u32 vidfreq)
5660 {
5661 unsigned long freq;
5662 int div = (vidfreq & 0x3f0000) >> 16;
5663 int post = (vidfreq & 0x3000) >> 12;
5664 int pre = (vidfreq & 0x7);
5665
5666 if (!pre)
5667 return 0;
5668
5669 freq = ((div * 133333) / ((1<<post) * pre));
5670
5671 return freq;
5672 }
5673
5674 void intel_init_emon(struct drm_device *dev)
5675 {
5676 struct drm_i915_private *dev_priv = dev->dev_private;
5677 u32 lcfuse;
5678 u8 pxw[16];
5679 int i;
5680
5681 /* Disable to program */
5682 I915_WRITE(ECR, 0);
5683 POSTING_READ(ECR);
5684
5685 /* Program energy weights for various events */
5686 I915_WRITE(SDEW, 0x15040d00);
5687 I915_WRITE(CSIEW0, 0x007f0000);
5688 I915_WRITE(CSIEW1, 0x1e220004);
5689 I915_WRITE(CSIEW2, 0x04000004);
5690
5691 for (i = 0; i < 5; i++)
5692 I915_WRITE(PEW + (i * 4), 0);
5693 for (i = 0; i < 3; i++)
5694 I915_WRITE(DEW + (i * 4), 0);
5695
5696 /* Program P-state weights to account for frequency power adjustment */
5697 for (i = 0; i < 16; i++) {
5698 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5699 unsigned long freq = intel_pxfreq(pxvidfreq);
5700 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5701 PXVFREQ_PX_SHIFT;
5702 unsigned long val;
5703
5704 val = vid * vid;
5705 val *= (freq / 1000);
5706 val *= 255;
5707 val /= (127*127*900);
5708 if (val > 0xff)
5709 DRM_ERROR("bad pxval: %ld\n", val);
5710 pxw[i] = val;
5711 }
5712 /* Render standby states get 0 weight */
5713 pxw[14] = 0;
5714 pxw[15] = 0;
5715
5716 for (i = 0; i < 4; i++) {
5717 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5718 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5719 I915_WRITE(PXW + (i * 4), val);
5720 }
5721
5722 /* Adjust magic regs to magic values (more experimental results) */
5723 I915_WRITE(OGW0, 0);
5724 I915_WRITE(OGW1, 0);
5725 I915_WRITE(EG0, 0x00007f00);
5726 I915_WRITE(EG1, 0x0000000e);
5727 I915_WRITE(EG2, 0x000e0000);
5728 I915_WRITE(EG3, 0x68000300);
5729 I915_WRITE(EG4, 0x42000000);
5730 I915_WRITE(EG5, 0x00140031);
5731 I915_WRITE(EG6, 0);
5732 I915_WRITE(EG7, 0);
5733
5734 for (i = 0; i < 8; i++)
5735 I915_WRITE(PXWL + (i * 4), 0);
5736
5737 /* Enable PMON + select events */
5738 I915_WRITE(ECR, 0x80000019);
5739
5740 lcfuse = I915_READ(LCFUSE02);
5741
5742 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5743 }
5744
5745 void intel_init_clock_gating(struct drm_device *dev)
5746 {
5747 struct drm_i915_private *dev_priv = dev->dev_private;
5748
5749 /*
5750 * Disable clock gating reported to work incorrectly according to the
5751 * specs, but enable as much else as we can.
5752 */
5753 if (HAS_PCH_SPLIT(dev)) {
5754 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5755
5756 if (IS_IRONLAKE(dev)) {
5757 /* Required for FBC */
5758 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5759 /* Required for CxSR */
5760 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5761
5762 I915_WRITE(PCH_3DCGDIS0,
5763 MARIUNIT_CLOCK_GATE_DISABLE |
5764 SVSMUNIT_CLOCK_GATE_DISABLE);
5765 }
5766
5767 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5768
5769 /*
5770 * According to the spec the following bits should be set in
5771 * order to enable memory self-refresh
5772 * The bit 22/21 of 0x42004
5773 * The bit 5 of 0x42020
5774 * The bit 15 of 0x45000
5775 */
5776 if (IS_IRONLAKE(dev)) {
5777 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5778 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5779 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5780 I915_WRITE(ILK_DSPCLK_GATE,
5781 (I915_READ(ILK_DSPCLK_GATE) |
5782 ILK_DPARB_CLK_GATE));
5783 I915_WRITE(DISP_ARB_CTL,
5784 (I915_READ(DISP_ARB_CTL) |
5785 DISP_FBC_WM_DIS));
5786 I915_WRITE(WM3_LP_ILK, 0);
5787 I915_WRITE(WM2_LP_ILK, 0);
5788 I915_WRITE(WM1_LP_ILK, 0);
5789 }
5790 /*
5791 * Based on the document from hardware guys the following bits
5792 * should be set unconditionally in order to enable FBC.
5793 * The bit 22 of 0x42000
5794 * The bit 22 of 0x42004
5795 * The bit 7,8,9 of 0x42020.
5796 */
5797 if (IS_IRONLAKE_M(dev)) {
5798 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5799 I915_READ(ILK_DISPLAY_CHICKEN1) |
5800 ILK_FBCQ_DIS);
5801 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5802 I915_READ(ILK_DISPLAY_CHICKEN2) |
5803 ILK_DPARB_GATE);
5804 I915_WRITE(ILK_DSPCLK_GATE,
5805 I915_READ(ILK_DSPCLK_GATE) |
5806 ILK_DPFC_DIS1 |
5807 ILK_DPFC_DIS2 |
5808 ILK_CLK_FBC);
5809 }
5810 return;
5811 } else if (IS_G4X(dev)) {
5812 uint32_t dspclk_gate;
5813 I915_WRITE(RENCLK_GATE_D1, 0);
5814 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5815 GS_UNIT_CLOCK_GATE_DISABLE |
5816 CL_UNIT_CLOCK_GATE_DISABLE);
5817 I915_WRITE(RAMCLK_GATE_D, 0);
5818 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5819 OVRUNIT_CLOCK_GATE_DISABLE |
5820 OVCUNIT_CLOCK_GATE_DISABLE;
5821 if (IS_GM45(dev))
5822 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5823 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5824 } else if (IS_CRESTLINE(dev)) {
5825 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5826 I915_WRITE(RENCLK_GATE_D2, 0);
5827 I915_WRITE(DSPCLK_GATE_D, 0);
5828 I915_WRITE(RAMCLK_GATE_D, 0);
5829 I915_WRITE16(DEUC, 0);
5830 } else if (IS_BROADWATER(dev)) {
5831 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5832 I965_RCC_CLOCK_GATE_DISABLE |
5833 I965_RCPB_CLOCK_GATE_DISABLE |
5834 I965_ISC_CLOCK_GATE_DISABLE |
5835 I965_FBC_CLOCK_GATE_DISABLE);
5836 I915_WRITE(RENCLK_GATE_D2, 0);
5837 } else if (IS_GEN3(dev)) {
5838 u32 dstate = I915_READ(D_STATE);
5839
5840 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5841 DSTATE_DOT_CLOCK_GATING;
5842 I915_WRITE(D_STATE, dstate);
5843 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5844 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5845 } else if (IS_I830(dev)) {
5846 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5847 }
5848
5849 /*
5850 * GPU can automatically power down the render unit if given a page
5851 * to save state.
5852 */
5853 if (IS_IRONLAKE_M(dev)) {
5854 if (dev_priv->renderctx == NULL)
5855 dev_priv->renderctx = intel_alloc_context_page(dev);
5856 if (dev_priv->renderctx) {
5857 struct drm_i915_gem_object *obj_priv;
5858 obj_priv = to_intel_bo(dev_priv->renderctx);
5859 if (obj_priv) {
5860 BEGIN_LP_RING(4);
5861 OUT_RING(MI_SET_CONTEXT);
5862 OUT_RING(obj_priv->gtt_offset |
5863 MI_MM_SPACE_GTT |
5864 MI_SAVE_EXT_STATE_EN |
5865 MI_RESTORE_EXT_STATE_EN |
5866 MI_RESTORE_INHIBIT);
5867 OUT_RING(MI_NOOP);
5868 OUT_RING(MI_FLUSH);
5869 ADVANCE_LP_RING();
5870 }
5871 } else
5872 DRM_DEBUG_KMS("Failed to allocate render context."
5873 "Disable RC6\n");
5874 }
5875
5876 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5877 struct drm_i915_gem_object *obj_priv = NULL;
5878
5879 if (dev_priv->pwrctx) {
5880 obj_priv = to_intel_bo(dev_priv->pwrctx);
5881 } else {
5882 struct drm_gem_object *pwrctx;
5883
5884 pwrctx = intel_alloc_context_page(dev);
5885 if (pwrctx) {
5886 dev_priv->pwrctx = pwrctx;
5887 obj_priv = to_intel_bo(pwrctx);
5888 }
5889 }
5890
5891 if (obj_priv) {
5892 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5893 I915_WRITE(MCHBAR_RENDER_STANDBY,
5894 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5895 }
5896 }
5897 }
5898
5899 /* Set up chip specific display functions */
5900 static void intel_init_display(struct drm_device *dev)
5901 {
5902 struct drm_i915_private *dev_priv = dev->dev_private;
5903
5904 /* We always want a DPMS function */
5905 if (HAS_PCH_SPLIT(dev))
5906 dev_priv->display.dpms = ironlake_crtc_dpms;
5907 else
5908 dev_priv->display.dpms = i9xx_crtc_dpms;
5909
5910 if (I915_HAS_FBC(dev)) {
5911 if (IS_IRONLAKE_M(dev)) {
5912 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5913 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5914 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5915 } else if (IS_GM45(dev)) {
5916 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5917 dev_priv->display.enable_fbc = g4x_enable_fbc;
5918 dev_priv->display.disable_fbc = g4x_disable_fbc;
5919 } else if (IS_CRESTLINE(dev)) {
5920 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5921 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5922 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5923 }
5924 /* 855GM needs testing */
5925 }
5926
5927 /* Returns the core display clock speed */
5928 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5929 dev_priv->display.get_display_clock_speed =
5930 i945_get_display_clock_speed;
5931 else if (IS_I915G(dev))
5932 dev_priv->display.get_display_clock_speed =
5933 i915_get_display_clock_speed;
5934 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5935 dev_priv->display.get_display_clock_speed =
5936 i9xx_misc_get_display_clock_speed;
5937 else if (IS_I915GM(dev))
5938 dev_priv->display.get_display_clock_speed =
5939 i915gm_get_display_clock_speed;
5940 else if (IS_I865G(dev))
5941 dev_priv->display.get_display_clock_speed =
5942 i865_get_display_clock_speed;
5943 else if (IS_I85X(dev))
5944 dev_priv->display.get_display_clock_speed =
5945 i855_get_display_clock_speed;
5946 else /* 852, 830 */
5947 dev_priv->display.get_display_clock_speed =
5948 i830_get_display_clock_speed;
5949
5950 /* For FIFO watermark updates */
5951 if (HAS_PCH_SPLIT(dev)) {
5952 if (IS_IRONLAKE(dev)) {
5953 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5954 dev_priv->display.update_wm = ironlake_update_wm;
5955 else {
5956 DRM_DEBUG_KMS("Failed to get proper latency. "
5957 "Disable CxSR\n");
5958 dev_priv->display.update_wm = NULL;
5959 }
5960 } else
5961 dev_priv->display.update_wm = NULL;
5962 } else if (IS_PINEVIEW(dev)) {
5963 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5964 dev_priv->is_ddr3,
5965 dev_priv->fsb_freq,
5966 dev_priv->mem_freq)) {
5967 DRM_INFO("failed to find known CxSR latency "
5968 "(found ddr%s fsb freq %d, mem freq %d), "
5969 "disabling CxSR\n",
5970 (dev_priv->is_ddr3 == 1) ? "3": "2",
5971 dev_priv->fsb_freq, dev_priv->mem_freq);
5972 /* Disable CxSR and never update its watermark again */
5973 pineview_disable_cxsr(dev);
5974 dev_priv->display.update_wm = NULL;
5975 } else
5976 dev_priv->display.update_wm = pineview_update_wm;
5977 } else if (IS_G4X(dev))
5978 dev_priv->display.update_wm = g4x_update_wm;
5979 else if (IS_GEN4(dev))
5980 dev_priv->display.update_wm = i965_update_wm;
5981 else if (IS_GEN3(dev)) {
5982 dev_priv->display.update_wm = i9xx_update_wm;
5983 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5984 } else if (IS_I85X(dev)) {
5985 dev_priv->display.update_wm = i9xx_update_wm;
5986 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5987 } else {
5988 dev_priv->display.update_wm = i830_update_wm;
5989 if (IS_845G(dev))
5990 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5991 else
5992 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5993 }
5994 }
5995
5996 /*
5997 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5998 * resume, or other times. This quirk makes sure that's the case for
5999 * affected systems.
6000 */
6001 static void quirk_pipea_force (struct drm_device *dev)
6002 {
6003 struct drm_i915_private *dev_priv = dev->dev_private;
6004
6005 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6006 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6007 }
6008
6009 struct intel_quirk {
6010 int device;
6011 int subsystem_vendor;
6012 int subsystem_device;
6013 void (*hook)(struct drm_device *dev);
6014 };
6015
6016 struct intel_quirk intel_quirks[] = {
6017 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6018 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6019 /* HP Mini needs pipe A force quirk (LP: #322104) */
6020 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6021
6022 /* Thinkpad R31 needs pipe A force quirk */
6023 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6024 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6025 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6026
6027 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6028 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6029 /* ThinkPad X40 needs pipe A force quirk */
6030
6031 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6032 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6033
6034 /* 855 & before need to leave pipe A & dpll A up */
6035 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6036 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6037 };
6038
6039 static void intel_init_quirks(struct drm_device *dev)
6040 {
6041 struct pci_dev *d = dev->pdev;
6042 int i;
6043
6044 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6045 struct intel_quirk *q = &intel_quirks[i];
6046
6047 if (d->device == q->device &&
6048 (d->subsystem_vendor == q->subsystem_vendor ||
6049 q->subsystem_vendor == PCI_ANY_ID) &&
6050 (d->subsystem_device == q->subsystem_device ||
6051 q->subsystem_device == PCI_ANY_ID))
6052 q->hook(dev);
6053 }
6054 }
6055
6056 /* Disable the VGA plane that we never use */
6057 static void i915_disable_vga(struct drm_device *dev)
6058 {
6059 struct drm_i915_private *dev_priv = dev->dev_private;
6060 u8 sr1;
6061 u32 vga_reg;
6062
6063 if (HAS_PCH_SPLIT(dev))
6064 vga_reg = CPU_VGACNTRL;
6065 else
6066 vga_reg = VGACNTRL;
6067
6068 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6069 outb(1, VGA_SR_INDEX);
6070 sr1 = inb(VGA_SR_DATA);
6071 outb(sr1 | 1<<5, VGA_SR_DATA);
6072 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6073 udelay(300);
6074
6075 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6076 POSTING_READ(vga_reg);
6077 }
6078
6079 void intel_modeset_init(struct drm_device *dev)
6080 {
6081 struct drm_i915_private *dev_priv = dev->dev_private;
6082 int i;
6083
6084 drm_mode_config_init(dev);
6085
6086 dev->mode_config.min_width = 0;
6087 dev->mode_config.min_height = 0;
6088
6089 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6090
6091 intel_init_quirks(dev);
6092
6093 intel_init_display(dev);
6094
6095 if (IS_GEN2(dev)) {
6096 dev->mode_config.max_width = 2048;
6097 dev->mode_config.max_height = 2048;
6098 } else if (IS_GEN3(dev)) {
6099 dev->mode_config.max_width = 4096;
6100 dev->mode_config.max_height = 4096;
6101 } else {
6102 dev->mode_config.max_width = 8192;
6103 dev->mode_config.max_height = 8192;
6104 }
6105
6106 /* set memory base */
6107 if (IS_GEN2(dev))
6108 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6109 else
6110 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6111
6112 if (IS_MOBILE(dev) || !IS_GEN2(dev))
6113 dev_priv->num_pipe = 2;
6114 else
6115 dev_priv->num_pipe = 1;
6116 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6117 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6118
6119 for (i = 0; i < dev_priv->num_pipe; i++) {
6120 intel_crtc_init(dev, i);
6121 }
6122
6123 intel_setup_outputs(dev);
6124
6125 intel_init_clock_gating(dev);
6126
6127 /* Just disable it once at startup */
6128 i915_disable_vga(dev);
6129
6130 if (IS_IRONLAKE_M(dev)) {
6131 ironlake_enable_drps(dev);
6132 intel_init_emon(dev);
6133 }
6134
6135 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6136 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6137 (unsigned long)dev);
6138
6139 intel_setup_overlay(dev);
6140 }
6141
6142 void intel_modeset_cleanup(struct drm_device *dev)
6143 {
6144 struct drm_i915_private *dev_priv = dev->dev_private;
6145 struct drm_crtc *crtc;
6146 struct intel_crtc *intel_crtc;
6147
6148 drm_kms_helper_poll_fini(dev);
6149 mutex_lock(&dev->struct_mutex);
6150
6151 intel_unregister_dsm_handler();
6152
6153
6154 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6155 /* Skip inactive CRTCs */
6156 if (!crtc->fb)
6157 continue;
6158
6159 intel_crtc = to_intel_crtc(crtc);
6160 intel_increase_pllclock(crtc);
6161 }
6162
6163 if (dev_priv->display.disable_fbc)
6164 dev_priv->display.disable_fbc(dev);
6165
6166 if (dev_priv->renderctx) {
6167 struct drm_i915_gem_object *obj_priv;
6168
6169 obj_priv = to_intel_bo(dev_priv->renderctx);
6170 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6171 I915_READ(CCID);
6172 i915_gem_object_unpin(dev_priv->renderctx);
6173 drm_gem_object_unreference(dev_priv->renderctx);
6174 }
6175
6176 if (dev_priv->pwrctx) {
6177 struct drm_i915_gem_object *obj_priv;
6178
6179 obj_priv = to_intel_bo(dev_priv->pwrctx);
6180 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6181 I915_READ(PWRCTXA);
6182 i915_gem_object_unpin(dev_priv->pwrctx);
6183 drm_gem_object_unreference(dev_priv->pwrctx);
6184 }
6185
6186 if (IS_IRONLAKE_M(dev))
6187 ironlake_disable_drps(dev);
6188
6189 mutex_unlock(&dev->struct_mutex);
6190
6191 /* Disable the irq before mode object teardown, for the irq might
6192 * enqueue unpin/hotplug work. */
6193 drm_irq_uninstall(dev);
6194 cancel_work_sync(&dev_priv->hotplug_work);
6195
6196 /* Shut off idle work before the crtcs get freed. */
6197 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6198 intel_crtc = to_intel_crtc(crtc);
6199 del_timer_sync(&intel_crtc->idle_timer);
6200 }
6201 del_timer_sync(&dev_priv->idle_timer);
6202 cancel_work_sync(&dev_priv->idle_work);
6203
6204 drm_mode_config_cleanup(dev);
6205 }
6206
6207 /*
6208 * Return which encoder is currently attached for connector.
6209 */
6210 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6211 {
6212 return &intel_attached_encoder(connector)->base;
6213 }
6214
6215 void intel_connector_attach_encoder(struct intel_connector *connector,
6216 struct intel_encoder *encoder)
6217 {
6218 connector->encoder = encoder;
6219 drm_mode_connector_attach_encoder(&connector->base,
6220 &encoder->base);
6221 }
6222
6223 /*
6224 * set vga decode state - true == enable VGA decode
6225 */
6226 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6227 {
6228 struct drm_i915_private *dev_priv = dev->dev_private;
6229 u16 gmch_ctrl;
6230
6231 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6232 if (state)
6233 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6234 else
6235 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6236 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6237 return 0;
6238 }
Linux with added FPC-III support