drivers/net/wireless/b43/phy_common.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   Common PHY routines
   5
   6   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
   7   Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
   8   Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
   9   Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
  10   Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  11
  12   This program is free software; you can redistribute it and/or modify
  13   it under the terms of the GNU General Public License as published by
  14   the Free Software Foundation; either version 2 of the License, or
  15   (at your option) any later version.
  16
  17   This program is distributed in the hope that it will be useful,
  18   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20   GNU General Public License for more details.
  21
  22   You should have received a copy of the GNU General Public License
  23   along with this program; see the file COPYING.  If not, write to
  24   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  25   Boston, MA 02110-1301, USA.
  26
  27 */
  28
  29 #include "phy_common.h"
  30 #include "phy_g.h"
  31 #include "phy_a.h"
  32 #include "phy_n.h"
  33 #include "phy_lp.h"
  34 #include "phy_ht.h"
  35 #include "phy_lcn.h"
  36 #include "b43.h"
  37 #include "main.h"
  38
  39
  40 int b43_phy_allocate(struct b43_wldev *dev)
  41 {
  42         struct b43_phy *phy = &(dev->phy);
  43         int err;
  44
  45         phy->ops = NULL;
  46
  47         switch (phy->type) {
  48         case B43_PHYTYPE_G:
  49 #ifdef CONFIG_B43_PHY_G
  50                 phy->ops = &b43_phyops_g;
  51 #endif
  52                 break;
  53         case B43_PHYTYPE_N:
  54 #ifdef CONFIG_B43_PHY_N
  55                 phy->ops = &b43_phyops_n;
  56 #endif
  57                 break;
  58         case B43_PHYTYPE_LP:
  59 #ifdef CONFIG_B43_PHY_LP
  60                 phy->ops = &b43_phyops_lp;
  61 #endif
  62                 break;
  63         case B43_PHYTYPE_HT:
  64 #ifdef CONFIG_B43_PHY_HT
  65                 phy->ops = &b43_phyops_ht;
  66 #endif
  67                 break;
  68         case B43_PHYTYPE_LCN:
  69 #ifdef CONFIG_B43_PHY_LCN
  70                 phy->ops = &b43_phyops_lcn;
  71 #endif
  72                 break;
  73         }
  74         if (B43_WARN_ON(!phy->ops))
  75                 return -ENODEV;
  76
  77         err = phy->ops->allocate(dev);
  78         if (err)
  79                 phy->ops = NULL;
  80
  81         return err;
  82 }
  83
  84 void b43_phy_free(struct b43_wldev *dev)
  85 {
  86         dev->phy.ops->free(dev);
  87         dev->phy.ops = NULL;
  88 }
  89
  90 int b43_phy_init(struct b43_wldev *dev)
  91 {
  92         struct b43_phy *phy = &dev->phy;
  93         const struct b43_phy_operations *ops = phy->ops;
  94         int err;
  95
  96         /* During PHY init we need to use some channel. On the first init this
  97          * function is called *before* b43_op_config, so our pointer is NULL.
  98          */
  99         if (!phy->chandef) {
 100                 phy->chandef = &dev->wl->hw->conf.chandef;
 101                 phy->channel = phy->chandef->chan->hw_value;
 102         }
 103
 104         phy->ops->switch_analog(dev, true);
 105         b43_software_rfkill(dev, false);
 106
 107         err = ops->init(dev);
 108         if (err) {
 109                 b43err(dev->wl, "PHY init failed\n");
 110                 goto err_block_rf;
 111         }
 112         phy->do_full_init = false;
 113
 114         err = b43_switch_channel(dev, phy->channel);
 115         if (err) {
 116                 b43err(dev->wl, "PHY init: Channel switch to default failed\n");
 117                 goto err_phy_exit;
 118         }
 119
 120         return 0;
 121
 122 err_phy_exit:
 123         phy->do_full_init = true;
 124         if (ops->exit)
 125                 ops->exit(dev);
 126 err_block_rf:
 127         b43_software_rfkill(dev, true);
 128
 129         return err;
 130 }
 131
 132 void b43_phy_exit(struct b43_wldev *dev)
 133 {
 134         const struct b43_phy_operations *ops = dev->phy.ops;
 135
 136         b43_software_rfkill(dev, true);
 137         dev->phy.do_full_init = true;
 138         if (ops->exit)
 139                 ops->exit(dev);
 140 }
 141
 142 bool b43_has_hardware_pctl(struct b43_wldev *dev)
 143 {
 144         if (!dev->phy.hardware_power_control)
 145                 return false;
 146         if (!dev->phy.ops->supports_hwpctl)
 147                 return false;
 148         return dev->phy.ops->supports_hwpctl(dev);
 149 }
 150
 151 void b43_radio_lock(struct b43_wldev *dev)
 152 {
 153         u32 macctl;
 154
 155 #if B43_DEBUG
 156         B43_WARN_ON(dev->phy.radio_locked);
 157         dev->phy.radio_locked = true;
 158 #endif
 159
 160         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 161         macctl |= B43_MACCTL_RADIOLOCK;
 162         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 163         /* Commit the write and wait for the firmware
 164          * to finish any radio register access. */
 165         b43_read32(dev, B43_MMIO_MACCTL);
 166         udelay(10);
 167 }
 168
 169 void b43_radio_unlock(struct b43_wldev *dev)
 170 {
 171         u32 macctl;
 172
 173 #if B43_DEBUG
 174         B43_WARN_ON(!dev->phy.radio_locked);
 175         dev->phy.radio_locked = false;
 176 #endif
 177
 178         /* Commit any write */
 179         b43_read16(dev, B43_MMIO_PHY_VER);
 180         /* unlock */
 181         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 182         macctl &= ~B43_MACCTL_RADIOLOCK;
 183         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 184 }
 185
 186 void b43_phy_lock(struct b43_wldev *dev)
 187 {
 188 #if B43_DEBUG
 189         B43_WARN_ON(dev->phy.phy_locked);
 190         dev->phy.phy_locked = true;
 191 #endif
 192         B43_WARN_ON(dev->dev->core_rev < 3);
 193
 194         if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
 195                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
 196 }
 197
 198 void b43_phy_unlock(struct b43_wldev *dev)
 199 {
 200 #if B43_DEBUG
 201         B43_WARN_ON(!dev->phy.phy_locked);
 202         dev->phy.phy_locked = false;
 203 #endif
 204         B43_WARN_ON(dev->dev->core_rev < 3);
 205
 206         if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
 207                 b43_power_saving_ctl_bits(dev, 0);
 208 }
 209
 210 static inline void assert_mac_suspended(struct b43_wldev *dev)
 211 {
 212         if (!B43_DEBUG)
 213                 return;
 214         if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
 215             (dev->mac_suspended <= 0)) {
 216                 b43dbg(dev->wl, "PHY/RADIO register access with "
 217                        "enabled MAC.\n");
 218                 dump_stack();
 219         }
 220 }
 221
 222 u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
 223 {
 224         assert_mac_suspended(dev);
 225         dev->phy.writes_counter = 0;
 226         return dev->phy.ops->radio_read(dev, reg);
 227 }
 228
 229 void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
 230 {
 231         assert_mac_suspended(dev);
 232         if (b43_bus_host_is_pci(dev->dev) &&
 233             ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
 234                 b43_read32(dev, B43_MMIO_MACCTL);
 235                 dev->phy.writes_counter = 1;
 236         }
 237         dev->phy.ops->radio_write(dev, reg, value);
 238 }
 239
 240 void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
 241 {
 242         b43_radio_write16(dev, offset,
 243                           b43_radio_read16(dev, offset) & mask);
 244 }
 245
 246 void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
 247 {
 248         b43_radio_write16(dev, offset,
 249                           b43_radio_read16(dev, offset) | set);
 250 }
 251
 252 void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
 253 {
 254         b43_radio_write16(dev, offset,
 255                           (b43_radio_read16(dev, offset) & mask) | set);
 256 }
 257
 258 bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask,
 259                           u16 value, int delay, int timeout)
 260 {
 261         u16 val;
 262         int i;
 263
 264         for (i = 0; i < timeout; i += delay) {
 265                 val = b43_radio_read(dev, offset);
 266                 if ((val & mask) == value)
 267                         return true;
 268                 udelay(delay);
 269         }
 270         return false;
 271 }
 272
 273 u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
 274 {
 275         assert_mac_suspended(dev);
 276         dev->phy.writes_counter = 0;
 277
 278         if (dev->phy.ops->phy_read)
 279                 return dev->phy.ops->phy_read(dev, reg);
 280
 281         b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
 282         return b43_read16(dev, B43_MMIO_PHY_DATA);
 283 }
 284
 285 void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
 286 {
 287         assert_mac_suspended(dev);
 288         if (b43_bus_host_is_pci(dev->dev) &&
 289             ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
 290                 b43_read16(dev, B43_MMIO_PHY_VER);
 291                 dev->phy.writes_counter = 1;
 292         }
 293
 294         if (dev->phy.ops->phy_write)
 295                 return dev->phy.ops->phy_write(dev, reg, value);
 296
 297         b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
 298         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 299 }
 300
 301 void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
 302 {
 303         b43_phy_write(dev, destreg, b43_phy_read(dev, srcreg));
 304 }
 305
 306 void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
 307 {
 308         if (dev->phy.ops->phy_maskset) {
 309                 assert_mac_suspended(dev);
 310                 dev->phy.ops->phy_maskset(dev, offset, mask, 0);
 311         } else {
 312                 b43_phy_write(dev, offset,
 313                               b43_phy_read(dev, offset) & mask);
 314         }
 315 }
 316
 317 void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
 318 {
 319         if (dev->phy.ops->phy_maskset) {
 320                 assert_mac_suspended(dev);
 321                 dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
 322         } else {
 323                 b43_phy_write(dev, offset,
 324                               b43_phy_read(dev, offset) | set);
 325         }
 326 }
 327
 328 void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
 329 {
 330         if (dev->phy.ops->phy_maskset) {
 331                 assert_mac_suspended(dev);
 332                 dev->phy.ops->phy_maskset(dev, offset, mask, set);
 333         } else {
 334                 b43_phy_write(dev, offset,
 335                               (b43_phy_read(dev, offset) & mask) | set);
 336         }
 337 }
 338
 339 void b43_phy_put_into_reset(struct b43_wldev *dev)
 340 {
 341         u32 tmp;
 342
 343         switch (dev->dev->bus_type) {
 344 #ifdef CONFIG_B43_BCMA
 345         case B43_BUS_BCMA:
 346                 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
 347                 tmp &= ~B43_BCMA_IOCTL_GMODE;
 348                 tmp |= B43_BCMA_IOCTL_PHY_RESET;
 349                 tmp |= BCMA_IOCTL_FGC;
 350                 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
 351                 udelay(1);
 352
 353                 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
 354                 tmp &= ~BCMA_IOCTL_FGC;
 355                 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
 356                 udelay(1);
 357                 break;
 358 #endif
 359 #ifdef CONFIG_B43_SSB
 360         case B43_BUS_SSB:
 361                 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
 362                 tmp &= ~B43_TMSLOW_GMODE;
 363                 tmp |= B43_TMSLOW_PHYRESET;
 364                 tmp |= SSB_TMSLOW_FGC;
 365                 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
 366                 usleep_range(1000, 2000);
 367
 368                 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
 369                 tmp &= ~SSB_TMSLOW_FGC;
 370                 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
 371                 usleep_range(1000, 2000);
 372
 373                 break;
 374 #endif
 375         }
 376 }
 377
 378 void b43_phy_take_out_of_reset(struct b43_wldev *dev)
 379 {
 380         u32 tmp;
 381
 382         switch (dev->dev->bus_type) {
 383 #ifdef CONFIG_B43_BCMA
 384         case B43_BUS_BCMA:
 385                 /* Unset reset bit (with forcing clock) */
 386                 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
 387                 tmp &= ~B43_BCMA_IOCTL_PHY_RESET;
 388                 tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
 389                 tmp |= BCMA_IOCTL_FGC;
 390                 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
 391                 udelay(1);
 392
 393                 /* Do not force clock anymore */
 394                 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
 395                 tmp &= ~BCMA_IOCTL_FGC;
 396                 tmp |= B43_BCMA_IOCTL_PHY_CLKEN;
 397                 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
 398                 udelay(1);
 399                 break;
 400 #endif
 401 #ifdef CONFIG_B43_SSB
 402         case B43_BUS_SSB:
 403                 /* Unset reset bit (with forcing clock) */
 404                 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
 405                 tmp &= ~B43_TMSLOW_PHYRESET;
 406                 tmp &= ~B43_TMSLOW_PHYCLKEN;
 407                 tmp |= SSB_TMSLOW_FGC;
 408                 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
 409                 ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
 410                 usleep_range(1000, 2000);
 411
 412                 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
 413                 tmp &= ~SSB_TMSLOW_FGC;
 414                 tmp |= B43_TMSLOW_PHYCLKEN;
 415                 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
 416                 ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
 417                 usleep_range(1000, 2000);
 418                 break;
 419 #endif
 420         }
 421 }
 422
 423 int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
 424 {
 425         struct b43_phy *phy = &(dev->phy);
 426         u16 channelcookie, savedcookie;
 427         int err;
 428
 429         /* First we set the channel radio code to prevent the
 430          * firmware from sending ghost packets.
 431          */
 432         channelcookie = new_channel;
 433         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
 434                 channelcookie |= B43_SHM_SH_CHAN_5GHZ;
 435         /* FIXME: set 40Mhz flag if required */
 436         if (0)
 437                 channelcookie |= B43_SHM_SH_CHAN_40MHZ;
 438         savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
 439         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
 440
 441         /* Now try to switch the PHY hardware channel. */
 442         err = phy->ops->switch_channel(dev, new_channel);
 443         if (err)
 444                 goto err_restore_cookie;
 445
 446         /* Wait for the radio to tune to the channel and stabilize. */
 447         msleep(8);
 448
 449         return 0;
 450
 451 err_restore_cookie:
 452         b43_shm_write16(dev, B43_SHM_SHARED,
 453                         B43_SHM_SH_CHAN, savedcookie);
 454
 455         return err;
 456 }
 457
 458 void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
 459 {
 460         struct b43_phy *phy = &dev->phy;
 461
 462         b43_mac_suspend(dev);
 463         phy->ops->software_rfkill(dev, blocked);
 464         phy->radio_on = !blocked;
 465         b43_mac_enable(dev);
 466 }
 467
 468 /**
 469  * b43_phy_txpower_adjust_work - TX power workqueue.
 470  *
 471  * Workqueue for updating the TX power parameters in hardware.
 472  */
 473 void b43_phy_txpower_adjust_work(struct work_struct *work)
 474 {
 475         struct b43_wl *wl = container_of(work, struct b43_wl,
 476                                          txpower_adjust_work);
 477         struct b43_wldev *dev;
 478
 479         mutex_lock(&wl->mutex);
 480         dev = wl->current_dev;
 481
 482         if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
 483                 dev->phy.ops->adjust_txpower(dev);
 484
 485         mutex_unlock(&wl->mutex);
 486 }
 487
 488 void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
 489 {
 490         struct b43_phy *phy = &dev->phy;
 491         unsigned long now = jiffies;
 492         enum b43_txpwr_result result;
 493
 494         if (!(flags & B43_TXPWR_IGNORE_TIME)) {
 495                 /* Check if it's time for a TXpower check. */
 496                 if (time_before(now, phy->next_txpwr_check_time))
 497                         return; /* Not yet */
 498         }
 499         /* The next check will be needed in two seconds, or later. */
 500         phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
 501
 502         if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
 503             (dev->dev->board_type == SSB_BOARD_BU4306))
 504                 return; /* No software txpower adjustment needed */
 505
 506         result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
 507         if (result == B43_TXPWR_RES_DONE)
 508                 return; /* We are done. */
 509         B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
 510         B43_WARN_ON(phy->ops->adjust_txpower == NULL);
 511
 512         /* We must adjust the transmission power in hardware.
 513          * Schedule b43_phy_txpower_adjust_work(). */
 514         ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
 515 }
 516
 517 int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
 518 {
 519         const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
 520         unsigned int a, b, c, d;
 521         unsigned int average;
 522         u32 tmp;
 523
 524         tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
 525         a = tmp & 0xFF;
 526         b = (tmp >> 8) & 0xFF;
 527         c = (tmp >> 16) & 0xFF;
 528         d = (tmp >> 24) & 0xFF;
 529         if (a == 0 || a == B43_TSSI_MAX ||
 530             b == 0 || b == B43_TSSI_MAX ||
 531             c == 0 || c == B43_TSSI_MAX ||
 532             d == 0 || d == B43_TSSI_MAX)
 533                 return -ENOENT;
 534         /* The values are OK. Clear them. */
 535         tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
 536               (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
 537         b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
 538
 539         if (is_ofdm) {
 540                 a = (a + 32) & 0x3F;
 541                 b = (b + 32) & 0x3F;
 542                 c = (c + 32) & 0x3F;
 543                 d = (d + 32) & 0x3F;
 544         }
 545
 546         /* Get the average of the values with 0.5 added to each value. */
 547         average = (a + b + c + d + 2) / 4;
 548         if (is_ofdm) {
 549                 /* Adjust for CCK-boost */
 550                 if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1)
 551                     & B43_HF_CCKBOOST)
 552                         average = (average >= 13) ? (average - 13) : 0;
 553         }
 554
 555         return average;
 556 }
 557
 558 void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
 559 {
 560         b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
 561 }
 562
 563
 564 bool b43_is_40mhz(struct b43_wldev *dev)
 565 {
 566         return dev->phy.chandef->width == NL80211_CHAN_WIDTH_40;
 567 }
 568
 569 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 570 void b43_phy_force_clock(struct b43_wldev *dev, bool force)
 571 {
 572         u32 tmp;
 573
 574         WARN_ON(dev->phy.type != B43_PHYTYPE_N &&
 575                 dev->phy.type != B43_PHYTYPE_HT);
 576
 577         switch (dev->dev->bus_type) {
 578 #ifdef CONFIG_B43_BCMA
 579         case B43_BUS_BCMA:
 580                 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
 581                 if (force)
 582                         tmp |= BCMA_IOCTL_FGC;
 583                 else
 584                         tmp &= ~BCMA_IOCTL_FGC;
 585                 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
 586                 break;
 587 #endif
 588 #ifdef CONFIG_B43_SSB
 589         case B43_BUS_SSB:
 590                 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
 591                 if (force)
 592                         tmp |= SSB_TMSLOW_FGC;
 593                 else
 594                         tmp &= ~SSB_TMSLOW_FGC;
 595                 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
 596                 break;
 597 #endif
 598         }
 599 }
 600
 601 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
 602 struct b43_c32 b43_cordic(int theta)
 603 {
 604         static const u32 arctg[] = {
 605                 2949120, 1740967, 919879, 466945, 234379, 117304,
 606                   58666,   29335,  14668,   7334,   3667,   1833,
 607                     917,     458,    229,    115,     57,     29,
 608         };
 609         u8 i;
 610         s32 tmp;
 611         s8 signx = 1;
 612         u32 angle = 0;
 613         struct b43_c32 ret = { .i = 39797, .q = 0, };
 614
 615         while (theta > (180 << 16))
 616                 theta -= (360 << 16);
 617         while (theta < -(180 << 16))
 618                 theta += (360 << 16);
 619
 620         if (theta > (90 << 16)) {
 621                 theta -= (180 << 16);
 622                 signx = -1;
 623         } else if (theta < -(90 << 16)) {
 624                 theta += (180 << 16);
 625                 signx = -1;
 626         }
 627
 628         for (i = 0; i <= 17; i++) {
 629                 if (theta > angle) {
 630                         tmp = ret.i - (ret.q >> i);
 631                         ret.q += ret.i >> i;
 632                         ret.i = tmp;
 633                         angle += arctg[i];
 634                 } else {
 635                         tmp = ret.i + (ret.q >> i);
 636                         ret.q -= ret.i >> i;
 637                         ret.i = tmp;
 638                         angle -= arctg[i];
 639                 }
 640         }
 641
 642         ret.i *= signx;
 643         ret.q *= signx;
 644
 645         return ret;
 646 }