drivers/net/wireless/mwifiex/pcie.h

   1 /* @file mwifiex_pcie.h
   2  *
   3  * @brief This file contains definitions for PCI-E interface.
   4  * driver.
   5  *
   6  * Copyright (C) 2011-2014, Marvell International Ltd.
   7  *
   8  * This software file (the "File") is distributed by Marvell International
   9  * Ltd. under the terms of the GNU General Public License Version 2, June 1991
  10  * (the "License").  You may use, redistribute and/or modify this File in
  11  * accordance with the terms and conditions of the License, a copy of which
  12  * is available by writing to the Free Software Foundation, Inc.,
  13  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
  14  * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
  15  *
  16  * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
  19  * this warranty disclaimer.
  20  */
  21
  22 #ifndef _MWIFIEX_PCIE_H
  23 #define _MWIFIEX_PCIE_H
  24
  25 #include    <linux/pci.h>
  26 #include    <linux/pcieport_if.h>
  27 #include    <linux/interrupt.h>
  28
  29 #include    "main.h"
  30
  31 #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
  32 #define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin"
  33
  34 #define PCIE_VENDOR_ID_MARVELL              (0x11ab)
  35 #define PCIE_DEVICE_ID_MARVELL_88W8766P         (0x2b30)
  36 #define PCIE_DEVICE_ID_MARVELL_88W8897          (0x2b38)
  37
  38 /* Constants for Buffer Descriptor (BD) rings */
  39 #define MWIFIEX_MAX_TXRX_BD                     0x20
  40 #define MWIFIEX_TXBD_MASK                       0x3F
  41 #define MWIFIEX_RXBD_MASK                       0x3F
  42
  43 #define MWIFIEX_MAX_EVT_BD                      0x08
  44 #define MWIFIEX_EVTBD_MASK                      0x0f
  45
  46 /* PCIE INTERNAL REGISTERS */
  47 #define PCIE_SCRATCH_0_REG                              0xC10
  48 #define PCIE_SCRATCH_1_REG                              0xC14
  49 #define PCIE_CPU_INT_EVENT                              0xC18
  50 #define PCIE_CPU_INT_STATUS                             0xC1C
  51 #define PCIE_HOST_INT_STATUS                            0xC30
  52 #define PCIE_HOST_INT_MASK                              0xC34
  53 #define PCIE_HOST_INT_STATUS_MASK                       0xC3C
  54 #define PCIE_SCRATCH_2_REG                              0xC40
  55 #define PCIE_SCRATCH_3_REG                              0xC44
  56 #define PCIE_SCRATCH_4_REG                              0xCD0
  57 #define PCIE_SCRATCH_5_REG                              0xCD4
  58 #define PCIE_SCRATCH_6_REG                              0xCD8
  59 #define PCIE_SCRATCH_7_REG                              0xCDC
  60 #define PCIE_SCRATCH_8_REG                              0xCE0
  61 #define PCIE_SCRATCH_9_REG                              0xCE4
  62 #define PCIE_SCRATCH_10_REG                             0xCE8
  63 #define PCIE_SCRATCH_11_REG                             0xCEC
  64 #define PCIE_SCRATCH_12_REG                             0xCF0
  65 #define PCIE_RD_DATA_PTR_Q0_Q1                          0xC08C
  66 #define PCIE_WR_DATA_PTR_Q0_Q1                          0xC05C
  67
  68 #define CPU_INTR_DNLD_RDY                               BIT(0)
  69 #define CPU_INTR_DOOR_BELL                              BIT(1)
  70 #define CPU_INTR_SLEEP_CFM_DONE                 BIT(2)
  71 #define CPU_INTR_RESET                                  BIT(3)
  72 #define CPU_INTR_EVENT_DONE                             BIT(5)
  73
  74 #define HOST_INTR_DNLD_DONE                             BIT(0)
  75 #define HOST_INTR_UPLD_RDY                              BIT(1)
  76 #define HOST_INTR_CMD_DONE                              BIT(2)
  77 #define HOST_INTR_EVENT_RDY                             BIT(3)
  78 #define HOST_INTR_MASK                                  (HOST_INTR_DNLD_DONE | \
  79                                                          HOST_INTR_UPLD_RDY  | \
  80                                                          HOST_INTR_CMD_DONE  | \
  81                                                          HOST_INTR_EVENT_RDY)
  82
  83 #define MWIFIEX_BD_FLAG_ROLLOVER_IND                    BIT(7)
  84 #define MWIFIEX_BD_FLAG_FIRST_DESC                      BIT(0)
  85 #define MWIFIEX_BD_FLAG_LAST_DESC                       BIT(1)
  86 #define MWIFIEX_BD_FLAG_SOP                             BIT(0)
  87 #define MWIFIEX_BD_FLAG_EOP                             BIT(1)
  88 #define MWIFIEX_BD_FLAG_XS_SOP                          BIT(2)
  89 #define MWIFIEX_BD_FLAG_XS_EOP                          BIT(3)
  90 #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND                BIT(7)
  91 #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND                 BIT(10)
  92 #define MWIFIEX_BD_FLAG_TX_START_PTR                    BIT(16)
  93 #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND                 BIT(26)
  94
  95 /* Max retry number of command write */
  96 #define MAX_WRITE_IOMEM_RETRY                           2
  97 /* Define PCIE block size for firmware download */
  98 #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD         256
  99 /* FW awake cookie after FW ready */
 100 #define FW_AWAKE_COOKIE                                         (0xAA55AA55)
 101 #define MWIFIEX_DEF_SLEEP_COOKIE                        0xBEEFBEEF
 102 #define MWIFIEX_MAX_DELAY_COUNT                         5
 103
 104 struct mwifiex_pcie_card_reg {
 105         u16 cmd_addr_lo;
 106         u16 cmd_addr_hi;
 107         u16 fw_status;
 108         u16 cmd_size;
 109         u16 cmdrsp_addr_lo;
 110         u16 cmdrsp_addr_hi;
 111         u16 tx_rdptr;
 112         u16 tx_wrptr;
 113         u16 rx_rdptr;
 114         u16 rx_wrptr;
 115         u16 evt_rdptr;
 116         u16 evt_wrptr;
 117         u16 drv_rdy;
 118         u16 tx_start_ptr;
 119         u32 tx_mask;
 120         u32 tx_wrap_mask;
 121         u32 rx_mask;
 122         u32 rx_wrap_mask;
 123         u32 tx_rollover_ind;
 124         u32 rx_rollover_ind;
 125         u32 evt_rollover_ind;
 126         u8 ring_flag_sop;
 127         u8 ring_flag_eop;
 128         u8 ring_flag_xs_sop;
 129         u8 ring_flag_xs_eop;
 130         u32 ring_tx_start_ptr;
 131         u8 pfu_enabled;
 132         u8 sleep_cookie;
 133         u16 fw_dump_ctrl;
 134         u16 fw_dump_start;
 135         u16 fw_dump_end;
 136 };
 137
 138 static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
 139         .cmd_addr_lo = PCIE_SCRATCH_0_REG,
 140         .cmd_addr_hi = PCIE_SCRATCH_1_REG,
 141         .cmd_size = PCIE_SCRATCH_2_REG,
 142         .fw_status = PCIE_SCRATCH_3_REG,
 143         .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
 144         .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
 145         .tx_rdptr = PCIE_SCRATCH_6_REG,
 146         .tx_wrptr = PCIE_SCRATCH_7_REG,
 147         .rx_rdptr = PCIE_SCRATCH_8_REG,
 148         .rx_wrptr = PCIE_SCRATCH_9_REG,
 149         .evt_rdptr = PCIE_SCRATCH_10_REG,
 150         .evt_wrptr = PCIE_SCRATCH_11_REG,
 151         .drv_rdy = PCIE_SCRATCH_12_REG,
 152         .tx_start_ptr = 0,
 153         .tx_mask = MWIFIEX_TXBD_MASK,
 154         .tx_wrap_mask = 0,
 155         .rx_mask = MWIFIEX_RXBD_MASK,
 156         .rx_wrap_mask = 0,
 157         .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
 158         .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
 159         .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
 160         .ring_flag_sop = 0,
 161         .ring_flag_eop = 0,
 162         .ring_flag_xs_sop = 0,
 163         .ring_flag_xs_eop = 0,
 164         .ring_tx_start_ptr = 0,
 165         .pfu_enabled = 0,
 166         .sleep_cookie = 1,
 167 };
 168
 169 static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
 170         .cmd_addr_lo = PCIE_SCRATCH_0_REG,
 171         .cmd_addr_hi = PCIE_SCRATCH_1_REG,
 172         .cmd_size = PCIE_SCRATCH_2_REG,
 173         .fw_status = PCIE_SCRATCH_3_REG,
 174         .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
 175         .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
 176         .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
 177         .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
 178         .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
 179         .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
 180         .evt_rdptr = PCIE_SCRATCH_10_REG,
 181         .evt_wrptr = PCIE_SCRATCH_11_REG,
 182         .drv_rdy = PCIE_SCRATCH_12_REG,
 183         .tx_start_ptr = 16,
 184         .tx_mask = 0x03FF0000,
 185         .tx_wrap_mask = 0x07FF0000,
 186         .rx_mask = 0x000003FF,
 187         .rx_wrap_mask = 0x000007FF,
 188         .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
 189         .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
 190         .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
 191         .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
 192         .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
 193         .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
 194         .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
 195         .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
 196         .pfu_enabled = 1,
 197         .sleep_cookie = 0,
 198         .fw_dump_ctrl = 0xcf4,
 199         .fw_dump_start = 0xcf8,
 200         .fw_dump_end = 0xcff
 201 };
 202
 203 struct mwifiex_pcie_device {
 204         const char *firmware;
 205         const struct mwifiex_pcie_card_reg *reg;
 206         u16 blksz_fw_dl;
 207         u16 tx_buf_size;
 208         bool supports_fw_dump;
 209 };
 210
 211 static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
 212         .firmware       = PCIE8766_DEFAULT_FW_NAME,
 213         .reg            = &mwifiex_reg_8766,
 214         .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
 215         .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
 216         .supports_fw_dump = false,
 217 };
 218
 219 static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
 220         .firmware       = PCIE8897_DEFAULT_FW_NAME,
 221         .reg            = &mwifiex_reg_8897,
 222         .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
 223         .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
 224         .supports_fw_dump = true,
 225 };
 226
 227 struct mwifiex_evt_buf_desc {
 228         u64 paddr;
 229         u16 len;
 230         u16 flags;
 231 } __packed;
 232
 233 struct mwifiex_pcie_buf_desc {
 234         u64 paddr;
 235         u16 len;
 236         u16 flags;
 237 } __packed;
 238
 239 struct mwifiex_pfu_buf_desc {
 240         u16 flags;
 241         u16 offset;
 242         u16 frag_len;
 243         u16 len;
 244         u64 paddr;
 245         u32 reserved;
 246 } __packed;
 247
 248 struct pcie_service_card {
 249         struct pci_dev *dev;
 250         struct mwifiex_adapter *adapter;
 251         struct mwifiex_pcie_device pcie;
 252
 253         u8 txbd_flush;
 254         u32 txbd_wrptr;
 255         u32 txbd_rdptr;
 256         u32 txbd_ring_size;
 257         u8 *txbd_ring_vbase;
 258         dma_addr_t txbd_ring_pbase;
 259         void *txbd_ring[MWIFIEX_MAX_TXRX_BD];
 260         struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];
 261
 262         u32 rxbd_wrptr;
 263         u32 rxbd_rdptr;
 264         u32 rxbd_ring_size;
 265         u8 *rxbd_ring_vbase;
 266         dma_addr_t rxbd_ring_pbase;
 267         void *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
 268         struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];
 269
 270         u32 evtbd_wrptr;
 271         u32 evtbd_rdptr;
 272         u32 evtbd_ring_size;
 273         u8 *evtbd_ring_vbase;
 274         dma_addr_t evtbd_ring_pbase;
 275         void *evtbd_ring[MWIFIEX_MAX_EVT_BD];
 276         struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];
 277
 278         struct sk_buff *cmd_buf;
 279         struct sk_buff *cmdrsp_buf;
 280         u8 *sleep_cookie_vbase;
 281         dma_addr_t sleep_cookie_pbase;
 282         void __iomem *pci_mmap;
 283         void __iomem *pci_mmap1;
 284 };
 285
 286 static inline int
 287 mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
 288 {
 289         const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
 290
 291         switch (card->dev->device) {
 292         case PCIE_DEVICE_ID_MARVELL_88W8766P:
 293                 if (((card->txbd_wrptr & reg->tx_mask) ==
 294                      (rdptr & reg->tx_mask)) &&
 295                     ((card->txbd_wrptr & reg->tx_rollover_ind) !=
 296                      (rdptr & reg->tx_rollover_ind)))
 297                         return 1;
 298                 break;
 299         case PCIE_DEVICE_ID_MARVELL_88W8897:
 300                 if (((card->txbd_wrptr & reg->tx_mask) ==
 301                      (rdptr & reg->tx_mask)) &&
 302                     ((card->txbd_wrptr & reg->tx_rollover_ind) ==
 303                         (rdptr & reg->tx_rollover_ind)))
 304                         return 1;
 305                 break;
 306         }
 307
 308         return 0;
 309 }
 310
 311 static inline int
 312 mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
 313 {
 314         const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
 315
 316         switch (card->dev->device) {
 317         case PCIE_DEVICE_ID_MARVELL_88W8766P:
 318                 if (((card->txbd_wrptr & reg->tx_mask) !=
 319                      (card->txbd_rdptr & reg->tx_mask)) ||
 320                     ((card->txbd_wrptr & reg->tx_rollover_ind) !=
 321                      (card->txbd_rdptr & reg->tx_rollover_ind)))
 322                         return 1;
 323                 break;
 324         case PCIE_DEVICE_ID_MARVELL_88W8897:
 325                 if (((card->txbd_wrptr & reg->tx_mask) !=
 326                      (card->txbd_rdptr & reg->tx_mask)) ||
 327                     ((card->txbd_wrptr & reg->tx_rollover_ind) ==
 328                      (card->txbd_rdptr & reg->tx_rollover_ind)))
 329                         return 1;
 330                 break;
 331         }
 332
 333         return 0;
 334 }
 335
 336 #endif /* _MWIFIEX_PCIE_H */