drivers/pci/setup-res.c

   1 /*
   2  *      drivers/pci/setup-res.c
   3  *
   4  * Extruded from code written by
   5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
   6  *      David Mosberger (davidm@cs.arizona.edu)
   7  *      David Miller (davem@redhat.com)
   8  *
   9  * Support routines for initializing a PCI subsystem.
  10  */
  11
  12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
  13
  14 /*
  15  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  16  *           Resource sorting
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/export.h>
  21 #include <linux/pci.h>
  22 #include <linux/errno.h>
  23 #include <linux/ioport.h>
  24 #include <linux/cache.h>
  25 #include <linux/slab.h>
  26 #include "pci.h"
  27
  28
  29 void pci_update_resource(struct pci_dev *dev, int resno)
  30 {
  31         struct pci_bus_region region;
  32         bool disable;
  33         u16 cmd;
  34         u32 new, check, mask;
  35         int reg;
  36         enum pci_bar_type type;
  37         struct resource *res = dev->resource + resno;
  38
  39         /*
  40          * Ignore resources for unimplemented BARs and unused resource slots
  41          * for 64 bit BARs.
  42          */
  43         if (!res->flags)
  44                 return;
  45
  46         if (res->flags & IORESOURCE_UNSET)
  47                 return;
  48
  49         /*
  50          * Ignore non-moveable resources.  This might be legacy resources for
  51          * which no functional BAR register exists or another important
  52          * system resource we shouldn't move around.
  53          */
  54         if (res->flags & IORESOURCE_PCI_FIXED)
  55                 return;
  56
  57         pcibios_resource_to_bus(dev->bus, &region, res);
  58
  59         new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
  60         if (res->flags & IORESOURCE_IO)
  61                 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
  62         else
  63                 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
  64
  65         reg = pci_resource_bar(dev, resno, &type);
  66         if (!reg)
  67                 return;
  68         if (type != pci_bar_unknown) {
  69                 if (!(res->flags & IORESOURCE_ROM_ENABLE))
  70                         return;
  71                 new |= PCI_ROM_ADDRESS_ENABLE;
  72         }
  73
  74         /*
  75          * We can't update a 64-bit BAR atomically, so when possible,
  76          * disable decoding so that a half-updated BAR won't conflict
  77          * with another device.
  78          */
  79         disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
  80         if (disable) {
  81                 pci_read_config_word(dev, PCI_COMMAND, &cmd);
  82                 pci_write_config_word(dev, PCI_COMMAND,
  83                                       cmd & ~PCI_COMMAND_MEMORY);
  84         }
  85
  86         pci_write_config_dword(dev, reg, new);
  87         pci_read_config_dword(dev, reg, &check);
  88
  89         if ((new ^ check) & mask) {
  90                 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
  91                         resno, new, check);
  92         }
  93
  94         if (res->flags & IORESOURCE_MEM_64) {
  95                 new = region.start >> 16 >> 16;
  96                 pci_write_config_dword(dev, reg + 4, new);
  97                 pci_read_config_dword(dev, reg + 4, &check);
  98                 if (check != new) {
  99                         dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
 100                                 resno, new, check);
 101                 }
 102         }
 103
 104         if (disable)
 105                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 106 }
 107
 108 int pci_claim_resource(struct pci_dev *dev, int resource)
 109 {
 110         struct resource *res = &dev->resource[resource];
 111         struct resource *root, *conflict;
 112
 113         if (res->flags & IORESOURCE_UNSET) {
 114                 dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
 115                          resource, res);
 116                 return -EINVAL;
 117         }
 118
 119         root = pci_find_parent_resource(dev, res);
 120         if (!root) {
 121                 dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
 122                          resource, res);
 123                 return -EINVAL;
 124         }
 125
 126         conflict = request_resource_conflict(root, res);
 127         if (conflict) {
 128                 dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
 129                          resource, res, conflict->name, conflict);
 130                 return -EBUSY;
 131         }
 132
 133         return 0;
 134 }
 135 EXPORT_SYMBOL(pci_claim_resource);
 136
 137 void pci_disable_bridge_window(struct pci_dev *dev)
 138 {
 139         dev_info(&dev->dev, "disabling bridge mem windows\n");
 140
 141         /* MMIO Base/Limit */
 142         pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
 143
 144         /* Prefetchable MMIO Base/Limit */
 145         pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
 146         pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
 147         pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
 148 }
 149
 150 /*
 151  * Generic function that returns a value indicating that the device's
 152  * original BIOS BAR address was not saved and so is not available for
 153  * reinstatement.
 154  *
 155  * Can be over-ridden by architecture specific code that implements
 156  * reinstatement functionality rather than leaving it disabled when
 157  * normal allocation attempts fail.
 158  */
 159 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
 160 {
 161         return 0;
 162 }
 163
 164 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
 165                 int resno, resource_size_t size)
 166 {
 167         struct resource *root, *conflict;
 168         resource_size_t fw_addr, start, end;
 169
 170         fw_addr = pcibios_retrieve_fw_addr(dev, resno);
 171         if (!fw_addr)
 172                 return -ENOMEM;
 173
 174         start = res->start;
 175         end = res->end;
 176         res->start = fw_addr;
 177         res->end = res->start + size - 1;
 178
 179         root = pci_find_parent_resource(dev, res);
 180         if (!root) {
 181                 if (res->flags & IORESOURCE_IO)
 182                         root = &ioport_resource;
 183                 else
 184                         root = &iomem_resource;
 185         }
 186
 187         dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
 188                  resno, res);
 189         conflict = request_resource_conflict(root, res);
 190         if (conflict) {
 191                 dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
 192                          resno, res, conflict->name, conflict);
 193                 res->start = start;
 194                 res->end = end;
 195                 return -EBUSY;
 196         }
 197         return 0;
 198 }
 199
 200 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
 201                 int resno, resource_size_t size, resource_size_t align)
 202 {
 203         struct resource *res = dev->resource + resno;
 204         resource_size_t min;
 205         int ret;
 206
 207         min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
 208
 209         /*
 210          * First, try exact prefetching match.  Even if a 64-bit
 211          * prefetchable bridge window is below 4GB, we can't put a 32-bit
 212          * prefetchable resource in it because pbus_size_mem() assumes a
 213          * 64-bit window will contain no 32-bit resources.  If we assign
 214          * things differently than they were sized, not everything will fit.
 215          */
 216         ret = pci_bus_alloc_resource(bus, res, size, align, min,
 217                                      IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
 218                                      pcibios_align_resource, dev);
 219         if (ret == 0)
 220                 return 0;
 221
 222         /*
 223          * If the prefetchable window is only 32 bits wide, we can put
 224          * 64-bit prefetchable resources in it.
 225          */
 226         if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
 227              (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
 228                 ret = pci_bus_alloc_resource(bus, res, size, align, min,
 229                                              IORESOURCE_PREFETCH,
 230                                              pcibios_align_resource, dev);
 231                 if (ret == 0)
 232                         return 0;
 233         }
 234
 235         /*
 236          * If we didn't find a better match, we can put any memory resource
 237          * in a non-prefetchable window.  If this resource is 32 bits and
 238          * non-prefetchable, the first call already tried the only possibility
 239          * so we don't need to try again.
 240          */
 241         if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
 242                 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
 243                                              pcibios_align_resource, dev);
 244
 245         return ret;
 246 }
 247
 248 static int _pci_assign_resource(struct pci_dev *dev, int resno,
 249                                 resource_size_t size, resource_size_t min_align)
 250 {
 251         struct pci_bus *bus;
 252         int ret;
 253
 254         bus = dev->bus;
 255         while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
 256                 if (!bus->parent || !bus->self->transparent)
 257                         break;
 258                 bus = bus->parent;
 259         }
 260
 261         return ret;
 262 }
 263
 264 int pci_assign_resource(struct pci_dev *dev, int resno)
 265 {
 266         struct resource *res = dev->resource + resno;
 267         resource_size_t align, size;
 268         int ret;
 269
 270         res->flags |= IORESOURCE_UNSET;
 271         align = pci_resource_alignment(dev, res);
 272         if (!align) {
 273                 dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
 274                          resno, res);
 275                 return -EINVAL;
 276         }
 277
 278         size = resource_size(res);
 279         ret = _pci_assign_resource(dev, resno, size, align);
 280
 281         /*
 282          * If we failed to assign anything, let's try the address
 283          * where firmware left it.  That at least has a chance of
 284          * working, which is better than just leaving it disabled.
 285          */
 286         if (ret < 0) {
 287                 dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
 288                 ret = pci_revert_fw_address(res, dev, resno, size);
 289         }
 290
 291         if (ret < 0) {
 292                 dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
 293                          res);
 294                 return ret;
 295         }
 296
 297         res->flags &= ~IORESOURCE_UNSET;
 298         res->flags &= ~IORESOURCE_STARTALIGN;
 299         dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
 300         if (resno < PCI_BRIDGE_RESOURCES)
 301                 pci_update_resource(dev, resno);
 302
 303         return 0;
 304 }
 305 EXPORT_SYMBOL(pci_assign_resource);
 306
 307 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
 308                         resource_size_t min_align)
 309 {
 310         struct resource *res = dev->resource + resno;
 311         unsigned long flags;
 312         resource_size_t new_size;
 313         int ret;
 314
 315         flags = res->flags;
 316         res->flags |= IORESOURCE_UNSET;
 317         if (!res->parent) {
 318                 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
 319                          resno, res);
 320                 return -EINVAL;
 321         }
 322
 323         /* already aligned with min_align */
 324         new_size = resource_size(res) + addsize;
 325         ret = _pci_assign_resource(dev, resno, new_size, min_align);
 326         if (ret) {
 327                 res->flags = flags;
 328                 dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
 329                          resno, res, (unsigned long long) addsize);
 330                 return ret;
 331         }
 332
 333         res->flags &= ~IORESOURCE_UNSET;
 334         res->flags &= ~IORESOURCE_STARTALIGN;
 335         dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
 336                  resno, res, (unsigned long long) addsize);
 337         if (resno < PCI_BRIDGE_RESOURCES)
 338                 pci_update_resource(dev, resno);
 339
 340         return 0;
 341 }
 342
 343 int pci_enable_resources(struct pci_dev *dev, int mask)
 344 {
 345         u16 cmd, old_cmd;
 346         int i;
 347         struct resource *r;
 348
 349         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 350         old_cmd = cmd;
 351
 352         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 353                 if (!(mask & (1 << i)))
 354                         continue;
 355
 356                 r = &dev->resource[i];
 357
 358                 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
 359                         continue;
 360                 if ((i == PCI_ROM_RESOURCE) &&
 361                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 362                         continue;
 363
 364                 if (r->flags & IORESOURCE_UNSET) {
 365                         dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
 366                                 i, r);
 367                         return -EINVAL;
 368                 }
 369
 370                 if (!r->parent) {
 371                         dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
 372                                 i, r);
 373                         return -EINVAL;
 374                 }
 375
 376                 if (r->flags & IORESOURCE_IO)
 377                         cmd |= PCI_COMMAND_IO;
 378                 if (r->flags & IORESOURCE_MEM)
 379                         cmd |= PCI_COMMAND_MEMORY;
 380         }
 381
 382         if (cmd != old_cmd) {
 383                 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
 384                          old_cmd, cmd);
 385                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 386         }
 387         return 0;
 388 }