2 * This file is part of the Chelsio FCoE driver for Linux.
4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
36 #include <linux/jiffies.h>
37 #include <linux/string.h>
38 #include <scsi/scsi_device.h>
39 #include <scsi/scsi_transport_fc.h>
42 #include "csio_lnode.h"
43 #include "csio_rnode.h"
47 #define csio_mb_is_host_owner(__owner) ((__owner) == CSIO_MBOWNER_PL)
49 /* MB Command/Response Helpers */
51 * csio_mb_fw_retval - FW return value from a mailbox response.
52 * @mbp: Mailbox structure
56 csio_mb_fw_retval(struct csio_mb
*mbp
)
58 struct fw_cmd_hdr
*hdr
;
60 hdr
= (struct fw_cmd_hdr
*)(mbp
->mb
);
62 return FW_CMD_RETVAL_G(ntohl(hdr
->lo
));
66 * csio_mb_hello - FW HELLO command helper
67 * @hw: The HW structure
68 * @mbp: Mailbox structure
69 * @m_mbox: Master mailbox number, if any.
70 * @a_mbox: Mailbox number for asycn notifications.
71 * @master: Device mastership.
72 * @cbfn: Callback, if any.
76 csio_mb_hello(struct csio_hw
*hw
, struct csio_mb
*mbp
, uint32_t tmo
,
77 uint32_t m_mbox
, uint32_t a_mbox
, enum csio_dev_master master
,
78 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
80 struct fw_hello_cmd
*cmdp
= (struct fw_hello_cmd
*)(mbp
->mb
);
82 CSIO_INIT_MBP(mbp
, cmdp
, tmo
, hw
, cbfn
, 1);
84 cmdp
->op_to_write
= htonl(FW_CMD_OP_V(FW_HELLO_CMD
) |
85 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
);
86 cmdp
->retval_len16
= htonl(FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
87 cmdp
->err_to_clearinit
= htonl(
88 FW_HELLO_CMD_MASTERDIS_V(master
== CSIO_MASTER_CANT
) |
89 FW_HELLO_CMD_MASTERFORCE_V(master
== CSIO_MASTER_MUST
) |
90 FW_HELLO_CMD_MBMASTER_V(master
== CSIO_MASTER_MUST
?
91 m_mbox
: FW_HELLO_CMD_MBMASTER_M
) |
92 FW_HELLO_CMD_MBASYNCNOT_V(a_mbox
) |
93 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os
) |
94 FW_HELLO_CMD_CLEARINIT_F
);
99 * csio_mb_process_hello_rsp - FW HELLO response processing helper
100 * @hw: The HW structure
101 * @mbp: Mailbox structure
102 * @retval: Mailbox return value from Firmware
103 * @state: State that the function is in.
108 csio_mb_process_hello_rsp(struct csio_hw
*hw
, struct csio_mb
*mbp
,
109 enum fw_retval
*retval
, enum csio_dev_state
*state
,
112 struct fw_hello_cmd
*rsp
= (struct fw_hello_cmd
*)(mbp
->mb
);
115 *retval
= FW_CMD_RETVAL_G(ntohl(rsp
->retval_len16
));
117 if (*retval
== FW_SUCCESS
) {
118 hw
->fwrev
= ntohl(rsp
->fwrev
);
120 value
= ntohl(rsp
->err_to_clearinit
);
121 *mpfn
= FW_HELLO_CMD_MBMASTER_G(value
);
123 if (value
& FW_HELLO_CMD_INIT_F
)
124 *state
= CSIO_DEV_STATE_INIT
;
125 else if (value
& FW_HELLO_CMD_ERR_F
)
126 *state
= CSIO_DEV_STATE_ERR
;
128 *state
= CSIO_DEV_STATE_UNINIT
;
133 * csio_mb_bye - FW BYE command helper
134 * @hw: The HW structure
135 * @mbp: Mailbox structure
136 * @cbfn: Callback, if any.
140 csio_mb_bye(struct csio_hw
*hw
, struct csio_mb
*mbp
, uint32_t tmo
,
141 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
143 struct fw_bye_cmd
*cmdp
= (struct fw_bye_cmd
*)(mbp
->mb
);
145 CSIO_INIT_MBP(mbp
, cmdp
, tmo
, hw
, cbfn
, 1);
147 cmdp
->op_to_write
= htonl(FW_CMD_OP_V(FW_BYE_CMD
) |
148 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
);
149 cmdp
->retval_len16
= htonl(FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
154 * csio_mb_reset - FW RESET command helper
155 * @hw: The HW structure
156 * @mbp: Mailbox structure
157 * @reset: Type of reset.
158 * @cbfn: Callback, if any.
162 csio_mb_reset(struct csio_hw
*hw
, struct csio_mb
*mbp
, uint32_t tmo
,
164 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
166 struct fw_reset_cmd
*cmdp
= (struct fw_reset_cmd
*)(mbp
->mb
);
168 CSIO_INIT_MBP(mbp
, cmdp
, tmo
, hw
, cbfn
, 1);
170 cmdp
->op_to_write
= htonl(FW_CMD_OP_V(FW_RESET_CMD
) |
171 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
);
172 cmdp
->retval_len16
= htonl(FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
173 cmdp
->val
= htonl(reset
);
174 cmdp
->halt_pkd
= htonl(halt
);
179 * csio_mb_params - FW PARAMS command helper
180 * @hw: The HW structure
181 * @mbp: Mailbox structure
182 * @tmo: Command timeout.
185 * @nparams: Number of parameters
186 * @params: Parameter mnemonic array.
187 * @val: Parameter value array.
188 * @wr: Write/Read PARAMS.
189 * @cbfn: Callback, if any.
193 csio_mb_params(struct csio_hw
*hw
, struct csio_mb
*mbp
, uint32_t tmo
,
194 unsigned int pf
, unsigned int vf
, unsigned int nparams
,
195 const u32
*params
, u32
*val
, bool wr
,
196 void (*cbfn
)(struct csio_hw
*, struct csio_mb
*))
199 uint32_t temp_params
= 0, temp_val
= 0;
200 struct fw_params_cmd
*cmdp
= (struct fw_params_cmd
*)(mbp
->mb
);
201 __be32
*p
= &cmdp
->param
[0].mnem
;
203 CSIO_INIT_MBP(mbp
, cmdp
, tmo
, hw
, cbfn
, 1);
205 cmdp
->op_to_vfn
= htonl(FW_CMD_OP_V(FW_PARAMS_CMD
) |
207 (wr
? FW_CMD_WRITE_F
: FW_CMD_READ_F
) |
208 FW_PARAMS_CMD_PFN_V(pf
) |
209 FW_PARAMS_CMD_VFN_V(vf
));
210 cmdp
->retval_len16
= htonl(FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
215 temp_params
= *params
++;
218 *p
++ = htonl(temp_params
);
219 *p
++ = htonl(temp_val
);
222 for (i
= 0; i
< nparams
; i
++, p
+= 2) {
223 temp_params
= *params
++;
224 *p
= htonl(temp_params
);
231 * csio_mb_process_read_params_rsp - FW PARAMS response processing helper
232 * @hw: The HW structure
233 * @mbp: Mailbox structure
234 * @retval: Mailbox return value from Firmware
235 * @nparams: Number of parameters
236 * @val: Parameter value array.
240 csio_mb_process_read_params_rsp(struct csio_hw
*hw
, struct csio_mb
*mbp
,
241 enum fw_retval
*retval
, unsigned int nparams
,
244 struct fw_params_cmd
*rsp
= (struct fw_params_cmd
*)(mbp
->mb
);
246 __be32
*p
= &rsp
->param
[0].val
;
248 *retval
= FW_CMD_RETVAL_G(ntohl(rsp
->retval_len16
));
250 if (*retval
== FW_SUCCESS
)
251 for (i
= 0; i
< nparams
; i
++, p
+= 2)
256 * csio_mb_ldst - FW LDST command
257 * @hw: The HW structure
258 * @mbp: Mailbox structure
264 csio_mb_ldst(struct csio_hw
*hw
, struct csio_mb
*mbp
, uint32_t tmo
, int reg
)
266 struct fw_ldst_cmd
*ldst_cmd
= (struct fw_ldst_cmd
*)(mbp
->mb
);
267 CSIO_INIT_MBP(mbp
, ldst_cmd
, tmo
, hw
, NULL
, 1);
270 * Construct and send the Firmware LDST Command to retrieve the
271 * specified PCI-E Configuration Space register.
273 ldst_cmd
->op_to_addrspace
=
274 htonl(FW_CMD_OP_V(FW_LDST_CMD
) |
277 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE
));
278 ldst_cmd
->cycles_to_len16
= htonl(FW_LEN16(struct fw_ldst_cmd
));
279 ldst_cmd
->u
.pcie
.select_naccess
= FW_LDST_CMD_NACCESS_V(1);
280 ldst_cmd
->u
.pcie
.ctrl_to_fn
=
281 (FW_LDST_CMD_LC_F
| FW_LDST_CMD_FN_V(hw
->pfn
));
282 ldst_cmd
->u
.pcie
.r
= (uint8_t)reg
;
287 * csio_mb_caps_config - FW Read/Write Capabilities command helper
288 * @hw: The HW structure
289 * @mbp: Mailbox structure
290 * @wr: Write if 1, Read if 0
291 * @init: Turn on initiator mode.
292 * @tgt: Turn on target mode.
293 * @cofld: If 1, Control Offload for FCoE
294 * @cbfn: Callback, if any.
296 * This helper assumes that cmdp has MB payload from a previous CAPS
300 csio_mb_caps_config(struct csio_hw
*hw
, struct csio_mb
*mbp
, uint32_t tmo
,
301 bool wr
, bool init
, bool tgt
, bool cofld
,
302 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
304 struct fw_caps_config_cmd
*cmdp
=
305 (struct fw_caps_config_cmd
*)(mbp
->mb
);
307 CSIO_INIT_MBP(mbp
, cmdp
, tmo
, hw
, cbfn
, wr
? 0 : 1);
309 cmdp
->op_to_write
= htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD
) |
311 (wr
? FW_CMD_WRITE_F
: FW_CMD_READ_F
));
312 cmdp
->cfvalid_to_len16
= htonl(FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
322 cmdp
->fcoecaps
|= htons(FW_CAPS_CONFIG_FCOE_CTRL_OFLD
);
324 cmdp
->fcoecaps
|= htons(FW_CAPS_CONFIG_FCOE_INITIATOR
);
326 cmdp
->fcoecaps
|= htons(FW_CAPS_CONFIG_FCOE_TARGET
);
329 #define CSIO_ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
330 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_ANEG)
333 * csio_mb_port- FW PORT command helper
334 * @hw: The HW structure
335 * @mbp: Mailbox structure
336 * @tmo: COmmand timeout
337 * @portid: Port ID to get/set info
338 * @wr: Write/Read PORT information.
340 * @caps: Port capabilites to set.
341 * @cbfn: Callback, if any.
345 csio_mb_port(struct csio_hw
*hw
, struct csio_mb
*mbp
, uint32_t tmo
,
346 uint8_t portid
, bool wr
, uint32_t fc
, uint16_t caps
,
347 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
349 struct fw_port_cmd
*cmdp
= (struct fw_port_cmd
*)(mbp
->mb
);
350 unsigned int lfc
= 0, mdi
= FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO
);
352 CSIO_INIT_MBP(mbp
, cmdp
, tmo
, hw
, cbfn
, 1);
354 cmdp
->op_to_portid
= htonl(FW_CMD_OP_V(FW_PORT_CMD
) |
356 (wr
? FW_CMD_EXEC_F
: FW_CMD_READ_F
) |
357 FW_PORT_CMD_PORTID_V(portid
));
359 cmdp
->action_to_len16
= htonl(
360 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO
) |
361 FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
366 cmdp
->action_to_len16
= htonl(
367 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG
) |
368 FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
371 lfc
|= FW_PORT_CAP_FC_RX
;
373 lfc
|= FW_PORT_CAP_FC_TX
;
375 if (!(caps
& FW_PORT_CAP_ANEG
))
376 cmdp
->u
.l1cfg
.rcap
= htonl((caps
& CSIO_ADVERT_MASK
) | lfc
);
378 cmdp
->u
.l1cfg
.rcap
= htonl((caps
& CSIO_ADVERT_MASK
) |
383 * csio_mb_process_read_port_rsp - FW PORT command response processing helper
384 * @hw: The HW structure
385 * @mbp: Mailbox structure
386 * @retval: Mailbox return value from Firmware
387 * @caps: port capabilities
391 csio_mb_process_read_port_rsp(struct csio_hw
*hw
, struct csio_mb
*mbp
,
392 enum fw_retval
*retval
, uint16_t *caps
)
394 struct fw_port_cmd
*rsp
= (struct fw_port_cmd
*)(mbp
->mb
);
396 *retval
= FW_CMD_RETVAL_G(ntohl(rsp
->action_to_len16
));
398 if (*retval
== FW_SUCCESS
)
399 *caps
= ntohs(rsp
->u
.info
.pcap
);
403 * csio_mb_initialize - FW INITIALIZE command helper
404 * @hw: The HW structure
405 * @mbp: Mailbox structure
406 * @tmo: COmmand timeout
407 * @cbfn: Callback, if any.
411 csio_mb_initialize(struct csio_hw
*hw
, struct csio_mb
*mbp
, uint32_t tmo
,
412 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
414 struct fw_initialize_cmd
*cmdp
= (struct fw_initialize_cmd
*)(mbp
->mb
);
416 CSIO_INIT_MBP(mbp
, cmdp
, tmo
, hw
, cbfn
, 1);
418 cmdp
->op_to_write
= htonl(FW_CMD_OP_V(FW_INITIALIZE_CMD
) |
419 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
);
420 cmdp
->retval_len16
= htonl(FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
425 * csio_mb_iq_alloc - Initializes the mailbox to allocate an
426 * Ingress DMA queue in the firmware.
428 * @hw: The hw structure
429 * @mbp: Mailbox structure to initialize
430 * @priv: Private object
431 * @mb_tmo: Mailbox time-out period (in ms).
432 * @iq_params: Ingress queue params needed for allocation.
433 * @cbfn: The call-back function
438 csio_mb_iq_alloc(struct csio_hw
*hw
, struct csio_mb
*mbp
, void *priv
,
439 uint32_t mb_tmo
, struct csio_iq_params
*iq_params
,
440 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
442 struct fw_iq_cmd
*cmdp
= (struct fw_iq_cmd
*)(mbp
->mb
);
444 CSIO_INIT_MBP(mbp
, cmdp
, mb_tmo
, priv
, cbfn
, 1);
446 cmdp
->op_to_vfn
= htonl(FW_CMD_OP_V(FW_IQ_CMD
) |
447 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
448 FW_IQ_CMD_PFN_V(iq_params
->pfn
) |
449 FW_IQ_CMD_VFN_V(iq_params
->vfn
));
451 cmdp
->alloc_to_len16
= htonl(FW_IQ_CMD_ALLOC_F
|
452 FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
454 cmdp
->type_to_iqandstindex
= htonl(
455 FW_IQ_CMD_VIID_V(iq_params
->viid
) |
456 FW_IQ_CMD_TYPE_V(iq_params
->type
) |
457 FW_IQ_CMD_IQASYNCH_V(iq_params
->iqasynch
));
459 cmdp
->fl0size
= htons(iq_params
->fl0size
);
460 cmdp
->fl0size
= htons(iq_params
->fl1size
);
462 } /* csio_mb_iq_alloc */
465 * csio_mb_iq_write - Initializes the mailbox for writing into an
468 * @hw: The HW structure
469 * @mbp: Mailbox structure to initialize
470 * @priv: Private object
471 * @mb_tmo: Mailbox time-out period (in ms).
472 * @cascaded_req: TRUE - if this request is cascased with iq-alloc request.
473 * @iq_params: Ingress queue params needed for writing.
474 * @cbfn: The call-back function
476 * NOTE: We OR relevant bits with cmdp->XXX, instead of just equating,
477 * because this IQ write request can be cascaded with a previous
478 * IQ alloc request, and we dont want to over-write the bits set by
479 * that request. This logic will work even in a non-cascaded case, since the
480 * cmdp structure is zeroed out by CSIO_INIT_MBP.
483 csio_mb_iq_write(struct csio_hw
*hw
, struct csio_mb
*mbp
, void *priv
,
484 uint32_t mb_tmo
, bool cascaded_req
,
485 struct csio_iq_params
*iq_params
,
486 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
488 struct fw_iq_cmd
*cmdp
= (struct fw_iq_cmd
*)(mbp
->mb
);
490 uint32_t iq_start_stop
= (iq_params
->iq_start
) ?
491 FW_IQ_CMD_IQSTART_F
:
495 * If this IQ write is cascaded with IQ alloc request, do not
496 * re-initialize with 0's.
500 CSIO_INIT_MBP(mbp
, cmdp
, mb_tmo
, priv
, cbfn
, 1);
502 cmdp
->op_to_vfn
|= htonl(FW_CMD_OP_V(FW_IQ_CMD
) |
503 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
504 FW_IQ_CMD_PFN_V(iq_params
->pfn
) |
505 FW_IQ_CMD_VFN_V(iq_params
->vfn
));
506 cmdp
->alloc_to_len16
|= htonl(iq_start_stop
|
507 FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
508 cmdp
->iqid
|= htons(iq_params
->iqid
);
509 cmdp
->fl0id
|= htons(iq_params
->fl0id
);
510 cmdp
->fl1id
|= htons(iq_params
->fl1id
);
511 cmdp
->type_to_iqandstindex
|= htonl(
512 FW_IQ_CMD_IQANDST_V(iq_params
->iqandst
) |
513 FW_IQ_CMD_IQANUS_V(iq_params
->iqanus
) |
514 FW_IQ_CMD_IQANUD_V(iq_params
->iqanud
) |
515 FW_IQ_CMD_IQANDSTINDEX_V(iq_params
->iqandstindex
));
516 cmdp
->iqdroprss_to_iqesize
|= htons(
517 FW_IQ_CMD_IQPCIECH_V(iq_params
->iqpciech
) |
518 FW_IQ_CMD_IQDCAEN_V(iq_params
->iqdcaen
) |
519 FW_IQ_CMD_IQDCACPU_V(iq_params
->iqdcacpu
) |
520 FW_IQ_CMD_IQINTCNTTHRESH_V(iq_params
->iqintcntthresh
) |
521 FW_IQ_CMD_IQCPRIO_V(iq_params
->iqcprio
) |
522 FW_IQ_CMD_IQESIZE_V(iq_params
->iqesize
));
524 cmdp
->iqsize
|= htons(iq_params
->iqsize
);
525 cmdp
->iqaddr
|= cpu_to_be64(iq_params
->iqaddr
);
527 if (iq_params
->type
== 0) {
528 cmdp
->iqns_to_fl0congen
|= htonl(
529 FW_IQ_CMD_IQFLINTIQHSEN_V(iq_params
->iqflintiqhsen
)|
530 FW_IQ_CMD_IQFLINTCONGEN_V(iq_params
->iqflintcongen
));
533 if (iq_params
->fl0size
&& iq_params
->fl0addr
&&
534 (iq_params
->fl0id
!= 0xFFFF)) {
536 cmdp
->iqns_to_fl0congen
|= htonl(
537 FW_IQ_CMD_FL0HOSTFCMODE_V(iq_params
->fl0hostfcmode
)|
538 FW_IQ_CMD_FL0CPRIO_V(iq_params
->fl0cprio
) |
539 FW_IQ_CMD_FL0PADEN_V(iq_params
->fl0paden
) |
540 FW_IQ_CMD_FL0PACKEN_V(iq_params
->fl0packen
));
541 cmdp
->fl0dcaen_to_fl0cidxfthresh
|= htons(
542 FW_IQ_CMD_FL0DCAEN_V(iq_params
->fl0dcaen
) |
543 FW_IQ_CMD_FL0DCACPU_V(iq_params
->fl0dcacpu
) |
544 FW_IQ_CMD_FL0FBMIN_V(iq_params
->fl0fbmin
) |
545 FW_IQ_CMD_FL0FBMAX_V(iq_params
->fl0fbmax
) |
546 FW_IQ_CMD_FL0CIDXFTHRESH_V(iq_params
->fl0cidxfthresh
));
547 cmdp
->fl0size
|= htons(iq_params
->fl0size
);
548 cmdp
->fl0addr
|= cpu_to_be64(iq_params
->fl0addr
);
550 } /* csio_mb_iq_write */
553 * csio_mb_iq_alloc_write - Initializes the mailbox for allocating an
556 * @hw: The HW structure
557 * @mbp: Mailbox structure to initialize
558 * @priv: Private data.
559 * @mb_tmo: Mailbox time-out period (in ms).
560 * @iq_params: Ingress queue params needed for allocation & writing.
561 * @cbfn: The call-back function
566 csio_mb_iq_alloc_write(struct csio_hw
*hw
, struct csio_mb
*mbp
, void *priv
,
567 uint32_t mb_tmo
, struct csio_iq_params
*iq_params
,
568 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
570 csio_mb_iq_alloc(hw
, mbp
, priv
, mb_tmo
, iq_params
, cbfn
);
571 csio_mb_iq_write(hw
, mbp
, priv
, mb_tmo
, true, iq_params
, cbfn
);
572 } /* csio_mb_iq_alloc_write */
575 * csio_mb_iq_alloc_write_rsp - Process the allocation & writing
576 * of ingress DMA queue mailbox's response.
578 * @hw: The HW structure.
579 * @mbp: Mailbox structure to initialize.
580 * @retval: Firmware return value.
581 * @iq_params: Ingress queue parameters, after allocation and write.
585 csio_mb_iq_alloc_write_rsp(struct csio_hw
*hw
, struct csio_mb
*mbp
,
586 enum fw_retval
*ret_val
,
587 struct csio_iq_params
*iq_params
)
589 struct fw_iq_cmd
*rsp
= (struct fw_iq_cmd
*)(mbp
->mb
);
591 *ret_val
= FW_CMD_RETVAL_G(ntohl(rsp
->alloc_to_len16
));
592 if (*ret_val
== FW_SUCCESS
) {
593 iq_params
->physiqid
= ntohs(rsp
->physiqid
);
594 iq_params
->iqid
= ntohs(rsp
->iqid
);
595 iq_params
->fl0id
= ntohs(rsp
->fl0id
);
596 iq_params
->fl1id
= ntohs(rsp
->fl1id
);
598 iq_params
->physiqid
= iq_params
->iqid
=
599 iq_params
->fl0id
= iq_params
->fl1id
= 0;
601 } /* csio_mb_iq_alloc_write_rsp */
604 * csio_mb_iq_free - Initializes the mailbox for freeing a
605 * specified Ingress DMA Queue.
607 * @hw: The HW structure
608 * @mbp: Mailbox structure to initialize
609 * @priv: Private data
610 * @mb_tmo: Mailbox time-out period (in ms).
611 * @iq_params: Parameters of ingress queue, that is to be freed.
612 * @cbfn: The call-back function
617 csio_mb_iq_free(struct csio_hw
*hw
, struct csio_mb
*mbp
, void *priv
,
618 uint32_t mb_tmo
, struct csio_iq_params
*iq_params
,
619 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
621 struct fw_iq_cmd
*cmdp
= (struct fw_iq_cmd
*)(mbp
->mb
);
623 CSIO_INIT_MBP(mbp
, cmdp
, mb_tmo
, priv
, cbfn
, 1);
625 cmdp
->op_to_vfn
= htonl(FW_CMD_OP_V(FW_IQ_CMD
) |
626 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
627 FW_IQ_CMD_PFN_V(iq_params
->pfn
) |
628 FW_IQ_CMD_VFN_V(iq_params
->vfn
));
629 cmdp
->alloc_to_len16
= htonl(FW_IQ_CMD_FREE_F
|
630 FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
631 cmdp
->type_to_iqandstindex
= htonl(FW_IQ_CMD_TYPE_V(iq_params
->type
));
633 cmdp
->iqid
= htons(iq_params
->iqid
);
634 cmdp
->fl0id
= htons(iq_params
->fl0id
);
635 cmdp
->fl1id
= htons(iq_params
->fl1id
);
637 } /* csio_mb_iq_free */
640 * csio_mb_eq_ofld_alloc - Initializes the mailbox for allocating
641 * an offload-egress queue.
643 * @hw: The HW structure
644 * @mbp: Mailbox structure to initialize
645 * @priv: Private data
646 * @mb_tmo: Mailbox time-out period (in ms).
647 * @eq_ofld_params: (Offload) Egress queue parameters.
648 * @cbfn: The call-back function
653 csio_mb_eq_ofld_alloc(struct csio_hw
*hw
, struct csio_mb
*mbp
, void *priv
,
654 uint32_t mb_tmo
, struct csio_eq_params
*eq_ofld_params
,
655 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
657 struct fw_eq_ofld_cmd
*cmdp
= (struct fw_eq_ofld_cmd
*)(mbp
->mb
);
659 CSIO_INIT_MBP(mbp
, cmdp
, mb_tmo
, priv
, cbfn
, 1);
660 cmdp
->op_to_vfn
= htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD
) |
661 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
662 FW_EQ_OFLD_CMD_PFN_V(eq_ofld_params
->pfn
) |
663 FW_EQ_OFLD_CMD_VFN_V(eq_ofld_params
->vfn
));
664 cmdp
->alloc_to_len16
= htonl(FW_EQ_OFLD_CMD_ALLOC_F
|
665 FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
667 } /* csio_mb_eq_ofld_alloc */
670 * csio_mb_eq_ofld_write - Initializes the mailbox for writing
671 * an alloacted offload-egress queue.
673 * @hw: The HW structure
674 * @mbp: Mailbox structure to initialize
675 * @priv: Private data
676 * @mb_tmo: Mailbox time-out period (in ms).
677 * @cascaded_req: TRUE - if this request is cascased with Eq-alloc request.
678 * @eq_ofld_params: (Offload) Egress queue parameters.
679 * @cbfn: The call-back function
682 * NOTE: We OR relevant bits with cmdp->XXX, instead of just equating,
683 * because this EQ write request can be cascaded with a previous
684 * EQ alloc request, and we dont want to over-write the bits set by
685 * that request. This logic will work even in a non-cascaded case, since the
686 * cmdp structure is zeroed out by CSIO_INIT_MBP.
689 csio_mb_eq_ofld_write(struct csio_hw
*hw
, struct csio_mb
*mbp
, void *priv
,
690 uint32_t mb_tmo
, bool cascaded_req
,
691 struct csio_eq_params
*eq_ofld_params
,
692 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
694 struct fw_eq_ofld_cmd
*cmdp
= (struct fw_eq_ofld_cmd
*)(mbp
->mb
);
696 uint32_t eq_start_stop
= (eq_ofld_params
->eqstart
) ?
697 FW_EQ_OFLD_CMD_EQSTART_F
:
698 FW_EQ_OFLD_CMD_EQSTOP_F
;
701 * If this EQ write is cascaded with EQ alloc request, do not
702 * re-initialize with 0's.
706 CSIO_INIT_MBP(mbp
, cmdp
, mb_tmo
, priv
, cbfn
, 1);
708 cmdp
->op_to_vfn
|= htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD
) |
709 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
710 FW_EQ_OFLD_CMD_PFN_V(eq_ofld_params
->pfn
) |
711 FW_EQ_OFLD_CMD_VFN_V(eq_ofld_params
->vfn
));
712 cmdp
->alloc_to_len16
|= htonl(eq_start_stop
|
713 FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
715 cmdp
->eqid_pkd
|= htonl(FW_EQ_OFLD_CMD_EQID_V(eq_ofld_params
->eqid
));
717 cmdp
->fetchszm_to_iqid
|= htonl(
718 FW_EQ_OFLD_CMD_HOSTFCMODE_V(eq_ofld_params
->hostfcmode
) |
719 FW_EQ_OFLD_CMD_CPRIO_V(eq_ofld_params
->cprio
) |
720 FW_EQ_OFLD_CMD_PCIECHN_V(eq_ofld_params
->pciechn
) |
721 FW_EQ_OFLD_CMD_IQID_V(eq_ofld_params
->iqid
));
723 cmdp
->dcaen_to_eqsize
|= htonl(
724 FW_EQ_OFLD_CMD_DCAEN_V(eq_ofld_params
->dcaen
) |
725 FW_EQ_OFLD_CMD_DCACPU_V(eq_ofld_params
->dcacpu
) |
726 FW_EQ_OFLD_CMD_FBMIN_V(eq_ofld_params
->fbmin
) |
727 FW_EQ_OFLD_CMD_FBMAX_V(eq_ofld_params
->fbmax
) |
728 FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(eq_ofld_params
->cidxfthresho
) |
729 FW_EQ_OFLD_CMD_CIDXFTHRESH_V(eq_ofld_params
->cidxfthresh
) |
730 FW_EQ_OFLD_CMD_EQSIZE_V(eq_ofld_params
->eqsize
));
732 cmdp
->eqaddr
|= cpu_to_be64(eq_ofld_params
->eqaddr
);
734 } /* csio_mb_eq_ofld_write */
737 * csio_mb_eq_ofld_alloc_write - Initializes the mailbox for allocation
738 * writing into an Engress DMA Queue.
740 * @hw: The HW structure
741 * @mbp: Mailbox structure to initialize
742 * @priv: Private data.
743 * @mb_tmo: Mailbox time-out period (in ms).
744 * @eq_ofld_params: (Offload) Egress queue parameters.
745 * @cbfn: The call-back function
750 csio_mb_eq_ofld_alloc_write(struct csio_hw
*hw
, struct csio_mb
*mbp
,
751 void *priv
, uint32_t mb_tmo
,
752 struct csio_eq_params
*eq_ofld_params
,
753 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
755 csio_mb_eq_ofld_alloc(hw
, mbp
, priv
, mb_tmo
, eq_ofld_params
, cbfn
);
756 csio_mb_eq_ofld_write(hw
, mbp
, priv
, mb_tmo
, true,
757 eq_ofld_params
, cbfn
);
758 } /* csio_mb_eq_ofld_alloc_write */
761 * csio_mb_eq_ofld_alloc_write_rsp - Process the allocation
762 * & write egress DMA queue mailbox's response.
764 * @hw: The HW structure.
765 * @mbp: Mailbox structure to initialize.
766 * @retval: Firmware return value.
767 * @eq_ofld_params: (Offload) Egress queue parameters.
771 csio_mb_eq_ofld_alloc_write_rsp(struct csio_hw
*hw
,
772 struct csio_mb
*mbp
, enum fw_retval
*ret_val
,
773 struct csio_eq_params
*eq_ofld_params
)
775 struct fw_eq_ofld_cmd
*rsp
= (struct fw_eq_ofld_cmd
*)(mbp
->mb
);
777 *ret_val
= FW_CMD_RETVAL_G(ntohl(rsp
->alloc_to_len16
));
779 if (*ret_val
== FW_SUCCESS
) {
780 eq_ofld_params
->eqid
= FW_EQ_OFLD_CMD_EQID_G(
781 ntohl(rsp
->eqid_pkd
));
782 eq_ofld_params
->physeqid
= FW_EQ_OFLD_CMD_PHYSEQID_G(
783 ntohl(rsp
->physeqid_pkd
));
785 eq_ofld_params
->eqid
= 0;
787 } /* csio_mb_eq_ofld_alloc_write_rsp */
790 * csio_mb_eq_ofld_free - Initializes the mailbox for freeing a
791 * specified Engress DMA Queue.
793 * @hw: The HW structure
794 * @mbp: Mailbox structure to initialize
795 * @priv: Private data area.
796 * @mb_tmo: Mailbox time-out period (in ms).
797 * @eq_ofld_params: (Offload) Egress queue parameters, that is to be freed.
798 * @cbfn: The call-back function
803 csio_mb_eq_ofld_free(struct csio_hw
*hw
, struct csio_mb
*mbp
, void *priv
,
804 uint32_t mb_tmo
, struct csio_eq_params
*eq_ofld_params
,
805 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
807 struct fw_eq_ofld_cmd
*cmdp
= (struct fw_eq_ofld_cmd
*)(mbp
->mb
);
809 CSIO_INIT_MBP(mbp
, cmdp
, mb_tmo
, priv
, cbfn
, 1);
811 cmdp
->op_to_vfn
= htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD
) |
812 FW_CMD_REQUEST_F
| FW_CMD_EXEC_F
|
813 FW_EQ_OFLD_CMD_PFN_V(eq_ofld_params
->pfn
) |
814 FW_EQ_OFLD_CMD_VFN_V(eq_ofld_params
->vfn
));
815 cmdp
->alloc_to_len16
= htonl(FW_EQ_OFLD_CMD_FREE_F
|
816 FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
817 cmdp
->eqid_pkd
= htonl(FW_EQ_OFLD_CMD_EQID_V(eq_ofld_params
->eqid
));
819 } /* csio_mb_eq_ofld_free */
822 * csio_write_fcoe_link_cond_init_mb - Initialize Mailbox to write FCoE link
825 * @ln: The Lnode structure
826 * @mbp: Mailbox structure to initialize
827 * @mb_tmo: Mailbox time-out period (in ms).
828 * @cbfn: The call back function.
833 csio_write_fcoe_link_cond_init_mb(struct csio_lnode
*ln
, struct csio_mb
*mbp
,
834 uint32_t mb_tmo
, uint8_t port_id
, uint32_t sub_opcode
,
835 uint8_t cos
, bool link_status
, uint32_t fcfi
,
836 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
838 struct fw_fcoe_link_cmd
*cmdp
=
839 (struct fw_fcoe_link_cmd
*)(mbp
->mb
);
841 CSIO_INIT_MBP(mbp
, cmdp
, mb_tmo
, ln
, cbfn
, 1);
843 cmdp
->op_to_portid
= htonl((
844 FW_CMD_OP_V(FW_FCOE_LINK_CMD
) |
847 FW_FCOE_LINK_CMD_PORTID(port_id
)));
848 cmdp
->sub_opcode_fcfi
= htonl(
849 FW_FCOE_LINK_CMD_SUB_OPCODE(sub_opcode
) |
850 FW_FCOE_LINK_CMD_FCFI(fcfi
));
851 cmdp
->lstatus
= link_status
;
852 cmdp
->retval_len16
= htonl(FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
854 } /* csio_write_fcoe_link_cond_init_mb */
857 * csio_fcoe_read_res_info_init_mb - Initializes the mailbox for reading FCoE
858 * resource information(FW_GET_RES_INFO_CMD).
860 * @hw: The HW structure
861 * @mbp: Mailbox structure to initialize
862 * @mb_tmo: Mailbox time-out period (in ms).
863 * @cbfn: The call-back function
868 csio_fcoe_read_res_info_init_mb(struct csio_hw
*hw
, struct csio_mb
*mbp
,
870 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
872 struct fw_fcoe_res_info_cmd
*cmdp
=
873 (struct fw_fcoe_res_info_cmd
*)(mbp
->mb
);
875 CSIO_INIT_MBP(mbp
, cmdp
, mb_tmo
, hw
, cbfn
, 1);
877 cmdp
->op_to_read
= htonl((FW_CMD_OP_V(FW_FCOE_RES_INFO_CMD
) |
881 cmdp
->retval_len16
= htonl(FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
883 } /* csio_fcoe_read_res_info_init_mb */
886 * csio_fcoe_vnp_alloc_init_mb - Initializes the mailbox for allocating VNP
887 * in the firmware (FW_FCOE_VNP_CMD).
889 * @ln: The Lnode structure.
890 * @mbp: Mailbox structure to initialize.
891 * @mb_tmo: Mailbox time-out period (in ms).
895 * @vnport_wwnn: vnport WWNN
896 * @vnport_wwpn: vnport WWPN
897 * @cbfn: The call-back function.
902 csio_fcoe_vnp_alloc_init_mb(struct csio_lnode
*ln
, struct csio_mb
*mbp
,
903 uint32_t mb_tmo
, uint32_t fcfi
, uint32_t vnpi
, uint16_t iqid
,
904 uint8_t vnport_wwnn
[8], uint8_t vnport_wwpn
[8],
905 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
907 struct fw_fcoe_vnp_cmd
*cmdp
=
908 (struct fw_fcoe_vnp_cmd
*)(mbp
->mb
);
910 CSIO_INIT_MBP(mbp
, cmdp
, mb_tmo
, ln
, cbfn
, 1);
912 cmdp
->op_to_fcfi
= htonl((FW_CMD_OP_V(FW_FCOE_VNP_CMD
) |
915 FW_FCOE_VNP_CMD_FCFI(fcfi
)));
917 cmdp
->alloc_to_len16
= htonl(FW_FCOE_VNP_CMD_ALLOC
|
918 FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
920 cmdp
->gen_wwn_to_vnpi
= htonl(FW_FCOE_VNP_CMD_VNPI(vnpi
));
922 cmdp
->iqid
= htons(iqid
);
924 if (!wwn_to_u64(vnport_wwnn
) && !wwn_to_u64(vnport_wwpn
))
925 cmdp
->gen_wwn_to_vnpi
|= htonl(FW_FCOE_VNP_CMD_GEN_WWN
);
928 memcpy(cmdp
->vnport_wwnn
, vnport_wwnn
, 8);
930 memcpy(cmdp
->vnport_wwpn
, vnport_wwpn
, 8);
932 } /* csio_fcoe_vnp_alloc_init_mb */
935 * csio_fcoe_vnp_read_init_mb - Prepares VNP read cmd.
936 * @ln: The Lnode structure.
937 * @mbp: Mailbox structure to initialize.
938 * @mb_tmo: Mailbox time-out period (in ms).
941 * @cbfn: The call-back handler.
944 csio_fcoe_vnp_read_init_mb(struct csio_lnode
*ln
, struct csio_mb
*mbp
,
945 uint32_t mb_tmo
, uint32_t fcfi
, uint32_t vnpi
,
946 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
948 struct fw_fcoe_vnp_cmd
*cmdp
=
949 (struct fw_fcoe_vnp_cmd
*)(mbp
->mb
);
951 CSIO_INIT_MBP(mbp
, cmdp
, mb_tmo
, ln
, cbfn
, 1);
952 cmdp
->op_to_fcfi
= htonl(FW_CMD_OP_V(FW_FCOE_VNP_CMD
) |
955 FW_FCOE_VNP_CMD_FCFI(fcfi
));
956 cmdp
->alloc_to_len16
= htonl(FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
957 cmdp
->gen_wwn_to_vnpi
= htonl(FW_FCOE_VNP_CMD_VNPI(vnpi
));
961 * csio_fcoe_vnp_free_init_mb - Initializes the mailbox for freeing an
962 * alloacted VNP in the firmware (FW_FCOE_VNP_CMD).
964 * @ln: The Lnode structure.
965 * @mbp: Mailbox structure to initialize.
966 * @mb_tmo: Mailbox time-out period (in ms).
969 * @cbfn: The call-back function.
973 csio_fcoe_vnp_free_init_mb(struct csio_lnode
*ln
, struct csio_mb
*mbp
,
974 uint32_t mb_tmo
, uint32_t fcfi
, uint32_t vnpi
,
975 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
977 struct fw_fcoe_vnp_cmd
*cmdp
=
978 (struct fw_fcoe_vnp_cmd
*)(mbp
->mb
);
980 CSIO_INIT_MBP(mbp
, cmdp
, mb_tmo
, ln
, cbfn
, 1);
982 cmdp
->op_to_fcfi
= htonl(FW_CMD_OP_V(FW_FCOE_VNP_CMD
) |
985 FW_FCOE_VNP_CMD_FCFI(fcfi
));
986 cmdp
->alloc_to_len16
= htonl(FW_FCOE_VNP_CMD_FREE
|
987 FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
988 cmdp
->gen_wwn_to_vnpi
= htonl(FW_FCOE_VNP_CMD_VNPI(vnpi
));
992 * csio_fcoe_read_fcf_init_mb - Initializes the mailbox to read the
995 * @ln: The Lnode structure
996 * @mbp: Mailbox structure to initialize
997 * @mb_tmo: Mailbox time-out period (in ms).
998 * @fcf_params: FC-Forwarder parameters.
999 * @cbfn: The call-back function
1004 csio_fcoe_read_fcf_init_mb(struct csio_lnode
*ln
, struct csio_mb
*mbp
,
1005 uint32_t mb_tmo
, uint32_t portid
, uint32_t fcfi
,
1006 void (*cbfn
) (struct csio_hw
*, struct csio_mb
*))
1008 struct fw_fcoe_fcf_cmd
*cmdp
=
1009 (struct fw_fcoe_fcf_cmd
*)(mbp
->mb
);
1011 CSIO_INIT_MBP(mbp
, cmdp
, mb_tmo
, ln
, cbfn
, 1);
1013 cmdp
->op_to_fcfi
= htonl(FW_CMD_OP_V(FW_FCOE_FCF_CMD
) |
1016 FW_FCOE_FCF_CMD_FCFI(fcfi
));
1017 cmdp
->retval_len16
= htonl(FW_CMD_LEN16_V(sizeof(*cmdp
) / 16));
1019 } /* csio_fcoe_read_fcf_init_mb */
1022 csio_fcoe_read_portparams_init_mb(struct csio_hw
*hw
, struct csio_mb
*mbp
,
1024 struct fw_fcoe_port_cmd_params
*portparams
,
1025 void (*cbfn
)(struct csio_hw
*,
1028 struct fw_fcoe_stats_cmd
*cmdp
= (struct fw_fcoe_stats_cmd
*)(mbp
->mb
);
1030 CSIO_INIT_MBP(mbp
, cmdp
, mb_tmo
, hw
, cbfn
, 1);
1033 cmdp
->op_to_flowid
= htonl(FW_CMD_OP_V(FW_FCOE_STATS_CMD
) |
1034 FW_CMD_REQUEST_F
| FW_CMD_READ_F
);
1035 cmdp
->free_to_len16
= htonl(FW_CMD_LEN16_V(CSIO_MAX_MB_SIZE
/16));
1037 cmdp
->u
.ctl
.nstats_port
= FW_FCOE_STATS_CMD_NSTATS(portparams
->nstats
) |
1038 FW_FCOE_STATS_CMD_PORT(portparams
->portid
);
1040 cmdp
->u
.ctl
.port_valid_ix
= FW_FCOE_STATS_CMD_IX(portparams
->idx
) |
1041 FW_FCOE_STATS_CMD_PORT_VALID
;
1043 } /* csio_fcoe_read_portparams_init_mb */
1046 csio_mb_process_portparams_rsp(struct csio_hw
*hw
,
1047 struct csio_mb
*mbp
,
1048 enum fw_retval
*retval
,
1049 struct fw_fcoe_port_cmd_params
*portparams
,
1050 struct fw_fcoe_port_stats
*portstats
)
1052 struct fw_fcoe_stats_cmd
*rsp
= (struct fw_fcoe_stats_cmd
*)(mbp
->mb
);
1053 struct fw_fcoe_port_stats stats
;
1057 *retval
= FW_CMD_RETVAL_G(ntohl(rsp
->free_to_len16
));
1059 memset(&stats
, 0, sizeof(struct fw_fcoe_port_stats
));
1061 if (*retval
== FW_SUCCESS
) {
1062 dst
= (uint8_t *)(&stats
) + ((portparams
->idx
- 1) * 8);
1063 src
= (uint8_t *)rsp
+ (CSIO_STATS_OFFSET
* 8);
1064 memcpy(dst
, src
, (portparams
->nstats
* 8));
1065 if (portparams
->idx
== 1) {
1066 /* Get the first 6 flits from the Mailbox */
1067 portstats
->tx_bcast_bytes
= stats
.tx_bcast_bytes
;
1068 portstats
->tx_bcast_frames
= stats
.tx_bcast_frames
;
1069 portstats
->tx_mcast_bytes
= stats
.tx_mcast_bytes
;
1070 portstats
->tx_mcast_frames
= stats
.tx_mcast_frames
;
1071 portstats
->tx_ucast_bytes
= stats
.tx_ucast_bytes
;
1072 portstats
->tx_ucast_frames
= stats
.tx_ucast_frames
;
1074 if (portparams
->idx
== 7) {
1075 /* Get the second 6 flits from the Mailbox */
1076 portstats
->tx_drop_frames
= stats
.tx_drop_frames
;
1077 portstats
->tx_offload_bytes
= stats
.tx_offload_bytes
;
1078 portstats
->tx_offload_frames
= stats
.tx_offload_frames
;
1080 portstats
->rx_pf_bytes
= stats
.rx_pf_bytes
;
1081 portstats
->rx_pf_frames
= stats
.rx_pf_frames
;
1083 portstats
->rx_bcast_bytes
= stats
.rx_bcast_bytes
;
1084 portstats
->rx_bcast_frames
= stats
.rx_bcast_frames
;
1085 portstats
->rx_mcast_bytes
= stats
.rx_mcast_bytes
;
1087 if (portparams
->idx
== 13) {
1088 /* Get the last 4 flits from the Mailbox */
1089 portstats
->rx_mcast_frames
= stats
.rx_mcast_frames
;
1090 portstats
->rx_ucast_bytes
= stats
.rx_ucast_bytes
;
1091 portstats
->rx_ucast_frames
= stats
.rx_ucast_frames
;
1092 portstats
->rx_err_frames
= stats
.rx_err_frames
;
1097 /* Entry points/APIs for MB module */
1099 * csio_mb_intr_enable - Enable Interrupts from mailboxes.
1100 * @hw: The HW structure
1102 * Enables CIM interrupt bit in appropriate INT_ENABLE registers.
1105 csio_mb_intr_enable(struct csio_hw
*hw
)
1107 csio_wr_reg32(hw
, MBMSGRDYINTEN(1), MYPF_REG(CIM_PF_HOST_INT_ENABLE
));
1108 csio_rd_reg32(hw
, MYPF_REG(CIM_PF_HOST_INT_ENABLE
));
1112 * csio_mb_intr_disable - Disable Interrupts from mailboxes.
1113 * @hw: The HW structure
1115 * Disable bit in HostInterruptEnable CIM register.
1118 csio_mb_intr_disable(struct csio_hw
*hw
)
1120 csio_wr_reg32(hw
, MBMSGRDYINTEN(0), MYPF_REG(CIM_PF_HOST_INT_ENABLE
));
1121 csio_rd_reg32(hw
, MYPF_REG(CIM_PF_HOST_INT_ENABLE
));
1125 csio_mb_dump_fw_dbg(struct csio_hw
*hw
, __be64
*cmd
)
1127 struct fw_debug_cmd
*dbg
= (struct fw_debug_cmd
*)cmd
;
1129 if ((FW_DEBUG_CMD_TYPE_G(ntohl(dbg
->op_type
))) == 1) {
1130 csio_info(hw
, "FW print message:\n");
1131 csio_info(hw
, "\tdebug->dprtstridx = %d\n",
1132 ntohs(dbg
->u
.prt
.dprtstridx
));
1133 csio_info(hw
, "\tdebug->dprtstrparam0 = 0x%x\n",
1134 ntohl(dbg
->u
.prt
.dprtstrparam0
));
1135 csio_info(hw
, "\tdebug->dprtstrparam1 = 0x%x\n",
1136 ntohl(dbg
->u
.prt
.dprtstrparam1
));
1137 csio_info(hw
, "\tdebug->dprtstrparam2 = 0x%x\n",
1138 ntohl(dbg
->u
.prt
.dprtstrparam2
));
1139 csio_info(hw
, "\tdebug->dprtstrparam3 = 0x%x\n",
1140 ntohl(dbg
->u
.prt
.dprtstrparam3
));
1142 /* This is a FW assertion */
1143 csio_fatal(hw
, "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
1144 dbg
->u
.assert.filename_0_7
,
1145 ntohl(dbg
->u
.assert.line
),
1146 ntohl(dbg
->u
.assert.x
),
1147 ntohl(dbg
->u
.assert.y
));
1152 csio_mb_debug_cmd_handler(struct csio_hw
*hw
)
1155 __be64 cmd
[CSIO_MB_MAX_REGS
];
1156 uint32_t ctl_reg
= PF_REG(hw
->pfn
, CIM_PF_MAILBOX_CTRL
);
1157 uint32_t data_reg
= PF_REG(hw
->pfn
, CIM_PF_MAILBOX_DATA
);
1158 int size
= sizeof(struct fw_debug_cmd
);
1160 /* Copy mailbox data */
1161 for (i
= 0; i
< size
; i
+= 8)
1162 cmd
[i
/ 8] = cpu_to_be64(csio_rd_reg64(hw
, data_reg
+ i
));
1164 csio_mb_dump_fw_dbg(hw
, cmd
);
1166 /* Notify FW of mailbox by setting owner as UP */
1167 csio_wr_reg32(hw
, MBMSGVALID
| MBINTREQ
| MBOWNER(CSIO_MBOWNER_FW
),
1170 csio_rd_reg32(hw
, ctl_reg
);
1175 * csio_mb_issue - generic routine for issuing Mailbox commands.
1176 * @hw: The HW structure
1177 * @mbp: Mailbox command to issue
1179 * Caller should hold hw lock across this call.
1182 csio_mb_issue(struct csio_hw
*hw
, struct csio_mb
*mbp
)
1184 uint32_t owner
, ctl
;
1187 __be64
*cmd
= mbp
->mb
;
1189 struct csio_mbm
*mbm
= &hw
->mbm
;
1190 uint32_t ctl_reg
= PF_REG(hw
->pfn
, CIM_PF_MAILBOX_CTRL
);
1191 uint32_t data_reg
= PF_REG(hw
->pfn
, CIM_PF_MAILBOX_DATA
);
1192 int size
= mbp
->mb_size
;
1194 struct fw_cmd_hdr
*fw_hdr
;
1196 /* Determine mode */
1197 if (mbp
->mb_cbfn
== NULL
) {
1198 /* Need to issue/get results in the same context */
1199 if (mbp
->tmo
< CSIO_MB_POLL_FREQ
) {
1200 csio_err(hw
, "Invalid tmo: 0x%x\n", mbp
->tmo
);
1203 } else if (!csio_is_host_intr_enabled(hw
) ||
1204 !csio_is_hw_intr_enabled(hw
)) {
1205 csio_err(hw
, "Cannot issue mailbox in interrupt mode 0x%x\n",
1206 *((uint8_t *)mbp
->mb
));
1210 if (mbm
->mcurrent
!= NULL
) {
1211 /* Queue mbox cmd, if another mbox cmd is active */
1212 if (mbp
->mb_cbfn
== NULL
) {
1214 csio_dbg(hw
, "Couldnt own Mailbox %x op:0x%x\n",
1215 hw
->pfn
, *((uint8_t *)mbp
->mb
));
1219 list_add_tail(&mbp
->list
, &mbm
->req_q
);
1220 CSIO_INC_STATS(mbm
, n_activeq
);
1226 /* Now get ownership of mailbox */
1227 owner
= MBOWNER_GET(csio_rd_reg32(hw
, ctl_reg
));
1229 if (!csio_mb_is_host_owner(owner
)) {
1231 for (i
= 0; (owner
== CSIO_MBOWNER_NONE
) && (i
< 3); i
++)
1232 owner
= MBOWNER_GET(csio_rd_reg32(hw
, ctl_reg
));
1234 * Mailbox unavailable. In immediate mode, fail the command.
1235 * In other modes, enqueue the request.
1237 if (!csio_mb_is_host_owner(owner
)) {
1238 if (mbp
->mb_cbfn
== NULL
) {
1239 rv
= owner
? -EBUSY
: -ETIMEDOUT
;
1242 "Couldnt own Mailbox %x op:0x%x "
1244 hw
->pfn
, *((uint8_t *)mbp
->mb
), owner
);
1247 if (mbm
->mcurrent
== NULL
) {
1249 "Couldnt own Mailbox %x "
1250 "op:0x%x owner:%x\n",
1251 hw
->pfn
, *((uint8_t *)mbp
->mb
),
1254 "No outstanding driver"
1255 " mailbox as well\n");
1262 /* Mailbox is available, copy mailbox data into it */
1263 for (i
= 0; i
< size
; i
+= 8) {
1264 csio_wr_reg64(hw
, be64_to_cpu(*cmd
), data_reg
+ i
);
1268 CSIO_DUMP_MB(hw
, hw
->pfn
, data_reg
);
1270 /* Start completion timers in non-immediate modes and notify FW */
1271 if (mbp
->mb_cbfn
!= NULL
) {
1272 mbm
->mcurrent
= mbp
;
1273 mod_timer(&mbm
->timer
, jiffies
+ msecs_to_jiffies(mbp
->tmo
));
1274 csio_wr_reg32(hw
, MBMSGVALID
| MBINTREQ
|
1275 MBOWNER(CSIO_MBOWNER_FW
), ctl_reg
);
1277 csio_wr_reg32(hw
, MBMSGVALID
| MBOWNER(CSIO_MBOWNER_FW
),
1280 /* Flush posted writes */
1281 csio_rd_reg32(hw
, ctl_reg
);
1284 CSIO_INC_STATS(mbm
, n_req
);
1289 /* Poll for completion in immediate mode */
1292 for (ii
= 0; ii
< mbp
->tmo
; ii
+= CSIO_MB_POLL_FREQ
) {
1293 mdelay(CSIO_MB_POLL_FREQ
);
1295 /* Check for response */
1296 ctl
= csio_rd_reg32(hw
, ctl_reg
);
1297 if (csio_mb_is_host_owner(MBOWNER_GET(ctl
))) {
1299 if (!(ctl
& MBMSGVALID
)) {
1300 csio_wr_reg32(hw
, 0, ctl_reg
);
1304 CSIO_DUMP_MB(hw
, hw
->pfn
, data_reg
);
1306 hdr
= cpu_to_be64(csio_rd_reg64(hw
, data_reg
));
1307 fw_hdr
= (struct fw_cmd_hdr
*)&hdr
;
1309 switch (FW_CMD_OP_G(ntohl(fw_hdr
->hi
))) {
1311 csio_mb_debug_cmd_handler(hw
);
1316 for (i
= 0; i
< size
; i
+= 8)
1317 *cmd
++ = cpu_to_be64(csio_rd_reg64
1318 (hw
, data_reg
+ i
));
1319 csio_wr_reg32(hw
, 0, ctl_reg
);
1321 if (csio_mb_fw_retval(mbp
) != FW_SUCCESS
)
1322 CSIO_INC_STATS(mbm
, n_err
);
1324 CSIO_INC_STATS(mbm
, n_rsp
);
1329 CSIO_INC_STATS(mbm
, n_tmo
);
1331 csio_err(hw
, "Mailbox %x op:0x%x timed out!\n",
1332 hw
->pfn
, *((uint8_t *)cmd
));
1337 CSIO_INC_STATS(mbm
, n_err
);
1342 * csio_mb_completions - Completion handler for Mailbox commands
1343 * @hw: The HW structure
1344 * @cbfn_q: Completion queue.
1348 csio_mb_completions(struct csio_hw
*hw
, struct list_head
*cbfn_q
)
1350 struct csio_mb
*mbp
;
1351 struct csio_mbm
*mbm
= &hw
->mbm
;
1354 while (!list_empty(cbfn_q
)) {
1355 mbp
= list_first_entry(cbfn_q
, struct csio_mb
, list
);
1356 list_del_init(&mbp
->list
);
1358 rv
= csio_mb_fw_retval(mbp
);
1359 if ((rv
!= FW_SUCCESS
) && (rv
!= FW_HOSTERROR
))
1360 CSIO_INC_STATS(mbm
, n_err
);
1361 else if (rv
!= FW_HOSTERROR
)
1362 CSIO_INC_STATS(mbm
, n_rsp
);
1365 mbp
->mb_cbfn(hw
, mbp
);
1370 csio_mb_portmod_changed(struct csio_hw
*hw
, uint8_t port_id
)
1372 static char *mod_str
[] = {
1373 NULL
, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
1376 struct csio_pport
*port
= &hw
->pport
[port_id
];
1378 if (port
->mod_type
== FW_PORT_MOD_TYPE_NONE
)
1379 csio_info(hw
, "Port:%d - port module unplugged\n", port_id
);
1380 else if (port
->mod_type
< ARRAY_SIZE(mod_str
))
1381 csio_info(hw
, "Port:%d - %s port module inserted\n", port_id
,
1382 mod_str
[port
->mod_type
]);
1383 else if (port
->mod_type
== FW_PORT_MOD_TYPE_NOTSUPPORTED
)
1385 "Port:%d - unsupported optical port module "
1386 "inserted\n", port_id
);
1387 else if (port
->mod_type
== FW_PORT_MOD_TYPE_UNKNOWN
)
1389 "Port:%d - unknown port module inserted, forcing "
1390 "TWINAX\n", port_id
);
1391 else if (port
->mod_type
== FW_PORT_MOD_TYPE_ERROR
)
1392 csio_info(hw
, "Port:%d - transceiver module error\n", port_id
);
1394 csio_info(hw
, "Port:%d - unknown module type %d inserted\n",
1395 port_id
, port
->mod_type
);
1399 csio_mb_fwevt_handler(struct csio_hw
*hw
, __be64
*cmd
)
1401 uint8_t opcode
= *(uint8_t *)cmd
;
1402 struct fw_port_cmd
*pcmd
;
1404 uint32_t link_status
;
1408 if (opcode
== FW_PORT_CMD
) {
1409 pcmd
= (struct fw_port_cmd
*)cmd
;
1410 port_id
= FW_PORT_CMD_PORTID_G(
1411 ntohl(pcmd
->op_to_portid
));
1412 action
= FW_PORT_CMD_ACTION_G(
1413 ntohl(pcmd
->action_to_len16
));
1414 if (action
!= FW_PORT_ACTION_GET_PORT_INFO
) {
1415 csio_err(hw
, "Unhandled FW_PORT_CMD action: %u\n",
1420 link_status
= ntohl(pcmd
->u
.info
.lstatus_to_modtype
);
1421 mod_type
= FW_PORT_CMD_MODTYPE_G(link_status
);
1423 hw
->pport
[port_id
].link_status
=
1424 FW_PORT_CMD_LSTATUS_G(link_status
);
1425 hw
->pport
[port_id
].link_speed
=
1426 FW_PORT_CMD_LSPEED_G(link_status
);
1428 csio_info(hw
, "Port:%x - LINK %s\n", port_id
,
1429 FW_PORT_CMD_LSTATUS_G(link_status
) ? "UP" : "DOWN");
1431 if (mod_type
!= hw
->pport
[port_id
].mod_type
) {
1432 hw
->pport
[port_id
].mod_type
= mod_type
;
1433 csio_mb_portmod_changed(hw
, port_id
);
1435 } else if (opcode
== FW_DEBUG_CMD
) {
1436 csio_mb_dump_fw_dbg(hw
, cmd
);
1438 csio_dbg(hw
, "Gen MB can't handle op:0x%x on evtq.\n", opcode
);
1446 * csio_mb_isr_handler - Handle mailboxes related interrupts.
1447 * @hw: The HW structure
1449 * Called from the ISR to handle Mailbox related interrupts.
1450 * HW Lock should be held across this call.
1453 csio_mb_isr_handler(struct csio_hw
*hw
)
1455 struct csio_mbm
*mbm
= &hw
->mbm
;
1456 struct csio_mb
*mbp
= mbm
->mcurrent
;
1458 uint32_t ctl
, cim_cause
, pl_cause
;
1460 uint32_t ctl_reg
= PF_REG(hw
->pfn
, CIM_PF_MAILBOX_CTRL
);
1461 uint32_t data_reg
= PF_REG(hw
->pfn
, CIM_PF_MAILBOX_DATA
);
1464 struct fw_cmd_hdr
*fw_hdr
;
1466 pl_cause
= csio_rd_reg32(hw
, MYPF_REG(PL_PF_INT_CAUSE
));
1467 cim_cause
= csio_rd_reg32(hw
, MYPF_REG(CIM_PF_HOST_INT_CAUSE
));
1469 if (!(pl_cause
& PFCIM
) || !(cim_cause
& MBMSGRDYINT
)) {
1470 CSIO_INC_STATS(hw
, n_mbint_unexp
);
1475 * The cause registers below HAVE to be cleared in the SAME
1476 * order as below: The low level cause register followed by
1477 * the upper level cause register. In other words, CIM-cause
1478 * first followed by PL-Cause next.
1480 csio_wr_reg32(hw
, MBMSGRDYINT
, MYPF_REG(CIM_PF_HOST_INT_CAUSE
));
1481 csio_wr_reg32(hw
, PFCIM
, MYPF_REG(PL_PF_INT_CAUSE
));
1483 ctl
= csio_rd_reg32(hw
, ctl_reg
);
1485 if (csio_mb_is_host_owner(MBOWNER_GET(ctl
))) {
1487 CSIO_DUMP_MB(hw
, hw
->pfn
, data_reg
);
1489 if (!(ctl
& MBMSGVALID
)) {
1491 "Stray mailbox interrupt recvd,"
1492 " mailbox data not valid\n");
1493 csio_wr_reg32(hw
, 0, ctl_reg
);
1495 csio_rd_reg32(hw
, ctl_reg
);
1499 hdr
= cpu_to_be64(csio_rd_reg64(hw
, data_reg
));
1500 fw_hdr
= (struct fw_cmd_hdr
*)&hdr
;
1502 switch (FW_CMD_OP_G(ntohl(fw_hdr
->hi
))) {
1504 csio_mb_debug_cmd_handler(hw
);
1508 case FW_INITIALIZE_CMD
: /* When we are not master */
1512 CSIO_ASSERT(mbp
!= NULL
);
1515 size
= mbp
->mb_size
;
1517 for (i
= 0; i
< size
; i
+= 8)
1518 *cmd
++ = cpu_to_be64(csio_rd_reg64
1519 (hw
, data_reg
+ i
));
1521 csio_wr_reg32(hw
, 0, ctl_reg
);
1523 csio_rd_reg32(hw
, ctl_reg
);
1525 mbm
->mcurrent
= NULL
;
1527 /* Add completion to tail of cbfn queue */
1528 list_add_tail(&mbp
->list
, &mbm
->cbfn_q
);
1529 CSIO_INC_STATS(mbm
, n_cbfnq
);
1532 * Enqueue event to EventQ. Events processing happens
1533 * in Event worker thread context
1535 if (csio_enqueue_evt(hw
, CSIO_EVT_MBX
, mbp
, sizeof(mbp
)))
1536 CSIO_INC_STATS(hw
, n_evt_drop
);
1542 * We can get here if mailbox MSIX vector is shared,
1543 * or in INTx case. Or a stray interrupt.
1545 csio_dbg(hw
, "Host not owner, no mailbox interrupt\n");
1546 CSIO_INC_STATS(hw
, n_int_stray
);
1552 * csio_mb_tmo_handler - Timeout handler
1553 * @hw: The HW structure
1557 csio_mb_tmo_handler(struct csio_hw
*hw
)
1559 struct csio_mbm
*mbm
= &hw
->mbm
;
1560 struct csio_mb
*mbp
= mbm
->mcurrent
;
1561 struct fw_cmd_hdr
*fw_hdr
;
1564 * Could be a race b/w the completion handler and the timer
1565 * and the completion handler won that race.
1572 fw_hdr
= (struct fw_cmd_hdr
*)(mbp
->mb
);
1574 csio_dbg(hw
, "Mailbox num:%x op:0x%x timed out\n", hw
->pfn
,
1575 FW_CMD_OP_G(ntohl(fw_hdr
->hi
)));
1577 mbm
->mcurrent
= NULL
;
1578 CSIO_INC_STATS(mbm
, n_tmo
);
1579 fw_hdr
->lo
= htonl(FW_CMD_RETVAL_V(FW_ETIMEDOUT
));
1585 * csio_mb_cancel_all - Cancel all waiting commands.
1586 * @hw: The HW structure
1587 * @cbfn_q: The callback queue.
1589 * Caller should hold hw lock across this call.
1592 csio_mb_cancel_all(struct csio_hw
*hw
, struct list_head
*cbfn_q
)
1594 struct csio_mb
*mbp
;
1595 struct csio_mbm
*mbm
= &hw
->mbm
;
1596 struct fw_cmd_hdr
*hdr
;
1597 struct list_head
*tmp
;
1599 if (mbm
->mcurrent
) {
1600 mbp
= mbm
->mcurrent
;
1602 /* Stop mailbox completion timer */
1603 del_timer_sync(&mbm
->timer
);
1605 /* Add completion to tail of cbfn queue */
1606 list_add_tail(&mbp
->list
, cbfn_q
);
1607 mbm
->mcurrent
= NULL
;
1610 if (!list_empty(&mbm
->req_q
)) {
1611 list_splice_tail_init(&mbm
->req_q
, cbfn_q
);
1612 mbm
->stats
.n_activeq
= 0;
1615 if (!list_empty(&mbm
->cbfn_q
)) {
1616 list_splice_tail_init(&mbm
->cbfn_q
, cbfn_q
);
1617 mbm
->stats
.n_cbfnq
= 0;
1620 if (list_empty(cbfn_q
))
1623 list_for_each(tmp
, cbfn_q
) {
1624 mbp
= (struct csio_mb
*)tmp
;
1625 hdr
= (struct fw_cmd_hdr
*)(mbp
->mb
);
1627 csio_dbg(hw
, "Cancelling pending mailbox num %x op:%x\n",
1628 hw
->pfn
, FW_CMD_OP_G(ntohl(hdr
->hi
)));
1630 CSIO_INC_STATS(mbm
, n_cancel
);
1631 hdr
->lo
= htonl(FW_CMD_RETVAL_V(FW_HOSTERROR
));
1636 * csio_mbm_init - Initialize Mailbox module
1637 * @mbm: Mailbox module
1638 * @hw: The HW structure
1639 * @timer: Timing function for interrupting mailboxes
1641 * Initialize timer and the request/response queues.
1644 csio_mbm_init(struct csio_mbm
*mbm
, struct csio_hw
*hw
,
1645 void (*timer_fn
)(uintptr_t))
1647 struct timer_list
*timer
= &mbm
->timer
;
1650 timer
->function
= timer_fn
;
1651 timer
->data
= (unsigned long)hw
;
1653 INIT_LIST_HEAD(&mbm
->req_q
);
1654 INIT_LIST_HEAD(&mbm
->cbfn_q
);
1655 csio_set_mb_intr_idx(mbm
, -1);
1661 * csio_mbm_exit - Uninitialize mailbox module
1662 * @mbm: Mailbox module
1667 csio_mbm_exit(struct csio_mbm
*mbm
)
1669 del_timer_sync(&mbm
->timer
);
1671 CSIO_DB_ASSERT(mbm
->mcurrent
== NULL
);
1672 CSIO_DB_ASSERT(list_empty(&mbm
->req_q
));
1673 CSIO_DB_ASSERT(list_empty(&mbm
->cbfn_q
));