| blob | bb788eddf9f4e8cc0493c62279745f6475ec6250 |
1 /*
2 * Device Tree Include file for Freescale Layerscape-1012A family SoC.
3 *
4 * Copyright 2016 Freescale Semiconductor, Inc.
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPLv2 or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 / {
49 compatible = "fsl,ls1012a";
50 interrupt-parent = <&gic>;
51 #address-cells = <2>;
52 #size-cells = <2>;
54 aliases {
55 crypto = &crypto;
56 rtic_a = &rtic_a;
57 rtic_b = &rtic_b;
58 rtic_c = &rtic_c;
59 rtic_d = &rtic_d;
60 sec_mon = &sec_mon;
61 };
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
67 cpu0: cpu@0 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a53";
70 reg = <0x0>;
71 clocks = <&clockgen 1 0>;
72 #cooling-cells = <2>;
73 cpu-idle-states = <&CPU_PH20>;
74 };
75 };
77 idle-states {
78 /*
79 * PSCI node is not added default, U-boot will add missing
80 * parts if it determines to use PSCI.
81 */
82 entry-method = "arm,psci";
84 CPU_PH20: cpu-ph20 {
85 compatible = "arm,idle-state";
86 idle-state-name = "PH20";
87 arm,psci-suspend-param = <0x0>;
88 entry-latency-us = <1000>;
89 exit-latency-us = <1000>;
90 min-residency-us = <3000>;
91 };
92 };
94 sysclk: sysclk {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <125000000>;
98 clock-output-names = "sysclk";
99 };
101 coreclk: coreclk {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <100000000>;
105 clock-output-names = "coreclk";
106 };
108 timer {
109 compatible = "arm,armv8-timer";
110 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
111 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
112 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
113 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
114 };
116 pmu {
117 compatible = "arm,armv8-pmuv3";
118 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
119 };
121 gic: interrupt-controller@1400000 {
122 compatible = "arm,gic-400";
123 #interrupt-cells = <3>;
124 interrupt-controller;
125 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
126 <0x0 0x1402000 0 0x2000>, /* GICC */
127 <0x0 0x1404000 0 0x2000>, /* GICH */
128 <0x0 0x1406000 0 0x2000>; /* GICV */
129 interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
130 };
132 reboot {
133 compatible = "syscon-reboot";
134 regmap = <&dcfg>;
135 offset = <0xb0>;
136 mask = <0x02>;
137 };
139 thermal-zones {
140 cpu_thermal: cpu-thermal {
141 polling-delay-passive = <1000>;
142 polling-delay = <5000>;
143 thermal-sensors = <&tmu 0>;
145 trips {
146 cpu_alert: cpu-alert {
147 temperature = <85000>;
148 hysteresis = <2000>;
149 type = "passive";
150 };
152 cpu_crit: cpu-crit {
153 temperature = <95000>;
154 hysteresis = <2000>;
155 type = "critical";
156 };
157 };
159 cooling-maps {
160 map0 {
161 trip = <&cpu_alert>;
162 cooling-device =
163 <&cpu0 THERMAL_NO_LIMIT
164 THERMAL_NO_LIMIT>;
165 };
166 };
167 };
168 };
170 soc {
171 compatible = "simple-bus";
172 #address-cells = <2>;
173 #size-cells = <2>;
174 ranges;
176 esdhc0: esdhc@1560000 {
177 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
178 reg = <0x0 0x1560000 0x0 0x10000>;
179 interrupts = <0 62 0x4>;
180 clocks = <&clockgen 4 0>;
181 voltage-ranges = <1800 1800 3300 3300>;
182 sdhci,auto-cmd12;
183 big-endian;
184 bus-width = <4>;
185 status = "disabled";
186 };
188 scfg: scfg@1570000 {
189 compatible = "fsl,ls1012a-scfg", "syscon";
190 reg = <0x0 0x1570000 0x0 0x10000>;
191 big-endian;
192 };
194 esdhc1: esdhc@1580000 {
195 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
196 reg = <0x0 0x1580000 0x0 0x10000>;
197 interrupts = <0 65 0x4>;
198 clocks = <&clockgen 4 0>;
199 voltage-ranges = <1800 1800 3300 3300>;
200 sdhci,auto-cmd12;
201 big-endian;
202 broken-cd;
203 bus-width = <4>;
204 status = "disabled";
205 };
207 crypto: crypto@1700000 {
208 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
209 "fsl,sec-v4.0";
210 fsl,sec-era = <8>;
211 #address-cells = <1>;
212 #size-cells = <1>;
213 ranges = <0x0 0x00 0x1700000 0x100000>;
214 reg = <0x00 0x1700000 0x0 0x100000>;
215 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
217 sec_jr0: jr@10000 {
218 compatible = "fsl,sec-v5.4-job-ring",
219 "fsl,sec-v5.0-job-ring",
220 "fsl,sec-v4.0-job-ring";
221 reg = <0x10000 0x10000>;
222 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
223 };
225 sec_jr1: jr@20000 {
226 compatible = "fsl,sec-v5.4-job-ring",
227 "fsl,sec-v5.0-job-ring",
228 "fsl,sec-v4.0-job-ring";
229 reg = <0x20000 0x10000>;
230 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
231 };
233 sec_jr2: jr@30000 {
234 compatible = "fsl,sec-v5.4-job-ring",
235 "fsl,sec-v5.0-job-ring",
236 "fsl,sec-v4.0-job-ring";
237 reg = <0x30000 0x10000>;
238 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
239 };
241 sec_jr3: jr@40000 {
242 compatible = "fsl,sec-v5.4-job-ring",
243 "fsl,sec-v5.0-job-ring",
244 "fsl,sec-v4.0-job-ring";
245 reg = <0x40000 0x10000>;
246 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
247 };
249 rtic@60000 {
250 compatible = "fsl,sec-v5.4-rtic",
251 "fsl,sec-v5.0-rtic",
252 "fsl,sec-v4.0-rtic";
253 #address-cells = <1>;
254 #size-cells = <1>;
255 reg = <0x60000 0x100 0x60e00 0x18>;
256 ranges = <0x0 0x60100 0x500>;
258 rtic_a: rtic-a@0 {
259 compatible = "fsl,sec-v5.4-rtic-memory",
260 "fsl,sec-v5.0-rtic-memory",
261 "fsl,sec-v4.0-rtic-memory";
262 reg = <0x00 0x20 0x100 0x100>;
263 };
265 rtic_b: rtic-b@20 {
266 compatible = "fsl,sec-v5.4-rtic-memory",
267 "fsl,sec-v5.0-rtic-memory",
268 "fsl,sec-v4.0-rtic-memory";
269 reg = <0x20 0x20 0x200 0x100>;
270 };
272 rtic_c: rtic-c@40 {
273 compatible = "fsl,sec-v5.4-rtic-memory",
274 "fsl,sec-v5.0-rtic-memory",
275 "fsl,sec-v4.0-rtic-memory";
276 reg = <0x40 0x20 0x300 0x100>;
277 };
279 rtic_d: rtic-d@60 {
280 compatible = "fsl,sec-v5.4-rtic-memory",
281 "fsl,sec-v5.0-rtic-memory",
282 "fsl,sec-v4.0-rtic-memory";
283 reg = <0x60 0x20 0x400 0x100>;
284 };
285 };
286 };
288 sec_mon: sec_mon@1e90000 {
289 compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
290 "fsl,sec-v4.0-mon";
291 reg = <0x0 0x1e90000 0x0 0x10000>;
292 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
294 };
296 dcfg: dcfg@1ee0000 {
297 compatible = "fsl,ls1012a-dcfg",
298 "syscon";
299 reg = <0x0 0x1ee0000 0x0 0x10000>;
300 big-endian;
301 };
303 clockgen: clocking@1ee1000 {
304 compatible = "fsl,ls1012a-clockgen";
305 reg = <0x0 0x1ee1000 0x0 0x1000>;
306 #clock-cells = <2>;
307 clocks = <&sysclk &coreclk>;
308 clock-names = "sysclk", "coreclk";
309 };
311 tmu: tmu@1f00000 {
312 compatible = "fsl,qoriq-tmu";
313 reg = <0x0 0x1f00000 0x0 0x10000>;
314 interrupts = <0 33 0x4>;
315 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
316 fsl,tmu-calibration = <0x00000000 0x00000026
317 0x00000001 0x0000002d
318 0x00000002 0x00000032
319 0x00000003 0x00000039
320 0x00000004 0x0000003f
321 0x00000005 0x00000046
322 0x00000006 0x0000004d
323 0x00000007 0x00000054
324 0x00000008 0x0000005a
325 0x00000009 0x00000061
326 0x0000000a 0x0000006a
327 0x0000000b 0x00000071
329 0x00010000 0x00000025
330 0x00010001 0x0000002c
331 0x00010002 0x00000035
332 0x00010003 0x0000003d
333 0x00010004 0x00000045
334 0x00010005 0x0000004e
335 0x00010006 0x00000057
336 0x00010007 0x00000061
337 0x00010008 0x0000006b
338 0x00010009 0x00000076
340 0x00020000 0x00000029
341 0x00020001 0x00000033
342 0x00020002 0x0000003d
343 0x00020003 0x00000049
344 0x00020004 0x00000056
345 0x00020005 0x00000061
346 0x00020006 0x0000006d
348 0x00030000 0x00000021
349 0x00030001 0x0000002a
350 0x00030002 0x0000003c
351 0x00030003 0x0000004e>;
352 big-endian;
353 #thermal-sensor-cells = <1>;
354 };
356 i2c0: i2c@2180000 {
357 compatible = "fsl,vf610-i2c";
358 #address-cells = <1>;
359 #size-cells = <0>;
360 reg = <0x0 0x2180000 0x0 0x10000>;
361 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&clockgen 4 0>;
363 status = "disabled";
364 };
366 i2c1: i2c@2190000 {
367 compatible = "fsl,vf610-i2c";
368 #address-cells = <1>;
369 #size-cells = <0>;
370 reg = <0x0 0x2190000 0x0 0x10000>;
371 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&clockgen 4 0>;
373 status = "disabled";
374 };
376 dspi: dspi@2100000 {
377 compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
378 #address-cells = <1>;
379 #size-cells = <0>;
380 reg = <0x0 0x2100000 0x0 0x10000>;
381 interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
382 clock-names = "dspi";
383 clocks = <&clockgen 4 0>;
384 spi-num-chipselects = <5>;
385 big-endian;
386 status = "disabled";
387 };
389 duart0: serial@21c0500 {
390 compatible = "fsl,ns16550", "ns16550a";
391 reg = <0x00 0x21c0500 0x0 0x100>;
392 interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&clockgen 4 0>;
394 status = "disabled";
395 };
397 duart1: serial@21c0600 {
398 compatible = "fsl,ns16550", "ns16550a";
399 reg = <0x00 0x21c0600 0x0 0x100>;
400 interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&clockgen 4 0>;
402 status = "disabled";
403 };
405 gpio0: gpio@2300000 {
406 compatible = "fsl,qoriq-gpio";
407 reg = <0x0 0x2300000 0x0 0x10000>;
408 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
409 gpio-controller;
410 #gpio-cells = <2>;
411 interrupt-controller;
412 #interrupt-cells = <2>;
413 };
415 gpio1: gpio@2310000 {
416 compatible = "fsl,qoriq-gpio";
417 reg = <0x0 0x2310000 0x0 0x10000>;
418 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
419 gpio-controller;
420 #gpio-cells = <2>;
421 interrupt-controller;
422 #interrupt-cells = <2>;
423 };
425 wdog0: wdog@2ad0000 {
426 compatible = "fsl,ls1012a-wdt",
427 "fsl,imx21-wdt";
428 reg = <0x0 0x2ad0000 0x0 0x10000>;
429 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clockgen 4 0>;
431 big-endian;
432 };
434 sai1: sai@2b50000 {
435 #sound-dai-cells = <0>;
436 compatible = "fsl,vf610-sai";
437 reg = <0x0 0x2b50000 0x0 0x10000>;
438 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&clockgen 4 3>, <&clockgen 4 3>,
440 <&clockgen 4 3>, <&clockgen 4 3>;
441 clock-names = "bus", "mclk1", "mclk2", "mclk3";
442 dma-names = "tx", "rx";
443 dmas = <&edma0 1 47>,
444 <&edma0 1 46>;
445 status = "disabled";
446 };
448 sai2: sai@2b60000 {
449 #sound-dai-cells = <0>;
450 compatible = "fsl,vf610-sai";
451 reg = <0x0 0x2b60000 0x0 0x10000>;
452 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&clockgen 4 3>, <&clockgen 4 3>,
454 <&clockgen 4 3>, <&clockgen 4 3>;
455 clock-names = "bus", "mclk1", "mclk2", "mclk3";
456 dma-names = "tx", "rx";
457 dmas = <&edma0 1 45>,
458 <&edma0 1 44>;
459 status = "disabled";
460 };
462 edma0: edma@2c00000 {
463 #dma-cells = <2>;
464 compatible = "fsl,vf610-edma";
465 reg = <0x0 0x2c00000 0x0 0x10000>,
466 <0x0 0x2c10000 0x0 0x10000>,
467 <0x0 0x2c20000 0x0 0x10000>;
468 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
469 <0 103 IRQ_TYPE_LEVEL_HIGH>;
470 interrupt-names = "edma-tx", "edma-err";
471 dma-channels = <32>;
472 big-endian;
473 clock-names = "dmamux0", "dmamux1";
474 clocks = <&clockgen 4 3>,
475 <&clockgen 4 3>;
476 };
478 usb0: usb3@2f00000 {
479 compatible = "snps,dwc3";
480 reg = <0x0 0x2f00000 0x0 0x10000>;
481 interrupts = <0 60 0x4>;
482 dr_mode = "host";
483 snps,quirk-frame-length-adjustment = <0x20>;
484 snps,dis_rxdet_inp3_quirk;
485 };
487 sata: sata@3200000 {
488 compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
489 reg = <0x0 0x3200000 0x0 0x10000>,
490 <0x0 0x20140520 0x0 0x4>;
491 reg-names = "ahci", "sata-ecc";
492 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&clockgen 4 0>;
494 dma-coherent;
495 status = "disabled";
496 };
498 usb1: usb2@8600000 {
499 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
500 reg = <0x0 0x8600000 0x0 0x1000>;
501 interrupts = <0 139 0x4>;
502 dr_mode = "host";
503 phy_type = "ulpi";
504 };
506 msi: msi-controller1@1572000 {
507 compatible = "fsl,ls1012a-msi";
508 reg = <0x0 0x1572000 0x0 0x8>;
509 msi-controller;
510 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
511 };
513 pcie@3400000 {
514 compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
515 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
516 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
517 reg-names = "regs", "config";
518 interrupts = <0 118 0x4>, /* controller interrupt */
519 <0 117 0x4>; /* PME interrupt */
520 interrupt-names = "aer", "pme";
521 #address-cells = <3>;
522 #size-cells = <2>;
523 device_type = "pci";
524 num-lanes = <4>;
525 bus-range = <0x0 0xff>;
526 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
527 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
528 msi-parent = <&msi>;
529 #interrupt-cells = <1>;
530 interrupt-map-mask = <0 0 0 7>;
531 interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
532 <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
533 <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
534 <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
535 };
536 };
538 firmware {
539 optee {
540 compatible = "linaro,optee-tz";
541 method = "smc";
542 };
543 };
544 };