| blob | 136ebfa9b3332018f24dce132d6acc6b6b5c5326 |
1 /*
2 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3 *
4 * Copyright 2016 Freescale Semiconductor, Inc.
5 *
6 * Mingkai Hu <mingkai.hu@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 / {
51 compatible = "fsl,ls1046a";
52 interrupt-parent = <&gic>;
53 #address-cells = <2>;
54 #size-cells = <2>;
56 aliases {
57 crypto = &crypto;
58 fman0 = &fman0;
59 ethernet0 = &enet0;
60 ethernet1 = &enet1;
61 ethernet2 = &enet2;
62 ethernet3 = &enet3;
63 ethernet4 = &enet4;
64 ethernet5 = &enet5;
65 ethernet6 = &enet6;
66 ethernet7 = &enet7;
67 };
69 cpus {
70 #address-cells = <1>;
71 #size-cells = <0>;
73 cpu0: cpu@0 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a72";
76 reg = <0x0>;
77 clocks = <&clockgen 1 0>;
78 next-level-cache = <&l2>;
79 cpu-idle-states = <&CPU_PH20>;
80 #cooling-cells = <2>;
81 };
83 cpu1: cpu@1 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a72";
86 reg = <0x1>;
87 clocks = <&clockgen 1 0>;
88 next-level-cache = <&l2>;
89 cpu-idle-states = <&CPU_PH20>;
90 };
92 cpu2: cpu@2 {
93 device_type = "cpu";
94 compatible = "arm,cortex-a72";
95 reg = <0x2>;
96 clocks = <&clockgen 1 0>;
97 next-level-cache = <&l2>;
98 cpu-idle-states = <&CPU_PH20>;
99 };
101 cpu3: cpu@3 {
102 device_type = "cpu";
103 compatible = "arm,cortex-a72";
104 reg = <0x3>;
105 clocks = <&clockgen 1 0>;
106 next-level-cache = <&l2>;
107 cpu-idle-states = <&CPU_PH20>;
108 };
110 l2: l2-cache {
111 compatible = "cache";
112 };
113 };
115 idle-states {
116 /*
117 * PSCI node is not added default, U-boot will add missing
118 * parts if it determines to use PSCI.
119 */
120 entry-method = "arm,psci";
122 CPU_PH20: cpu-ph20 {
123 compatible = "arm,idle-state";
124 idle-state-name = "PH20";
125 arm,psci-suspend-param = <0x0>;
126 entry-latency-us = <1000>;
127 exit-latency-us = <1000>;
128 min-residency-us = <3000>;
129 };
130 };
132 memory@80000000 {
133 device_type = "memory";
134 /* Real size will be filled by bootloader */
135 reg = <0x0 0x80000000 0x0 0x0>;
136 };
138 sysclk: sysclk {
139 compatible = "fixed-clock";
140 #clock-cells = <0>;
141 clock-frequency = <100000000>;
142 clock-output-names = "sysclk";
143 };
145 reboot {
146 compatible ="syscon-reboot";
147 regmap = <&dcfg>;
148 offset = <0xb0>;
149 mask = <0x02>;
150 };
152 thermal-zones {
153 cpu_thermal: cpu-thermal {
154 polling-delay-passive = <1000>;
155 polling-delay = <5000>;
156 thermal-sensors = <&tmu 3>;
158 trips {
159 cpu_alert: cpu-alert {
160 temperature = <85000>;
161 hysteresis = <2000>;
162 type = "passive";
163 };
165 cpu_crit: cpu-crit {
166 temperature = <95000>;
167 hysteresis = <2000>;
168 type = "critical";
169 };
170 };
172 cooling-maps {
173 map0 {
174 trip = <&cpu_alert>;
175 cooling-device =
176 <&cpu0 THERMAL_NO_LIMIT
177 THERMAL_NO_LIMIT>;
178 };
179 };
180 };
181 };
183 timer {
184 compatible = "arm,armv8-timer";
185 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
186 IRQ_TYPE_LEVEL_LOW)>,
187 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
188 IRQ_TYPE_LEVEL_LOW)>,
189 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
190 IRQ_TYPE_LEVEL_LOW)>,
191 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
192 IRQ_TYPE_LEVEL_LOW)>;
193 };
195 pmu {
196 compatible = "arm,cortex-a72-pmu";
197 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-affinity = <&cpu0>,
202 <&cpu1>,
203 <&cpu2>,
204 <&cpu3>;
205 };
207 gic: interrupt-controller@1400000 {
208 compatible = "arm,gic-400";
209 #interrupt-cells = <3>;
210 interrupt-controller;
211 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
212 <0x0 0x1420000 0 0x20000>, /* GICC */
213 <0x0 0x1440000 0 0x20000>, /* GICH */
214 <0x0 0x1460000 0 0x20000>; /* GICV */
215 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
216 IRQ_TYPE_LEVEL_LOW)>;
217 };
219 soc: soc {
220 compatible = "simple-bus";
221 #address-cells = <2>;
222 #size-cells = <2>;
223 ranges;
225 ddr: memory-controller@1080000 {
226 compatible = "fsl,qoriq-memory-controller";
227 reg = <0x0 0x1080000 0x0 0x1000>;
228 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
229 big-endian;
230 };
232 ifc: ifc@1530000 {
233 compatible = "fsl,ifc", "simple-bus";
234 reg = <0x0 0x1530000 0x0 0x10000>;
235 big-endian;
236 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
237 };
239 qspi: quadspi@1550000 {
240 compatible = "fsl,ls1021a-qspi";
241 #address-cells = <1>;
242 #size-cells = <0>;
243 reg = <0x0 0x1550000 0x0 0x10000>,
244 <0x0 0x40000000 0x0 0x10000000>;
245 reg-names = "QuadSPI", "QuadSPI-memory";
246 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
247 clock-names = "qspi_en", "qspi";
248 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
249 big-endian;
250 fsl,qspi-has-second-chip;
251 status = "disabled";
252 };
254 esdhc: esdhc@1560000 {
255 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
256 reg = <0x0 0x1560000 0x0 0x10000>;
257 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&clockgen 2 1>;
259 voltage-ranges = <1800 1800 3300 3300>;
260 sdhci,auto-cmd12;
261 big-endian;
262 bus-width = <4>;
263 };
265 scfg: scfg@1570000 {
266 compatible = "fsl,ls1046a-scfg", "syscon";
267 reg = <0x0 0x1570000 0x0 0x10000>;
268 big-endian;
269 };
271 crypto: crypto@1700000 {
272 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
273 "fsl,sec-v4.0";
274 fsl,sec-era = <8>;
275 #address-cells = <1>;
276 #size-cells = <1>;
277 ranges = <0x0 0x00 0x1700000 0x100000>;
278 reg = <0x00 0x1700000 0x0 0x100000>;
279 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
281 sec_jr0: jr@10000 {
282 compatible = "fsl,sec-v5.4-job-ring",
283 "fsl,sec-v5.0-job-ring",
284 "fsl,sec-v4.0-job-ring";
285 reg = <0x10000 0x10000>;
286 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
287 };
289 sec_jr1: jr@20000 {
290 compatible = "fsl,sec-v5.4-job-ring",
291 "fsl,sec-v5.0-job-ring",
292 "fsl,sec-v4.0-job-ring";
293 reg = <0x20000 0x10000>;
294 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
295 };
297 sec_jr2: jr@30000 {
298 compatible = "fsl,sec-v5.4-job-ring",
299 "fsl,sec-v5.0-job-ring",
300 "fsl,sec-v4.0-job-ring";
301 reg = <0x30000 0x10000>;
302 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
303 };
305 sec_jr3: jr@40000 {
306 compatible = "fsl,sec-v5.4-job-ring",
307 "fsl,sec-v5.0-job-ring",
308 "fsl,sec-v4.0-job-ring";
309 reg = <0x40000 0x10000>;
310 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
311 };
312 };
314 qman: qman@1880000 {
315 compatible = "fsl,qman";
316 reg = <0x0 0x1880000 0x0 0x10000>;
317 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
318 memory-region = <&qman_fqd &qman_pfdr>;
320 };
322 bman: bman@1890000 {
323 compatible = "fsl,bman";
324 reg = <0x0 0x1890000 0x0 0x10000>;
325 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
326 memory-region = <&bman_fbpr>;
328 };
330 qportals: qman-portals@500000000 {
331 ranges = <0x0 0x5 0x00000000 0x8000000>;
332 };
334 bportals: bman-portals@508000000 {
335 ranges = <0x0 0x5 0x08000000 0x8000000>;
336 };
338 dcfg: dcfg@1ee0000 {
339 compatible = "fsl,ls1046a-dcfg", "syscon";
340 reg = <0x0 0x1ee0000 0x0 0x10000>;
341 big-endian;
342 };
344 clockgen: clocking@1ee1000 {
345 compatible = "fsl,ls1046a-clockgen";
346 reg = <0x0 0x1ee1000 0x0 0x1000>;
347 #clock-cells = <2>;
348 clocks = <&sysclk>;
349 };
351 tmu: tmu@1f00000 {
352 compatible = "fsl,qoriq-tmu";
353 reg = <0x0 0x1f00000 0x0 0x10000>;
354 interrupts = <0 33 0x4>;
355 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
356 fsl,tmu-calibration =
357 /* Calibration data group 1 */
358 <0x00000000 0x00000026
359 0x00000001 0x0000002d
360 0x00000002 0x00000032
361 0x00000003 0x00000039
362 0x00000004 0x0000003f
363 0x00000005 0x00000046
364 0x00000006 0x0000004d
365 0x00000007 0x00000054
366 0x00000008 0x0000005a
367 0x00000009 0x00000061
368 0x0000000a 0x0000006a
369 0x0000000b 0x00000071
370 /* Calibration data group 2 */
371 0x00010000 0x00000025
372 0x00010001 0x0000002c
373 0x00010002 0x00000035
374 0x00010003 0x0000003d
375 0x00010004 0x00000045
376 0x00010005 0x0000004e
377 0x00010006 0x00000057
378 0x00010007 0x00000061
379 0x00010008 0x0000006b
380 0x00010009 0x00000076
381 /* Calibration data group 3 */
382 0x00020000 0x00000029
383 0x00020001 0x00000033
384 0x00020002 0x0000003d
385 0x00020003 0x00000049
386 0x00020004 0x00000056
387 0x00020005 0x00000061
388 0x00020006 0x0000006d
389 /* Calibration data group 4 */
390 0x00030000 0x00000021
391 0x00030001 0x0000002a
392 0x00030002 0x0000003c
393 0x00030003 0x0000004e>;
394 big-endian;
395 #thermal-sensor-cells = <1>;
396 };
398 dspi: dspi@2100000 {
399 compatible = "fsl,ls1021a-v1.0-dspi";
400 #address-cells = <1>;
401 #size-cells = <0>;
402 reg = <0x0 0x2100000 0x0 0x10000>;
403 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
404 clock-names = "dspi";
405 clocks = <&clockgen 4 1>;
406 spi-num-chipselects = <5>;
407 big-endian;
408 status = "disabled";
409 };
411 i2c0: i2c@2180000 {
412 compatible = "fsl,vf610-i2c";
413 #address-cells = <1>;
414 #size-cells = <0>;
415 reg = <0x0 0x2180000 0x0 0x10000>;
416 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&clockgen 4 1>;
418 dmas = <&edma0 1 39>,
419 <&edma0 1 38>;
420 dma-names = "tx", "rx";
421 status = "disabled";
422 };
424 i2c1: i2c@2190000 {
425 compatible = "fsl,vf610-i2c";
426 #address-cells = <1>;
427 #size-cells = <0>;
428 reg = <0x0 0x2190000 0x0 0x10000>;
429 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clockgen 4 1>;
431 status = "disabled";
432 };
434 i2c2: i2c@21a0000 {
435 compatible = "fsl,vf610-i2c";
436 #address-cells = <1>;
437 #size-cells = <0>;
438 reg = <0x0 0x21a0000 0x0 0x10000>;
439 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&clockgen 4 1>;
441 status = "disabled";
442 };
444 i2c3: i2c@21b0000 {
445 compatible = "fsl,vf610-i2c";
446 #address-cells = <1>;
447 #size-cells = <0>;
448 reg = <0x0 0x21b0000 0x0 0x10000>;
449 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clockgen 4 1>;
451 status = "disabled";
452 };
454 duart0: serial@21c0500 {
455 compatible = "fsl,ns16550", "ns16550a";
456 reg = <0x00 0x21c0500 0x0 0x100>;
457 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&clockgen 4 1>;
459 };
461 duart1: serial@21c0600 {
462 compatible = "fsl,ns16550", "ns16550a";
463 reg = <0x00 0x21c0600 0x0 0x100>;
464 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&clockgen 4 1>;
466 };
468 duart2: serial@21d0500 {
469 compatible = "fsl,ns16550", "ns16550a";
470 reg = <0x0 0x21d0500 0x0 0x100>;
471 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&clockgen 4 1>;
473 };
475 duart3: serial@21d0600 {
476 compatible = "fsl,ns16550", "ns16550a";
477 reg = <0x0 0x21d0600 0x0 0x100>;
478 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&clockgen 4 1>;
480 };
482 gpio0: gpio@2300000 {
483 compatible = "fsl,qoriq-gpio";
484 reg = <0x0 0x2300000 0x0 0x10000>;
485 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
486 gpio-controller;
487 #gpio-cells = <2>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
490 };
492 gpio1: gpio@2310000 {
493 compatible = "fsl,qoriq-gpio";
494 reg = <0x0 0x2310000 0x0 0x10000>;
495 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
496 gpio-controller;
497 #gpio-cells = <2>;
498 interrupt-controller;
499 #interrupt-cells = <2>;
500 };
502 gpio2: gpio@2320000 {
503 compatible = "fsl,qoriq-gpio";
504 reg = <0x0 0x2320000 0x0 0x10000>;
505 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
506 gpio-controller;
507 #gpio-cells = <2>;
508 interrupt-controller;
509 #interrupt-cells = <2>;
510 };
512 gpio3: gpio@2330000 {
513 compatible = "fsl,qoriq-gpio";
514 reg = <0x0 0x2330000 0x0 0x10000>;
515 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
516 gpio-controller;
517 #gpio-cells = <2>;
518 interrupt-controller;
519 #interrupt-cells = <2>;
520 };
522 lpuart0: serial@2950000 {
523 compatible = "fsl,ls1021a-lpuart";
524 reg = <0x0 0x2950000 0x0 0x1000>;
525 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&clockgen 4 0>;
527 clock-names = "ipg";
528 status = "disabled";
529 };
531 lpuart1: serial@2960000 {
532 compatible = "fsl,ls1021a-lpuart";
533 reg = <0x0 0x2960000 0x0 0x1000>;
534 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&clockgen 4 1>;
536 clock-names = "ipg";
537 status = "disabled";
538 };
540 lpuart2: serial@2970000 {
541 compatible = "fsl,ls1021a-lpuart";
542 reg = <0x0 0x2970000 0x0 0x1000>;
543 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&clockgen 4 1>;
545 clock-names = "ipg";
546 status = "disabled";
547 };
549 lpuart3: serial@2980000 {
550 compatible = "fsl,ls1021a-lpuart";
551 reg = <0x0 0x2980000 0x0 0x1000>;
552 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&clockgen 4 1>;
554 clock-names = "ipg";
555 status = "disabled";
556 };
558 lpuart4: serial@2990000 {
559 compatible = "fsl,ls1021a-lpuart";
560 reg = <0x0 0x2990000 0x0 0x1000>;
561 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&clockgen 4 1>;
563 clock-names = "ipg";
564 status = "disabled";
565 };
567 lpuart5: serial@29a0000 {
568 compatible = "fsl,ls1021a-lpuart";
569 reg = <0x0 0x29a0000 0x0 0x1000>;
570 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&clockgen 4 1>;
572 clock-names = "ipg";
573 status = "disabled";
574 };
576 wdog0: watchdog@2ad0000 {
577 compatible = "fsl,imx21-wdt";
578 reg = <0x0 0x2ad0000 0x0 0x10000>;
579 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&clockgen 4 1>;
581 big-endian;
582 };
584 edma0: edma@2c00000 {
585 #dma-cells = <2>;
586 compatible = "fsl,vf610-edma";
587 reg = <0x0 0x2c00000 0x0 0x10000>,
588 <0x0 0x2c10000 0x0 0x10000>,
589 <0x0 0x2c20000 0x0 0x10000>;
590 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
592 interrupt-names = "edma-tx", "edma-err";
593 dma-channels = <32>;
594 big-endian;
595 clock-names = "dmamux0", "dmamux1";
596 clocks = <&clockgen 4 1>,
597 <&clockgen 4 1>;
598 };
600 usb0: usb@2f00000 {
601 compatible = "snps,dwc3";
602 reg = <0x0 0x2f00000 0x0 0x10000>;
603 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
604 dr_mode = "host";
605 snps,quirk-frame-length-adjustment = <0x20>;
606 snps,dis_rxdet_inp3_quirk;
607 };
609 usb1: usb@3000000 {
610 compatible = "snps,dwc3";
611 reg = <0x0 0x3000000 0x0 0x10000>;
612 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
613 dr_mode = "host";
614 snps,quirk-frame-length-adjustment = <0x20>;
615 snps,dis_rxdet_inp3_quirk;
616 };
618 usb2: usb@3100000 {
619 compatible = "snps,dwc3";
620 reg = <0x0 0x3100000 0x0 0x10000>;
621 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
622 dr_mode = "host";
623 snps,quirk-frame-length-adjustment = <0x20>;
624 snps,dis_rxdet_inp3_quirk;
625 };
627 sata: sata@3200000 {
628 compatible = "fsl,ls1046a-ahci";
629 reg = <0x0 0x3200000 0x0 0x10000>,
630 <0x0 0x20140520 0x0 0x4>;
631 reg-names = "ahci", "sata-ecc";
632 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&clockgen 4 1>;
634 };
636 msi1: msi-controller@1580000 {
637 compatible = "fsl,ls1046a-msi";
638 msi-controller;
639 reg = <0x0 0x1580000 0x0 0x10000>;
640 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
644 };
646 msi2: msi-controller@1590000 {
647 compatible = "fsl,ls1046a-msi";
648 msi-controller;
649 reg = <0x0 0x1590000 0x0 0x10000>;
650 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
654 };
656 msi3: msi-controller@15a0000 {
657 compatible = "fsl,ls1046a-msi";
658 msi-controller;
659 reg = <0x0 0x15a0000 0x0 0x10000>;
660 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
664 };
666 pcie@3400000 {
667 compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
668 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
669 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
670 reg-names = "regs", "config";
671 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
672 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
673 interrupt-names = "aer", "pme";
674 #address-cells = <3>;
675 #size-cells = <2>;
676 device_type = "pci";
677 dma-coherent;
678 num-lanes = <4>;
679 bus-range = <0x0 0xff>;
680 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
681 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
682 msi-parent = <&msi1>, <&msi2>, <&msi3>;
683 #interrupt-cells = <1>;
684 interrupt-map-mask = <0 0 0 7>;
685 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
686 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
687 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
688 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
689 };
691 pcie@3500000 {
692 compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
693 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
694 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
695 reg-names = "regs", "config";
696 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
697 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
698 interrupt-names = "aer", "pme";
699 #address-cells = <3>;
700 #size-cells = <2>;
701 device_type = "pci";
702 dma-coherent;
703 num-lanes = <2>;
704 bus-range = <0x0 0xff>;
705 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
706 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
707 msi-parent = <&msi2>, <&msi3>, <&msi1>;
708 #interrupt-cells = <1>;
709 interrupt-map-mask = <0 0 0 7>;
710 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
711 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
712 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
713 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
714 };
716 pcie@3600000 {
717 compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
718 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
719 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
720 reg-names = "regs", "config";
721 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
722 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
723 interrupt-names = "aer", "pme";
724 #address-cells = <3>;
725 #size-cells = <2>;
726 device_type = "pci";
727 dma-coherent;
728 num-lanes = <2>;
729 bus-range = <0x0 0xff>;
730 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
731 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
732 msi-parent = <&msi3>, <&msi1>, <&msi2>;
733 #interrupt-cells = <1>;
734 interrupt-map-mask = <0 0 0 7>;
735 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
736 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
737 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
738 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
739 };
741 };
743 reserved-memory {
744 #address-cells = <2>;
745 #size-cells = <2>;
746 ranges;
748 bman_fbpr: bman-fbpr {
749 compatible = "shared-dma-pool";
750 size = <0 0x1000000>;
751 alignment = <0 0x1000000>;
752 no-map;
753 };
755 qman_fqd: qman-fqd {
756 compatible = "shared-dma-pool";
757 size = <0 0x800000>;
758 alignment = <0 0x800000>;
759 no-map;
760 };
762 qman_pfdr: qman-pfdr {
763 compatible = "shared-dma-pool";
764 size = <0 0x2000000>;
765 alignment = <0 0x2000000>;
766 no-map;
767 };
768 };
770 firmware {
771 optee {
772 compatible = "linaro,optee-tz";
773 method = "smc";
774 };
775 };
776 };
778 #include "qoriq-qman-portals.dtsi"
779 #include "qoriq-bman-portals.dtsi"