sound/soc/codecs/tlv320aic31xx.h

   1 /*
   2  * ALSA SoC TLV320AIC31XX codec driver
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This package is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  11  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  12  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  13  *
  14  */
  15 #ifndef _TLV320AIC31XX_H
  16 #define _TLV320AIC31XX_H
  17
  18 #define AIC31XX_RATES   SNDRV_PCM_RATE_8000_192000
  19
  20 #define AIC31XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
  21                          | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \
  22                          | SNDRV_PCM_FMTBIT_S32_LE)
  23
  24
  25 #define AIC31XX_STEREO_CLASS_D_BIT      0x1
  26 #define AIC31XX_MINIDSP_BIT             0x2
  27 #define DAC31XX_BIT                     0x4
  28
  29 enum aic31xx_type {
  30         AIC3100 = 0,
  31         AIC3110 = AIC31XX_STEREO_CLASS_D_BIT,
  32         AIC3120 = AIC31XX_MINIDSP_BIT,
  33         AIC3111 = (AIC31XX_STEREO_CLASS_D_BIT | AIC31XX_MINIDSP_BIT),
  34         DAC3100 = DAC31XX_BIT,
  35         DAC3101 = DAC31XX_BIT | AIC31XX_STEREO_CLASS_D_BIT,
  36 };
  37
  38 struct aic31xx_pdata {
  39         enum aic31xx_type codec_type;
  40         unsigned int gpio_reset;
  41         int micbias_vg;
  42 };
  43
  44 #define AIC31XX_REG(page, reg)  ((page * 128) + reg)
  45
  46 /* Page Control Register */
  47 #define AIC31XX_PAGECTL         AIC31XX_REG(0, 0)
  48
  49 /* Page 0 Registers */
  50 /* Software reset register */
  51 #define AIC31XX_RESET           AIC31XX_REG(0, 1)
  52 /* OT FLAG register */
  53 #define AIC31XX_OT_FLAG         AIC31XX_REG(0, 3)
  54 /* Clock clock Gen muxing, Multiplexers*/
  55 #define AIC31XX_CLKMUX          AIC31XX_REG(0, 4)
  56 /* PLL P and R-VAL register */
  57 #define AIC31XX_PLLPR           AIC31XX_REG(0, 5)
  58 /* PLL J-VAL register */
  59 #define AIC31XX_PLLJ            AIC31XX_REG(0, 6)
  60 /* PLL D-VAL MSB register */
  61 #define AIC31XX_PLLDMSB         AIC31XX_REG(0, 7)
  62 /* PLL D-VAL LSB register */
  63 #define AIC31XX_PLLDLSB         AIC31XX_REG(0, 8)
  64 /* DAC NDAC_VAL register*/
  65 #define AIC31XX_NDAC            AIC31XX_REG(0, 11)
  66 /* DAC MDAC_VAL register */
  67 #define AIC31XX_MDAC            AIC31XX_REG(0, 12)
  68 /* DAC OSR setting register 1, MSB value */
  69 #define AIC31XX_DOSRMSB         AIC31XX_REG(0, 13)
  70 /* DAC OSR setting register 2, LSB value */
  71 #define AIC31XX_DOSRLSB         AIC31XX_REG(0, 14)
  72 #define AIC31XX_MINI_DSP_INPOL  AIC31XX_REG(0, 16)
  73 /* Clock setting register 8, PLL */
  74 #define AIC31XX_NADC            AIC31XX_REG(0, 18)
  75 /* Clock setting register 9, PLL */
  76 #define AIC31XX_MADC            AIC31XX_REG(0, 19)
  77 /* ADC Oversampling (AOSR) Register */
  78 #define AIC31XX_AOSR            AIC31XX_REG(0, 20)
  79 /* Clock setting register 9, Multiplexers */
  80 #define AIC31XX_CLKOUTMUX       AIC31XX_REG(0, 25)
  81 /* Clock setting register 10, CLOCKOUT M divider value */
  82 #define AIC31XX_CLKOUTMVAL      AIC31XX_REG(0, 26)
  83 /* Audio Interface Setting Register 1 */
  84 #define AIC31XX_IFACE1          AIC31XX_REG(0, 27)
  85 /* Audio Data Slot Offset Programming */
  86 #define AIC31XX_DATA_OFFSET     AIC31XX_REG(0, 28)
  87 /* Audio Interface Setting Register 2 */
  88 #define AIC31XX_IFACE2          AIC31XX_REG(0, 29)
  89 /* Clock setting register 11, BCLK N Divider */
  90 #define AIC31XX_BCLKN           AIC31XX_REG(0, 30)
  91 /* Audio Interface Setting Register 3, Secondary Audio Interface */
  92 #define AIC31XX_IFACESEC1       AIC31XX_REG(0, 31)
  93 /* Audio Interface Setting Register 4 */
  94 #define AIC31XX_IFACESEC2       AIC31XX_REG(0, 32)
  95 /* Audio Interface Setting Register 5 */
  96 #define AIC31XX_IFACESEC3       AIC31XX_REG(0, 33)
  97 /* I2C Bus Condition */
  98 #define AIC31XX_I2C             AIC31XX_REG(0, 34)
  99 /* ADC FLAG */
 100 #define AIC31XX_ADCFLAG         AIC31XX_REG(0, 36)
 101 /* DAC Flag Registers */
 102 #define AIC31XX_DACFLAG1        AIC31XX_REG(0, 37)
 103 #define AIC31XX_DACFLAG2        AIC31XX_REG(0, 38)
 104 /* Sticky Interrupt flag (overflow) */
 105 #define AIC31XX_OFFLAG          AIC31XX_REG(0, 39)
 106 /* Sticy DAC Interrupt flags */
 107 #define AIC31XX_INTRDACFLAG     AIC31XX_REG(0, 44)
 108 /* Sticy ADC Interrupt flags */
 109 #define AIC31XX_INTRADCFLAG     AIC31XX_REG(0, 45)
 110 /* DAC Interrupt flags 2 */
 111 #define AIC31XX_INTRDACFLAG2    AIC31XX_REG(0, 46)
 112 /* ADC Interrupt flags 2 */
 113 #define AIC31XX_INTRADCFLAG2    AIC31XX_REG(0, 47)
 114 /* INT1 interrupt control */
 115 #define AIC31XX_INT1CTRL        AIC31XX_REG(0, 48)
 116 /* INT2 interrupt control */
 117 #define AIC31XX_INT2CTRL        AIC31XX_REG(0, 49)
 118 /* GPIO1 control */
 119 #define AIC31XX_GPIO1           AIC31XX_REG(0, 51)
 120
 121 #define AIC31XX_DACPRB          AIC31XX_REG(0, 60)
 122 /* ADC Instruction Set Register */
 123 #define AIC31XX_ADCPRB          AIC31XX_REG(0, 61)
 124 /* DAC channel setup register */
 125 #define AIC31XX_DACSETUP        AIC31XX_REG(0, 63)
 126 /* DAC Mute and volume control register */
 127 #define AIC31XX_DACMUTE         AIC31XX_REG(0, 64)
 128 /* Left DAC channel digital volume control */
 129 #define AIC31XX_LDACVOL         AIC31XX_REG(0, 65)
 130 /* Right DAC channel digital volume control */
 131 #define AIC31XX_RDACVOL         AIC31XX_REG(0, 66)
 132 /* Headset detection */
 133 #define AIC31XX_HSDETECT        AIC31XX_REG(0, 67)
 134 /* ADC Digital Mic */
 135 #define AIC31XX_ADCSETUP        AIC31XX_REG(0, 81)
 136 /* ADC Digital Volume Control Fine Adjust */
 137 #define AIC31XX_ADCFGA          AIC31XX_REG(0, 82)
 138 /* ADC Digital Volume Control Coarse Adjust */
 139 #define AIC31XX_ADCVOL          AIC31XX_REG(0, 83)
 140
 141
 142 /* Page 1 Registers */
 143 /* Headphone drivers */
 144 #define AIC31XX_HPDRIVER        AIC31XX_REG(1, 31)
 145 /* Class-D Speakear Amplifier */
 146 #define AIC31XX_SPKAMP          AIC31XX_REG(1, 32)
 147 /* HP Output Drivers POP Removal Settings */
 148 #define AIC31XX_HPPOP           AIC31XX_REG(1, 33)
 149 /* Output Driver PGA Ramp-Down Period Control */
 150 #define AIC31XX_SPPGARAMP       AIC31XX_REG(1, 34)
 151 /* DAC_L and DAC_R Output Mixer Routing */
 152 #define AIC31XX_DACMIXERROUTE   AIC31XX_REG(1, 35)
 153 /* Left Analog Vol to HPL */
 154 #define AIC31XX_LANALOGHPL      AIC31XX_REG(1, 36)
 155 /* Right Analog Vol to HPR */
 156 #define AIC31XX_RANALOGHPR      AIC31XX_REG(1, 37)
 157 /* Left Analog Vol to SPL */
 158 #define AIC31XX_LANALOGSPL      AIC31XX_REG(1, 38)
 159 /* Right Analog Vol to SPR */
 160 #define AIC31XX_RANALOGSPR      AIC31XX_REG(1, 39)
 161 /* HPL Driver */
 162 #define AIC31XX_HPLGAIN         AIC31XX_REG(1, 40)
 163 /* HPR Driver */
 164 #define AIC31XX_HPRGAIN         AIC31XX_REG(1, 41)
 165 /* SPL Driver */
 166 #define AIC31XX_SPLGAIN         AIC31XX_REG(1, 42)
 167 /* SPR Driver */
 168 #define AIC31XX_SPRGAIN         AIC31XX_REG(1, 43)
 169 /* HP Driver Control */
 170 #define AIC31XX_HPCONTROL       AIC31XX_REG(1, 44)
 171 /* MIC Bias Control */
 172 #define AIC31XX_MICBIAS         AIC31XX_REG(1, 46)
 173 /* MIC PGA*/
 174 #define AIC31XX_MICPGA          AIC31XX_REG(1, 47)
 175 /* Delta-Sigma Mono ADC Channel Fine-Gain Input Selection for P-Terminal */
 176 #define AIC31XX_MICPGAPI        AIC31XX_REG(1, 48)
 177 /* ADC Input Selection for M-Terminal */
 178 #define AIC31XX_MICPGAMI        AIC31XX_REG(1, 49)
 179 /* Input CM Settings */
 180 #define AIC31XX_MICPGACM        AIC31XX_REG(1, 50)
 181
 182 /* Bits, masks and shifts */
 183
 184 /* AIC31XX_CLKMUX */
 185 #define AIC31XX_PLL_CLKIN_MASK                  0x0c
 186 #define AIC31XX_PLL_CLKIN_SHIFT                 2
 187 #define AIC31XX_PLL_CLKIN_MCLK                  0
 188 #define AIC31XX_CODEC_CLKIN_MASK                0x03
 189 #define AIC31XX_CODEC_CLKIN_SHIFT               0
 190 #define AIC31XX_CODEC_CLKIN_PLL                 3
 191 #define AIC31XX_CODEC_CLKIN_BCLK                1
 192
 193 /* AIC31XX_PLLPR, AIC31XX_NDAC, AIC31XX_MDAC, AIC31XX_NADC, AIC31XX_MADC,
 194    AIC31XX_BCLKN */
 195 #define AIC31XX_PLL_MASK                0x7f
 196 #define AIC31XX_PM_MASK                 0x80
 197
 198 /* AIC31XX_IFACE1 */
 199 #define AIC31XX_WORD_LEN_16BITS         0x00
 200 #define AIC31XX_WORD_LEN_20BITS         0x01
 201 #define AIC31XX_WORD_LEN_24BITS         0x02
 202 #define AIC31XX_WORD_LEN_32BITS         0x03
 203 #define AIC31XX_IFACE1_DATALEN_MASK     0x30
 204 #define AIC31XX_IFACE1_DATALEN_SHIFT    (4)
 205 #define AIC31XX_IFACE1_DATATYPE_MASK    0xC0
 206 #define AIC31XX_IFACE1_DATATYPE_SHIFT   (6)
 207 #define AIC31XX_I2S_MODE                0x00
 208 #define AIC31XX_DSP_MODE                0x01
 209 #define AIC31XX_RIGHT_JUSTIFIED_MODE    0x02
 210 #define AIC31XX_LEFT_JUSTIFIED_MODE     0x03
 211 #define AIC31XX_IFACE1_MASTER_MASK      0x0C
 212 #define AIC31XX_BCLK_MASTER             0x08
 213 #define AIC31XX_WCLK_MASTER             0x04
 214
 215 /* AIC31XX_DATA_OFFSET */
 216 #define AIC31XX_DATA_OFFSET_MASK        0xFF
 217
 218 /* AIC31XX_IFACE2 */
 219 #define AIC31XX_BCLKINV_MASK            0x08
 220 #define AIC31XX_BDIVCLK_MASK            0x03
 221 #define AIC31XX_DAC2BCLK                0x00
 222 #define AIC31XX_DACMOD2BCLK             0x01
 223 #define AIC31XX_ADC2BCLK                0x02
 224 #define AIC31XX_ADCMOD2BCLK             0x03
 225
 226 /* AIC31XX_ADCFLAG */
 227 #define AIC31XX_ADCPWRSTATUS_MASK               0x40
 228
 229 /* AIC31XX_DACFLAG1 */
 230 #define AIC31XX_LDACPWRSTATUS_MASK              0x80
 231 #define AIC31XX_RDACPWRSTATUS_MASK              0x08
 232 #define AIC31XX_HPLDRVPWRSTATUS_MASK            0x20
 233 #define AIC31XX_HPRDRVPWRSTATUS_MASK            0x02
 234 #define AIC31XX_SPLDRVPWRSTATUS_MASK            0x10
 235 #define AIC31XX_SPRDRVPWRSTATUS_MASK            0x01
 236
 237 /* AIC31XX_INTRDACFLAG */
 238 #define AIC31XX_HPSCDETECT_MASK                 0x80
 239 #define AIC31XX_BUTTONPRESS_MASK                0x20
 240 #define AIC31XX_HSPLUG_MASK                     0x10
 241 #define AIC31XX_LDRCTHRES_MASK                  0x08
 242 #define AIC31XX_RDRCTHRES_MASK                  0x04
 243 #define AIC31XX_DACSINT_MASK                    0x02
 244 #define AIC31XX_DACAINT_MASK                    0x01
 245
 246 /* AIC31XX_INT1CTRL */
 247 #define AIC31XX_HSPLUGDET_MASK                  0x80
 248 #define AIC31XX_BUTTONPRESSDET_MASK             0x40
 249 #define AIC31XX_DRCTHRES_MASK                   0x20
 250 #define AIC31XX_AGCNOISE_MASK                   0x10
 251 #define AIC31XX_OC_MASK                         0x08
 252 #define AIC31XX_ENGINE_MASK                     0x04
 253
 254 /* AIC31XX_DACSETUP */
 255 #define AIC31XX_SOFTSTEP_MASK                   0x03
 256
 257 /* AIC31XX_DACMUTE */
 258 #define AIC31XX_DACMUTE_MASK                    0x0C
 259
 260 /* AIC31XX_MICBIAS */
 261 #define AIC31XX_MICBIAS_MASK                    0x03
 262 #define AIC31XX_MICBIAS_SHIFT                   0
 263
 264 #endif  /* _TLV320AIC31XX_H */