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btrfs: add missing initialization in btrfs_check_shared
[linux/fpc-iii.git] / sound / soc / codecs / wm8580.c
blob910801dddd64d00e299533ff8ae2886a81de1410
1 /*
2 * wm8580.c -- WM8580 and WM8581 ALSA Soc Audio driver
3 *
4 * Copyright 2008-12 Wolfson Microelectronics PLC.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Notes:
12 * The WM8580 is a multichannel codec with S/PDIF support, featuring six
13 * DAC channels and two ADC channels.
14 *
15 * The WM8581 is a multichannel codec with S/PDIF support, featuring eight
16 * DAC channels and two ADC channels.
17 *
18 * Currently only the primary audio interface is supported - S/PDIF and
19 * the secondary audio interfaces are not.
20 */
21
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/pm.h>
28 #include <linux/i2c.h>
29 #include <linux/regmap.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/slab.h>
32 #include <linux/of_device.h>
33
34 #include <sound/core.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/soc.h>
38 #include <sound/tlv.h>
39 #include <sound/initval.h>
40 #include <asm/div64.h>
41
42 #include "wm8580.h"
43
44 /* WM8580 register space */
45 #define WM8580_PLLA1 0x00
46 #define WM8580_PLLA2 0x01
47 #define WM8580_PLLA3 0x02
48 #define WM8580_PLLA4 0x03
49 #define WM8580_PLLB1 0x04
50 #define WM8580_PLLB2 0x05
51 #define WM8580_PLLB3 0x06
52 #define WM8580_PLLB4 0x07
53 #define WM8580_CLKSEL 0x08
54 #define WM8580_PAIF1 0x09
55 #define WM8580_PAIF2 0x0A
56 #define WM8580_SAIF1 0x0B
57 #define WM8580_PAIF3 0x0C
58 #define WM8580_PAIF4 0x0D
59 #define WM8580_SAIF2 0x0E
60 #define WM8580_DAC_CONTROL1 0x0F
61 #define WM8580_DAC_CONTROL2 0x10
62 #define WM8580_DAC_CONTROL3 0x11
63 #define WM8580_DAC_CONTROL4 0x12
64 #define WM8580_DAC_CONTROL5 0x13
65 #define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
66 #define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
67 #define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
68 #define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
69 #define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
70 #define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
71 #define WM8581_DIGITAL_ATTENUATION_DACL4 0x1A
72 #define WM8581_DIGITAL_ATTENUATION_DACR4 0x1B
73 #define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
74 #define WM8580_ADC_CONTROL1 0x1D
75 #define WM8580_SPDTXCHAN0 0x1E
76 #define WM8580_SPDTXCHAN1 0x1F
77 #define WM8580_SPDTXCHAN2 0x20
78 #define WM8580_SPDTXCHAN3 0x21
79 #define WM8580_SPDTXCHAN4 0x22
80 #define WM8580_SPDTXCHAN5 0x23
81 #define WM8580_SPDMODE 0x24
82 #define WM8580_INTMASK 0x25
83 #define WM8580_GPO1 0x26
84 #define WM8580_GPO2 0x27
85 #define WM8580_GPO3 0x28
86 #define WM8580_GPO4 0x29
87 #define WM8580_GPO5 0x2A
88 #define WM8580_INTSTAT 0x2B
89 #define WM8580_SPDRXCHAN1 0x2C
90 #define WM8580_SPDRXCHAN2 0x2D
91 #define WM8580_SPDRXCHAN3 0x2E
92 #define WM8580_SPDRXCHAN4 0x2F
93 #define WM8580_SPDRXCHAN5 0x30
94 #define WM8580_SPDSTAT 0x31
95 #define WM8580_PWRDN1 0x32
96 #define WM8580_PWRDN2 0x33
97 #define WM8580_READBACK 0x34
98 #define WM8580_RESET 0x35
99
100 #define WM8580_MAX_REGISTER 0x35
101
102 #define WM8580_DACOSR 0x40
103
104 /* PLLB4 (register 7h) */
105 #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
106 #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
107 #define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
108 #define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
109
110 #define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
111 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
112 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
113 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
114
115 /* CLKSEL (register 8h) */
116 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
117 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
118 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
119
120 /* AIF control 1 (registers 9h-bh) */
121 #define WM8580_AIF_RATE_MASK 0x7
122 #define WM8580_AIF_BCLKSEL_MASK 0x18
123
124 #define WM8580_AIF_MS 0x20
125
126 #define WM8580_AIF_CLKSRC_MASK 0xc0
127 #define WM8580_AIF_CLKSRC_PLLA 0x40
128 #define WM8580_AIF_CLKSRC_PLLB 0x40
129 #define WM8580_AIF_CLKSRC_MCLK 0xc0
130
131 /* AIF control 2 (registers ch-eh) */
132 #define WM8580_AIF_FMT_MASK 0x03
133 #define WM8580_AIF_FMT_RIGHTJ 0x00
134 #define WM8580_AIF_FMT_LEFTJ 0x01
135 #define WM8580_AIF_FMT_I2S 0x02
136 #define WM8580_AIF_FMT_DSP 0x03
137
138 #define WM8580_AIF_LENGTH_MASK 0x0c
139 #define WM8580_AIF_LENGTH_16 0x00
140 #define WM8580_AIF_LENGTH_20 0x04
141 #define WM8580_AIF_LENGTH_24 0x08
142 #define WM8580_AIF_LENGTH_32 0x0c
143
144 #define WM8580_AIF_LRP 0x10
145 #define WM8580_AIF_BCP 0x20
146
147 /* Powerdown Register 1 (register 32h) */
148 #define WM8580_PWRDN1_PWDN 0x001
149 #define WM8580_PWRDN1_ALLDACPD 0x040
150
151 /* Powerdown Register 2 (register 33h) */
152 #define WM8580_PWRDN2_OSSCPD 0x001
153 #define WM8580_PWRDN2_PLLAPD 0x002
154 #define WM8580_PWRDN2_PLLBPD 0x004
155 #define WM8580_PWRDN2_SPDIFPD 0x008
156 #define WM8580_PWRDN2_SPDIFTXD 0x010
157 #define WM8580_PWRDN2_SPDIFRXD 0x020
158
159 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
160
161 /*
162 * wm8580 register cache
163 * We can't read the WM8580 register space when we
164 * are using 2 wire for device control, so we cache them instead.
165 */
166 static const struct reg_default wm8580_reg_defaults[] = {
167 { 0, 0x0121 },
168 { 1, 0x017e },
169 { 2, 0x007d },
170 { 3, 0x0014 },
171 { 4, 0x0121 },
172 { 5, 0x017e },
173 { 6, 0x007d },
174 { 7, 0x0194 },
175 { 8, 0x0010 },
176 { 9, 0x0002 },
177 { 10, 0x0002 },
178 { 11, 0x00c2 },
179 { 12, 0x0182 },
180 { 13, 0x0082 },
181 { 14, 0x000a },
182 { 15, 0x0024 },
183 { 16, 0x0009 },
184 { 17, 0x0000 },
185 { 18, 0x00ff },
186 { 19, 0x0000 },
187 { 20, 0x00ff },
188 { 21, 0x00ff },
189 { 22, 0x00ff },
190 { 23, 0x00ff },
191 { 24, 0x00ff },
192 { 25, 0x00ff },
193 { 26, 0x00ff },
194 { 27, 0x00ff },
195 { 28, 0x01f0 },
196 { 29, 0x0040 },
197 { 30, 0x0000 },
198 { 31, 0x0000 },
199 { 32, 0x0000 },
200 { 33, 0x0000 },
201 { 34, 0x0031 },
202 { 35, 0x000b },
203 { 36, 0x0039 },
204 { 37, 0x0000 },
205 { 38, 0x0010 },
206 { 39, 0x0032 },
207 { 40, 0x0054 },
208 { 41, 0x0076 },
209 { 42, 0x0098 },
210 { 43, 0x0000 },
211 { 44, 0x0000 },
212 { 45, 0x0000 },
213 { 46, 0x0000 },
214 { 47, 0x0000 },
215 { 48, 0x0000 },
216 { 49, 0x0000 },
217 { 50, 0x005e },
218 { 51, 0x003e },
219 { 52, 0x0000 },
220 };
221
222 static bool wm8580_volatile(struct device *dev, unsigned int reg)
223 {
224 switch (reg) {
225 case WM8580_RESET:
226 return true;
227 default:
228 return false;
229 }
230 }
231
232 struct pll_state {
233 unsigned int in;
234 unsigned int out;
235 };
236
237 #define WM8580_NUM_SUPPLIES 3
238 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
239 "AVDD",
240 "DVDD",
241 "PVDD",
242 };
243
244 struct wm8580_driver_data {
245 int num_dacs;
246 };
247
248 /* codec private data */
249 struct wm8580_priv {
250 struct regmap *regmap;
251 struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
252 struct pll_state a;
253 struct pll_state b;
254 const struct wm8580_driver_data *drvdata;
255 int sysclk[2];
256 };
257
258 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
259
260 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
261 struct snd_ctl_elem_value *ucontrol)
262 {
263 struct soc_mixer_control *mc =
264 (struct soc_mixer_control *)kcontrol->private_value;
265 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
266 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
267 unsigned int reg = mc->reg;
268 unsigned int reg2 = mc->rreg;
269 int ret;
270
271 /* Clear the register cache VU so we write without VU set */
272 regcache_cache_only(wm8580->regmap, true);
273 regmap_update_bits(wm8580->regmap, reg, 0x100, 0x000);
274 regmap_update_bits(wm8580->regmap, reg2, 0x100, 0x000);
275 regcache_cache_only(wm8580->regmap, false);
276
277 ret = snd_soc_put_volsw(kcontrol, ucontrol);
278 if (ret < 0)
279 return ret;
280
281 /* Now write again with the volume update bit set */
282 snd_soc_update_bits(codec, reg, 0x100, 0x100);
283 snd_soc_update_bits(codec, reg2, 0x100, 0x100);
284
285 return 0;
286 }
287
288 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
289 SOC_DOUBLE_R_EXT_TLV("DAC1 Playback Volume",
290 WM8580_DIGITAL_ATTENUATION_DACL1,
291 WM8580_DIGITAL_ATTENUATION_DACR1,
292 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
293 SOC_DOUBLE_R_EXT_TLV("DAC2 Playback Volume",
294 WM8580_DIGITAL_ATTENUATION_DACL2,
295 WM8580_DIGITAL_ATTENUATION_DACR2,
296 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
297 SOC_DOUBLE_R_EXT_TLV("DAC3 Playback Volume",
298 WM8580_DIGITAL_ATTENUATION_DACL3,
299 WM8580_DIGITAL_ATTENUATION_DACR3,
300 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
301
302 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
303 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
304 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
305
306 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0),
307 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0),
308 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0),
309
310 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
311 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1),
312 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1),
313 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1),
314
315 SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
316 SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
317 };
318
319 static const struct snd_kcontrol_new wm8581_snd_controls[] = {
320 SOC_DOUBLE_R_EXT_TLV("DAC4 Playback Volume",
321 WM8581_DIGITAL_ATTENUATION_DACL4,
322 WM8581_DIGITAL_ATTENUATION_DACR4,
323 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
324
325 SOC_SINGLE("DAC4 Deemphasis Switch", WM8580_DAC_CONTROL3, 3, 1, 0),
326
327 SOC_DOUBLE("DAC4 Invert Switch", WM8580_DAC_CONTROL4, 8, 7, 1, 0),
328
329 SOC_SINGLE("DAC4 Switch", WM8580_DAC_CONTROL5, 3, 1, 1),
330 };
331
332 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
333 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
334 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
335 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
336
337 SND_SOC_DAPM_OUTPUT("VOUT1L"),
338 SND_SOC_DAPM_OUTPUT("VOUT1R"),
339 SND_SOC_DAPM_OUTPUT("VOUT2L"),
340 SND_SOC_DAPM_OUTPUT("VOUT2R"),
341 SND_SOC_DAPM_OUTPUT("VOUT3L"),
342 SND_SOC_DAPM_OUTPUT("VOUT3R"),
343
344 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
345
346 SND_SOC_DAPM_INPUT("AINL"),
347 SND_SOC_DAPM_INPUT("AINR"),
348 };
349
350 static const struct snd_soc_dapm_widget wm8581_dapm_widgets[] = {
351 SND_SOC_DAPM_DAC("DAC4", "Playback", WM8580_PWRDN1, 5, 1),
352
353 SND_SOC_DAPM_OUTPUT("VOUT4L"),
354 SND_SOC_DAPM_OUTPUT("VOUT4R"),
355 };
356
357 static const struct snd_soc_dapm_route wm8580_dapm_routes[] = {
358 { "VOUT1L", NULL, "DAC1" },
359 { "VOUT1R", NULL, "DAC1" },
360
361 { "VOUT2L", NULL, "DAC2" },
362 { "VOUT2R", NULL, "DAC2" },
363
364 { "VOUT3L", NULL, "DAC3" },
365 { "VOUT3R", NULL, "DAC3" },
366
367 { "ADC", NULL, "AINL" },
368 { "ADC", NULL, "AINR" },
369 };
370
371 static const struct snd_soc_dapm_route wm8581_dapm_routes[] = {
372 { "VOUT4L", NULL, "DAC4" },
373 { "VOUT4R", NULL, "DAC4" },
374 };
375
376 /* PLL divisors */
377 struct _pll_div {
378 u32 prescale:1;
379 u32 postscale:1;
380 u32 freqmode:2;
381 u32 n:4;
382 u32 k:24;
383 };
384
385 /* The size in bits of the pll divide */
386 #define FIXED_PLL_SIZE (1 << 22)
387
388 /* PLL rate to output rate divisions */
389 static struct {
390 unsigned int div;
391 unsigned int freqmode;
392 unsigned int postscale;
393 } post_table[] = {
394 { 2, 0, 0 },
395 { 4, 0, 1 },
396 { 4, 1, 0 },
397 { 8, 1, 1 },
398 { 8, 2, 0 },
399 { 16, 2, 1 },
400 { 12, 3, 0 },
401 { 24, 3, 1 }
402 };
403
404 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
405 unsigned int source)
406 {
407 u64 Kpart;
408 unsigned int K, Ndiv, Nmod;
409 int i;
410
411 pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
412
413 /* Scale the output frequency up; the PLL should run in the
414 * region of 90-100MHz.
415 */
416 for (i = 0; i < ARRAY_SIZE(post_table); i++) {
417 if (target * post_table[i].div >= 90000000 &&
418 target * post_table[i].div <= 100000000) {
419 pll_div->freqmode = post_table[i].freqmode;
420 pll_div->postscale = post_table[i].postscale;
421 target *= post_table[i].div;
422 break;
423 }
424 }
425
426 if (i == ARRAY_SIZE(post_table)) {
427 printk(KERN_ERR "wm8580: Unable to scale output frequency "
428 "%u\n", target);
429 return -EINVAL;
430 }
431
432 Ndiv = target / source;
433
434 if (Ndiv < 5) {
435 source /= 2;
436 pll_div->prescale = 1;
437 Ndiv = target / source;
438 } else
439 pll_div->prescale = 0;
440
441 if ((Ndiv < 5) || (Ndiv > 13)) {
442 printk(KERN_ERR
443 "WM8580 N=%u outside supported range\n", Ndiv);
444 return -EINVAL;
445 }
446
447 pll_div->n = Ndiv;
448 Nmod = target % source;
449 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
450
451 do_div(Kpart, source);
452
453 K = Kpart & 0xFFFFFFFF;
454
455 pll_div->k = K;
456
457 pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
458 pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
459 pll_div->postscale);
460
461 return 0;
462 }
463
464 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
465 int source, unsigned int freq_in, unsigned int freq_out)
466 {
467 int offset;
468 struct snd_soc_codec *codec = codec_dai->codec;
469 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
470 struct pll_state *state;
471 struct _pll_div pll_div;
472 unsigned int reg;
473 unsigned int pwr_mask;
474 int ret;
475
476 /* GCC isn't able to work out the ifs below for initialising/using
477 * pll_div so suppress warnings.
478 */
479 memset(&pll_div, 0, sizeof(pll_div));
480
481 switch (pll_id) {
482 case WM8580_PLLA:
483 state = &wm8580->a;
484 offset = 0;
485 pwr_mask = WM8580_PWRDN2_PLLAPD;
486 break;
487 case WM8580_PLLB:
488 state = &wm8580->b;
489 offset = 4;
490 pwr_mask = WM8580_PWRDN2_PLLBPD;
491 break;
492 default:
493 return -ENODEV;
494 }
495
496 if (freq_in && freq_out) {
497 ret = pll_factors(&pll_div, freq_out, freq_in);
498 if (ret != 0)
499 return ret;
500 }
501
502 state->in = freq_in;
503 state->out = freq_out;
504
505 /* Always disable the PLL - it is not safe to leave it running
506 * while reprogramming it.
507 */
508 snd_soc_update_bits(codec, WM8580_PWRDN2, pwr_mask, pwr_mask);
509
510 if (!freq_in || !freq_out)
511 return 0;
512
513 snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
514 snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
515 snd_soc_write(codec, WM8580_PLLA3 + offset,
516 (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
517
518 reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
519 reg &= ~0x1b;
520 reg |= pll_div.prescale | pll_div.postscale << 1 |
521 pll_div.freqmode << 3;
522
523 snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
524
525 /* All done, turn it on */
526 snd_soc_update_bits(codec, WM8580_PWRDN2, pwr_mask, 0);
527
528 return 0;
529 }
530
531 static const int wm8580_sysclk_ratios[] = {
532 128, 192, 256, 384, 512, 768, 1152,
533 };
534
535 /*
536 * Set PCM DAI bit size and sample rate.
537 */
538 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
539 struct snd_pcm_hw_params *params,
540 struct snd_soc_dai *dai)
541 {
542 struct snd_soc_codec *codec = dai->codec;
543 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
544 u16 paifa = 0;
545 u16 paifb = 0;
546 int i, ratio, osr;
547
548 /* bit size */
549 switch (params_width(params)) {
550 case 16:
551 paifa |= 0x8;
552 break;
553 case 20:
554 paifa |= 0x0;
555 paifb |= WM8580_AIF_LENGTH_20;
556 break;
557 case 24:
558 paifa |= 0x0;
559 paifb |= WM8580_AIF_LENGTH_24;
560 break;
561 case 32:
562 paifa |= 0x0;
563 paifb |= WM8580_AIF_LENGTH_32;
564 break;
565 default:
566 return -EINVAL;
567 }
568
569 /* Look up the SYSCLK ratio; accept only exact matches */
570 ratio = wm8580->sysclk[dai->driver->id] / params_rate(params);
571 for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
572 if (ratio == wm8580_sysclk_ratios[i])
573 break;
574 if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
575 dev_err(codec->dev, "Invalid clock ratio %d/%d\n",
576 wm8580->sysclk[dai->driver->id], params_rate(params));
577 return -EINVAL;
578 }
579 paifa |= i;
580 dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n",
581 wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
582
583 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
584 switch (ratio) {
585 case 128:
586 case 192:
587 osr = WM8580_DACOSR;
588 dev_dbg(codec->dev, "Selecting 64x OSR\n");
589 break;
590 default:
591 osr = 0;
592 dev_dbg(codec->dev, "Selecting 128x OSR\n");
593 break;
594 }
595
596 snd_soc_update_bits(codec, WM8580_PAIF3, WM8580_DACOSR, osr);
597 }
598
599 snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id,
600 WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
601 paifa);
602 snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id,
603 WM8580_AIF_LENGTH_MASK, paifb);
604 return 0;
605 }
606
607 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
608 unsigned int fmt)
609 {
610 struct snd_soc_codec *codec = codec_dai->codec;
611 unsigned int aifa;
612 unsigned int aifb;
613 int can_invert_lrclk;
614
615 aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id);
616 aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id);
617
618 aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
619
620 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
621 case SND_SOC_DAIFMT_CBS_CFS:
622 aifa &= ~WM8580_AIF_MS;
623 break;
624 case SND_SOC_DAIFMT_CBM_CFM:
625 aifa |= WM8580_AIF_MS;
626 break;
627 default:
628 return -EINVAL;
629 }
630
631 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
632 case SND_SOC_DAIFMT_I2S:
633 can_invert_lrclk = 1;
634 aifb |= WM8580_AIF_FMT_I2S;
635 break;
636 case SND_SOC_DAIFMT_RIGHT_J:
637 can_invert_lrclk = 1;
638 aifb |= WM8580_AIF_FMT_RIGHTJ;
639 break;
640 case SND_SOC_DAIFMT_LEFT_J:
641 can_invert_lrclk = 1;
642 aifb |= WM8580_AIF_FMT_LEFTJ;
643 break;
644 case SND_SOC_DAIFMT_DSP_A:
645 can_invert_lrclk = 0;
646 aifb |= WM8580_AIF_FMT_DSP;
647 break;
648 case SND_SOC_DAIFMT_DSP_B:
649 can_invert_lrclk = 0;
650 aifb |= WM8580_AIF_FMT_DSP;
651 aifb |= WM8580_AIF_LRP;
652 break;
653 default:
654 return -EINVAL;
655 }
656
657 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
658 case SND_SOC_DAIFMT_NB_NF:
659 break;
660
661 case SND_SOC_DAIFMT_IB_IF:
662 if (!can_invert_lrclk)
663 return -EINVAL;
664 aifb |= WM8580_AIF_BCP;
665 aifb |= WM8580_AIF_LRP;
666 break;
667
668 case SND_SOC_DAIFMT_IB_NF:
669 aifb |= WM8580_AIF_BCP;
670 break;
671
672 case SND_SOC_DAIFMT_NB_IF:
673 if (!can_invert_lrclk)
674 return -EINVAL;
675 aifb |= WM8580_AIF_LRP;
676 break;
677
678 default:
679 return -EINVAL;
680 }
681
682 snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa);
683 snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb);
684
685 return 0;
686 }
687
688 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
689 int div_id, int div)
690 {
691 struct snd_soc_codec *codec = codec_dai->codec;
692 unsigned int reg;
693
694 switch (div_id) {
695 case WM8580_MCLK:
696 reg = snd_soc_read(codec, WM8580_PLLB4);
697 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
698
699 switch (div) {
700 case WM8580_CLKSRC_MCLK:
701 /* Input */
702 break;
703
704 case WM8580_CLKSRC_PLLA:
705 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
706 break;
707 case WM8580_CLKSRC_PLLB:
708 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
709 break;
710
711 case WM8580_CLKSRC_OSC:
712 reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
713 break;
714
715 default:
716 return -EINVAL;
717 }
718 snd_soc_write(codec, WM8580_PLLB4, reg);
719 break;
720
721 case WM8580_CLKOUTSRC:
722 reg = snd_soc_read(codec, WM8580_PLLB4);
723 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
724
725 switch (div) {
726 case WM8580_CLKSRC_NONE:
727 break;
728
729 case WM8580_CLKSRC_PLLA:
730 reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
731 break;
732
733 case WM8580_CLKSRC_PLLB:
734 reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
735 break;
736
737 case WM8580_CLKSRC_OSC:
738 reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
739 break;
740
741 default:
742 return -EINVAL;
743 }
744 snd_soc_write(codec, WM8580_PLLB4, reg);
745 break;
746
747 default:
748 return -EINVAL;
749 }
750
751 return 0;
752 }
753
754 static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
755 unsigned int freq, int dir)
756 {
757 struct snd_soc_codec *codec = dai->codec;
758 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
759 int ret, sel, sel_mask, sel_shift;
760
761 switch (dai->driver->id) {
762 case WM8580_DAI_PAIFRX:
763 sel_mask = 0x3;
764 sel_shift = 0;
765 break;
766
767 case WM8580_DAI_PAIFTX:
768 sel_mask = 0xc;
769 sel_shift = 2;
770 break;
771
772 default:
773 WARN(1, "Unknown DAI driver ID\n");
774 return -EINVAL;
775 }
776
777 switch (clk_id) {
778 case WM8580_CLKSRC_ADCMCLK:
779 if (dai->driver->id != WM8580_DAI_PAIFTX)
780 return -EINVAL;
781 sel = 0 << sel_shift;
782 break;
783 case WM8580_CLKSRC_PLLA:
784 sel = 1 << sel_shift;
785 break;
786 case WM8580_CLKSRC_PLLB:
787 sel = 2 << sel_shift;
788 break;
789 case WM8580_CLKSRC_MCLK:
790 sel = 3 << sel_shift;
791 break;
792 default:
793 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
794 return -EINVAL;
795 }
796
797 /* We really should validate PLL settings but not yet */
798 wm8580->sysclk[dai->driver->id] = freq;
799
800 ret = snd_soc_update_bits(codec, WM8580_CLKSEL, sel_mask, sel);
801 if (ret < 0)
802 return ret;
803
804 return 0;
805 }
806
807 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
808 {
809 struct snd_soc_codec *codec = codec_dai->codec;
810 unsigned int reg;
811
812 reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
813
814 if (mute)
815 reg |= WM8580_DAC_CONTROL5_MUTEALL;
816 else
817 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
818
819 snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
820
821 return 0;
822 }
823
824 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
825 enum snd_soc_bias_level level)
826 {
827 switch (level) {
828 case SND_SOC_BIAS_ON:
829 case SND_SOC_BIAS_PREPARE:
830 break;
831
832 case SND_SOC_BIAS_STANDBY:
833 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
834 /* Power up and get individual control of the DACs */
835 snd_soc_update_bits(codec, WM8580_PWRDN1,
836 WM8580_PWRDN1_PWDN |
837 WM8580_PWRDN1_ALLDACPD, 0);
838
839 /* Make VMID high impedance */
840 snd_soc_update_bits(codec, WM8580_ADC_CONTROL1,
841 0x100, 0);
842 }
843 break;
844
845 case SND_SOC_BIAS_OFF:
846 snd_soc_update_bits(codec, WM8580_PWRDN1,
847 WM8580_PWRDN1_PWDN, WM8580_PWRDN1_PWDN);
848 break;
849 }
850 return 0;
851 }
852
853 static int wm8580_playback_startup(struct snd_pcm_substream *substream,
854 struct snd_soc_dai *dai)
855 {
856 struct snd_soc_codec *codec = dai->codec;
857 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
858
859 return snd_pcm_hw_constraint_minmax(substream->runtime,
860 SNDRV_PCM_HW_PARAM_CHANNELS, 1, wm8580->drvdata->num_dacs * 2);
861 }
862
863 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
864 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
865
866 static const struct snd_soc_dai_ops wm8580_dai_ops_playback = {
867 .startup = wm8580_playback_startup,
868 .set_sysclk = wm8580_set_sysclk,
869 .hw_params = wm8580_paif_hw_params,
870 .set_fmt = wm8580_set_paif_dai_fmt,
871 .set_clkdiv = wm8580_set_dai_clkdiv,
872 .set_pll = wm8580_set_dai_pll,
873 .digital_mute = wm8580_digital_mute,
874 };
875
876 static const struct snd_soc_dai_ops wm8580_dai_ops_capture = {
877 .set_sysclk = wm8580_set_sysclk,
878 .hw_params = wm8580_paif_hw_params,
879 .set_fmt = wm8580_set_paif_dai_fmt,
880 .set_clkdiv = wm8580_set_dai_clkdiv,
881 .set_pll = wm8580_set_dai_pll,
882 };
883
884 static struct snd_soc_dai_driver wm8580_dai[] = {
885 {
886 .name = "wm8580-hifi-playback",
887 .id = WM8580_DAI_PAIFRX,
888 .playback = {
889 .stream_name = "Playback",
890 .channels_min = 1,
891 .rates = SNDRV_PCM_RATE_8000_192000,
892 .formats = WM8580_FORMATS,
893 },
894 .ops = &wm8580_dai_ops_playback,
895 },
896 {
897 .name = "wm8580-hifi-capture",
898 .id = WM8580_DAI_PAIFTX,
899 .capture = {
900 .stream_name = "Capture",
901 .channels_min = 2,
902 .channels_max = 2,
903 .rates = SNDRV_PCM_RATE_8000_192000,
904 .formats = WM8580_FORMATS,
905 },
906 .ops = &wm8580_dai_ops_capture,
907 },
908 };
909
910 static int wm8580_probe(struct snd_soc_codec *codec)
911 {
912 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
913 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
914 int ret = 0;
915
916 switch (wm8580->drvdata->num_dacs) {
917 case 4:
918 snd_soc_add_codec_controls(codec, wm8581_snd_controls,
919 ARRAY_SIZE(wm8581_snd_controls));
920 snd_soc_dapm_new_controls(dapm, wm8581_dapm_widgets,
921 ARRAY_SIZE(wm8581_dapm_widgets));
922 snd_soc_dapm_add_routes(dapm, wm8581_dapm_routes,
923 ARRAY_SIZE(wm8581_dapm_routes));
924 break;
925 default:
926 break;
927 }
928
929 ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
930 wm8580->supplies);
931 if (ret != 0) {
932 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
933 goto err_regulator_get;
934 }
935
936 /* Get the codec into a known state */
937 ret = snd_soc_write(codec, WM8580_RESET, 0);
938 if (ret != 0) {
939 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
940 goto err_regulator_enable;
941 }
942
943 return 0;
944
945 err_regulator_enable:
946 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
947 err_regulator_get:
948 return ret;
949 }
950
951 /* power down chip */
952 static int wm8580_remove(struct snd_soc_codec *codec)
953 {
954 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
955
956 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
957
958 return 0;
959 }
960
961 static const struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
962 .probe = wm8580_probe,
963 .remove = wm8580_remove,
964 .set_bias_level = wm8580_set_bias_level,
965
966 .component_driver = {
967 .controls = wm8580_snd_controls,
968 .num_controls = ARRAY_SIZE(wm8580_snd_controls),
969 .dapm_widgets = wm8580_dapm_widgets,
970 .num_dapm_widgets = ARRAY_SIZE(wm8580_dapm_widgets),
971 .dapm_routes = wm8580_dapm_routes,
972 .num_dapm_routes = ARRAY_SIZE(wm8580_dapm_routes),
973 },
974 };
975
976 static const struct regmap_config wm8580_regmap = {
977 .reg_bits = 7,
978 .val_bits = 9,
979 .max_register = WM8580_MAX_REGISTER,
980
981 .reg_defaults = wm8580_reg_defaults,
982 .num_reg_defaults = ARRAY_SIZE(wm8580_reg_defaults),
983 .cache_type = REGCACHE_RBTREE,
984
985 .volatile_reg = wm8580_volatile,
986 };
987
988 static const struct wm8580_driver_data wm8580_data = {
989 .num_dacs = 3,
990 };
991
992 static const struct wm8580_driver_data wm8581_data = {
993 .num_dacs = 4,
994 };
995
996 static const struct of_device_id wm8580_of_match[] = {
997 { .compatible = "wlf,wm8580", .data = &wm8580_data },
998 { .compatible = "wlf,wm8581", .data = &wm8581_data },
999 { },
1000 };
1001 MODULE_DEVICE_TABLE(of, wm8580_of_match);
1002
1003 static int wm8580_i2c_probe(struct i2c_client *i2c,
1004 const struct i2c_device_id *id)
1005 {
1006 const struct of_device_id *of_id;
1007 struct wm8580_priv *wm8580;
1008 int ret, i;
1009
1010 wm8580 = devm_kzalloc(&i2c->dev, sizeof(struct wm8580_priv),
1011 GFP_KERNEL);
1012 if (wm8580 == NULL)
1013 return -ENOMEM;
1014
1015 wm8580->regmap = devm_regmap_init_i2c(i2c, &wm8580_regmap);
1016 if (IS_ERR(wm8580->regmap))
1017 return PTR_ERR(wm8580->regmap);
1018
1019 for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
1020 wm8580->supplies[i].supply = wm8580_supply_names[i];
1021
1022 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8580->supplies),
1023 wm8580->supplies);
1024 if (ret != 0) {
1025 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1026 return ret;
1027 }
1028
1029 i2c_set_clientdata(i2c, wm8580);
1030
1031 of_id = of_match_device(wm8580_of_match, &i2c->dev);
1032 if (of_id)
1033 wm8580->drvdata = of_id->data;
1034
1035 if (!wm8580->drvdata) {
1036 dev_err(&i2c->dev, "failed to find driver data\n");
1037 return -EINVAL;
1038 }
1039
1040 ret = snd_soc_register_codec(&i2c->dev,
1041 &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
1042
1043 return ret;
1044 }
1045
1046 static int wm8580_i2c_remove(struct i2c_client *client)
1047 {
1048 snd_soc_unregister_codec(&client->dev);
1049 return 0;
1050 }
1051
1052 static const struct i2c_device_id wm8580_i2c_id[] = {
1053 { "wm8580", (kernel_ulong_t)&wm8580_data },
1054 { "wm8581", (kernel_ulong_t)&wm8581_data },
1055 { }
1056 };
1057 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
1058
1059 static struct i2c_driver wm8580_i2c_driver = {
1060 .driver = {
1061 .name = "wm8580",
1062 .of_match_table = wm8580_of_match,
1063 },
1064 .probe = wm8580_i2c_probe,
1065 .remove = wm8580_i2c_remove,
1066 .id_table = wm8580_i2c_id,
1067 };
1068
1069 module_i2c_driver(wm8580_i2c_driver);
1070
1071 MODULE_DESCRIPTION("ASoC WM8580 driver");
1072 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1073 MODULE_AUTHOR("Matt Flax <flatmax@flatmax.org>");
1074 MODULE_LICENSE("GPL");
Linux with added FPC-III support