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btrfs: add missing initialization in btrfs_check_shared
[linux/fpc-iii.git] / sound / soc / codecs / wm8995.c
blob19b08a5cae625f0362fc29e2b4e5198588ed089f
1 /*
2 * wm8995.c -- WM8995 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * Based on wm8994.c and wm_hubs.c by Mark Brown
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/pm.h>
20 #include <linux/i2c.h>
21 #include <linux/regmap.h>
22 #include <linux/spi/spi.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32
33 #include "wm8995.h"
34
35 #define WM8995_NUM_SUPPLIES 8
36 static const char *wm8995_supply_names[WM8995_NUM_SUPPLIES] = {
37 "DCVDD",
38 "DBVDD1",
39 "DBVDD2",
40 "DBVDD3",
41 "AVDD1",
42 "AVDD2",
43 "CPVDD",
44 "MICVDD"
45 };
46
47 static const struct reg_default wm8995_reg_defaults[] = {
48 { 0, 0x8995 },
49 { 5, 0x0100 },
50 { 16, 0x000b },
51 { 17, 0x000b },
52 { 24, 0x02c0 },
53 { 25, 0x02c0 },
54 { 26, 0x02c0 },
55 { 27, 0x02c0 },
56 { 28, 0x000f },
57 { 32, 0x0005 },
58 { 33, 0x0005 },
59 { 40, 0x0003 },
60 { 41, 0x0013 },
61 { 48, 0x0004 },
62 { 56, 0x09f8 },
63 { 64, 0x1f25 },
64 { 69, 0x0004 },
65 { 82, 0xaaaa },
66 { 84, 0x2a2a },
67 { 146, 0x0060 },
68 { 256, 0x0002 },
69 { 257, 0x8004 },
70 { 520, 0x0010 },
71 { 528, 0x0083 },
72 { 529, 0x0083 },
73 { 548, 0x0c80 },
74 { 580, 0x0c80 },
75 { 768, 0x4050 },
76 { 769, 0x4000 },
77 { 771, 0x0040 },
78 { 772, 0x0040 },
79 { 773, 0x0040 },
80 { 774, 0x0004 },
81 { 775, 0x0100 },
82 { 784, 0x4050 },
83 { 785, 0x4000 },
84 { 787, 0x0040 },
85 { 788, 0x0040 },
86 { 789, 0x0040 },
87 { 1024, 0x00c0 },
88 { 1025, 0x00c0 },
89 { 1026, 0x00c0 },
90 { 1027, 0x00c0 },
91 { 1028, 0x00c0 },
92 { 1029, 0x00c0 },
93 { 1030, 0x00c0 },
94 { 1031, 0x00c0 },
95 { 1056, 0x0200 },
96 { 1057, 0x0010 },
97 { 1058, 0x0200 },
98 { 1059, 0x0010 },
99 { 1088, 0x0098 },
100 { 1089, 0x0845 },
101 { 1104, 0x0098 },
102 { 1105, 0x0845 },
103 { 1152, 0x6318 },
104 { 1153, 0x6300 },
105 { 1154, 0x0fca },
106 { 1155, 0x0400 },
107 { 1156, 0x00d8 },
108 { 1157, 0x1eb5 },
109 { 1158, 0xf145 },
110 { 1159, 0x0b75 },
111 { 1160, 0x01c5 },
112 { 1161, 0x1c58 },
113 { 1162, 0xf373 },
114 { 1163, 0x0a54 },
115 { 1164, 0x0558 },
116 { 1165, 0x168e },
117 { 1166, 0xf829 },
118 { 1167, 0x07ad },
119 { 1168, 0x1103 },
120 { 1169, 0x0564 },
121 { 1170, 0x0559 },
122 { 1171, 0x4000 },
123 { 1184, 0x6318 },
124 { 1185, 0x6300 },
125 { 1186, 0x0fca },
126 { 1187, 0x0400 },
127 { 1188, 0x00d8 },
128 { 1189, 0x1eb5 },
129 { 1190, 0xf145 },
130 { 1191, 0x0b75 },
131 { 1192, 0x01c5 },
132 { 1193, 0x1c58 },
133 { 1194, 0xf373 },
134 { 1195, 0x0a54 },
135 { 1196, 0x0558 },
136 { 1197, 0x168e },
137 { 1198, 0xf829 },
138 { 1199, 0x07ad },
139 { 1200, 0x1103 },
140 { 1201, 0x0564 },
141 { 1202, 0x0559 },
142 { 1203, 0x4000 },
143 { 1280, 0x00c0 },
144 { 1281, 0x00c0 },
145 { 1282, 0x00c0 },
146 { 1283, 0x00c0 },
147 { 1312, 0x0200 },
148 { 1313, 0x0010 },
149 { 1344, 0x0098 },
150 { 1345, 0x0845 },
151 { 1408, 0x6318 },
152 { 1409, 0x6300 },
153 { 1410, 0x0fca },
154 { 1411, 0x0400 },
155 { 1412, 0x00d8 },
156 { 1413, 0x1eb5 },
157 { 1414, 0xf145 },
158 { 1415, 0x0b75 },
159 { 1416, 0x01c5 },
160 { 1417, 0x1c58 },
161 { 1418, 0xf373 },
162 { 1419, 0x0a54 },
163 { 1420, 0x0558 },
164 { 1421, 0x168e },
165 { 1422, 0xf829 },
166 { 1423, 0x07ad },
167 { 1424, 0x1103 },
168 { 1425, 0x0564 },
169 { 1426, 0x0559 },
170 { 1427, 0x4000 },
171 { 1568, 0x0002 },
172 { 1792, 0xa100 },
173 { 1793, 0xa101 },
174 { 1794, 0xa101 },
175 { 1795, 0xa101 },
176 { 1796, 0xa101 },
177 { 1797, 0xa101 },
178 { 1798, 0xa101 },
179 { 1799, 0xa101 },
180 { 1800, 0xa101 },
181 { 1801, 0xa101 },
182 { 1802, 0xa101 },
183 { 1803, 0xa101 },
184 { 1804, 0xa101 },
185 { 1805, 0xa101 },
186 { 1825, 0x0055 },
187 { 1848, 0x3fff },
188 { 1849, 0x1fff },
189 { 2049, 0x0001 },
190 { 2050, 0x0069 },
191 { 2056, 0x0002 },
192 { 2057, 0x0003 },
193 { 2058, 0x0069 },
194 { 12288, 0x0001 },
195 { 12289, 0x0001 },
196 { 12291, 0x0006 },
197 { 12292, 0x0040 },
198 { 12293, 0x0001 },
199 { 12294, 0x000f },
200 { 12295, 0x0006 },
201 { 12296, 0x0001 },
202 { 12297, 0x0003 },
203 { 12298, 0x0104 },
204 { 12300, 0x0060 },
205 { 12301, 0x0011 },
206 { 12302, 0x0401 },
207 { 12304, 0x0050 },
208 { 12305, 0x0003 },
209 { 12306, 0x0100 },
210 { 12308, 0x0051 },
211 { 12309, 0x0003 },
212 { 12310, 0x0104 },
213 { 12311, 0x000a },
214 { 12312, 0x0060 },
215 { 12313, 0x003b },
216 { 12314, 0x0502 },
217 { 12315, 0x0100 },
218 { 12316, 0x2fff },
219 { 12320, 0x2fff },
220 { 12324, 0x2fff },
221 { 12328, 0x2fff },
222 { 12332, 0x2fff },
223 { 12336, 0x2fff },
224 { 12340, 0x2fff },
225 { 12344, 0x2fff },
226 { 12348, 0x2fff },
227 { 12352, 0x0001 },
228 { 12353, 0x0001 },
229 { 12355, 0x0006 },
230 { 12356, 0x0040 },
231 { 12357, 0x0001 },
232 { 12358, 0x000f },
233 { 12359, 0x0006 },
234 { 12360, 0x0001 },
235 { 12361, 0x0003 },
236 { 12362, 0x0104 },
237 { 12364, 0x0060 },
238 { 12365, 0x0011 },
239 { 12366, 0x0401 },
240 { 12368, 0x0050 },
241 { 12369, 0x0003 },
242 { 12370, 0x0100 },
243 { 12372, 0x0060 },
244 { 12373, 0x003b },
245 { 12374, 0x0502 },
246 { 12375, 0x0100 },
247 { 12376, 0x2fff },
248 { 12380, 0x2fff },
249 { 12384, 0x2fff },
250 { 12388, 0x2fff },
251 { 12392, 0x2fff },
252 { 12396, 0x2fff },
253 { 12400, 0x2fff },
254 { 12404, 0x2fff },
255 { 12408, 0x2fff },
256 { 12412, 0x2fff },
257 { 12416, 0x0001 },
258 { 12417, 0x0001 },
259 { 12419, 0x0006 },
260 { 12420, 0x0040 },
261 { 12421, 0x0001 },
262 { 12422, 0x000f },
263 { 12423, 0x0006 },
264 { 12424, 0x0001 },
265 { 12425, 0x0003 },
266 { 12426, 0x0106 },
267 { 12428, 0x0061 },
268 { 12429, 0x0011 },
269 { 12430, 0x0401 },
270 { 12432, 0x0050 },
271 { 12433, 0x0003 },
272 { 12434, 0x0102 },
273 { 12436, 0x0051 },
274 { 12437, 0x0003 },
275 { 12438, 0x0106 },
276 { 12439, 0x000a },
277 { 12440, 0x0061 },
278 { 12441, 0x003b },
279 { 12442, 0x0502 },
280 { 12443, 0x0100 },
281 { 12444, 0x2fff },
282 { 12448, 0x2fff },
283 { 12452, 0x2fff },
284 { 12456, 0x2fff },
285 { 12460, 0x2fff },
286 { 12464, 0x2fff },
287 { 12468, 0x2fff },
288 { 12472, 0x2fff },
289 { 12476, 0x2fff },
290 { 12480, 0x0001 },
291 { 12481, 0x0001 },
292 { 12483, 0x0006 },
293 { 12484, 0x0040 },
294 { 12485, 0x0001 },
295 { 12486, 0x000f },
296 { 12487, 0x0006 },
297 { 12488, 0x0001 },
298 { 12489, 0x0003 },
299 { 12490, 0x0106 },
300 { 12492, 0x0061 },
301 { 12493, 0x0011 },
302 { 12494, 0x0401 },
303 { 12496, 0x0050 },
304 { 12497, 0x0003 },
305 { 12498, 0x0102 },
306 { 12500, 0x0061 },
307 { 12501, 0x003b },
308 { 12502, 0x0502 },
309 { 12503, 0x0100 },
310 { 12504, 0x2fff },
311 { 12508, 0x2fff },
312 { 12512, 0x2fff },
313 { 12516, 0x2fff },
314 { 12520, 0x2fff },
315 { 12524, 0x2fff },
316 { 12528, 0x2fff },
317 { 12532, 0x2fff },
318 { 12536, 0x2fff },
319 { 12540, 0x2fff },
320 { 12544, 0x0060 },
321 { 12546, 0x0601 },
322 { 12548, 0x0050 },
323 { 12550, 0x0100 },
324 { 12552, 0x0001 },
325 { 12554, 0x0104 },
326 { 12555, 0x0100 },
327 { 12556, 0x2fff },
328 { 12560, 0x2fff },
329 { 12564, 0x2fff },
330 { 12568, 0x2fff },
331 { 12572, 0x2fff },
332 { 12576, 0x2fff },
333 { 12580, 0x2fff },
334 { 12584, 0x2fff },
335 { 12588, 0x2fff },
336 { 12592, 0x2fff },
337 { 12596, 0x2fff },
338 { 12600, 0x2fff },
339 { 12604, 0x2fff },
340 { 12608, 0x0061 },
341 { 12610, 0x0601 },
342 { 12612, 0x0050 },
343 { 12614, 0x0102 },
344 { 12616, 0x0001 },
345 { 12618, 0x0106 },
346 { 12619, 0x0100 },
347 { 12620, 0x2fff },
348 { 12624, 0x2fff },
349 { 12628, 0x2fff },
350 { 12632, 0x2fff },
351 { 12636, 0x2fff },
352 { 12640, 0x2fff },
353 { 12644, 0x2fff },
354 { 12648, 0x2fff },
355 { 12652, 0x2fff },
356 { 12656, 0x2fff },
357 { 12660, 0x2fff },
358 { 12664, 0x2fff },
359 { 12668, 0x2fff },
360 { 12672, 0x0060 },
361 { 12674, 0x0601 },
362 { 12676, 0x0061 },
363 { 12678, 0x0601 },
364 { 12680, 0x0050 },
365 { 12682, 0x0300 },
366 { 12684, 0x0001 },
367 { 12686, 0x0304 },
368 { 12688, 0x0040 },
369 { 12690, 0x000f },
370 { 12692, 0x0001 },
371 { 12695, 0x0100 },
372 };
373
374 struct fll_config {
375 int src;
376 int in;
377 int out;
378 };
379
380 struct wm8995_priv {
381 struct regmap *regmap;
382 int sysclk[2];
383 int mclk[2];
384 int aifclk[2];
385 struct fll_config fll[2], fll_suspend[2];
386 struct regulator_bulk_data supplies[WM8995_NUM_SUPPLIES];
387 struct notifier_block disable_nb[WM8995_NUM_SUPPLIES];
388 struct snd_soc_codec *codec;
389 };
390
391 /*
392 * We can't use the same notifier block for more than one supply and
393 * there's no way I can see to get from a callback to the caller
394 * except container_of().
395 */
396 #define WM8995_REGULATOR_EVENT(n) \
397 static int wm8995_regulator_event_##n(struct notifier_block *nb, \
398 unsigned long event, void *data) \
399 { \
400 struct wm8995_priv *wm8995 = container_of(nb, struct wm8995_priv, \
401 disable_nb[n]); \
402 if (event & REGULATOR_EVENT_DISABLE) { \
403 regcache_mark_dirty(wm8995->regmap); \
404 } \
405 return 0; \
406 }
407
408 WM8995_REGULATOR_EVENT(0)
409 WM8995_REGULATOR_EVENT(1)
410 WM8995_REGULATOR_EVENT(2)
411 WM8995_REGULATOR_EVENT(3)
412 WM8995_REGULATOR_EVENT(4)
413 WM8995_REGULATOR_EVENT(5)
414 WM8995_REGULATOR_EVENT(6)
415 WM8995_REGULATOR_EVENT(7)
416
417 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
418 static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0);
419 static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0);
420 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
421
422 static const char *in1l_text[] = {
423 "Differential", "Single-ended IN1LN", "Single-ended IN1LP"
424 };
425
426 static SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
427 2, in1l_text);
428
429 static const char *in1r_text[] = {
430 "Differential", "Single-ended IN1RN", "Single-ended IN1RP"
431 };
432
433 static SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
434 0, in1r_text);
435
436 static const char *dmic_src_text[] = {
437 "DMICDAT1", "DMICDAT2", "DMICDAT3"
438 };
439
440 static SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5,
441 8, dmic_src_text);
442 static SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5,
443 6, dmic_src_text);
444
445 static const struct snd_kcontrol_new wm8995_snd_controls[] = {
446 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME,
447 WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
448 SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME,
449 WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1),
450
451 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME,
452 WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
453 SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME,
454 WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1),
455
456 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME,
457 WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
458 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME,
459 WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
460 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME,
461 WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
462
463 SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME,
464 WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv),
465
466 SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL,
467 4, 3, 0, in1l_boost_tlv),
468
469 SOC_ENUM("IN1L Mode", in1l_enum),
470 SOC_ENUM("IN1R Mode", in1r_enum),
471
472 SOC_ENUM("DMIC1 SRC", dmic_src1_enum),
473 SOC_ENUM("DMIC2 SRC", dmic_src2_enum),
474
475 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5,
476 24, 0, sidetone_tlv),
477 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5,
478 24, 0, sidetone_tlv),
479
480 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME,
481 WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
482 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME,
483 WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
484 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME,
485 WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv)
486 };
487
488 static void wm8995_update_class_w(struct snd_soc_codec *codec)
489 {
490 int enable = 1;
491 int source = 0; /* GCC flow analysis can't track enable */
492 int reg, reg_r;
493
494 /* We also need the same setting for L/R and only one path */
495 reg = snd_soc_read(codec, WM8995_DAC1_LEFT_MIXER_ROUTING);
496 switch (reg) {
497 case WM8995_AIF2DACL_TO_DAC1L:
498 dev_dbg(codec->dev, "Class W source AIF2DAC\n");
499 source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT;
500 break;
501 case WM8995_AIF1DAC2L_TO_DAC1L:
502 dev_dbg(codec->dev, "Class W source AIF1DAC2\n");
503 source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT;
504 break;
505 case WM8995_AIF1DAC1L_TO_DAC1L:
506 dev_dbg(codec->dev, "Class W source AIF1DAC1\n");
507 source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT;
508 break;
509 default:
510 dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg);
511 enable = 0;
512 break;
513 }
514
515 reg_r = snd_soc_read(codec, WM8995_DAC1_RIGHT_MIXER_ROUTING);
516 if (reg_r != reg) {
517 dev_dbg(codec->dev, "Left and right DAC mixers different\n");
518 enable = 0;
519 }
520
521 if (enable) {
522 dev_dbg(codec->dev, "Class W enabled\n");
523 snd_soc_update_bits(codec, WM8995_CLASS_W_1,
524 WM8995_CP_DYN_PWR_MASK |
525 WM8995_CP_DYN_SRC_SEL_MASK,
526 source | WM8995_CP_DYN_PWR);
527 } else {
528 dev_dbg(codec->dev, "Class W disabled\n");
529 snd_soc_update_bits(codec, WM8995_CLASS_W_1,
530 WM8995_CP_DYN_PWR_MASK, 0);
531 }
532 }
533
534 static int check_clk_sys(struct snd_soc_dapm_widget *source,
535 struct snd_soc_dapm_widget *sink)
536 {
537 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
538 unsigned int reg;
539 const char *clk;
540
541 reg = snd_soc_read(codec, WM8995_CLOCKING_1);
542 /* Check what we're currently using for CLK_SYS */
543 if (reg & WM8995_SYSCLK_SRC)
544 clk = "AIF2CLK";
545 else
546 clk = "AIF1CLK";
547 return !strcmp(source->name, clk);
548 }
549
550 static int wm8995_put_class_w(struct snd_kcontrol *kcontrol,
551 struct snd_ctl_elem_value *ucontrol)
552 {
553 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
554 int ret;
555
556 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
557 wm8995_update_class_w(codec);
558 return ret;
559 }
560
561 static int hp_supply_event(struct snd_soc_dapm_widget *w,
562 struct snd_kcontrol *kcontrol, int event)
563 {
564 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
565
566 switch (event) {
567 case SND_SOC_DAPM_PRE_PMU:
568 /* Enable the headphone amp */
569 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
570 WM8995_HPOUT1L_ENA_MASK |
571 WM8995_HPOUT1R_ENA_MASK,
572 WM8995_HPOUT1L_ENA |
573 WM8995_HPOUT1R_ENA);
574
575 /* Enable the second stage */
576 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
577 WM8995_HPOUT1L_DLY_MASK |
578 WM8995_HPOUT1R_DLY_MASK,
579 WM8995_HPOUT1L_DLY |
580 WM8995_HPOUT1R_DLY);
581 break;
582 case SND_SOC_DAPM_PRE_PMD:
583 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1,
584 WM8995_CP_ENA_MASK, 0);
585 break;
586 }
587
588 return 0;
589 }
590
591 static void dc_servo_cmd(struct snd_soc_codec *codec,
592 unsigned int reg, unsigned int val, unsigned int mask)
593 {
594 int timeout = 10;
595
596 dev_dbg(codec->dev, "%s: reg = %#x, val = %#x, mask = %#x\n",
597 __func__, reg, val, mask);
598
599 snd_soc_write(codec, reg, val);
600 while (timeout--) {
601 msleep(10);
602 val = snd_soc_read(codec, WM8995_DC_SERVO_READBACK_0);
603 if ((val & mask) == mask)
604 return;
605 }
606
607 dev_err(codec->dev, "Timed out waiting for DC Servo\n");
608 }
609
610 static int hp_event(struct snd_soc_dapm_widget *w,
611 struct snd_kcontrol *kcontrol, int event)
612 {
613 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
614 unsigned int reg;
615
616 reg = snd_soc_read(codec, WM8995_ANALOGUE_HP_1);
617
618 switch (event) {
619 case SND_SOC_DAPM_POST_PMU:
620 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1,
621 WM8995_CP_ENA_MASK, WM8995_CP_ENA);
622
623 msleep(5);
624
625 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
626 WM8995_HPOUT1L_ENA_MASK |
627 WM8995_HPOUT1R_ENA_MASK,
628 WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA);
629
630 udelay(20);
631
632 reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY;
633 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg);
634
635 snd_soc_write(codec, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 |
636 WM8995_DCS_ENA_CHAN_1);
637
638 dc_servo_cmd(codec, WM8995_DC_SERVO_2,
639 WM8995_DCS_TRIG_STARTUP_0 |
640 WM8995_DCS_TRIG_STARTUP_1,
641 WM8995_DCS_TRIG_DAC_WR_0 |
642 WM8995_DCS_TRIG_DAC_WR_1);
643
644 reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT |
645 WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT;
646 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg);
647
648 break;
649 case SND_SOC_DAPM_PRE_PMD:
650 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
651 WM8995_HPOUT1L_OUTP_MASK |
652 WM8995_HPOUT1R_OUTP_MASK |
653 WM8995_HPOUT1L_RMV_SHORT_MASK |
654 WM8995_HPOUT1R_RMV_SHORT_MASK, 0);
655
656 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
657 WM8995_HPOUT1L_DLY_MASK |
658 WM8995_HPOUT1R_DLY_MASK, 0);
659
660 snd_soc_write(codec, WM8995_DC_SERVO_1, 0);
661
662 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
663 WM8995_HPOUT1L_ENA_MASK |
664 WM8995_HPOUT1R_ENA_MASK,
665 0);
666 break;
667 }
668
669 return 0;
670 }
671
672 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
673 {
674 struct wm8995_priv *wm8995;
675 int rate;
676 int reg1 = 0;
677 int offset;
678
679 wm8995 = snd_soc_codec_get_drvdata(codec);
680
681 if (aif)
682 offset = 4;
683 else
684 offset = 0;
685
686 switch (wm8995->sysclk[aif]) {
687 case WM8995_SYSCLK_MCLK1:
688 rate = wm8995->mclk[0];
689 break;
690 case WM8995_SYSCLK_MCLK2:
691 reg1 |= 0x8;
692 rate = wm8995->mclk[1];
693 break;
694 case WM8995_SYSCLK_FLL1:
695 reg1 |= 0x10;
696 rate = wm8995->fll[0].out;
697 break;
698 case WM8995_SYSCLK_FLL2:
699 reg1 |= 0x18;
700 rate = wm8995->fll[1].out;
701 break;
702 default:
703 return -EINVAL;
704 }
705
706 if (rate >= 13500000) {
707 rate /= 2;
708 reg1 |= WM8995_AIF1CLK_DIV;
709
710 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
711 aif + 1, rate);
712 }
713
714 wm8995->aifclk[aif] = rate;
715
716 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1 + offset,
717 WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK,
718 reg1);
719 return 0;
720 }
721
722 static int configure_clock(struct snd_soc_codec *codec)
723 {
724 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
725 struct wm8995_priv *wm8995;
726 int change, new;
727
728 wm8995 = snd_soc_codec_get_drvdata(codec);
729
730 /* Bring up the AIF clocks first */
731 configure_aif_clock(codec, 0);
732 configure_aif_clock(codec, 1);
733
734 /*
735 * Then switch CLK_SYS over to the higher of them; a change
736 * can only happen as a result of a clocking change which can
737 * only be made outside of DAPM so we can safely redo the
738 * clocking.
739 */
740
741 /* If they're equal it doesn't matter which is used */
742 if (wm8995->aifclk[0] == wm8995->aifclk[1])
743 return 0;
744
745 if (wm8995->aifclk[0] < wm8995->aifclk[1])
746 new = WM8995_SYSCLK_SRC;
747 else
748 new = 0;
749
750 change = snd_soc_update_bits(codec, WM8995_CLOCKING_1,
751 WM8995_SYSCLK_SRC_MASK, new);
752 if (!change)
753 return 0;
754
755 snd_soc_dapm_sync(dapm);
756
757 return 0;
758 }
759
760 static int clk_sys_event(struct snd_soc_dapm_widget *w,
761 struct snd_kcontrol *kcontrol, int event)
762 {
763 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
764
765 switch (event) {
766 case SND_SOC_DAPM_PRE_PMU:
767 return configure_clock(codec);
768
769 case SND_SOC_DAPM_POST_PMD:
770 configure_clock(codec);
771 break;
772 }
773
774 return 0;
775 }
776
777 static const char *sidetone_text[] = {
778 "ADC/DMIC1", "DMIC2",
779 };
780
781 static SOC_ENUM_SINGLE_DECL(sidetone1_enum, WM8995_SIDETONE, 0, sidetone_text);
782
783 static const struct snd_kcontrol_new sidetone1_mux =
784 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
785
786 static SOC_ENUM_SINGLE_DECL(sidetone2_enum, WM8995_SIDETONE, 1, sidetone_text);
787
788 static const struct snd_kcontrol_new sidetone2_mux =
789 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
790
791 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
792 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
793 1, 1, 0),
794 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
795 0, 1, 0),
796 };
797
798 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
799 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
800 1, 1, 0),
801 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
802 0, 1, 0),
803 };
804
805 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
806 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
807 1, 1, 0),
808 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
809 0, 1, 0),
810 };
811
812 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
813 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
814 1, 1, 0),
815 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
816 0, 1, 0),
817 };
818
819 static const struct snd_kcontrol_new dac1l_mix[] = {
820 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
821 5, 1, 0),
822 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
823 4, 1, 0),
824 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
825 2, 1, 0),
826 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
827 1, 1, 0),
828 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
829 0, 1, 0),
830 };
831
832 static const struct snd_kcontrol_new dac1r_mix[] = {
833 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
834 5, 1, 0),
835 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
836 4, 1, 0),
837 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
838 2, 1, 0),
839 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
840 1, 1, 0),
841 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
842 0, 1, 0),
843 };
844
845 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
846 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
847 5, 1, 0),
848 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
849 4, 1, 0),
850 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
851 2, 1, 0),
852 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
853 1, 1, 0),
854 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
855 0, 1, 0),
856 };
857
858 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
859 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
860 5, 1, 0),
861 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
862 4, 1, 0),
863 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
864 2, 1, 0),
865 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
866 1, 1, 0),
867 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
868 0, 1, 0),
869 };
870
871 static const struct snd_kcontrol_new in1l_pga =
872 SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0);
873
874 static const struct snd_kcontrol_new in1r_pga =
875 SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0);
876
877 static const char *adc_mux_text[] = {
878 "ADC",
879 "DMIC",
880 };
881
882 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
883
884 static const struct snd_kcontrol_new adcl_mux =
885 SOC_DAPM_ENUM("ADCL Mux", adc_enum);
886
887 static const struct snd_kcontrol_new adcr_mux =
888 SOC_DAPM_ENUM("ADCR Mux", adc_enum);
889
890 static const char *spk_src_text[] = {
891 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
892 };
893
894 static SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1,
895 0, spk_src_text);
896 static SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1,
897 0, spk_src_text);
898 static SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2,
899 0, spk_src_text);
900 static SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2,
901 0, spk_src_text);
902
903 static const struct snd_kcontrol_new spk1l_mux =
904 SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum);
905 static const struct snd_kcontrol_new spk1r_mux =
906 SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum);
907 static const struct snd_kcontrol_new spk2l_mux =
908 SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum);
909 static const struct snd_kcontrol_new spk2r_mux =
910 SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum);
911
912 static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = {
913 SND_SOC_DAPM_INPUT("DMIC1DAT"),
914 SND_SOC_DAPM_INPUT("DMIC2DAT"),
915
916 SND_SOC_DAPM_INPUT("IN1L"),
917 SND_SOC_DAPM_INPUT("IN1R"),
918
919 SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0,
920 &in1l_pga, 1),
921 SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0,
922 &in1r_pga, 1),
923
924 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0,
925 NULL, 0),
926 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0,
927 NULL, 0),
928
929 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0),
930 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0),
931 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0),
932 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0),
933 SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0),
934 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
935 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
936
937 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0,
938 WM8995_POWER_MANAGEMENT_3, 9, 0),
939 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0,
940 WM8995_POWER_MANAGEMENT_3, 8, 0),
941 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0,
942 SND_SOC_NOPM, 0, 0),
943 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
944 0, WM8995_POWER_MANAGEMENT_3, 11, 0),
945 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
946 0, WM8995_POWER_MANAGEMENT_3, 10, 0),
947
948 SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, &adcl_mux),
949 SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, &adcr_mux),
950
951 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0),
952 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0),
953 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0),
954 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0),
955
956 SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0),
957 SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0),
958
959 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
960 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
961 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
962 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
963 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
964 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
965 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
966 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
967
968 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
969 9, 0),
970 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
971 8, 0),
972 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM,
973 0, 0),
974
975 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
976 11, 0),
977 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
978 10, 0),
979
980 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
981 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
982 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
983 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
984
985 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0),
986 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0),
987 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0),
988 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0),
989
990 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix,
991 ARRAY_SIZE(dac1l_mix)),
992 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix,
993 ARRAY_SIZE(dac1r_mix)),
994
995 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
996 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
997
998 SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
999 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1000
1001 SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0,
1002 hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1003
1004 SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1,
1005 4, 0, &spk1l_mux),
1006 SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1,
1007 4, 0, &spk1r_mux),
1008 SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2,
1009 4, 0, &spk2l_mux),
1010 SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2,
1011 4, 0, &spk2r_mux),
1012
1013 SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
1014
1015 SND_SOC_DAPM_OUTPUT("HP1L"),
1016 SND_SOC_DAPM_OUTPUT("HP1R"),
1017 SND_SOC_DAPM_OUTPUT("SPK1L"),
1018 SND_SOC_DAPM_OUTPUT("SPK1R"),
1019 SND_SOC_DAPM_OUTPUT("SPK2L"),
1020 SND_SOC_DAPM_OUTPUT("SPK2R")
1021 };
1022
1023 static const struct snd_soc_dapm_route wm8995_intercon[] = {
1024 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1025 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1026
1027 { "DSP1CLK", NULL, "CLK_SYS" },
1028 { "DSP2CLK", NULL, "CLK_SYS" },
1029 { "SYSDSPCLK", NULL, "CLK_SYS" },
1030
1031 { "AIF1ADC1L", NULL, "AIF1CLK" },
1032 { "AIF1ADC1L", NULL, "DSP1CLK" },
1033 { "AIF1ADC1R", NULL, "AIF1CLK" },
1034 { "AIF1ADC1R", NULL, "DSP1CLK" },
1035 { "AIF1ADC1R", NULL, "SYSDSPCLK" },
1036
1037 { "AIF1ADC2L", NULL, "AIF1CLK" },
1038 { "AIF1ADC2L", NULL, "DSP1CLK" },
1039 { "AIF1ADC2R", NULL, "AIF1CLK" },
1040 { "AIF1ADC2R", NULL, "DSP1CLK" },
1041 { "AIF1ADC2R", NULL, "SYSDSPCLK" },
1042
1043 { "DMIC1L", NULL, "DMIC1DAT" },
1044 { "DMIC1L", NULL, "CLK_SYS" },
1045 { "DMIC1R", NULL, "DMIC1DAT" },
1046 { "DMIC1R", NULL, "CLK_SYS" },
1047 { "DMIC2L", NULL, "DMIC2DAT" },
1048 { "DMIC2L", NULL, "CLK_SYS" },
1049 { "DMIC2R", NULL, "DMIC2DAT" },
1050 { "DMIC2R", NULL, "CLK_SYS" },
1051
1052 { "ADCL", NULL, "AIF1CLK" },
1053 { "ADCL", NULL, "DSP1CLK" },
1054 { "ADCL", NULL, "SYSDSPCLK" },
1055
1056 { "ADCR", NULL, "AIF1CLK" },
1057 { "ADCR", NULL, "DSP1CLK" },
1058 { "ADCR", NULL, "SYSDSPCLK" },
1059
1060 { "IN1L PGA", "IN1L Switch", "IN1L" },
1061 { "IN1R PGA", "IN1R Switch", "IN1R" },
1062 { "IN1L PGA", NULL, "LDO2" },
1063 { "IN1R PGA", NULL, "LDO2" },
1064
1065 { "ADCL", NULL, "IN1L PGA" },
1066 { "ADCR", NULL, "IN1R PGA" },
1067
1068 { "ADCL Mux", "ADC", "ADCL" },
1069 { "ADCL Mux", "DMIC", "DMIC1L" },
1070 { "ADCR Mux", "ADC", "ADCR" },
1071 { "ADCR Mux", "DMIC", "DMIC1R" },
1072
1073 /* AIF1 outputs */
1074 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1075 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1076
1077 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1078 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1079
1080 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1081 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1082
1083 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1084 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1085
1086 /* Sidetone */
1087 { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" },
1088 { "Left Sidetone", "DMIC2", "AIF1ADC2L" },
1089 { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" },
1090 { "Right Sidetone", "DMIC2", "AIF1ADC2R" },
1091
1092 { "AIF1DAC1L", NULL, "AIF1CLK" },
1093 { "AIF1DAC1L", NULL, "DSP1CLK" },
1094 { "AIF1DAC1R", NULL, "AIF1CLK" },
1095 { "AIF1DAC1R", NULL, "DSP1CLK" },
1096 { "AIF1DAC1R", NULL, "SYSDSPCLK" },
1097
1098 { "AIF1DAC2L", NULL, "AIF1CLK" },
1099 { "AIF1DAC2L", NULL, "DSP1CLK" },
1100 { "AIF1DAC2R", NULL, "AIF1CLK" },
1101 { "AIF1DAC2R", NULL, "DSP1CLK" },
1102 { "AIF1DAC2R", NULL, "SYSDSPCLK" },
1103
1104 { "DAC1L", NULL, "AIF1CLK" },
1105 { "DAC1L", NULL, "DSP1CLK" },
1106 { "DAC1L", NULL, "SYSDSPCLK" },
1107
1108 { "DAC1R", NULL, "AIF1CLK" },
1109 { "DAC1R", NULL, "DSP1CLK" },
1110 { "DAC1R", NULL, "SYSDSPCLK" },
1111
1112 { "AIF1DAC1L", NULL, "AIF1DACDAT" },
1113 { "AIF1DAC1R", NULL, "AIF1DACDAT" },
1114 { "AIF1DAC2L", NULL, "AIF1DACDAT" },
1115 { "AIF1DAC2R", NULL, "AIF1DACDAT" },
1116
1117 /* DAC1 inputs */
1118 { "DAC1L", NULL, "DAC1L Mixer" },
1119 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1120 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1121 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1122 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1123
1124 { "DAC1R", NULL, "DAC1R Mixer" },
1125 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1126 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1127 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1128 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1129
1130 /* DAC2/AIF2 outputs */
1131 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1132 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1133 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1134
1135 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1136 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1137 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1138
1139 /* Output stages */
1140 { "Headphone PGA", NULL, "DAC1L" },
1141 { "Headphone PGA", NULL, "DAC1R" },
1142
1143 { "Headphone PGA", NULL, "DAC2L" },
1144 { "Headphone PGA", NULL, "DAC2R" },
1145
1146 { "Headphone PGA", NULL, "Headphone Supply" },
1147 { "Headphone PGA", NULL, "CLK_SYS" },
1148 { "Headphone PGA", NULL, "LDO2" },
1149
1150 { "HP1L", NULL, "Headphone PGA" },
1151 { "HP1R", NULL, "Headphone PGA" },
1152
1153 { "SPK1L Driver", "DAC1L", "DAC1L" },
1154 { "SPK1L Driver", "DAC1R", "DAC1R" },
1155 { "SPK1L Driver", "DAC2L", "DAC2L" },
1156 { "SPK1L Driver", "DAC2R", "DAC2R" },
1157 { "SPK1L Driver", NULL, "CLK_SYS" },
1158
1159 { "SPK1R Driver", "DAC1L", "DAC1L" },
1160 { "SPK1R Driver", "DAC1R", "DAC1R" },
1161 { "SPK1R Driver", "DAC2L", "DAC2L" },
1162 { "SPK1R Driver", "DAC2R", "DAC2R" },
1163 { "SPK1R Driver", NULL, "CLK_SYS" },
1164
1165 { "SPK2L Driver", "DAC1L", "DAC1L" },
1166 { "SPK2L Driver", "DAC1R", "DAC1R" },
1167 { "SPK2L Driver", "DAC2L", "DAC2L" },
1168 { "SPK2L Driver", "DAC2R", "DAC2R" },
1169 { "SPK2L Driver", NULL, "CLK_SYS" },
1170
1171 { "SPK2R Driver", "DAC1L", "DAC1L" },
1172 { "SPK2R Driver", "DAC1R", "DAC1R" },
1173 { "SPK2R Driver", "DAC2L", "DAC2L" },
1174 { "SPK2R Driver", "DAC2R", "DAC2R" },
1175 { "SPK2R Driver", NULL, "CLK_SYS" },
1176
1177 { "SPK1L", NULL, "SPK1L Driver" },
1178 { "SPK1R", NULL, "SPK1R Driver" },
1179 { "SPK2L", NULL, "SPK2L Driver" },
1180 { "SPK2R", NULL, "SPK2R Driver" }
1181 };
1182
1183 static bool wm8995_readable(struct device *dev, unsigned int reg)
1184 {
1185 switch (reg) {
1186 case WM8995_SOFTWARE_RESET:
1187 case WM8995_POWER_MANAGEMENT_1:
1188 case WM8995_POWER_MANAGEMENT_2:
1189 case WM8995_POWER_MANAGEMENT_3:
1190 case WM8995_POWER_MANAGEMENT_4:
1191 case WM8995_POWER_MANAGEMENT_5:
1192 case WM8995_LEFT_LINE_INPUT_1_VOLUME:
1193 case WM8995_RIGHT_LINE_INPUT_1_VOLUME:
1194 case WM8995_LEFT_LINE_INPUT_CONTROL:
1195 case WM8995_DAC1_LEFT_VOLUME:
1196 case WM8995_DAC1_RIGHT_VOLUME:
1197 case WM8995_DAC2_LEFT_VOLUME:
1198 case WM8995_DAC2_RIGHT_VOLUME:
1199 case WM8995_OUTPUT_VOLUME_ZC_1:
1200 case WM8995_MICBIAS_1:
1201 case WM8995_MICBIAS_2:
1202 case WM8995_LDO_1:
1203 case WM8995_LDO_2:
1204 case WM8995_ACCESSORY_DETECT_MODE1:
1205 case WM8995_ACCESSORY_DETECT_MODE2:
1206 case WM8995_HEADPHONE_DETECT1:
1207 case WM8995_HEADPHONE_DETECT2:
1208 case WM8995_MIC_DETECT_1:
1209 case WM8995_MIC_DETECT_2:
1210 case WM8995_CHARGE_PUMP_1:
1211 case WM8995_CLASS_W_1:
1212 case WM8995_DC_SERVO_1:
1213 case WM8995_DC_SERVO_2:
1214 case WM8995_DC_SERVO_3:
1215 case WM8995_DC_SERVO_5:
1216 case WM8995_DC_SERVO_6:
1217 case WM8995_DC_SERVO_7:
1218 case WM8995_DC_SERVO_READBACK_0:
1219 case WM8995_ANALOGUE_HP_1:
1220 case WM8995_ANALOGUE_HP_2:
1221 case WM8995_CHIP_REVISION:
1222 case WM8995_CONTROL_INTERFACE_1:
1223 case WM8995_CONTROL_INTERFACE_2:
1224 case WM8995_WRITE_SEQUENCER_CTRL_1:
1225 case WM8995_WRITE_SEQUENCER_CTRL_2:
1226 case WM8995_AIF1_CLOCKING_1:
1227 case WM8995_AIF1_CLOCKING_2:
1228 case WM8995_AIF2_CLOCKING_1:
1229 case WM8995_AIF2_CLOCKING_2:
1230 case WM8995_CLOCKING_1:
1231 case WM8995_CLOCKING_2:
1232 case WM8995_AIF1_RATE:
1233 case WM8995_AIF2_RATE:
1234 case WM8995_RATE_STATUS:
1235 case WM8995_FLL1_CONTROL_1:
1236 case WM8995_FLL1_CONTROL_2:
1237 case WM8995_FLL1_CONTROL_3:
1238 case WM8995_FLL1_CONTROL_4:
1239 case WM8995_FLL1_CONTROL_5:
1240 case WM8995_FLL2_CONTROL_1:
1241 case WM8995_FLL2_CONTROL_2:
1242 case WM8995_FLL2_CONTROL_3:
1243 case WM8995_FLL2_CONTROL_4:
1244 case WM8995_FLL2_CONTROL_5:
1245 case WM8995_AIF1_CONTROL_1:
1246 case WM8995_AIF1_CONTROL_2:
1247 case WM8995_AIF1_MASTER_SLAVE:
1248 case WM8995_AIF1_BCLK:
1249 case WM8995_AIF1ADC_LRCLK:
1250 case WM8995_AIF1DAC_LRCLK:
1251 case WM8995_AIF1DAC_DATA:
1252 case WM8995_AIF1ADC_DATA:
1253 case WM8995_AIF2_CONTROL_1:
1254 case WM8995_AIF2_CONTROL_2:
1255 case WM8995_AIF2_MASTER_SLAVE:
1256 case WM8995_AIF2_BCLK:
1257 case WM8995_AIF2ADC_LRCLK:
1258 case WM8995_AIF2DAC_LRCLK:
1259 case WM8995_AIF2DAC_DATA:
1260 case WM8995_AIF2ADC_DATA:
1261 case WM8995_AIF1_ADC1_LEFT_VOLUME:
1262 case WM8995_AIF1_ADC1_RIGHT_VOLUME:
1263 case WM8995_AIF1_DAC1_LEFT_VOLUME:
1264 case WM8995_AIF1_DAC1_RIGHT_VOLUME:
1265 case WM8995_AIF1_ADC2_LEFT_VOLUME:
1266 case WM8995_AIF1_ADC2_RIGHT_VOLUME:
1267 case WM8995_AIF1_DAC2_LEFT_VOLUME:
1268 case WM8995_AIF1_DAC2_RIGHT_VOLUME:
1269 case WM8995_AIF1_ADC1_FILTERS:
1270 case WM8995_AIF1_ADC2_FILTERS:
1271 case WM8995_AIF1_DAC1_FILTERS_1:
1272 case WM8995_AIF1_DAC1_FILTERS_2:
1273 case WM8995_AIF1_DAC2_FILTERS_1:
1274 case WM8995_AIF1_DAC2_FILTERS_2:
1275 case WM8995_AIF1_DRC1_1:
1276 case WM8995_AIF1_DRC1_2:
1277 case WM8995_AIF1_DRC1_3:
1278 case WM8995_AIF1_DRC1_4:
1279 case WM8995_AIF1_DRC1_5:
1280 case WM8995_AIF1_DRC2_1:
1281 case WM8995_AIF1_DRC2_2:
1282 case WM8995_AIF1_DRC2_3:
1283 case WM8995_AIF1_DRC2_4:
1284 case WM8995_AIF1_DRC2_5:
1285 case WM8995_AIF1_DAC1_EQ_GAINS_1:
1286 case WM8995_AIF1_DAC1_EQ_GAINS_2:
1287 case WM8995_AIF1_DAC1_EQ_BAND_1_A:
1288 case WM8995_AIF1_DAC1_EQ_BAND_1_B:
1289 case WM8995_AIF1_DAC1_EQ_BAND_1_PG:
1290 case WM8995_AIF1_DAC1_EQ_BAND_2_A:
1291 case WM8995_AIF1_DAC1_EQ_BAND_2_B:
1292 case WM8995_AIF1_DAC1_EQ_BAND_2_C:
1293 case WM8995_AIF1_DAC1_EQ_BAND_2_PG:
1294 case WM8995_AIF1_DAC1_EQ_BAND_3_A:
1295 case WM8995_AIF1_DAC1_EQ_BAND_3_B:
1296 case WM8995_AIF1_DAC1_EQ_BAND_3_C:
1297 case WM8995_AIF1_DAC1_EQ_BAND_3_PG:
1298 case WM8995_AIF1_DAC1_EQ_BAND_4_A:
1299 case WM8995_AIF1_DAC1_EQ_BAND_4_B:
1300 case WM8995_AIF1_DAC1_EQ_BAND_4_C:
1301 case WM8995_AIF1_DAC1_EQ_BAND_4_PG:
1302 case WM8995_AIF1_DAC1_EQ_BAND_5_A:
1303 case WM8995_AIF1_DAC1_EQ_BAND_5_B:
1304 case WM8995_AIF1_DAC1_EQ_BAND_5_PG:
1305 case WM8995_AIF1_DAC2_EQ_GAINS_1:
1306 case WM8995_AIF1_DAC2_EQ_GAINS_2:
1307 case WM8995_AIF1_DAC2_EQ_BAND_1_A:
1308 case WM8995_AIF1_DAC2_EQ_BAND_1_B:
1309 case WM8995_AIF1_DAC2_EQ_BAND_1_PG:
1310 case WM8995_AIF1_DAC2_EQ_BAND_2_A:
1311 case WM8995_AIF1_DAC2_EQ_BAND_2_B:
1312 case WM8995_AIF1_DAC2_EQ_BAND_2_C:
1313 case WM8995_AIF1_DAC2_EQ_BAND_2_PG:
1314 case WM8995_AIF1_DAC2_EQ_BAND_3_A:
1315 case WM8995_AIF1_DAC2_EQ_BAND_3_B:
1316 case WM8995_AIF1_DAC2_EQ_BAND_3_C:
1317 case WM8995_AIF1_DAC2_EQ_BAND_3_PG:
1318 case WM8995_AIF1_DAC2_EQ_BAND_4_A:
1319 case WM8995_AIF1_DAC2_EQ_BAND_4_B:
1320 case WM8995_AIF1_DAC2_EQ_BAND_4_C:
1321 case WM8995_AIF1_DAC2_EQ_BAND_4_PG:
1322 case WM8995_AIF1_DAC2_EQ_BAND_5_A:
1323 case WM8995_AIF1_DAC2_EQ_BAND_5_B:
1324 case WM8995_AIF1_DAC2_EQ_BAND_5_PG:
1325 case WM8995_AIF2_ADC_LEFT_VOLUME:
1326 case WM8995_AIF2_ADC_RIGHT_VOLUME:
1327 case WM8995_AIF2_DAC_LEFT_VOLUME:
1328 case WM8995_AIF2_DAC_RIGHT_VOLUME:
1329 case WM8995_AIF2_ADC_FILTERS:
1330 case WM8995_AIF2_DAC_FILTERS_1:
1331 case WM8995_AIF2_DAC_FILTERS_2:
1332 case WM8995_AIF2_DRC_1:
1333 case WM8995_AIF2_DRC_2:
1334 case WM8995_AIF2_DRC_3:
1335 case WM8995_AIF2_DRC_4:
1336 case WM8995_AIF2_DRC_5:
1337 case WM8995_AIF2_EQ_GAINS_1:
1338 case WM8995_AIF2_EQ_GAINS_2:
1339 case WM8995_AIF2_EQ_BAND_1_A:
1340 case WM8995_AIF2_EQ_BAND_1_B:
1341 case WM8995_AIF2_EQ_BAND_1_PG:
1342 case WM8995_AIF2_EQ_BAND_2_A:
1343 case WM8995_AIF2_EQ_BAND_2_B:
1344 case WM8995_AIF2_EQ_BAND_2_C:
1345 case WM8995_AIF2_EQ_BAND_2_PG:
1346 case WM8995_AIF2_EQ_BAND_3_A:
1347 case WM8995_AIF2_EQ_BAND_3_B:
1348 case WM8995_AIF2_EQ_BAND_3_C:
1349 case WM8995_AIF2_EQ_BAND_3_PG:
1350 case WM8995_AIF2_EQ_BAND_4_A:
1351 case WM8995_AIF2_EQ_BAND_4_B:
1352 case WM8995_AIF2_EQ_BAND_4_C:
1353 case WM8995_AIF2_EQ_BAND_4_PG:
1354 case WM8995_AIF2_EQ_BAND_5_A:
1355 case WM8995_AIF2_EQ_BAND_5_B:
1356 case WM8995_AIF2_EQ_BAND_5_PG:
1357 case WM8995_DAC1_MIXER_VOLUMES:
1358 case WM8995_DAC1_LEFT_MIXER_ROUTING:
1359 case WM8995_DAC1_RIGHT_MIXER_ROUTING:
1360 case WM8995_DAC2_MIXER_VOLUMES:
1361 case WM8995_DAC2_LEFT_MIXER_ROUTING:
1362 case WM8995_DAC2_RIGHT_MIXER_ROUTING:
1363 case WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING:
1364 case WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING:
1365 case WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING:
1366 case WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING:
1367 case WM8995_DAC_SOFTMUTE:
1368 case WM8995_OVERSAMPLING:
1369 case WM8995_SIDETONE:
1370 case WM8995_GPIO_1:
1371 case WM8995_GPIO_2:
1372 case WM8995_GPIO_3:
1373 case WM8995_GPIO_4:
1374 case WM8995_GPIO_5:
1375 case WM8995_GPIO_6:
1376 case WM8995_GPIO_7:
1377 case WM8995_GPIO_8:
1378 case WM8995_GPIO_9:
1379 case WM8995_GPIO_10:
1380 case WM8995_GPIO_11:
1381 case WM8995_GPIO_12:
1382 case WM8995_GPIO_13:
1383 case WM8995_GPIO_14:
1384 case WM8995_PULL_CONTROL_1:
1385 case WM8995_PULL_CONTROL_2:
1386 case WM8995_INTERRUPT_STATUS_1:
1387 case WM8995_INTERRUPT_STATUS_2:
1388 case WM8995_INTERRUPT_RAW_STATUS_2:
1389 case WM8995_INTERRUPT_STATUS_1_MASK:
1390 case WM8995_INTERRUPT_STATUS_2_MASK:
1391 case WM8995_INTERRUPT_CONTROL:
1392 case WM8995_LEFT_PDM_SPEAKER_1:
1393 case WM8995_RIGHT_PDM_SPEAKER_1:
1394 case WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE:
1395 case WM8995_LEFT_PDM_SPEAKER_2:
1396 case WM8995_RIGHT_PDM_SPEAKER_2:
1397 case WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE:
1398 return true;
1399 default:
1400 return false;
1401 }
1402 }
1403
1404 static bool wm8995_volatile(struct device *dev, unsigned int reg)
1405 {
1406 switch (reg) {
1407 case WM8995_SOFTWARE_RESET:
1408 case WM8995_DC_SERVO_READBACK_0:
1409 case WM8995_INTERRUPT_STATUS_1:
1410 case WM8995_INTERRUPT_STATUS_2:
1411 case WM8995_INTERRUPT_CONTROL:
1412 case WM8995_ACCESSORY_DETECT_MODE1:
1413 case WM8995_ACCESSORY_DETECT_MODE2:
1414 case WM8995_HEADPHONE_DETECT1:
1415 case WM8995_HEADPHONE_DETECT2:
1416 case WM8995_RATE_STATUS:
1417 return true;
1418 default:
1419 return false;
1420 }
1421 }
1422
1423 static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute)
1424 {
1425 struct snd_soc_codec *codec = dai->codec;
1426 int mute_reg;
1427
1428 switch (dai->id) {
1429 case 0:
1430 mute_reg = WM8995_AIF1_DAC1_FILTERS_1;
1431 break;
1432 case 1:
1433 mute_reg = WM8995_AIF2_DAC_FILTERS_1;
1434 break;
1435 default:
1436 return -EINVAL;
1437 }
1438
1439 snd_soc_update_bits(codec, mute_reg, WM8995_AIF1DAC1_MUTE_MASK,
1440 !!mute << WM8995_AIF1DAC1_MUTE_SHIFT);
1441 return 0;
1442 }
1443
1444 static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1445 {
1446 struct snd_soc_codec *codec;
1447 int master;
1448 int aif;
1449
1450 codec = dai->codec;
1451
1452 master = 0;
1453 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1454 case SND_SOC_DAIFMT_CBS_CFS:
1455 break;
1456 case SND_SOC_DAIFMT_CBM_CFM:
1457 master = WM8995_AIF1_MSTR;
1458 break;
1459 default:
1460 dev_err(dai->dev, "Unknown master/slave configuration\n");
1461 return -EINVAL;
1462 }
1463
1464 aif = 0;
1465 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1466 case SND_SOC_DAIFMT_DSP_B:
1467 aif |= WM8995_AIF1_LRCLK_INV;
1468 case SND_SOC_DAIFMT_DSP_A:
1469 aif |= (0x3 << WM8995_AIF1_FMT_SHIFT);
1470 break;
1471 case SND_SOC_DAIFMT_I2S:
1472 aif |= (0x2 << WM8995_AIF1_FMT_SHIFT);
1473 break;
1474 case SND_SOC_DAIFMT_RIGHT_J:
1475 break;
1476 case SND_SOC_DAIFMT_LEFT_J:
1477 aif |= (0x1 << WM8995_AIF1_FMT_SHIFT);
1478 break;
1479 default:
1480 dev_err(dai->dev, "Unknown dai format\n");
1481 return -EINVAL;
1482 }
1483
1484 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1485 case SND_SOC_DAIFMT_DSP_A:
1486 case SND_SOC_DAIFMT_DSP_B:
1487 /* frame inversion not valid for DSP modes */
1488 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1489 case SND_SOC_DAIFMT_NB_NF:
1490 break;
1491 case SND_SOC_DAIFMT_IB_NF:
1492 aif |= WM8995_AIF1_BCLK_INV;
1493 break;
1494 default:
1495 return -EINVAL;
1496 }
1497 break;
1498
1499 case SND_SOC_DAIFMT_I2S:
1500 case SND_SOC_DAIFMT_RIGHT_J:
1501 case SND_SOC_DAIFMT_LEFT_J:
1502 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1503 case SND_SOC_DAIFMT_NB_NF:
1504 break;
1505 case SND_SOC_DAIFMT_IB_IF:
1506 aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV;
1507 break;
1508 case SND_SOC_DAIFMT_IB_NF:
1509 aif |= WM8995_AIF1_BCLK_INV;
1510 break;
1511 case SND_SOC_DAIFMT_NB_IF:
1512 aif |= WM8995_AIF1_LRCLK_INV;
1513 break;
1514 default:
1515 return -EINVAL;
1516 }
1517 break;
1518 default:
1519 return -EINVAL;
1520 }
1521
1522 snd_soc_update_bits(codec, WM8995_AIF1_CONTROL_1,
1523 WM8995_AIF1_BCLK_INV_MASK |
1524 WM8995_AIF1_LRCLK_INV_MASK |
1525 WM8995_AIF1_FMT_MASK, aif);
1526 snd_soc_update_bits(codec, WM8995_AIF1_MASTER_SLAVE,
1527 WM8995_AIF1_MSTR_MASK, master);
1528 return 0;
1529 }
1530
1531 static const int srs[] = {
1532 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100,
1533 48000, 88200, 96000
1534 };
1535
1536 static const int fs_ratios[] = {
1537 -1 /* reserved */,
1538 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
1539 };
1540
1541 static const int bclk_divs[] = {
1542 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480
1543 };
1544
1545 static int wm8995_hw_params(struct snd_pcm_substream *substream,
1546 struct snd_pcm_hw_params *params,
1547 struct snd_soc_dai *dai)
1548 {
1549 struct snd_soc_codec *codec;
1550 struct wm8995_priv *wm8995;
1551 int aif1_reg;
1552 int bclk_reg;
1553 int lrclk_reg;
1554 int rate_reg;
1555 int bclk_rate;
1556 int aif1;
1557 int lrclk, bclk;
1558 int i, rate_val, best, best_val, cur_val;
1559
1560 codec = dai->codec;
1561 wm8995 = snd_soc_codec_get_drvdata(codec);
1562
1563 switch (dai->id) {
1564 case 0:
1565 aif1_reg = WM8995_AIF1_CONTROL_1;
1566 bclk_reg = WM8995_AIF1_BCLK;
1567 rate_reg = WM8995_AIF1_RATE;
1568 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
1569 wm8995->lrclk_shared[0] */) {
1570 lrclk_reg = WM8995_AIF1DAC_LRCLK;
1571 } else {
1572 lrclk_reg = WM8995_AIF1ADC_LRCLK;
1573 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
1574 }
1575 break;
1576 case 1:
1577 aif1_reg = WM8995_AIF2_CONTROL_1;
1578 bclk_reg = WM8995_AIF2_BCLK;
1579 rate_reg = WM8995_AIF2_RATE;
1580 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
1581 wm8995->lrclk_shared[1] */) {
1582 lrclk_reg = WM8995_AIF2DAC_LRCLK;
1583 } else {
1584 lrclk_reg = WM8995_AIF2ADC_LRCLK;
1585 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
1586 }
1587 break;
1588 default:
1589 return -EINVAL;
1590 }
1591
1592 bclk_rate = snd_soc_params_to_bclk(params);
1593 if (bclk_rate < 0)
1594 return bclk_rate;
1595
1596 aif1 = 0;
1597 switch (params_width(params)) {
1598 case 16:
1599 break;
1600 case 20:
1601 aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT);
1602 break;
1603 case 24:
1604 aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT);
1605 break;
1606 case 32:
1607 aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT);
1608 break;
1609 default:
1610 dev_err(dai->dev, "Unsupported word length %u\n",
1611 params_width(params));
1612 return -EINVAL;
1613 }
1614
1615 /* try to find a suitable sample rate */
1616 for (i = 0; i < ARRAY_SIZE(srs); ++i)
1617 if (srs[i] == params_rate(params))
1618 break;
1619 if (i == ARRAY_SIZE(srs)) {
1620 dev_err(dai->dev, "Sample rate %d is not supported\n",
1621 params_rate(params));
1622 return -EINVAL;
1623 }
1624 rate_val = i << WM8995_AIF1_SR_SHIFT;
1625
1626 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]);
1627 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
1628 dai->id + 1, wm8995->aifclk[dai->id], bclk_rate);
1629
1630 /* AIFCLK/fs ratio; look for a close match in either direction */
1631 best = 1;
1632 best_val = abs((fs_ratios[1] * params_rate(params))
1633 - wm8995->aifclk[dai->id]);
1634 for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) {
1635 cur_val = abs((fs_ratios[i] * params_rate(params))
1636 - wm8995->aifclk[dai->id]);
1637 if (cur_val >= best_val)
1638 continue;
1639 best = i;
1640 best_val = cur_val;
1641 }
1642 rate_val |= best;
1643
1644 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
1645 dai->id + 1, fs_ratios[best]);
1646
1647 /*
1648 * We may not get quite the right frequency if using
1649 * approximate clocks so look for the closest match that is
1650 * higher than the target (we need to ensure that there enough
1651 * BCLKs to clock out the samples).
1652 */
1653 best = 0;
1654 bclk = 0;
1655 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1656 cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate;
1657 if (cur_val < 0) /* BCLK table is sorted */
1658 break;
1659 best = i;
1660 }
1661 bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT;
1662
1663 bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best];
1664 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1665 bclk_divs[best], bclk_rate);
1666
1667 lrclk = bclk_rate / params_rate(params);
1668 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1669 lrclk, bclk_rate / lrclk);
1670
1671 snd_soc_update_bits(codec, aif1_reg,
1672 WM8995_AIF1_WL_MASK, aif1);
1673 snd_soc_update_bits(codec, bclk_reg,
1674 WM8995_AIF1_BCLK_DIV_MASK, bclk);
1675 snd_soc_update_bits(codec, lrclk_reg,
1676 WM8995_AIF1DAC_RATE_MASK, lrclk);
1677 snd_soc_update_bits(codec, rate_reg,
1678 WM8995_AIF1_SR_MASK |
1679 WM8995_AIF1CLK_RATE_MASK, rate_val);
1680 return 0;
1681 }
1682
1683 static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
1684 {
1685 struct snd_soc_codec *codec = codec_dai->codec;
1686 int reg, val, mask;
1687
1688 switch (codec_dai->id) {
1689 case 0:
1690 reg = WM8995_AIF1_MASTER_SLAVE;
1691 mask = WM8995_AIF1_TRI;
1692 break;
1693 case 1:
1694 reg = WM8995_AIF2_MASTER_SLAVE;
1695 mask = WM8995_AIF2_TRI;
1696 break;
1697 case 2:
1698 reg = WM8995_POWER_MANAGEMENT_5;
1699 mask = WM8995_AIF3_TRI;
1700 break;
1701 default:
1702 return -EINVAL;
1703 }
1704
1705 if (tristate)
1706 val = mask;
1707 else
1708 val = 0;
1709
1710 return snd_soc_update_bits(codec, reg, mask, val);
1711 }
1712
1713 /* The size in bits of the FLL divide multiplied by 10
1714 * to allow rounding later */
1715 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1716
1717 struct fll_div {
1718 u16 outdiv;
1719 u16 n;
1720 u16 k;
1721 u16 clk_ref_div;
1722 u16 fll_fratio;
1723 };
1724
1725 static int wm8995_get_fll_config(struct fll_div *fll,
1726 int freq_in, int freq_out)
1727 {
1728 u64 Kpart;
1729 unsigned int K, Ndiv, Nmod;
1730
1731 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1732
1733 /* Scale the input frequency down to <= 13.5MHz */
1734 fll->clk_ref_div = 0;
1735 while (freq_in > 13500000) {
1736 fll->clk_ref_div++;
1737 freq_in /= 2;
1738
1739 if (fll->clk_ref_div > 3)
1740 return -EINVAL;
1741 }
1742 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1743
1744 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1745 fll->outdiv = 3;
1746 while (freq_out * (fll->outdiv + 1) < 90000000) {
1747 fll->outdiv++;
1748 if (fll->outdiv > 63)
1749 return -EINVAL;
1750 }
1751 freq_out *= fll->outdiv + 1;
1752 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1753
1754 if (freq_in > 1000000) {
1755 fll->fll_fratio = 0;
1756 } else if (freq_in > 256000) {
1757 fll->fll_fratio = 1;
1758 freq_in *= 2;
1759 } else if (freq_in > 128000) {
1760 fll->fll_fratio = 2;
1761 freq_in *= 4;
1762 } else if (freq_in > 64000) {
1763 fll->fll_fratio = 3;
1764 freq_in *= 8;
1765 } else {
1766 fll->fll_fratio = 4;
1767 freq_in *= 16;
1768 }
1769 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1770
1771 /* Now, calculate N.K */
1772 Ndiv = freq_out / freq_in;
1773
1774 fll->n = Ndiv;
1775 Nmod = freq_out % freq_in;
1776 pr_debug("Nmod=%d\n", Nmod);
1777
1778 /* Calculate fractional part - scale up so we can round. */
1779 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1780
1781 do_div(Kpart, freq_in);
1782
1783 K = Kpart & 0xFFFFFFFF;
1784
1785 if ((K % 10) >= 5)
1786 K += 5;
1787
1788 /* Move down to proper range now rounding is done */
1789 fll->k = K / 10;
1790
1791 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1792
1793 return 0;
1794 }
1795
1796 static int wm8995_set_fll(struct snd_soc_dai *dai, int id,
1797 int src, unsigned int freq_in,
1798 unsigned int freq_out)
1799 {
1800 struct snd_soc_codec *codec;
1801 struct wm8995_priv *wm8995;
1802 int reg_offset, ret;
1803 struct fll_div fll;
1804 u16 reg, aif1, aif2;
1805
1806 codec = dai->codec;
1807 wm8995 = snd_soc_codec_get_drvdata(codec);
1808
1809 aif1 = snd_soc_read(codec, WM8995_AIF1_CLOCKING_1)
1810 & WM8995_AIF1CLK_ENA;
1811
1812 aif2 = snd_soc_read(codec, WM8995_AIF2_CLOCKING_1)
1813 & WM8995_AIF2CLK_ENA;
1814
1815 switch (id) {
1816 case WM8995_FLL1:
1817 reg_offset = 0;
1818 id = 0;
1819 break;
1820 case WM8995_FLL2:
1821 reg_offset = 0x20;
1822 id = 1;
1823 break;
1824 default:
1825 return -EINVAL;
1826 }
1827
1828 switch (src) {
1829 case 0:
1830 /* Allow no source specification when stopping */
1831 if (freq_out)
1832 return -EINVAL;
1833 break;
1834 case WM8995_FLL_SRC_MCLK1:
1835 case WM8995_FLL_SRC_MCLK2:
1836 case WM8995_FLL_SRC_LRCLK:
1837 case WM8995_FLL_SRC_BCLK:
1838 break;
1839 default:
1840 return -EINVAL;
1841 }
1842
1843 /* Are we changing anything? */
1844 if (wm8995->fll[id].src == src &&
1845 wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out)
1846 return 0;
1847
1848 /* If we're stopping the FLL redo the old config - no
1849 * registers will actually be written but we avoid GCC flow
1850 * analysis bugs spewing warnings.
1851 */
1852 if (freq_out)
1853 ret = wm8995_get_fll_config(&fll, freq_in, freq_out);
1854 else
1855 ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in,
1856 wm8995->fll[id].out);
1857 if (ret < 0)
1858 return ret;
1859
1860 /* Gate the AIF clocks while we reclock */
1861 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1,
1862 WM8995_AIF1CLK_ENA_MASK, 0);
1863 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1,
1864 WM8995_AIF2CLK_ENA_MASK, 0);
1865
1866 /* We always need to disable the FLL while reconfiguring */
1867 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset,
1868 WM8995_FLL1_ENA_MASK, 0);
1869
1870 reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) |
1871 (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT);
1872 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset,
1873 WM8995_FLL1_OUTDIV_MASK |
1874 WM8995_FLL1_FRATIO_MASK, reg);
1875
1876 snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k);
1877
1878 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset,
1879 WM8995_FLL1_N_MASK,
1880 fll.n << WM8995_FLL1_N_SHIFT);
1881
1882 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset,
1883 WM8995_FLL1_REFCLK_DIV_MASK |
1884 WM8995_FLL1_REFCLK_SRC_MASK,
1885 (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) |
1886 (src - 1));
1887
1888 if (freq_out)
1889 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset,
1890 WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA);
1891
1892 wm8995->fll[id].in = freq_in;
1893 wm8995->fll[id].out = freq_out;
1894 wm8995->fll[id].src = src;
1895
1896 /* Enable any gated AIF clocks */
1897 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1,
1898 WM8995_AIF1CLK_ENA_MASK, aif1);
1899 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1,
1900 WM8995_AIF2CLK_ENA_MASK, aif2);
1901
1902 configure_clock(codec);
1903
1904 return 0;
1905 }
1906
1907 static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai,
1908 int clk_id, unsigned int freq, int dir)
1909 {
1910 struct snd_soc_codec *codec;
1911 struct wm8995_priv *wm8995;
1912
1913 codec = dai->codec;
1914 wm8995 = snd_soc_codec_get_drvdata(codec);
1915
1916 switch (dai->id) {
1917 case 0:
1918 case 1:
1919 break;
1920 default:
1921 /* AIF3 shares clocking with AIF1/2 */
1922 return -EINVAL;
1923 }
1924
1925 switch (clk_id) {
1926 case WM8995_SYSCLK_MCLK1:
1927 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
1928 wm8995->mclk[0] = freq;
1929 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1930 dai->id + 1, freq);
1931 break;
1932 case WM8995_SYSCLK_MCLK2:
1933 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK2;
1934 wm8995->mclk[1] = freq;
1935 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1936 dai->id + 1, freq);
1937 break;
1938 case WM8995_SYSCLK_FLL1:
1939 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1;
1940 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1);
1941 break;
1942 case WM8995_SYSCLK_FLL2:
1943 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2;
1944 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1);
1945 break;
1946 case WM8995_SYSCLK_OPCLK:
1947 default:
1948 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
1949 return -EINVAL;
1950 }
1951
1952 configure_clock(codec);
1953
1954 return 0;
1955 }
1956
1957 static int wm8995_set_bias_level(struct snd_soc_codec *codec,
1958 enum snd_soc_bias_level level)
1959 {
1960 struct wm8995_priv *wm8995;
1961 int ret;
1962
1963 wm8995 = snd_soc_codec_get_drvdata(codec);
1964 switch (level) {
1965 case SND_SOC_BIAS_ON:
1966 case SND_SOC_BIAS_PREPARE:
1967 break;
1968 case SND_SOC_BIAS_STANDBY:
1969 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1970 ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies),
1971 wm8995->supplies);
1972 if (ret)
1973 return ret;
1974
1975 ret = regcache_sync(wm8995->regmap);
1976 if (ret) {
1977 dev_err(codec->dev,
1978 "Failed to sync cache: %d\n", ret);
1979 return ret;
1980 }
1981
1982 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
1983 WM8995_BG_ENA_MASK, WM8995_BG_ENA);
1984 }
1985 break;
1986 case SND_SOC_BIAS_OFF:
1987 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
1988 WM8995_BG_ENA_MASK, 0);
1989 regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies),
1990 wm8995->supplies);
1991 break;
1992 }
1993
1994 return 0;
1995 }
1996
1997 static int wm8995_remove(struct snd_soc_codec *codec)
1998 {
1999 struct wm8995_priv *wm8995;
2000 int i;
2001
2002 wm8995 = snd_soc_codec_get_drvdata(codec);
2003
2004 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); ++i)
2005 regulator_unregister_notifier(wm8995->supplies[i].consumer,
2006 &wm8995->disable_nb[i]);
2007
2008 regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies);
2009 return 0;
2010 }
2011
2012 static int wm8995_probe(struct snd_soc_codec *codec)
2013 {
2014 struct wm8995_priv *wm8995;
2015 int i;
2016 int ret;
2017
2018 wm8995 = snd_soc_codec_get_drvdata(codec);
2019 wm8995->codec = codec;
2020
2021 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++)
2022 wm8995->supplies[i].supply = wm8995_supply_names[i];
2023
2024 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8995->supplies),
2025 wm8995->supplies);
2026 if (ret) {
2027 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2028 return ret;
2029 }
2030
2031 wm8995->disable_nb[0].notifier_call = wm8995_regulator_event_0;
2032 wm8995->disable_nb[1].notifier_call = wm8995_regulator_event_1;
2033 wm8995->disable_nb[2].notifier_call = wm8995_regulator_event_2;
2034 wm8995->disable_nb[3].notifier_call = wm8995_regulator_event_3;
2035 wm8995->disable_nb[4].notifier_call = wm8995_regulator_event_4;
2036 wm8995->disable_nb[5].notifier_call = wm8995_regulator_event_5;
2037 wm8995->disable_nb[6].notifier_call = wm8995_regulator_event_6;
2038 wm8995->disable_nb[7].notifier_call = wm8995_regulator_event_7;
2039
2040 /* This should really be moved into the regulator core */
2041 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) {
2042 ret = regulator_register_notifier(wm8995->supplies[i].consumer,
2043 &wm8995->disable_nb[i]);
2044 if (ret) {
2045 dev_err(codec->dev,
2046 "Failed to register regulator notifier: %d\n",
2047 ret);
2048 }
2049 }
2050
2051 ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies),
2052 wm8995->supplies);
2053 if (ret) {
2054 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2055 goto err_reg_get;
2056 }
2057
2058 ret = snd_soc_read(codec, WM8995_SOFTWARE_RESET);
2059 if (ret < 0) {
2060 dev_err(codec->dev, "Failed to read device ID: %d\n", ret);
2061 goto err_reg_enable;
2062 }
2063
2064 if (ret != 0x8995) {
2065 dev_err(codec->dev, "Invalid device ID: %#x\n", ret);
2066 ret = -EINVAL;
2067 goto err_reg_enable;
2068 }
2069
2070 ret = snd_soc_write(codec, WM8995_SOFTWARE_RESET, 0);
2071 if (ret < 0) {
2072 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
2073 goto err_reg_enable;
2074 }
2075
2076 /* Latch volume updates (right only; we always do left then right). */
2077 snd_soc_update_bits(codec, WM8995_AIF1_DAC1_RIGHT_VOLUME,
2078 WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU);
2079 snd_soc_update_bits(codec, WM8995_AIF1_DAC2_RIGHT_VOLUME,
2080 WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU);
2081 snd_soc_update_bits(codec, WM8995_AIF2_DAC_RIGHT_VOLUME,
2082 WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU);
2083 snd_soc_update_bits(codec, WM8995_AIF1_ADC1_RIGHT_VOLUME,
2084 WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU);
2085 snd_soc_update_bits(codec, WM8995_AIF1_ADC2_RIGHT_VOLUME,
2086 WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU);
2087 snd_soc_update_bits(codec, WM8995_AIF2_ADC_RIGHT_VOLUME,
2088 WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU);
2089 snd_soc_update_bits(codec, WM8995_DAC1_RIGHT_VOLUME,
2090 WM8995_DAC1_VU_MASK, WM8995_DAC1_VU);
2091 snd_soc_update_bits(codec, WM8995_DAC2_RIGHT_VOLUME,
2092 WM8995_DAC2_VU_MASK, WM8995_DAC2_VU);
2093 snd_soc_update_bits(codec, WM8995_RIGHT_LINE_INPUT_1_VOLUME,
2094 WM8995_IN1_VU_MASK, WM8995_IN1_VU);
2095
2096 wm8995_update_class_w(codec);
2097
2098 return 0;
2099
2100 err_reg_enable:
2101 regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), wm8995->supplies);
2102 err_reg_get:
2103 regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies);
2104 return ret;
2105 }
2106
2107 #define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2108 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2109
2110 static const struct snd_soc_dai_ops wm8995_aif1_dai_ops = {
2111 .set_sysclk = wm8995_set_dai_sysclk,
2112 .set_fmt = wm8995_set_dai_fmt,
2113 .hw_params = wm8995_hw_params,
2114 .digital_mute = wm8995_aif_mute,
2115 .set_pll = wm8995_set_fll,
2116 .set_tristate = wm8995_set_tristate,
2117 };
2118
2119 static const struct snd_soc_dai_ops wm8995_aif2_dai_ops = {
2120 .set_sysclk = wm8995_set_dai_sysclk,
2121 .set_fmt = wm8995_set_dai_fmt,
2122 .hw_params = wm8995_hw_params,
2123 .digital_mute = wm8995_aif_mute,
2124 .set_pll = wm8995_set_fll,
2125 .set_tristate = wm8995_set_tristate,
2126 };
2127
2128 static const struct snd_soc_dai_ops wm8995_aif3_dai_ops = {
2129 .set_tristate = wm8995_set_tristate,
2130 };
2131
2132 static struct snd_soc_dai_driver wm8995_dai[] = {
2133 {
2134 .name = "wm8995-aif1",
2135 .playback = {
2136 .stream_name = "AIF1 Playback",
2137 .channels_min = 2,
2138 .channels_max = 2,
2139 .rates = SNDRV_PCM_RATE_8000_96000,
2140 .formats = WM8995_FORMATS
2141 },
2142 .capture = {
2143 .stream_name = "AIF1 Capture",
2144 .channels_min = 2,
2145 .channels_max = 2,
2146 .rates = SNDRV_PCM_RATE_8000_48000,
2147 .formats = WM8995_FORMATS
2148 },
2149 .ops = &wm8995_aif1_dai_ops
2150 },
2151 {
2152 .name = "wm8995-aif2",
2153 .playback = {
2154 .stream_name = "AIF2 Playback",
2155 .channels_min = 2,
2156 .channels_max = 2,
2157 .rates = SNDRV_PCM_RATE_8000_96000,
2158 .formats = WM8995_FORMATS
2159 },
2160 .capture = {
2161 .stream_name = "AIF2 Capture",
2162 .channels_min = 2,
2163 .channels_max = 2,
2164 .rates = SNDRV_PCM_RATE_8000_48000,
2165 .formats = WM8995_FORMATS
2166 },
2167 .ops = &wm8995_aif2_dai_ops
2168 },
2169 {
2170 .name = "wm8995-aif3",
2171 .playback = {
2172 .stream_name = "AIF3 Playback",
2173 .channels_min = 2,
2174 .channels_max = 2,
2175 .rates = SNDRV_PCM_RATE_8000_96000,
2176 .formats = WM8995_FORMATS
2177 },
2178 .capture = {
2179 .stream_name = "AIF3 Capture",
2180 .channels_min = 2,
2181 .channels_max = 2,
2182 .rates = SNDRV_PCM_RATE_8000_48000,
2183 .formats = WM8995_FORMATS
2184 },
2185 .ops = &wm8995_aif3_dai_ops
2186 }
2187 };
2188
2189 static const struct snd_soc_codec_driver soc_codec_dev_wm8995 = {
2190 .probe = wm8995_probe,
2191 .remove = wm8995_remove,
2192 .set_bias_level = wm8995_set_bias_level,
2193 .idle_bias_off = true,
2194
2195 .component_driver = {
2196 .controls = wm8995_snd_controls,
2197 .num_controls = ARRAY_SIZE(wm8995_snd_controls),
2198 .dapm_widgets = wm8995_dapm_widgets,
2199 .num_dapm_widgets = ARRAY_SIZE(wm8995_dapm_widgets),
2200 .dapm_routes = wm8995_intercon,
2201 .num_dapm_routes = ARRAY_SIZE(wm8995_intercon),
2202 },
2203 };
2204
2205 static const struct regmap_config wm8995_regmap = {
2206 .reg_bits = 16,
2207 .val_bits = 16,
2208
2209 .max_register = WM8995_MAX_REGISTER,
2210 .reg_defaults = wm8995_reg_defaults,
2211 .num_reg_defaults = ARRAY_SIZE(wm8995_reg_defaults),
2212 .volatile_reg = wm8995_volatile,
2213 .readable_reg = wm8995_readable,
2214 .cache_type = REGCACHE_RBTREE,
2215 };
2216
2217 #if defined(CONFIG_SPI_MASTER)
2218 static int wm8995_spi_probe(struct spi_device *spi)
2219 {
2220 struct wm8995_priv *wm8995;
2221 int ret;
2222
2223 wm8995 = devm_kzalloc(&spi->dev, sizeof(*wm8995), GFP_KERNEL);
2224 if (!wm8995)
2225 return -ENOMEM;
2226
2227 spi_set_drvdata(spi, wm8995);
2228
2229 wm8995->regmap = devm_regmap_init_spi(spi, &wm8995_regmap);
2230 if (IS_ERR(wm8995->regmap)) {
2231 ret = PTR_ERR(wm8995->regmap);
2232 dev_err(&spi->dev, "Failed to register regmap: %d\n", ret);
2233 return ret;
2234 }
2235
2236 ret = snd_soc_register_codec(&spi->dev,
2237 &soc_codec_dev_wm8995, wm8995_dai,
2238 ARRAY_SIZE(wm8995_dai));
2239 return ret;
2240 }
2241
2242 static int wm8995_spi_remove(struct spi_device *spi)
2243 {
2244 snd_soc_unregister_codec(&spi->dev);
2245 return 0;
2246 }
2247
2248 static struct spi_driver wm8995_spi_driver = {
2249 .driver = {
2250 .name = "wm8995",
2251 },
2252 .probe = wm8995_spi_probe,
2253 .remove = wm8995_spi_remove
2254 };
2255 #endif
2256
2257 #if IS_ENABLED(CONFIG_I2C)
2258 static int wm8995_i2c_probe(struct i2c_client *i2c,
2259 const struct i2c_device_id *id)
2260 {
2261 struct wm8995_priv *wm8995;
2262 int ret;
2263
2264 wm8995 = devm_kzalloc(&i2c->dev, sizeof(*wm8995), GFP_KERNEL);
2265 if (!wm8995)
2266 return -ENOMEM;
2267
2268 i2c_set_clientdata(i2c, wm8995);
2269
2270 wm8995->regmap = devm_regmap_init_i2c(i2c, &wm8995_regmap);
2271 if (IS_ERR(wm8995->regmap)) {
2272 ret = PTR_ERR(wm8995->regmap);
2273 dev_err(&i2c->dev, "Failed to register regmap: %d\n", ret);
2274 return ret;
2275 }
2276
2277 ret = snd_soc_register_codec(&i2c->dev,
2278 &soc_codec_dev_wm8995, wm8995_dai,
2279 ARRAY_SIZE(wm8995_dai));
2280 if (ret < 0)
2281 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
2282
2283 return ret;
2284 }
2285
2286 static int wm8995_i2c_remove(struct i2c_client *client)
2287 {
2288 snd_soc_unregister_codec(&client->dev);
2289 return 0;
2290 }
2291
2292 static const struct i2c_device_id wm8995_i2c_id[] = {
2293 {"wm8995", 0},
2294 {}
2295 };
2296
2297 MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id);
2298
2299 static struct i2c_driver wm8995_i2c_driver = {
2300 .driver = {
2301 .name = "wm8995",
2302 },
2303 .probe = wm8995_i2c_probe,
2304 .remove = wm8995_i2c_remove,
2305 .id_table = wm8995_i2c_id
2306 };
2307 #endif
2308
2309 static int __init wm8995_modinit(void)
2310 {
2311 int ret = 0;
2312
2313 #if IS_ENABLED(CONFIG_I2C)
2314 ret = i2c_add_driver(&wm8995_i2c_driver);
2315 if (ret) {
2316 printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n",
2317 ret);
2318 }
2319 #endif
2320 #if defined(CONFIG_SPI_MASTER)
2321 ret = spi_register_driver(&wm8995_spi_driver);
2322 if (ret) {
2323 printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n",
2324 ret);
2325 }
2326 #endif
2327 return ret;
2328 }
2329
2330 module_init(wm8995_modinit);
2331
2332 static void __exit wm8995_exit(void)
2333 {
2334 #if IS_ENABLED(CONFIG_I2C)
2335 i2c_del_driver(&wm8995_i2c_driver);
2336 #endif
2337 #if defined(CONFIG_SPI_MASTER)
2338 spi_unregister_driver(&wm8995_spi_driver);
2339 #endif
2340 }
2341
2342 module_exit(wm8995_exit);
2343
2344 MODULE_DESCRIPTION("ASoC WM8995 driver");
2345 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
2346 MODULE_LICENSE("GPL");
Linux with added FPC-III support