| blob | 3288c9737671adc6362ba6a079a717d342fa487a |
1 /*
2 * Exception handling for Microblaze
3 *
4 * Rewriten interrupt handling
5 *
6 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
7 * Copyright (C) 2008-2009 PetaLogix
8 *
9 * uClinux customisation (C) 2005 John Williams
10 *
11 * MMU code derived from arch/ppc/kernel/head_4xx.S:
12 * Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org>
13 * Initial PowerPC version.
14 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
15 * Rewritten for PReP
16 * Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
17 * Low-level exception handers, MMU support, and rewrite.
18 * Copyright (C) 1997 Dan Malek <dmalek@jlc.net>
19 * PowerPC 8xx modifications.
20 * Copyright (C) 1998-1999 TiVo, Inc.
21 * PowerPC 403GCX modifications.
22 * Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu>
23 * PowerPC 403GCX/405GP modifications.
24 * Copyright 2000 MontaVista Software Inc.
25 * PPC405 modifications
26 * PowerPC 403GCX/405GP modifications.
27 * Author: MontaVista Software, Inc.
28 * frank_rowand@mvista.com or source@mvista.com
29 * debbie_chu@mvista.com
30 *
31 * Original code
32 * Copyright (C) 2004 Xilinx, Inc.
33 *
34 * This program is free software; you can redistribute it and/or modify it
35 * under the terms of the GNU General Public License version 2 as published
36 * by the Free Software Foundation.
37 */
39 /*
40 * Here are the handlers which don't require enabling translation
41 * and calling other kernel code thus we can keep their design very simple
42 * and do all processing in real mode. All what they need is a valid current
43 * (that is an issue for the CONFIG_REGISTER_TASK_PTR case)
44 * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore
45 * these registers are saved/restored
46 * The handlers which require translation are in entry.S --KAA
47 *
48 * Microblaze HW Exception Handler
49 * - Non self-modifying exception handler for the following exception conditions
50 * - Unalignment
51 * - Instruction bus error
52 * - Data bus error
53 * - Illegal instruction opcode
54 * - Divide-by-zero
55 *
56 * - Privileged instruction exception (MMU)
57 * - Data storage exception (MMU)
58 * - Instruction storage exception (MMU)
59 * - Data TLB miss exception (MMU)
60 * - Instruction TLB miss exception (MMU)
61 *
62 * Note we disable interrupts during exception handling, otherwise we will
63 * possibly get multiple re-entrancy if interrupt handles themselves cause
64 * exceptions. JW
65 */
67 #include <asm/exceptions.h>
68 #include <asm/unistd.h>
69 #include <asm/page.h>
71 #include <asm/entry.h>
72 #include <asm/current.h>
73 #include <linux/linkage.h>
75 #include <asm/mmu.h>
76 #include <asm/pgtable.h>
77 #include <asm/signal.h>
78 #include <asm/asm-offsets.h>
80 /* Helpful Macros */
81 #ifndef CONFIG_MMU
82 #define EX_HANDLER_STACK_SIZ (4*19)
83 #endif
84 #define NUM_TO_REG(num) r ## num
86 #ifdef CONFIG_MMU
87 /* FIXME you can't change first load of MSR because there is
88 * hardcoded jump bri 4 */
89 #define RESTORE_STATE \
90 lwi r3, r1, PT_R3; \
91 lwi r4, r1, PT_R4; \
92 lwi r5, r1, PT_R5; \
93 lwi r6, r1, PT_R6; \
94 lwi r11, r1, PT_R11; \
95 lwi r31, r1, PT_R31; \
96 lwi r1, r0, TOPHYS(r0_ram + 0);
97 #endif /* CONFIG_MMU */
99 #define LWREG_NOP \
100 bri ex_handler_unhandled; \
101 nop;
103 #define SWREG_NOP \
104 bri ex_handler_unhandled; \
105 nop;
107 /* FIXME this is weird - for noMMU kernel is not possible to use brid
108 * instruction which can shorten executed time
109 */
111 /* r3 is the source */
112 #define R3_TO_LWREG_V(regnum) \
113 swi r3, r1, 4 * regnum; \
114 bri ex_handler_done;
116 /* r3 is the source */
117 #define R3_TO_LWREG(regnum) \
118 or NUM_TO_REG (regnum), r0, r3; \
119 bri ex_handler_done;
121 /* r3 is the target */
122 #define SWREG_TO_R3_V(regnum) \
123 lwi r3, r1, 4 * regnum; \
124 bri ex_sw_tail;
126 /* r3 is the target */
127 #define SWREG_TO_R3(regnum) \
128 or r3, r0, NUM_TO_REG (regnum); \
129 bri ex_sw_tail;
131 #ifdef CONFIG_MMU
132 #define R3_TO_LWREG_VM_V(regnum) \
133 brid ex_lw_end_vm; \
134 swi r3, r7, 4 * regnum;
136 #define R3_TO_LWREG_VM(regnum) \
137 brid ex_lw_end_vm; \
138 or NUM_TO_REG (regnum), r0, r3;
140 #define SWREG_TO_R3_VM_V(regnum) \
141 brid ex_sw_tail_vm; \
142 lwi r3, r7, 4 * regnum;
144 #define SWREG_TO_R3_VM(regnum) \
145 brid ex_sw_tail_vm; \
146 or r3, r0, NUM_TO_REG (regnum);
148 /* Shift right instruction depending on available configuration */
149 #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
150 #define BSRLI(rD, rA, imm) \
151 bsrli rD, rA, imm
152 #elif CONFIG_XILINX_MICROBLAZE0_USE_DIV > 0
153 #define BSRLI(rD, rA, imm) \
154 ori rD, r0, (1 << imm); \
155 idivu rD, rD, rA
156 #else
157 #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
158 /* Only the used shift constants defined here - add more if needed */
159 #define BSRLI2(rD, rA) \
160 srl rD, rA; /* << 1 */ \
161 srl rD, rD; /* << 2 */
162 #define BSRLI10(rD, rA) \
163 srl rD, rA; /* << 1 */ \
164 srl rD, rD; /* << 2 */ \
165 srl rD, rD; /* << 3 */ \
166 srl rD, rD; /* << 4 */ \
167 srl rD, rD; /* << 5 */ \
168 srl rD, rD; /* << 6 */ \
169 srl rD, rD; /* << 7 */ \
170 srl rD, rD; /* << 8 */ \
171 srl rD, rD; /* << 9 */ \
172 srl rD, rD /* << 10 */
173 #define BSRLI20(rD, rA) \
174 BSRLI10(rD, rA); \
175 BSRLI10(rD, rD)
176 #endif
177 #endif /* CONFIG_MMU */
179 .extern other_exception_handler /* Defined in exception.c */
181 /*
182 * hw_exception_handler - Handler for exceptions
183 *
184 * Exception handler notes:
185 * - Handles all exceptions
186 * - Does not handle unaligned exceptions during load into r17, r1, r0.
187 * - Does not handle unaligned exceptions during store from r17 (cannot be
188 * done) and r1 (slows down common case)
189 *
190 * Relevant register structures
191 *
192 * EAR - |----|----|----|----|----|----|----|----|
193 * - < ## 32 bit faulting address ## >
194 *
195 * ESR - |----|----|----|----|----| - | - |-----|-----|
196 * - W S REG EXC
197 *
198 *
199 * STACK FRAME STRUCTURE (for NO_MMU)
200 * ---------------------------------
201 *
202 * +-------------+ + 0
203 * | MSR |
204 * +-------------+ + 4
205 * | r1 |
206 * | . |
207 * | . |
208 * | . |
209 * | . |
210 * | r18 |
211 * +-------------+ + 76
212 * | . |
213 * | . |
214 *
215 * NO_MMU kernel use the same r0_ram pointed space - look to vmlinux.lds.S
216 * which is used for storing register values - old style was, that value were
217 * stored in stack but in case of failure you lost information about register.
218 * Currently you can see register value in memory in specific place.
219 * In compare to with previous solution the speed should be the same.
220 *
221 * MMU exception handler has different handling compare to no MMU kernel.
222 * Exception handler use jump table for directing of what happen. For MMU kernel
223 * is this approach better because MMU relate exception are handled by asm code
224 * in this file. In compare to with MMU expect of unaligned exception
225 * is everything handled by C code.
226 */
228 /*
229 * every of these handlers is entered having R3/4/5/6/11/current saved on stack
230 * and clobbered so care should be taken to restore them if someone is going to
231 * return from exception
232 */
234 /* wrappers to restore state before coming to entry.S */
236 #ifdef CONFIG_MMU
237 .section .rodata
238 .align 4
239 _MB_HW_ExceptionVectorTable:
240 /* 0 - Undefined */
241 .long TOPHYS(ex_handler_unhandled)
242 /* 1 - Unaligned data access exception */
243 .long TOPHYS(handle_unaligned_ex)
244 /* 2 - Illegal op-code exception */
245 .long TOPHYS(full_exception_trapw)
246 /* 3 - Instruction bus error exception */
247 .long TOPHYS(full_exception_trapw)
248 /* 4 - Data bus error exception */
249 .long TOPHYS(full_exception_trapw)
250 /* 5 - Divide by zero exception */
251 .long TOPHYS(full_exception_trapw)
252 /* 6 - Floating point unit exception */
253 .long TOPHYS(full_exception_trapw)
254 /* 7 - Privileged instruction exception */
255 .long TOPHYS(full_exception_trapw)
256 /* 8 - 15 - Undefined */
257 .long TOPHYS(ex_handler_unhandled)
258 .long TOPHYS(ex_handler_unhandled)
259 .long TOPHYS(ex_handler_unhandled)
260 .long TOPHYS(ex_handler_unhandled)
261 .long TOPHYS(ex_handler_unhandled)
262 .long TOPHYS(ex_handler_unhandled)
263 .long TOPHYS(ex_handler_unhandled)
264 .long TOPHYS(ex_handler_unhandled)
265 /* 16 - Data storage exception */
266 .long TOPHYS(handle_data_storage_exception)
267 /* 17 - Instruction storage exception */
268 .long TOPHYS(handle_instruction_storage_exception)
269 /* 18 - Data TLB miss exception */
270 .long TOPHYS(handle_data_tlb_miss_exception)
271 /* 19 - Instruction TLB miss exception */
272 .long TOPHYS(handle_instruction_tlb_miss_exception)
273 /* 20 - 31 - Undefined */
274 .long TOPHYS(ex_handler_unhandled)
275 .long TOPHYS(ex_handler_unhandled)
276 .long TOPHYS(ex_handler_unhandled)
277 .long TOPHYS(ex_handler_unhandled)
278 .long TOPHYS(ex_handler_unhandled)
279 .long TOPHYS(ex_handler_unhandled)
280 .long TOPHYS(ex_handler_unhandled)
281 .long TOPHYS(ex_handler_unhandled)
282 .long TOPHYS(ex_handler_unhandled)
283 .long TOPHYS(ex_handler_unhandled)
284 .long TOPHYS(ex_handler_unhandled)
285 .long TOPHYS(ex_handler_unhandled)
286 #endif
288 .global _hw_exception_handler
289 .section .text
290 .align 4
291 .ent _hw_exception_handler
292 _hw_exception_handler:
293 #ifndef CONFIG_MMU
294 addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
295 #else
296 swi r1, r0, TOPHYS(r0_ram + 0); /* GET_SP */
297 /* Save date to kernel memory. Here is the problem
298 * when you came from user space */
299 ori r1, r0, TOPHYS(r0_ram + 28);
300 #endif
301 swi r3, r1, PT_R3
302 swi r4, r1, PT_R4
303 swi r5, r1, PT_R5
304 swi r6, r1, PT_R6
306 #ifdef CONFIG_MMU
307 swi r11, r1, PT_R11
308 swi r31, r1, PT_R31
309 lwi r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */
310 #endif
312 mfs r3, resr
313 nop
314 mfs r4, rear;
315 nop
317 #ifndef CONFIG_MMU
318 andi r5, r3, 0x1000; /* Check ESR[DS] */
319 beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
320 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
321 nop
322 not_in_delay_slot:
323 swi r17, r1, PT_R17
324 #endif
326 andi r5, r3, 0x1F; /* Extract ESR[EXC] */
328 #ifdef CONFIG_MMU
329 /* Calculate exception vector offset = r5 << 2 */
330 addk r6, r5, r5; /* << 1 */
331 addk r6, r6, r6; /* << 2 */
333 /* counting which exception happen */
334 lwi r5, r0, 0x200 + TOPHYS(r0_ram)
335 addi r5, r5, 1
336 swi r5, r0, 0x200 + TOPHYS(r0_ram)
337 lwi r5, r6, 0x200 + TOPHYS(r0_ram)
338 addi r5, r5, 1
339 swi r5, r6, 0x200 + TOPHYS(r0_ram)
340 /* end */
341 /* Load the HW Exception vector */
342 lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
343 bra r6
345 full_exception_trapw:
346 RESTORE_STATE
347 bri full_exception_trap
348 #else
349 /* Exceptions enabled here. This will allow nested exceptions */
350 mfs r6, rmsr;
351 nop
352 swi r6, r1, 0; /* RMSR_OFFSET */
353 ori r6, r6, 0x100; /* Turn ON the EE bit */
354 andi r6, r6, ~2; /* Disable interrupts */
355 mts rmsr, r6;
356 nop
358 xori r6, r5, 1; /* 00001 = Unaligned Exception */
359 /* Jump to unalignment exception handler */
360 beqi r6, handle_unaligned_ex;
362 handle_other_ex: /* Handle Other exceptions here */
363 /* Save other volatiles before we make procedure calls below */
364 swi r7, r1, PT_R7
365 swi r8, r1, PT_R8
366 swi r9, r1, PT_R9
367 swi r10, r1, PT_R10
368 swi r11, r1, PT_R11
369 swi r12, r1, PT_R12
370 swi r14, r1, PT_R14
371 swi r15, r1, PT_R15
372 swi r18, r1, PT_R18
374 or r5, r1, r0
375 andi r6, r3, 0x1F; /* Load ESR[EC] */
376 lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */
377 swi r7, r1, PT_MODE
378 mfs r7, rfsr
379 nop
380 addk r8, r17, r0; /* Load exception address */
381 bralid r15, full_exception; /* Branch to the handler */
382 nop;
384 /*
385 * Trigger execution of the signal handler by enabling
386 * interrupts and calling an invalid syscall.
387 */
388 mfs r5, rmsr;
389 nop
390 ori r5, r5, 2;
391 mts rmsr, r5; /* enable interrupt */
392 nop
393 addi r12, r0, __NR_syscalls;
394 brki r14, 0x08;
395 mfs r5, rmsr; /* disable interrupt */
396 nop
397 andi r5, r5, ~2;
398 mts rmsr, r5;
399 nop
401 lwi r7, r1, PT_R7
402 lwi r8, r1, PT_R8
403 lwi r9, r1, PT_R9
404 lwi r10, r1, PT_R10
405 lwi r11, r1, PT_R11
406 lwi r12, r1, PT_R12
407 lwi r14, r1, PT_R14
408 lwi r15, r1, PT_R15
409 lwi r18, r1, PT_R18
411 bri ex_handler_done; /* Complete exception handling */
412 #endif
414 /* 0x01 - Unaligned data access exception
415 * This occurs when a word access is not aligned on a word boundary,
416 * or when a 16-bit access is not aligned on a 16-bit boundary.
417 * This handler perform the access, and returns, except for MMU when
418 * the unaligned address is last on a 4k page or the physical address is
419 * not found in the page table, in which case unaligned_data_trap is called.
420 */
421 handle_unaligned_ex:
422 /* Working registers already saved: R3, R4, R5, R6
423 * R3 = ESR
424 * R4 = EAR
425 */
426 #ifdef CONFIG_MMU
427 andi r6, r3, 0x1000 /* Check ESR[DS] */
428 beqi r6, _no_delayslot /* Branch if ESR[DS] not set */
429 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
430 nop
431 _no_delayslot:
432 /* jump to high level unaligned handler */
433 RESTORE_STATE;
434 bri unaligned_data_trap
435 #endif
436 andi r6, r3, 0x3E0; /* Mask and extract the register operand */
437 srl r6, r6; /* r6 >> 5 */
438 srl r6, r6;
439 srl r6, r6;
440 srl r6, r6;
441 srl r6, r6;
442 /* Store the register operand in a temporary location */
443 sbi r6, r0, TOPHYS(ex_reg_op);
445 andi r6, r3, 0x400; /* Extract ESR[S] */
446 bnei r6, ex_sw;
447 ex_lw:
448 andi r6, r3, 0x800; /* Extract ESR[W] */
449 beqi r6, ex_lhw;
450 lbui r5, r4, 0; /* Exception address in r4 */
451 /* Load a word, byte-by-byte from destination address
452 and save it in tmp space */
453 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
454 lbui r5, r4, 1;
455 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
456 lbui r5, r4, 2;
457 sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);
458 lbui r5, r4, 3;
459 sbi r5, r0, TOPHYS(ex_tmp_data_loc_3);
460 /* Get the destination register value into r3 */
461 lwi r3, r0, TOPHYS(ex_tmp_data_loc_0);
462 bri ex_lw_tail;
463 ex_lhw:
464 lbui r5, r4, 0; /* Exception address in r4 */
465 /* Load a half-word, byte-by-byte from destination
466 address and save it in tmp space */
467 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
468 lbui r5, r4, 1;
469 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
470 /* Get the destination register value into r3 */
471 lhui r3, r0, TOPHYS(ex_tmp_data_loc_0);
472 ex_lw_tail:
473 /* Get the destination register number into r5 */
474 lbui r5, r0, TOPHYS(ex_reg_op);
475 /* Form load_word jump table offset (lw_table + (8 * regnum)) */
476 la r6, r0, TOPHYS(lw_table);
477 addk r5, r5, r5;
478 addk r5, r5, r5;
479 addk r5, r5, r5;
480 addk r5, r5, r6;
481 bra r5;
482 ex_lw_end: /* Exception handling of load word, ends */
483 ex_sw:
484 /* Get the destination register number into r5 */
485 lbui r5, r0, TOPHYS(ex_reg_op);
486 /* Form store_word jump table offset (sw_table + (8 * regnum)) */
487 la r6, r0, TOPHYS(sw_table);
488 add r5, r5, r5;
489 add r5, r5, r5;
490 add r5, r5, r5;
491 add r5, r5, r6;
492 bra r5;
493 ex_sw_tail:
494 mfs r6, resr;
495 nop
496 andi r6, r6, 0x800; /* Extract ESR[W] */
497 beqi r6, ex_shw;
498 /* Get the word - delay slot */
499 swi r3, r0, TOPHYS(ex_tmp_data_loc_0);
500 /* Store the word, byte-by-byte into destination address */
501 lbui r3, r0, TOPHYS(ex_tmp_data_loc_0);
502 sbi r3, r4, 0;
503 lbui r3, r0, TOPHYS(ex_tmp_data_loc_1);
504 sbi r3, r4, 1;
505 lbui r3, r0, TOPHYS(ex_tmp_data_loc_2);
506 sbi r3, r4, 2;
507 lbui r3, r0, TOPHYS(ex_tmp_data_loc_3);
508 sbi r3, r4, 3;
509 bri ex_handler_done;
511 ex_shw:
512 /* Store the lower half-word, byte-by-byte into destination address */
513 swi r3, r0, TOPHYS(ex_tmp_data_loc_0);
514 lbui r3, r0, TOPHYS(ex_tmp_data_loc_2);
515 sbi r3, r4, 0;
516 lbui r3, r0, TOPHYS(ex_tmp_data_loc_3);
517 sbi r3, r4, 1;
518 ex_sw_end: /* Exception handling of store word, ends. */
520 ex_handler_done:
521 #ifndef CONFIG_MMU
522 lwi r5, r1, 0 /* RMSR */
523 mts rmsr, r5
524 nop
525 lwi r3, r1, PT_R3
526 lwi r4, r1, PT_R4
527 lwi r5, r1, PT_R5
528 lwi r6, r1, PT_R6
529 lwi r17, r1, PT_R17
531 rted r17, 0
532 addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
533 #else
534 RESTORE_STATE;
535 rted r17, 0
536 nop
537 #endif
539 #ifdef CONFIG_MMU
540 /* Exception vector entry code. This code runs with address translation
541 * turned off (i.e. using physical addresses). */
543 /* Exception vectors. */
545 /* 0x10 - Data Storage Exception
546 * This happens for just a few reasons. U0 set (but we don't do that),
547 * or zone protection fault (user violation, write to protected page).
548 * If this is just an update of modified status, we do that quickly
549 * and exit. Otherwise, we call heavyweight functions to do the work.
550 */
551 handle_data_storage_exception:
552 /* Working registers already saved: R3, R4, R5, R6
553 * R3 = ESR
554 */
555 mfs r11, rpid
556 nop
557 bri 4
558 mfs r3, rear /* Get faulting address */
559 nop
560 /* If we are faulting a kernel address, we have to use the
561 * kernel page tables.
562 */
563 ori r4, r0, CONFIG_KERNEL_START
564 cmpu r4, r3, r4
565 bgti r4, ex3
566 /* First, check if it was a zone fault (which means a user
567 * tried to access a kernel or read-protected page - always
568 * a SEGV). All other faults here must be stores, so no
569 * need to check ESR_S as well. */
570 mfs r4, resr
571 nop
572 andi r4, r4, 0x800 /* ESR_Z - zone protection */
573 bnei r4, ex2
575 ori r4, r0, swapper_pg_dir
576 mts rpid, r0 /* TLB will have 0 TID */
577 nop
578 bri ex4
580 /* Get the PGD for the current thread. */
581 ex3:
582 /* First, check if it was a zone fault (which means a user
583 * tried to access a kernel or read-protected page - always
584 * a SEGV). All other faults here must be stores, so no
585 * need to check ESR_S as well. */
586 mfs r4, resr
587 nop
588 andi r4, r4, 0x800 /* ESR_Z */
589 bnei r4, ex2
590 /* get current task address */
591 addi r4 ,CURRENT_TASK, TOPHYS(0);
592 lwi r4, r4, TASK_THREAD+PGDIR
593 ex4:
594 tophys(r4,r4)
595 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
596 andi r5, r5, 0xffc
597 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
598 or r4, r4, r5
599 lwi r4, r4, 0 /* Get L1 entry */
600 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
601 beqi r5, ex2 /* Bail if no table */
603 tophys(r5,r5)
604 BSRLI(r6,r3,10) /* Compute PTE address */
605 andi r6, r6, 0xffc
606 andi r5, r5, 0xfffff003
607 or r5, r5, r6
608 lwi r4, r5, 0 /* Get Linux PTE */
610 andi r6, r4, _PAGE_RW /* Is it writeable? */
611 beqi r6, ex2 /* Bail if not */
613 /* Update 'changed' */
614 ori r4, r4, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
615 swi r4, r5, 0 /* Update Linux page table */
617 /* Most of the Linux PTE is ready to load into the TLB LO.
618 * We set ZSEL, where only the LS-bit determines user access.
619 * We set execute, because we don't have the granularity to
620 * properly set this at the page level (Linux problem).
621 * If shared is set, we cause a zero PID->TID load.
622 * Many of these bits are software only. Bits we don't set
623 * here we (properly should) assume have the appropriate value.
624 */
625 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
626 ori r4, r4, _PAGE_HWEXEC /* make it executable */
628 /* find the TLB index that caused the fault. It has to be here*/
629 mts rtlbsx, r3
630 nop
631 mfs r5, rtlbx /* DEBUG: TBD */
632 nop
633 mts rtlblo, r4 /* Load TLB LO */
634 nop
635 /* Will sync shadow TLBs */
637 /* Done...restore registers and get out of here. */
638 mts rpid, r11
639 nop
640 bri 4
642 RESTORE_STATE;
643 rted r17, 0
644 nop
645 ex2:
646 /* The bailout. Restore registers to pre-exception conditions
647 * and call the heavyweights to help us out. */
648 mts rpid, r11
649 nop
650 bri 4
651 RESTORE_STATE;
652 bri page_fault_data_trap
655 /* 0x11 - Instruction Storage Exception
656 * This is caused by a fetch from non-execute or guarded pages. */
657 handle_instruction_storage_exception:
658 /* Working registers already saved: R3, R4, R5, R6
659 * R3 = ESR
660 */
662 mfs r3, rear /* Get faulting address */
663 nop
664 RESTORE_STATE;
665 bri page_fault_instr_trap
667 /* 0x12 - Data TLB Miss Exception
668 * As the name implies, translation is not in the MMU, so search the
669 * page tables and fix it. The only purpose of this function is to
670 * load TLB entries from the page table if they exist.
671 */
672 handle_data_tlb_miss_exception:
673 /* Working registers already saved: R3, R4, R5, R6
674 * R3 = ESR
675 */
676 mfs r11, rpid
677 nop
678 bri 4
679 mfs r3, rear /* Get faulting address */
680 nop
682 /* If we are faulting a kernel address, we have to use the
683 * kernel page tables. */
684 ori r4, r0, CONFIG_KERNEL_START
685 cmpu r4, r3, r4
686 bgti r4, ex5
687 ori r4, r0, swapper_pg_dir
688 mts rpid, r0 /* TLB will have 0 TID */
689 nop
690 bri ex6
692 /* Get the PGD for the current thread. */
693 ex5:
694 /* get current task address */
695 addi r4 ,CURRENT_TASK, TOPHYS(0);
696 lwi r4, r4, TASK_THREAD+PGDIR
697 ex6:
698 tophys(r4,r4)
699 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
700 andi r5, r5, 0xffc
701 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
702 or r4, r4, r5
703 lwi r4, r4, 0 /* Get L1 entry */
704 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
705 beqi r5, ex7 /* Bail if no table */
707 tophys(r5,r5)
708 BSRLI(r6,r3,10) /* Compute PTE address */
709 andi r6, r6, 0xffc
710 andi r5, r5, 0xfffff003
711 or r5, r5, r6
712 lwi r4, r5, 0 /* Get Linux PTE */
714 andi r6, r4, _PAGE_PRESENT
715 beqi r6, ex7
717 ori r4, r4, _PAGE_ACCESSED
718 swi r4, r5, 0
720 /* Most of the Linux PTE is ready to load into the TLB LO.
721 * We set ZSEL, where only the LS-bit determines user access.
722 * We set execute, because we don't have the granularity to
723 * properly set this at the page level (Linux problem).
724 * If shared is set, we cause a zero PID->TID load.
725 * Many of these bits are software only. Bits we don't set
726 * here we (properly should) assume have the appropriate value.
727 */
728 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
730 bri finish_tlb_load
731 ex7:
732 /* The bailout. Restore registers to pre-exception conditions
733 * and call the heavyweights to help us out.
734 */
735 mts rpid, r11
736 nop
737 bri 4
738 RESTORE_STATE;
739 bri page_fault_data_trap
741 /* 0x13 - Instruction TLB Miss Exception
742 * Nearly the same as above, except we get our information from
743 * different registers and bailout to a different point.
744 */
745 handle_instruction_tlb_miss_exception:
746 /* Working registers already saved: R3, R4, R5, R6
747 * R3 = ESR
748 */
749 mfs r11, rpid
750 nop
751 bri 4
752 mfs r3, rear /* Get faulting address */
753 nop
755 /* If we are faulting a kernel address, we have to use the
756 * kernel page tables.
757 */
758 ori r4, r0, CONFIG_KERNEL_START
759 cmpu r4, r3, r4
760 bgti r4, ex8
761 ori r4, r0, swapper_pg_dir
762 mts rpid, r0 /* TLB will have 0 TID */
763 nop
764 bri ex9
766 /* Get the PGD for the current thread. */
767 ex8:
768 /* get current task address */
769 addi r4 ,CURRENT_TASK, TOPHYS(0);
770 lwi r4, r4, TASK_THREAD+PGDIR
771 ex9:
772 tophys(r4,r4)
773 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
774 andi r5, r5, 0xffc
775 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
776 or r4, r4, r5
777 lwi r4, r4, 0 /* Get L1 entry */
778 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
779 beqi r5, ex10 /* Bail if no table */
781 tophys(r5,r5)
782 BSRLI(r6,r3,10) /* Compute PTE address */
783 andi r6, r6, 0xffc
784 andi r5, r5, 0xfffff003
785 or r5, r5, r6
786 lwi r4, r5, 0 /* Get Linux PTE */
788 andi r6, r4, _PAGE_PRESENT
789 beqi r6, ex7
791 ori r4, r4, _PAGE_ACCESSED
792 swi r4, r5, 0
794 /* Most of the Linux PTE is ready to load into the TLB LO.
795 * We set ZSEL, where only the LS-bit determines user access.
796 * We set execute, because we don't have the granularity to
797 * properly set this at the page level (Linux problem).
798 * If shared is set, we cause a zero PID->TID load.
799 * Many of these bits are software only. Bits we don't set
800 * here we (properly should) assume have the appropriate value.
801 */
802 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
804 bri finish_tlb_load
805 ex10:
806 /* The bailout. Restore registers to pre-exception conditions
807 * and call the heavyweights to help us out.
808 */
809 mts rpid, r11
810 nop
811 bri 4
812 RESTORE_STATE;
813 bri page_fault_instr_trap
815 /* Both the instruction and data TLB miss get to this point to load the TLB.
816 * r3 - EA of fault
817 * r4 - TLB LO (info from Linux PTE)
818 * r5, r6 - available to use
819 * PID - loaded with proper value when we get here
820 * Upon exit, we reload everything and RFI.
821 * A common place to load the TLB.
822 */
823 tlb_index:
824 .long 1 /* MS: storing last used tlb index */
825 finish_tlb_load:
826 /* MS: load the last used TLB index. */
827 lwi r5, r0, TOPHYS(tlb_index)
828 addik r5, r5, 1 /* MS: inc tlb_index -> use next one */
830 /* MS: FIXME this is potential fault, because this is mask not count */
831 andi r5, r5, (MICROBLAZE_TLB_SIZE-1)
832 ori r6, r0, 1
833 cmp r31, r5, r6
834 blti r31, sem
835 addik r5, r6, 1
836 sem:
837 /* MS: save back current TLB index */
838 swi r5, r0, TOPHYS(tlb_index)
840 ori r4, r4, _PAGE_HWEXEC /* make it executable */
841 mts rtlbx, r5 /* MS: save current TLB */
842 nop
843 mts rtlblo, r4 /* MS: save to TLB LO */
844 nop
846 /* Create EPN. This is the faulting address plus a static
847 * set of bits. These are size, valid, E, U0, and ensure
848 * bits 20 and 21 are zero.
849 */
850 andi r3, r3, 0xfffff000
851 ori r3, r3, 0x0c0
852 mts rtlbhi, r3 /* Load TLB HI */
853 nop
855 /* Done...restore registers and get out of here. */
856 ex12:
857 mts rpid, r11
858 nop
859 bri 4
860 RESTORE_STATE;
861 rted r17, 0
862 nop
864 /* extern void giveup_fpu(struct task_struct *prev)
865 *
866 * The MicroBlaze processor may have an FPU, so this should not just
867 * return: TBD.
868 */
869 .globl giveup_fpu;
870 .align 4;
871 giveup_fpu:
872 bralid r15,0 /* TBD */
873 nop
875 /* At present, this routine just hangs. - extern void abort(void) */
876 .globl abort;
877 .align 4;
878 abort:
879 br r0
881 .globl set_context;
882 .align 4;
883 set_context:
884 mts rpid, r5 /* Shadow TLBs are automatically */
885 nop
886 bri 4 /* flushed by changing PID */
887 rtsd r15,8
888 nop
890 #endif
891 .end _hw_exception_handler
893 #ifdef CONFIG_MMU
894 /* Unaligned data access exception last on a 4k page for MMU.
895 * When this is called, we are in virtual mode with exceptions enabled
896 * and registers 1-13,15,17,18 saved.
897 *
898 * R3 = ESR
899 * R4 = EAR
900 * R7 = pointer to saved registers (struct pt_regs *regs)
901 *
902 * This handler perform the access, and returns via ret_from_exc.
903 */
904 .global _unaligned_data_exception
905 .ent _unaligned_data_exception
906 _unaligned_data_exception:
907 andi r8, r3, 0x3E0; /* Mask and extract the register operand */
908 BSRLI(r8,r8,2); /* r8 >> 2 = register operand * 8 */
909 andi r6, r3, 0x400; /* Extract ESR[S] */
910 bneid r6, ex_sw_vm;
911 andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */
912 ex_lw_vm:
913 beqid r6, ex_lhw_vm;
914 load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
915 /* Load a word, byte-by-byte from destination address and save it in tmp space*/
916 la r6, r0, ex_tmp_data_loc_0;
917 sbi r5, r6, 0;
918 load2: lbui r5, r4, 1;
919 sbi r5, r6, 1;
920 load3: lbui r5, r4, 2;
921 sbi r5, r6, 2;
922 load4: lbui r5, r4, 3;
923 sbi r5, r6, 3;
924 brid ex_lw_tail_vm;
925 /* Get the destination register value into r3 - delay slot */
926 lwi r3, r6, 0;
927 ex_lhw_vm:
928 /* Load a half-word, byte-by-byte from destination address and
929 * save it in tmp space */
930 la r6, r0, ex_tmp_data_loc_0;
931 sbi r5, r6, 0;
932 load5: lbui r5, r4, 1;
933 sbi r5, r6, 1;
934 lhui r3, r6, 0; /* Get the destination register value into r3 */
935 ex_lw_tail_vm:
936 /* Form load_word jump table offset (lw_table_vm + (8 * regnum)) */
937 addik r5, r8, lw_table_vm;
938 bra r5;
939 ex_lw_end_vm: /* Exception handling of load word, ends */
940 brai ret_from_exc;
941 ex_sw_vm:
942 /* Form store_word jump table offset (sw_table_vm + (8 * regnum)) */
943 addik r5, r8, sw_table_vm;
944 bra r5;
945 ex_sw_tail_vm:
946 la r5, r0, ex_tmp_data_loc_0;
947 beqid r6, ex_shw_vm;
948 swi r3, r5, 0; /* Get the word - delay slot */
949 /* Store the word, byte-by-byte into destination address */
950 lbui r3, r5, 0;
951 store1: sbi r3, r4, 0;
952 lbui r3, r5, 1;
953 store2: sbi r3, r4, 1;
954 lbui r3, r5, 2;
955 store3: sbi r3, r4, 2;
956 lbui r3, r5, 3;
957 brid ret_from_exc;
958 store4: sbi r3, r4, 3; /* Delay slot */
959 ex_shw_vm:
960 /* Store the lower half-word, byte-by-byte into destination address */
961 lbui r3, r5, 2;
962 store5: sbi r3, r4, 0;
963 lbui r3, r5, 3;
964 brid ret_from_exc;
965 store6: sbi r3, r4, 1; /* Delay slot */
966 ex_sw_end_vm: /* Exception handling of store word, ends. */
968 /* We have to prevent cases that get/put_user macros get unaligned pointer
969 * to bad page area. We have to find out which origin instruction caused it
970 * and called fixup for that origin instruction not instruction in unaligned
971 * handler */
972 ex_unaligned_fixup:
973 ori r5, r7, 0 /* setup pointer to pt_regs */
974 lwi r6, r7, PT_PC; /* faulting address is one instruction above */
975 addik r6, r6, -4 /* for finding proper fixup */
976 swi r6, r7, PT_PC; /* a save back it to PT_PC */
977 addik r7, r0, SIGSEGV
978 /* call bad_page_fault for finding aligned fixup, fixup address is saved
979 * in PT_PC which is used as return address from exception */
980 la r15, r0, ret_from_exc-8 /* setup return address */
981 brid bad_page_fault
982 nop
984 /* We prevent all load/store because it could failed any attempt to access */
985 .section __ex_table,"a";
986 .word load1,ex_unaligned_fixup;
987 .word load2,ex_unaligned_fixup;
988 .word load3,ex_unaligned_fixup;
989 .word load4,ex_unaligned_fixup;
990 .word load5,ex_unaligned_fixup;
991 .word store1,ex_unaligned_fixup;
992 .word store2,ex_unaligned_fixup;
993 .word store3,ex_unaligned_fixup;
994 .word store4,ex_unaligned_fixup;
995 .word store5,ex_unaligned_fixup;
996 .word store6,ex_unaligned_fixup;
997 .previous;
998 .end _unaligned_data_exception
999 #endif /* CONFIG_MMU */
1001 ex_handler_unhandled:
1002 /* FIXME add handle function for unhandled exception - dump register */
1003 bri 0
1005 /*
1006 * hw_exception_handler Jump Table
1007 * - Contains code snippets for each register that caused the unalign exception
1008 * - Hence exception handler is NOT self-modifying
1009 * - Separate table for load exceptions and store exceptions.
1010 * - Each table is of size: (8 * 32) = 256 bytes
1011 */
1013 .section .text
1014 .align 4
1015 lw_table:
1016 lw_r0: R3_TO_LWREG (0);
1017 lw_r1: LWREG_NOP;
1018 lw_r2: R3_TO_LWREG (2);
1019 lw_r3: R3_TO_LWREG_V (3);
1020 lw_r4: R3_TO_LWREG_V (4);
1021 lw_r5: R3_TO_LWREG_V (5);
1022 lw_r6: R3_TO_LWREG_V (6);
1023 lw_r7: R3_TO_LWREG (7);
1024 lw_r8: R3_TO_LWREG (8);
1025 lw_r9: R3_TO_LWREG (9);
1026 lw_r10: R3_TO_LWREG (10);
1027 lw_r11: R3_TO_LWREG (11);
1028 lw_r12: R3_TO_LWREG (12);
1029 lw_r13: R3_TO_LWREG (13);
1030 lw_r14: R3_TO_LWREG (14);
1031 lw_r15: R3_TO_LWREG (15);
1032 lw_r16: R3_TO_LWREG (16);
1033 lw_r17: LWREG_NOP;
1034 lw_r18: R3_TO_LWREG (18);
1035 lw_r19: R3_TO_LWREG (19);
1036 lw_r20: R3_TO_LWREG (20);
1037 lw_r21: R3_TO_LWREG (21);
1038 lw_r22: R3_TO_LWREG (22);
1039 lw_r23: R3_TO_LWREG (23);
1040 lw_r24: R3_TO_LWREG (24);
1041 lw_r25: R3_TO_LWREG (25);
1042 lw_r26: R3_TO_LWREG (26);
1043 lw_r27: R3_TO_LWREG (27);
1044 lw_r28: R3_TO_LWREG (28);
1045 lw_r29: R3_TO_LWREG (29);
1046 lw_r30: R3_TO_LWREG (30);
1047 #ifdef CONFIG_MMU
1048 lw_r31: R3_TO_LWREG_V (31);
1049 #else
1050 lw_r31: R3_TO_LWREG (31);
1051 #endif
1053 sw_table:
1054 sw_r0: SWREG_TO_R3 (0);
1055 sw_r1: SWREG_NOP;
1056 sw_r2: SWREG_TO_R3 (2);
1057 sw_r3: SWREG_TO_R3_V (3);
1058 sw_r4: SWREG_TO_R3_V (4);
1059 sw_r5: SWREG_TO_R3_V (5);
1060 sw_r6: SWREG_TO_R3_V (6);
1061 sw_r7: SWREG_TO_R3 (7);
1062 sw_r8: SWREG_TO_R3 (8);
1063 sw_r9: SWREG_TO_R3 (9);
1064 sw_r10: SWREG_TO_R3 (10);
1065 sw_r11: SWREG_TO_R3 (11);
1066 sw_r12: SWREG_TO_R3 (12);
1067 sw_r13: SWREG_TO_R3 (13);
1068 sw_r14: SWREG_TO_R3 (14);
1069 sw_r15: SWREG_TO_R3 (15);
1070 sw_r16: SWREG_TO_R3 (16);
1071 sw_r17: SWREG_NOP;
1072 sw_r18: SWREG_TO_R3 (18);
1073 sw_r19: SWREG_TO_R3 (19);
1074 sw_r20: SWREG_TO_R3 (20);
1075 sw_r21: SWREG_TO_R3 (21);
1076 sw_r22: SWREG_TO_R3 (22);
1077 sw_r23: SWREG_TO_R3 (23);
1078 sw_r24: SWREG_TO_R3 (24);
1079 sw_r25: SWREG_TO_R3 (25);
1080 sw_r26: SWREG_TO_R3 (26);
1081 sw_r27: SWREG_TO_R3 (27);
1082 sw_r28: SWREG_TO_R3 (28);
1083 sw_r29: SWREG_TO_R3 (29);
1084 sw_r30: SWREG_TO_R3 (30);
1085 #ifdef CONFIG_MMU
1086 sw_r31: SWREG_TO_R3_V (31);
1087 #else
1088 sw_r31: SWREG_TO_R3 (31);
1089 #endif
1091 #ifdef CONFIG_MMU
1092 lw_table_vm:
1093 lw_r0_vm: R3_TO_LWREG_VM (0);
1094 lw_r1_vm: R3_TO_LWREG_VM_V (1);
1095 lw_r2_vm: R3_TO_LWREG_VM_V (2);
1096 lw_r3_vm: R3_TO_LWREG_VM_V (3);
1097 lw_r4_vm: R3_TO_LWREG_VM_V (4);
1098 lw_r5_vm: R3_TO_LWREG_VM_V (5);
1099 lw_r6_vm: R3_TO_LWREG_VM_V (6);
1100 lw_r7_vm: R3_TO_LWREG_VM_V (7);
1101 lw_r8_vm: R3_TO_LWREG_VM_V (8);
1102 lw_r9_vm: R3_TO_LWREG_VM_V (9);
1103 lw_r10_vm: R3_TO_LWREG_VM_V (10);
1104 lw_r11_vm: R3_TO_LWREG_VM_V (11);
1105 lw_r12_vm: R3_TO_LWREG_VM_V (12);
1106 lw_r13_vm: R3_TO_LWREG_VM_V (13);
1107 lw_r14_vm: R3_TO_LWREG_VM (14);
1108 lw_r15_vm: R3_TO_LWREG_VM_V (15);
1109 lw_r16_vm: R3_TO_LWREG_VM (16);
1110 lw_r17_vm: R3_TO_LWREG_VM_V (17);
1111 lw_r18_vm: R3_TO_LWREG_VM_V (18);
1112 lw_r19_vm: R3_TO_LWREG_VM (19);
1113 lw_r20_vm: R3_TO_LWREG_VM (20);
1114 lw_r21_vm: R3_TO_LWREG_VM (21);
1115 lw_r22_vm: R3_TO_LWREG_VM (22);
1116 lw_r23_vm: R3_TO_LWREG_VM (23);
1117 lw_r24_vm: R3_TO_LWREG_VM (24);
1118 lw_r25_vm: R3_TO_LWREG_VM (25);
1119 lw_r26_vm: R3_TO_LWREG_VM (26);
1120 lw_r27_vm: R3_TO_LWREG_VM (27);
1121 lw_r28_vm: R3_TO_LWREG_VM (28);
1122 lw_r29_vm: R3_TO_LWREG_VM (29);
1123 lw_r30_vm: R3_TO_LWREG_VM (30);
1124 lw_r31_vm: R3_TO_LWREG_VM_V (31);
1126 sw_table_vm:
1127 sw_r0_vm: SWREG_TO_R3_VM (0);
1128 sw_r1_vm: SWREG_TO_R3_VM_V (1);
1129 sw_r2_vm: SWREG_TO_R3_VM_V (2);
1130 sw_r3_vm: SWREG_TO_R3_VM_V (3);
1131 sw_r4_vm: SWREG_TO_R3_VM_V (4);
1132 sw_r5_vm: SWREG_TO_R3_VM_V (5);
1133 sw_r6_vm: SWREG_TO_R3_VM_V (6);
1134 sw_r7_vm: SWREG_TO_R3_VM_V (7);
1135 sw_r8_vm: SWREG_TO_R3_VM_V (8);
1136 sw_r9_vm: SWREG_TO_R3_VM_V (9);
1137 sw_r10_vm: SWREG_TO_R3_VM_V (10);
1138 sw_r11_vm: SWREG_TO_R3_VM_V (11);
1139 sw_r12_vm: SWREG_TO_R3_VM_V (12);
1140 sw_r13_vm: SWREG_TO_R3_VM_V (13);
1141 sw_r14_vm: SWREG_TO_R3_VM (14);
1142 sw_r15_vm: SWREG_TO_R3_VM_V (15);
1143 sw_r16_vm: SWREG_TO_R3_VM (16);
1144 sw_r17_vm: SWREG_TO_R3_VM_V (17);
1145 sw_r18_vm: SWREG_TO_R3_VM_V (18);
1146 sw_r19_vm: SWREG_TO_R3_VM (19);
1147 sw_r20_vm: SWREG_TO_R3_VM (20);
1148 sw_r21_vm: SWREG_TO_R3_VM (21);
1149 sw_r22_vm: SWREG_TO_R3_VM (22);
1150 sw_r23_vm: SWREG_TO_R3_VM (23);
1151 sw_r24_vm: SWREG_TO_R3_VM (24);
1152 sw_r25_vm: SWREG_TO_R3_VM (25);
1153 sw_r26_vm: SWREG_TO_R3_VM (26);
1154 sw_r27_vm: SWREG_TO_R3_VM (27);
1155 sw_r28_vm: SWREG_TO_R3_VM (28);
1156 sw_r29_vm: SWREG_TO_R3_VM (29);
1157 sw_r30_vm: SWREG_TO_R3_VM (30);
1158 sw_r31_vm: SWREG_TO_R3_VM_V (31);
1159 #endif /* CONFIG_MMU */
1161 /* Temporary data structures used in the handler */
1162 .section .data
1163 .align 4
1164 ex_tmp_data_loc_0:
1165 .byte 0
1166 ex_tmp_data_loc_1:
1167 .byte 0
1168 ex_tmp_data_loc_2:
1169 .byte 0
1170 ex_tmp_data_loc_3:
1171 .byte 0
1172 ex_reg_op:
1173 .byte 0