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ext3: Update MAINTAINERS for ext3 and JBD
[linux/fpc-iii.git] / sound / soc / davinci / davinci-mcasp.c
blobeca22d7829d22744d1a57f797a3740ff1d8af96d
1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/initval.h>
29 #include <sound/soc.h>
30
31 #include "davinci-pcm.h"
32 #include "davinci-mcasp.h"
33
34 /*
35 * McASP register definitions
36 */
37 #define DAVINCI_MCASP_PID_REG 0x00
38 #define DAVINCI_MCASP_PWREMUMGT_REG 0x04
39
40 #define DAVINCI_MCASP_PFUNC_REG 0x10
41 #define DAVINCI_MCASP_PDIR_REG 0x14
42 #define DAVINCI_MCASP_PDOUT_REG 0x18
43 #define DAVINCI_MCASP_PDSET_REG 0x1c
44
45 #define DAVINCI_MCASP_PDCLR_REG 0x20
46
47 #define DAVINCI_MCASP_TLGC_REG 0x30
48 #define DAVINCI_MCASP_TLMR_REG 0x34
49
50 #define DAVINCI_MCASP_GBLCTL_REG 0x44
51 #define DAVINCI_MCASP_AMUTE_REG 0x48
52 #define DAVINCI_MCASP_LBCTL_REG 0x4c
53
54 #define DAVINCI_MCASP_TXDITCTL_REG 0x50
55
56 #define DAVINCI_MCASP_GBLCTLR_REG 0x60
57 #define DAVINCI_MCASP_RXMASK_REG 0x64
58 #define DAVINCI_MCASP_RXFMT_REG 0x68
59 #define DAVINCI_MCASP_RXFMCTL_REG 0x6c
60
61 #define DAVINCI_MCASP_ACLKRCTL_REG 0x70
62 #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
63 #define DAVINCI_MCASP_RXTDM_REG 0x78
64 #define DAVINCI_MCASP_EVTCTLR_REG 0x7c
65
66 #define DAVINCI_MCASP_RXSTAT_REG 0x80
67 #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
68 #define DAVINCI_MCASP_RXCLKCHK_REG 0x88
69 #define DAVINCI_MCASP_REVTCTL_REG 0x8c
70
71 #define DAVINCI_MCASP_GBLCTLX_REG 0xa0
72 #define DAVINCI_MCASP_TXMASK_REG 0xa4
73 #define DAVINCI_MCASP_TXFMT_REG 0xa8
74 #define DAVINCI_MCASP_TXFMCTL_REG 0xac
75
76 #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
77 #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
78 #define DAVINCI_MCASP_TXTDM_REG 0xb8
79 #define DAVINCI_MCASP_EVTCTLX_REG 0xbc
80
81 #define DAVINCI_MCASP_TXSTAT_REG 0xc0
82 #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
83 #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
84 #define DAVINCI_MCASP_XEVTCTL_REG 0xcc
85
86 /* Left(even TDM Slot) Channel Status Register File */
87 #define DAVINCI_MCASP_DITCSRA_REG 0x100
88 /* Right(odd TDM slot) Channel Status Register File */
89 #define DAVINCI_MCASP_DITCSRB_REG 0x118
90 /* Left(even TDM slot) User Data Register File */
91 #define DAVINCI_MCASP_DITUDRA_REG 0x130
92 /* Right(odd TDM Slot) User Data Register File */
93 #define DAVINCI_MCASP_DITUDRB_REG 0x148
94
95 /* Serializer n Control Register */
96 #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
97 #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
98 (n << 2))
99
100 /* Transmit Buffer for Serializer n */
101 #define DAVINCI_MCASP_TXBUF_REG 0x200
102 /* Receive Buffer for Serializer n */
103 #define DAVINCI_MCASP_RXBUF_REG 0x280
104
105 /* McASP FIFO Registers */
106 #define DAVINCI_MCASP_WFIFOCTL (0x1010)
107 #define DAVINCI_MCASP_WFIFOSTS (0x1014)
108 #define DAVINCI_MCASP_RFIFOCTL (0x1018)
109 #define DAVINCI_MCASP_RFIFOSTS (0x101C)
110
111 /*
112 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
113 * Register Bits
114 */
115 #define MCASP_FREE BIT(0)
116 #define MCASP_SOFT BIT(1)
117
118 /*
119 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
120 */
121 #define AXR(n) (1<<n)
122 #define PFUNC_AMUTE BIT(25)
123 #define ACLKX BIT(26)
124 #define AHCLKX BIT(27)
125 #define AFSX BIT(28)
126 #define ACLKR BIT(29)
127 #define AHCLKR BIT(30)
128 #define AFSR BIT(31)
129
130 /*
131 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
132 */
133 #define AXR(n) (1<<n)
134 #define PDIR_AMUTE BIT(25)
135 #define ACLKX BIT(26)
136 #define AHCLKX BIT(27)
137 #define AFSX BIT(28)
138 #define ACLKR BIT(29)
139 #define AHCLKR BIT(30)
140 #define AFSR BIT(31)
141
142 /*
143 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
144 */
145 #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
146 #define VA BIT(2)
147 #define VB BIT(3)
148
149 /*
150 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
151 */
152 #define TXROT(val) (val)
153 #define TXSEL BIT(3)
154 #define TXSSZ(val) (val<<4)
155 #define TXPBIT(val) (val<<8)
156 #define TXPAD(val) (val<<13)
157 #define TXORD BIT(15)
158 #define FSXDLY(val) (val<<16)
159
160 /*
161 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
162 */
163 #define RXROT(val) (val)
164 #define RXSEL BIT(3)
165 #define RXSSZ(val) (val<<4)
166 #define RXPBIT(val) (val<<8)
167 #define RXPAD(val) (val<<13)
168 #define RXORD BIT(15)
169 #define FSRDLY(val) (val<<16)
170
171 /*
172 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
173 */
174 #define FSXPOL BIT(0)
175 #define AFSXE BIT(1)
176 #define FSXDUR BIT(4)
177 #define FSXMOD(val) (val<<7)
178
179 /*
180 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
181 */
182 #define FSRPOL BIT(0)
183 #define AFSRE BIT(1)
184 #define FSRDUR BIT(4)
185 #define FSRMOD(val) (val<<7)
186
187 /*
188 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
189 */
190 #define ACLKXDIV(val) (val)
191 #define ACLKXE BIT(5)
192 #define TX_ASYNC BIT(6)
193 #define ACLKXPOL BIT(7)
194
195 /*
196 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
197 */
198 #define ACLKRDIV(val) (val)
199 #define ACLKRE BIT(5)
200 #define RX_ASYNC BIT(6)
201 #define ACLKRPOL BIT(7)
202
203 /*
204 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
205 * Register Bits
206 */
207 #define AHCLKXDIV(val) (val)
208 #define AHCLKXPOL BIT(14)
209 #define AHCLKXE BIT(15)
210
211 /*
212 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
213 * Register Bits
214 */
215 #define AHCLKRDIV(val) (val)
216 #define AHCLKRPOL BIT(14)
217 #define AHCLKRE BIT(15)
218
219 /*
220 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
221 */
222 #define MODE(val) (val)
223 #define DISMOD (val)(val<<2)
224 #define TXSTATE BIT(4)
225 #define RXSTATE BIT(5)
226
227 /*
228 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
229 */
230 #define LBEN BIT(0)
231 #define LBORD BIT(1)
232 #define LBGENMODE(val) (val<<2)
233
234 /*
235 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
236 */
237 #define TXTDMS(n) (1<<n)
238
239 /*
240 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
241 */
242 #define RXTDMS(n) (1<<n)
243
244 /*
245 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
246 */
247 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
248 #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
249 #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
250 #define RXSMRST BIT(3) /* Receiver State Machine Reset */
251 #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
252 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
253 #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
254 #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
255 #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
256 #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
257
258 /*
259 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
260 */
261 #define MUTENA(val) (val)
262 #define MUTEINPOL BIT(2)
263 #define MUTEINENA BIT(3)
264 #define MUTEIN BIT(4)
265 #define MUTER BIT(5)
266 #define MUTEX BIT(6)
267 #define MUTEFSR BIT(7)
268 #define MUTEFSX BIT(8)
269 #define MUTEBADCLKR BIT(9)
270 #define MUTEBADCLKX BIT(10)
271 #define MUTERXDMAERR BIT(11)
272 #define MUTETXDMAERR BIT(12)
273
274 /*
275 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
276 */
277 #define RXDATADMADIS BIT(0)
278
279 /*
280 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
281 */
282 #define TXDATADMADIS BIT(0)
283
284 /*
285 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
286 */
287 #define FIFO_ENABLE BIT(16)
288 #define NUMEVT_MASK (0xFF << 8)
289 #define NUMDMA_MASK (0xFF)
290
291 #define DAVINCI_MCASP_NUM_SERIALIZER 16
292
293 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
294 {
295 __raw_writel(__raw_readl(reg) | val, reg);
296 }
297
298 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
299 {
300 __raw_writel((__raw_readl(reg) & ~(val)), reg);
301 }
302
303 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
304 {
305 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
306 }
307
308 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
309 {
310 __raw_writel(val, reg);
311 }
312
313 static inline u32 mcasp_get_reg(void __iomem *reg)
314 {
315 return (unsigned int)__raw_readl(reg);
316 }
317
318 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
319 {
320 int i = 0;
321
322 mcasp_set_bits(regs, val);
323
324 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
325 /* loop count is to avoid the lock-up */
326 for (i = 0; i < 1000; i++) {
327 if ((mcasp_get_reg(regs) & val) == val)
328 break;
329 }
330
331 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
332 printk(KERN_ERR "GBLCTL write error\n");
333 }
334
335 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
336 struct snd_soc_dai *cpu_dai)
337 {
338 struct davinci_audio_dev *dev = cpu_dai->private_data;
339 cpu_dai->dma_data = dev->dma_params[substream->stream];
340 return 0;
341 }
342
343 static void mcasp_start_rx(struct davinci_audio_dev *dev)
344 {
345 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
346 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
347 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
348 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
349
350 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
351 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
352 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
353
354 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
355 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
356 }
357
358 static void mcasp_start_tx(struct davinci_audio_dev *dev)
359 {
360 u8 offset = 0, i;
361 u32 cnt;
362
363 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
364 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
365 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
366 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
367
368 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
369 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
370 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
371 for (i = 0; i < dev->num_serializer; i++) {
372 if (dev->serial_dir[i] == TX_MODE) {
373 offset = i;
374 break;
375 }
376 }
377
378 /* wait for TX ready */
379 cnt = 0;
380 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
381 TXSTATE) && (cnt < 100000))
382 cnt++;
383
384 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
385 }
386
387 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
388 {
389 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
390 mcasp_start_tx(dev);
391 else
392 mcasp_start_rx(dev);
393
394 /* enable FIFO */
395 if (dev->txnumevt)
396 mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
397
398 if (dev->rxnumevt)
399 mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
400 }
401
402 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
403 {
404 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
405 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
406 }
407
408 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
409 {
410 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
411 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
412 }
413
414 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
415 {
416 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
417 mcasp_stop_tx(dev);
418 else
419 mcasp_stop_rx(dev);
420
421 /* disable FIFO */
422 if (dev->txnumevt)
423 mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
424
425 if (dev->rxnumevt)
426 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
427 }
428
429 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
430 unsigned int fmt)
431 {
432 struct davinci_audio_dev *dev = cpu_dai->private_data;
433 void __iomem *base = dev->base;
434
435 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
436 case SND_SOC_DAIFMT_CBS_CFS:
437 /* codec is clock and frame slave */
438 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
439 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
440
441 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
442 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
443
444 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26));
445 break;
446 case SND_SOC_DAIFMT_CBM_CFS:
447 /* codec is clock master and frame slave */
448 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
449 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
450
451 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
452 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
453
454 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x2d << 26));
455 break;
456 case SND_SOC_DAIFMT_CBM_CFM:
457 /* codec is clock and frame master */
458 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
459 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
460
461 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
462 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
463
464 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, (0x3f << 26));
465 break;
466
467 default:
468 return -EINVAL;
469 }
470
471 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
472 case SND_SOC_DAIFMT_IB_NF:
473 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
474 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
475
476 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
477 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
478 break;
479
480 case SND_SOC_DAIFMT_NB_IF:
481 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
482 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
483
484 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
485 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
486 break;
487
488 case SND_SOC_DAIFMT_IB_IF:
489 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
490 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
491
492 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
493 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
494 break;
495
496 case SND_SOC_DAIFMT_NB_NF:
497 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
498 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
499
500 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
501 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
502 break;
503
504 default:
505 return -EINVAL;
506 }
507
508 return 0;
509 }
510
511 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
512 int channel_size)
513 {
514 u32 fmt = 0;
515
516 switch (channel_size) {
517 case DAVINCI_AUDIO_WORD_8:
518 fmt = 0x03;
519 break;
520
521 case DAVINCI_AUDIO_WORD_12:
522 fmt = 0x05;
523 break;
524
525 case DAVINCI_AUDIO_WORD_16:
526 fmt = 0x07;
527 break;
528
529 case DAVINCI_AUDIO_WORD_20:
530 fmt = 0x09;
531 break;
532
533 case DAVINCI_AUDIO_WORD_24:
534 fmt = 0x0B;
535 break;
536
537 case DAVINCI_AUDIO_WORD_28:
538 fmt = 0x0D;
539 break;
540
541 case DAVINCI_AUDIO_WORD_32:
542 fmt = 0x0F;
543 break;
544
545 default:
546 return -EINVAL;
547 }
548
549 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
550 RXSSZ(fmt), RXSSZ(0x0F));
551 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
552 TXSSZ(fmt), TXSSZ(0x0F));
553 return 0;
554 }
555
556 static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
557 {
558 int i;
559 u8 tx_ser = 0;
560 u8 rx_ser = 0;
561
562 /* Default configuration */
563 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
564
565 /* All PINS as McASP */
566 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
567
568 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
569 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
570 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
571 TXDATADMADIS);
572 } else {
573 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
574 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
575 RXDATADMADIS);
576 }
577
578 for (i = 0; i < dev->num_serializer; i++) {
579 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
580 dev->serial_dir[i]);
581 if (dev->serial_dir[i] == TX_MODE) {
582 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
583 AXR(i));
584 tx_ser++;
585 } else if (dev->serial_dir[i] == RX_MODE) {
586 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
587 AXR(i));
588 rx_ser++;
589 }
590 }
591
592 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
593 if (dev->txnumevt * tx_ser > 64)
594 dev->txnumevt = 1;
595
596 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, tx_ser,
597 NUMDMA_MASK);
598 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
599 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
600 mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
601 }
602
603 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
604 if (dev->rxnumevt * rx_ser > 64)
605 dev->rxnumevt = 1;
606
607 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, rx_ser,
608 NUMDMA_MASK);
609 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
610 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
611 mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
612 }
613 }
614
615 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
616 {
617 int i, active_slots;
618 u32 mask = 0;
619
620 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
621 for (i = 0; i < active_slots; i++)
622 mask |= (1 << i);
623
624 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
625
626 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
627 /* bit stream is MSB first with no delay */
628 /* DSP_B mode */
629 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
630 AHCLKXE);
631 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
632 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
633
634 if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
635 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
636 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
637 else
638 printk(KERN_ERR "playback tdm slot %d not supported\n",
639 dev->tdm_slots);
640
641 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0xFFFFFFFF);
642 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
643 } else {
644 /* bit stream is MSB first with no delay */
645 /* DSP_B mode */
646 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
647 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
648 AHCLKRE);
649 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
650
651 if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
652 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
653 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
654 else
655 printk(KERN_ERR "capture tdm slot %d not supported\n",
656 dev->tdm_slots);
657
658 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, 0xFFFFFFFF);
659 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
660 }
661 }
662
663 /* S/PDIF */
664 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
665 {
666 /* Set the PDIR for Serialiser as output */
667 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
668
669 /* TXMASK for 24 bits */
670 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
671
672 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
673 and LSB first */
674 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
675 TXROT(6) | TXSSZ(15));
676
677 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
678 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
679 AFSXE | FSXMOD(0x180));
680
681 /* Set the TX tdm : for all the slots */
682 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
683
684 /* Set the TX clock controls : div = 1 and internal */
685 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
686 ACLKXE | TX_ASYNC);
687
688 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
689
690 /* Only 44100 and 48000 are valid, both have the same setting */
691 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
692
693 /* Enable the DIT */
694 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
695 }
696
697 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
698 struct snd_pcm_hw_params *params,
699 struct snd_soc_dai *cpu_dai)
700 {
701 struct davinci_audio_dev *dev = cpu_dai->private_data;
702 struct davinci_pcm_dma_params *dma_params =
703 dev->dma_params[substream->stream];
704 int word_length;
705 u8 numevt;
706
707 davinci_hw_common_param(dev, substream->stream);
708 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
709 numevt = dev->txnumevt;
710 else
711 numevt = dev->rxnumevt;
712
713 if (!numevt)
714 numevt = 1;
715
716 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
717 davinci_hw_dit_param(dev);
718 else
719 davinci_hw_param(dev, substream->stream);
720
721 switch (params_format(params)) {
722 case SNDRV_PCM_FORMAT_S8:
723 dma_params->data_type = 1;
724 word_length = DAVINCI_AUDIO_WORD_8;
725 break;
726
727 case SNDRV_PCM_FORMAT_S16_LE:
728 dma_params->data_type = 2;
729 word_length = DAVINCI_AUDIO_WORD_16;
730 break;
731
732 case SNDRV_PCM_FORMAT_S32_LE:
733 dma_params->data_type = 4;
734 word_length = DAVINCI_AUDIO_WORD_32;
735 break;
736
737 default:
738 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
739 return -EINVAL;
740 }
741
742 if (dev->version == MCASP_VERSION_2) {
743 dma_params->data_type *= numevt;
744 dma_params->acnt = 4 * numevt;
745 } else
746 dma_params->acnt = dma_params->data_type;
747
748 davinci_config_channel_size(dev, word_length);
749
750 return 0;
751 }
752
753 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
754 int cmd, struct snd_soc_dai *cpu_dai)
755 {
756 struct snd_soc_pcm_runtime *rtd = substream->private_data;
757 struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data;
758 int ret = 0;
759
760 switch (cmd) {
761 case SNDRV_PCM_TRIGGER_START:
762 case SNDRV_PCM_TRIGGER_RESUME:
763 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
764 davinci_mcasp_start(dev, substream->stream);
765 break;
766
767 case SNDRV_PCM_TRIGGER_STOP:
768 case SNDRV_PCM_TRIGGER_SUSPEND:
769 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
770 davinci_mcasp_stop(dev, substream->stream);
771 break;
772
773 default:
774 ret = -EINVAL;
775 }
776
777 return ret;
778 }
779
780 static struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
781 .startup = davinci_mcasp_startup,
782 .trigger = davinci_mcasp_trigger,
783 .hw_params = davinci_mcasp_hw_params,
784 .set_fmt = davinci_mcasp_set_dai_fmt,
785
786 };
787
788 struct snd_soc_dai davinci_mcasp_dai[] = {
789 {
790 .name = "davinci-i2s",
791 .id = 0,
792 .playback = {
793 .channels_min = 2,
794 .channels_max = 2,
795 .rates = DAVINCI_MCASP_RATES,
796 .formats = SNDRV_PCM_FMTBIT_S8 |
797 SNDRV_PCM_FMTBIT_S16_LE |
798 SNDRV_PCM_FMTBIT_S32_LE,
799 },
800 .capture = {
801 .channels_min = 2,
802 .channels_max = 2,
803 .rates = DAVINCI_MCASP_RATES,
804 .formats = SNDRV_PCM_FMTBIT_S8 |
805 SNDRV_PCM_FMTBIT_S16_LE |
806 SNDRV_PCM_FMTBIT_S32_LE,
807 },
808 .ops = &davinci_mcasp_dai_ops,
809
810 },
811 {
812 .name = "davinci-dit",
813 .id = 1,
814 .playback = {
815 .channels_min = 1,
816 .channels_max = 384,
817 .rates = DAVINCI_MCASP_RATES,
818 .formats = SNDRV_PCM_FMTBIT_S16_LE,
819 },
820 .ops = &davinci_mcasp_dai_ops,
821 },
822
823 };
824 EXPORT_SYMBOL_GPL(davinci_mcasp_dai);
825
826 static int davinci_mcasp_probe(struct platform_device *pdev)
827 {
828 struct davinci_pcm_dma_params *dma_data;
829 struct resource *mem, *ioarea, *res;
830 struct snd_platform_data *pdata;
831 struct davinci_audio_dev *dev;
832 int count = 0;
833 int ret = 0;
834
835 dev = kzalloc(sizeof(struct davinci_audio_dev), GFP_KERNEL);
836 if (!dev)
837 return -ENOMEM;
838
839 dma_data = kzalloc(sizeof(struct davinci_pcm_dma_params) * 2,
840 GFP_KERNEL);
841 if (!dma_data) {
842 ret = -ENOMEM;
843 goto err_release_dev;
844 }
845
846 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
847 if (!mem) {
848 dev_err(&pdev->dev, "no mem resource?\n");
849 ret = -ENODEV;
850 goto err_release_data;
851 }
852
853 ioarea = request_mem_region(mem->start,
854 (mem->end - mem->start) + 1, pdev->name);
855 if (!ioarea) {
856 dev_err(&pdev->dev, "Audio region already claimed\n");
857 ret = -EBUSY;
858 goto err_release_data;
859 }
860
861 pdata = pdev->dev.platform_data;
862 dev->clk = clk_get(&pdev->dev, NULL);
863 if (IS_ERR(dev->clk)) {
864 ret = -ENODEV;
865 goto err_release_region;
866 }
867
868 clk_enable(dev->clk);
869
870 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
871 dev->op_mode = pdata->op_mode;
872 dev->tdm_slots = pdata->tdm_slots;
873 dev->num_serializer = pdata->num_serializer;
874 dev->serial_dir = pdata->serial_dir;
875 dev->codec_fmt = pdata->codec_fmt;
876 dev->version = pdata->version;
877 dev->txnumevt = pdata->txnumevt;
878 dev->rxnumevt = pdata->rxnumevt;
879
880 dma_data[count].name = "I2S PCM Stereo out";
881 dma_data[count].eventq_no = pdata->eventq_no;
882 dma_data[count].dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
883 io_v2p(dev->base));
884 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &dma_data[count];
885
886 /* first TX, then RX */
887 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
888 if (!res) {
889 dev_err(&pdev->dev, "no DMA resource\n");
890 goto err_release_region;
891 }
892
893 dma_data[count].channel = res->start;
894 count++;
895 dma_data[count].name = "I2S PCM Stereo in";
896 dma_data[count].eventq_no = pdata->eventq_no;
897 dma_data[count].dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
898 io_v2p(dev->base));
899 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &dma_data[count];
900
901 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
902 if (!res) {
903 dev_err(&pdev->dev, "no DMA resource\n");
904 goto err_release_region;
905 }
906
907 dma_data[count].channel = res->start;
908 davinci_mcasp_dai[pdata->op_mode].private_data = dev;
909 davinci_mcasp_dai[pdata->op_mode].dev = &pdev->dev;
910 ret = snd_soc_register_dai(&davinci_mcasp_dai[pdata->op_mode]);
911
912 if (ret != 0)
913 goto err_release_region;
914 return 0;
915
916 err_release_region:
917 release_mem_region(mem->start, (mem->end - mem->start) + 1);
918 err_release_data:
919 kfree(dma_data);
920 err_release_dev:
921 kfree(dev);
922
923 return ret;
924 }
925
926 static int davinci_mcasp_remove(struct platform_device *pdev)
927 {
928 struct snd_platform_data *pdata = pdev->dev.platform_data;
929 struct davinci_pcm_dma_params *dma_data;
930 struct davinci_audio_dev *dev;
931 struct resource *mem;
932
933 snd_soc_unregister_dai(&davinci_mcasp_dai[pdata->op_mode]);
934 dev = davinci_mcasp_dai[pdata->op_mode].private_data;
935 clk_disable(dev->clk);
936 clk_put(dev->clk);
937 dev->clk = NULL;
938
939 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
940 release_mem_region(mem->start, (mem->end - mem->start) + 1);
941
942 dma_data = dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
943 kfree(dma_data);
944 kfree(dev);
945
946 return 0;
947 }
948
949 static struct platform_driver davinci_mcasp_driver = {
950 .probe = davinci_mcasp_probe,
951 .remove = davinci_mcasp_remove,
952 .driver = {
953 .name = "davinci-mcasp",
954 .owner = THIS_MODULE,
955 },
956 };
957
958 static int __init davinci_mcasp_init(void)
959 {
960 return platform_driver_register(&davinci_mcasp_driver);
961 }
962 module_init(davinci_mcasp_init);
963
964 static void __exit davinci_mcasp_exit(void)
965 {
966 platform_driver_unregister(&davinci_mcasp_driver);
967 }
968 module_exit(davinci_mcasp_exit);
969
970 MODULE_AUTHOR("Steve Chen");
971 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
972 MODULE_LICENSE("GPL");
973
Linux with added FPC-III support