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[ALSA] oxygen: generalize handling of DAC volume limits
[linux/fpc-iii.git] / include / asm-x86 / paravirt.h
blob3d419398499b4a6fe14de3eec92761f2e80ba19a
1 #ifndef __ASM_PARAVIRT_H
2 #define __ASM_PARAVIRT_H
3 /* Various instructions on x86 need to be replaced for
4 * para-virtualization: those hooks are defined here. */
5
6 #ifdef CONFIG_PARAVIRT
7 #include <asm/page.h>
8 #include <asm/asm.h>
9
10 /* Bitmask of what can be clobbered: usually at least eax. */
11 #define CLBR_NONE 0
12 #define CLBR_EAX (1 << 0)
13 #define CLBR_ECX (1 << 1)
14 #define CLBR_EDX (1 << 2)
15
16 #ifdef CONFIG_X86_64
17 #define CLBR_RSI (1 << 3)
18 #define CLBR_RDI (1 << 4)
19 #define CLBR_R8 (1 << 5)
20 #define CLBR_R9 (1 << 6)
21 #define CLBR_R10 (1 << 7)
22 #define CLBR_R11 (1 << 8)
23 #define CLBR_ANY ((1 << 9) - 1)
24 #include <asm/desc_defs.h>
25 #else
26 /* CLBR_ANY should match all regs platform has. For i386, that's just it */
27 #define CLBR_ANY ((1 << 3) - 1)
28 #endif /* X86_64 */
29
30 #ifndef __ASSEMBLY__
31 #include <linux/types.h>
32 #include <linux/cpumask.h>
33 #include <asm/kmap_types.h>
34 #include <asm/desc_defs.h>
35
36 struct page;
37 struct thread_struct;
38 struct desc_ptr;
39 struct tss_struct;
40 struct mm_struct;
41 struct desc_struct;
42
43 /* general info */
44 struct pv_info {
45 unsigned int kernel_rpl;
46 int shared_kernel_pmd;
47 int paravirt_enabled;
48 const char *name;
49 };
50
51 struct pv_init_ops {
52 /*
53 * Patch may replace one of the defined code sequences with
54 * arbitrary code, subject to the same register constraints.
55 * This generally means the code is not free to clobber any
56 * registers other than EAX. The patch function should return
57 * the number of bytes of code generated, as we nop pad the
58 * rest in generic code.
59 */
60 unsigned (*patch)(u8 type, u16 clobber, void *insnbuf,
61 unsigned long addr, unsigned len);
62
63 /* Basic arch-specific setup */
64 void (*arch_setup)(void);
65 char *(*memory_setup)(void);
66 void (*post_allocator_init)(void);
67
68 /* Print a banner to identify the environment */
69 void (*banner)(void);
70 };
71
72
73 struct pv_lazy_ops {
74 /* Set deferred update mode, used for batching operations. */
75 void (*enter)(void);
76 void (*leave)(void);
77 };
78
79 struct pv_time_ops {
80 void (*time_init)(void);
81
82 /* Set and set time of day */
83 unsigned long (*get_wallclock)(void);
84 int (*set_wallclock)(unsigned long);
85
86 unsigned long long (*sched_clock)(void);
87 unsigned long (*get_cpu_khz)(void);
88 };
89
90 struct pv_cpu_ops {
91 /* hooks for various privileged instructions */
92 unsigned long (*get_debugreg)(int regno);
93 void (*set_debugreg)(int regno, unsigned long value);
94
95 void (*clts)(void);
96
97 unsigned long (*read_cr0)(void);
98 void (*write_cr0)(unsigned long);
99
100 unsigned long (*read_cr4_safe)(void);
101 unsigned long (*read_cr4)(void);
102 void (*write_cr4)(unsigned long);
103
104 #ifdef CONFIG_X86_64
105 unsigned long (*read_cr8)(void);
106 void (*write_cr8)(unsigned long);
107 #endif
108
109 /* Segment descriptor handling */
110 void (*load_tr_desc)(void);
111 void (*load_gdt)(const struct desc_ptr *);
112 void (*load_idt)(const struct desc_ptr *);
113 void (*store_gdt)(struct desc_ptr *);
114 void (*store_idt)(struct desc_ptr *);
115 void (*set_ldt)(const void *desc, unsigned entries);
116 unsigned long (*store_tr)(void);
117 void (*load_tls)(struct thread_struct *t, unsigned int cpu);
118 void (*write_ldt_entry)(struct desc_struct *ldt, int entrynum,
119 const void *desc);
120 void (*write_gdt_entry)(struct desc_struct *,
121 int entrynum, const void *desc, int size);
122 void (*write_idt_entry)(gate_desc *,
123 int entrynum, const gate_desc *gate);
124 void (*load_sp0)(struct tss_struct *tss, struct thread_struct *t);
125
126 void (*set_iopl_mask)(unsigned mask);
127
128 void (*wbinvd)(void);
129 void (*io_delay)(void);
130
131 /* cpuid emulation, mostly so that caps bits can be disabled */
132 void (*cpuid)(unsigned int *eax, unsigned int *ebx,
133 unsigned int *ecx, unsigned int *edx);
134
135 /* MSR, PMC and TSR operations.
136 err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */
137 u64 (*read_msr)(unsigned int msr, int *err);
138 int (*write_msr)(unsigned int msr, unsigned low, unsigned high);
139
140 u64 (*read_tsc)(void);
141 u64 (*read_pmc)(int counter);
142 unsigned long long (*read_tscp)(unsigned int *aux);
143
144 /* These two are jmp to, not actually called. */
145 void (*irq_enable_syscall_ret)(void);
146 void (*iret)(void);
147
148 void (*swapgs)(void);
149
150 struct pv_lazy_ops lazy_mode;
151 };
152
153 struct pv_irq_ops {
154 void (*init_IRQ)(void);
155
156 /*
157 * Get/set interrupt state. save_fl and restore_fl are only
158 * expected to use X86_EFLAGS_IF; all other bits
159 * returned from save_fl are undefined, and may be ignored by
160 * restore_fl.
161 */
162 unsigned long (*save_fl)(void);
163 void (*restore_fl)(unsigned long);
164 void (*irq_disable)(void);
165 void (*irq_enable)(void);
166 void (*safe_halt)(void);
167 void (*halt)(void);
168 };
169
170 struct pv_apic_ops {
171 #ifdef CONFIG_X86_LOCAL_APIC
172 /*
173 * Direct APIC operations, principally for VMI. Ideally
174 * these shouldn't be in this interface.
175 */
176 void (*apic_write)(unsigned long reg, u32 v);
177 void (*apic_write_atomic)(unsigned long reg, u32 v);
178 u32 (*apic_read)(unsigned long reg);
179 void (*setup_boot_clock)(void);
180 void (*setup_secondary_clock)(void);
181
182 void (*startup_ipi_hook)(int phys_apicid,
183 unsigned long start_eip,
184 unsigned long start_esp);
185 #endif
186 };
187
188 struct pv_mmu_ops {
189 /*
190 * Called before/after init_mm pagetable setup. setup_start
191 * may reset %cr3, and may pre-install parts of the pagetable;
192 * pagetable setup is expected to preserve any existing
193 * mapping.
194 */
195 void (*pagetable_setup_start)(pgd_t *pgd_base);
196 void (*pagetable_setup_done)(pgd_t *pgd_base);
197
198 unsigned long (*read_cr2)(void);
199 void (*write_cr2)(unsigned long);
200
201 unsigned long (*read_cr3)(void);
202 void (*write_cr3)(unsigned long);
203
204 /*
205 * Hooks for intercepting the creation/use/destruction of an
206 * mm_struct.
207 */
208 void (*activate_mm)(struct mm_struct *prev,
209 struct mm_struct *next);
210 void (*dup_mmap)(struct mm_struct *oldmm,
211 struct mm_struct *mm);
212 void (*exit_mmap)(struct mm_struct *mm);
213
214
215 /* TLB operations */
216 void (*flush_tlb_user)(void);
217 void (*flush_tlb_kernel)(void);
218 void (*flush_tlb_single)(unsigned long addr);
219 void (*flush_tlb_others)(const cpumask_t *cpus, struct mm_struct *mm,
220 unsigned long va);
221
222 /* Hooks for allocating/releasing pagetable pages */
223 void (*alloc_pt)(struct mm_struct *mm, u32 pfn);
224 void (*alloc_pd)(struct mm_struct *mm, u32 pfn);
225 void (*alloc_pd_clone)(u32 pfn, u32 clonepfn, u32 start, u32 count);
226 void (*release_pt)(u32 pfn);
227 void (*release_pd)(u32 pfn);
228
229 /* Pagetable manipulation functions */
230 void (*set_pte)(pte_t *ptep, pte_t pteval);
231 void (*set_pte_at)(struct mm_struct *mm, unsigned long addr,
232 pte_t *ptep, pte_t pteval);
233 void (*set_pmd)(pmd_t *pmdp, pmd_t pmdval);
234 void (*pte_update)(struct mm_struct *mm, unsigned long addr,
235 pte_t *ptep);
236 void (*pte_update_defer)(struct mm_struct *mm,
237 unsigned long addr, pte_t *ptep);
238
239 pteval_t (*pte_val)(pte_t);
240 pte_t (*make_pte)(pteval_t pte);
241
242 pgdval_t (*pgd_val)(pgd_t);
243 pgd_t (*make_pgd)(pgdval_t pgd);
244
245 #if PAGETABLE_LEVELS >= 3
246 #ifdef CONFIG_X86_PAE
247 void (*set_pte_atomic)(pte_t *ptep, pte_t pteval);
248 void (*set_pte_present)(struct mm_struct *mm, unsigned long addr,
249 pte_t *ptep, pte_t pte);
250 void (*pte_clear)(struct mm_struct *mm, unsigned long addr,
251 pte_t *ptep);
252 void (*pmd_clear)(pmd_t *pmdp);
253
254 #endif /* CONFIG_X86_PAE */
255
256 void (*set_pud)(pud_t *pudp, pud_t pudval);
257
258 pmdval_t (*pmd_val)(pmd_t);
259 pmd_t (*make_pmd)(pmdval_t pmd);
260
261 #if PAGETABLE_LEVELS == 4
262 pudval_t (*pud_val)(pud_t);
263 pud_t (*make_pud)(pudval_t pud);
264
265 void (*set_pgd)(pgd_t *pudp, pgd_t pgdval);
266 #endif /* PAGETABLE_LEVELS == 4 */
267 #endif /* PAGETABLE_LEVELS >= 3 */
268
269 #ifdef CONFIG_HIGHPTE
270 void *(*kmap_atomic_pte)(struct page *page, enum km_type type);
271 #endif
272
273 struct pv_lazy_ops lazy_mode;
274 };
275
276 /* This contains all the paravirt structures: we get a convenient
277 * number for each function using the offset which we use to indicate
278 * what to patch. */
279 struct paravirt_patch_template {
280 struct pv_init_ops pv_init_ops;
281 struct pv_time_ops pv_time_ops;
282 struct pv_cpu_ops pv_cpu_ops;
283 struct pv_irq_ops pv_irq_ops;
284 struct pv_apic_ops pv_apic_ops;
285 struct pv_mmu_ops pv_mmu_ops;
286 };
287
288 extern struct pv_info pv_info;
289 extern struct pv_init_ops pv_init_ops;
290 extern struct pv_time_ops pv_time_ops;
291 extern struct pv_cpu_ops pv_cpu_ops;
292 extern struct pv_irq_ops pv_irq_ops;
293 extern struct pv_apic_ops pv_apic_ops;
294 extern struct pv_mmu_ops pv_mmu_ops;
295
296 #define PARAVIRT_PATCH(x) \
297 (offsetof(struct paravirt_patch_template, x) / sizeof(void *))
298
299 #define paravirt_type(op) \
300 [paravirt_typenum] "i" (PARAVIRT_PATCH(op)), \
301 [paravirt_opptr] "m" (op)
302 #define paravirt_clobber(clobber) \
303 [paravirt_clobber] "i" (clobber)
304
305 /*
306 * Generate some code, and mark it as patchable by the
307 * apply_paravirt() alternate instruction patcher.
308 */
309 #define _paravirt_alt(insn_string, type, clobber) \
310 "771:\n\t" insn_string "\n" "772:\n" \
311 ".pushsection .parainstructions,\"a\"\n" \
312 _ASM_ALIGN "\n" \
313 _ASM_PTR " 771b\n" \
314 " .byte " type "\n" \
315 " .byte 772b-771b\n" \
316 " .short " clobber "\n" \
317 ".popsection\n"
318
319 /* Generate patchable code, with the default asm parameters. */
320 #define paravirt_alt(insn_string) \
321 _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]")
322
323 /* Simple instruction patching code. */
324 #define DEF_NATIVE(ops, name, code) \
325 extern const char start_##ops##_##name[], end_##ops##_##name[]; \
326 asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":")
327
328 unsigned paravirt_patch_nop(void);
329 unsigned paravirt_patch_ignore(unsigned len);
330 unsigned paravirt_patch_call(void *insnbuf,
331 const void *target, u16 tgt_clobbers,
332 unsigned long addr, u16 site_clobbers,
333 unsigned len);
334 unsigned paravirt_patch_jmp(void *insnbuf, const void *target,
335 unsigned long addr, unsigned len);
336 unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf,
337 unsigned long addr, unsigned len);
338
339 unsigned paravirt_patch_insns(void *insnbuf, unsigned len,
340 const char *start, const char *end);
341
342 unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
343 unsigned long addr, unsigned len);
344
345 int paravirt_disable_iospace(void);
346
347 /*
348 * This generates an indirect call based on the operation type number.
349 * The type number, computed in PARAVIRT_PATCH, is derived from the
350 * offset into the paravirt_patch_template structure, and can therefore be
351 * freely converted back into a structure offset.
352 */
353 #define PARAVIRT_CALL "call *%[paravirt_opptr];"
354
355 /*
356 * These macros are intended to wrap calls through one of the paravirt
357 * ops structs, so that they can be later identified and patched at
358 * runtime.
359 *
360 * Normally, a call to a pv_op function is a simple indirect call:
361 * (pv_op_struct.operations)(args...).
362 *
363 * Unfortunately, this is a relatively slow operation for modern CPUs,
364 * because it cannot necessarily determine what the destination
365 * address is. In this case, the address is a runtime constant, so at
366 * the very least we can patch the call to e a simple direct call, or
367 * ideally, patch an inline implementation into the callsite. (Direct
368 * calls are essentially free, because the call and return addresses
369 * are completely predictable.)
370 *
371 * For i386, these macros rely on the standard gcc "regparm(3)" calling
372 * convention, in which the first three arguments are placed in %eax,
373 * %edx, %ecx (in that order), and the remaining arguments are placed
374 * on the stack. All caller-save registers (eax,edx,ecx) are expected
375 * to be modified (either clobbered or used for return values).
376 * X86_64, on the other hand, already specifies a register-based calling
377 * conventions, returning at %rax, with parameteres going on %rdi, %rsi,
378 * %rdx, and %rcx. Note that for this reason, x86_64 does not need any
379 * special handling for dealing with 4 arguments, unlike i386.
380 * However, x86_64 also have to clobber all caller saved registers, which
381 * unfortunately, are quite a bit (r8 - r11)
382 *
383 * The call instruction itself is marked by placing its start address
384 * and size into the .parainstructions section, so that
385 * apply_paravirt() in arch/i386/kernel/alternative.c can do the
386 * appropriate patching under the control of the backend pv_init_ops
387 * implementation.
388 *
389 * Unfortunately there's no way to get gcc to generate the args setup
390 * for the call, and then allow the call itself to be generated by an
391 * inline asm. Because of this, we must do the complete arg setup and
392 * return value handling from within these macros. This is fairly
393 * cumbersome.
394 *
395 * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments.
396 * It could be extended to more arguments, but there would be little
397 * to be gained from that. For each number of arguments, there are
398 * the two VCALL and CALL variants for void and non-void functions.
399 *
400 * When there is a return value, the invoker of the macro must specify
401 * the return type. The macro then uses sizeof() on that type to
402 * determine whether its a 32 or 64 bit value, and places the return
403 * in the right register(s) (just %eax for 32-bit, and %edx:%eax for
404 * 64-bit). For x86_64 machines, it just returns at %rax regardless of
405 * the return value size.
406 *
407 * 64-bit arguments are passed as a pair of adjacent 32-bit arguments
408 * i386 also passes 64-bit arguments as a pair of adjacent 32-bit arguments
409 * in low,high order
410 *
411 * Small structures are passed and returned in registers. The macro
412 * calling convention can't directly deal with this, so the wrapper
413 * functions must do this.
414 *
415 * These PVOP_* macros are only defined within this header. This
416 * means that all uses must be wrapped in inline functions. This also
417 * makes sure the incoming and outgoing types are always correct.
418 */
419 #ifdef CONFIG_X86_32
420 #define PVOP_VCALL_ARGS unsigned long __eax, __edx, __ecx
421 #define PVOP_CALL_ARGS PVOP_VCALL_ARGS
422 #define PVOP_VCALL_CLOBBERS "=a" (__eax), "=d" (__edx), \
423 "=c" (__ecx)
424 #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS
425 #define EXTRA_CLOBBERS
426 #define VEXTRA_CLOBBERS
427 #else
428 #define PVOP_VCALL_ARGS unsigned long __edi, __esi, __edx, __ecx
429 #define PVOP_CALL_ARGS PVOP_VCALL_ARGS, __eax
430 #define PVOP_VCALL_CLOBBERS "=D" (__edi), \
431 "=S" (__esi), "=d" (__edx), \
432 "=c" (__ecx)
433
434 #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS, "=a" (__eax)
435
436 #define EXTRA_CLOBBERS , "r8", "r9", "r10", "r11"
437 #define VEXTRA_CLOBBERS , "rax", "r8", "r9", "r10", "r11"
438 #endif
439
440 #define __PVOP_CALL(rettype, op, pre, post, ...) \
441 ({ \
442 rettype __ret; \
443 PVOP_CALL_ARGS; \
444 /* This is 32-bit specific, but is okay in 64-bit */ \
445 /* since this condition will never hold */ \
446 if (sizeof(rettype) > sizeof(unsigned long)) { \
447 asm volatile(pre \
448 paravirt_alt(PARAVIRT_CALL) \
449 post \
450 : PVOP_CALL_CLOBBERS \
451 : paravirt_type(op), \
452 paravirt_clobber(CLBR_ANY), \
453 ##__VA_ARGS__ \
454 : "memory", "cc" EXTRA_CLOBBERS); \
455 __ret = (rettype)((((u64)__edx) << 32) | __eax); \
456 } else { \
457 asm volatile(pre \
458 paravirt_alt(PARAVIRT_CALL) \
459 post \
460 : PVOP_CALL_CLOBBERS \
461 : paravirt_type(op), \
462 paravirt_clobber(CLBR_ANY), \
463 ##__VA_ARGS__ \
464 : "memory", "cc" EXTRA_CLOBBERS); \
465 __ret = (rettype)__eax; \
466 } \
467 __ret; \
468 })
469 #define __PVOP_VCALL(op, pre, post, ...) \
470 ({ \
471 PVOP_VCALL_ARGS; \
472 asm volatile(pre \
473 paravirt_alt(PARAVIRT_CALL) \
474 post \
475 : PVOP_VCALL_CLOBBERS \
476 : paravirt_type(op), \
477 paravirt_clobber(CLBR_ANY), \
478 ##__VA_ARGS__ \
479 : "memory", "cc" VEXTRA_CLOBBERS); \
480 })
481
482 #define PVOP_CALL0(rettype, op) \
483 __PVOP_CALL(rettype, op, "", "")
484 #define PVOP_VCALL0(op) \
485 __PVOP_VCALL(op, "", "")
486
487 #define PVOP_CALL1(rettype, op, arg1) \
488 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)))
489 #define PVOP_VCALL1(op, arg1) \
490 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)))
491
492 #define PVOP_CALL2(rettype, op, arg1, arg2) \
493 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
494 "1" ((unsigned long)(arg2)))
495 #define PVOP_VCALL2(op, arg1, arg2) \
496 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
497 "1" ((unsigned long)(arg2)))
498
499 #define PVOP_CALL3(rettype, op, arg1, arg2, arg3) \
500 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
501 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)))
502 #define PVOP_VCALL3(op, arg1, arg2, arg3) \
503 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
504 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)))
505
506 /* This is the only difference in x86_64. We can make it much simpler */
507 #ifdef CONFIG_X86_32
508 #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \
509 __PVOP_CALL(rettype, op, \
510 "push %[_arg4];", "lea 4(%%esp),%%esp;", \
511 "0" ((u32)(arg1)), "1" ((u32)(arg2)), \
512 "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
513 #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \
514 __PVOP_VCALL(op, \
515 "push %[_arg4];", "lea 4(%%esp),%%esp;", \
516 "0" ((u32)(arg1)), "1" ((u32)(arg2)), \
517 "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
518 #else
519 #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \
520 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
521 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \
522 "3"((unsigned long)(arg4)))
523 #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \
524 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
525 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \
526 "3"((unsigned long)(arg4)))
527 #endif
528
529 static inline int paravirt_enabled(void)
530 {
531 return pv_info.paravirt_enabled;
532 }
533
534 static inline void load_sp0(struct tss_struct *tss,
535 struct thread_struct *thread)
536 {
537 PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread);
538 }
539
540 #define ARCH_SETUP pv_init_ops.arch_setup();
541 static inline unsigned long get_wallclock(void)
542 {
543 return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock);
544 }
545
546 static inline int set_wallclock(unsigned long nowtime)
547 {
548 return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime);
549 }
550
551 static inline void (*choose_time_init(void))(void)
552 {
553 return pv_time_ops.time_init;
554 }
555
556 /* The paravirtualized CPUID instruction. */
557 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
558 unsigned int *ecx, unsigned int *edx)
559 {
560 PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx);
561 }
562
563 /*
564 * These special macros can be used to get or set a debugging register
565 */
566 static inline unsigned long paravirt_get_debugreg(int reg)
567 {
568 return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg);
569 }
570 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
571 static inline void set_debugreg(unsigned long val, int reg)
572 {
573 PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val);
574 }
575
576 static inline void clts(void)
577 {
578 PVOP_VCALL0(pv_cpu_ops.clts);
579 }
580
581 static inline unsigned long read_cr0(void)
582 {
583 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0);
584 }
585
586 static inline void write_cr0(unsigned long x)
587 {
588 PVOP_VCALL1(pv_cpu_ops.write_cr0, x);
589 }
590
591 static inline unsigned long read_cr2(void)
592 {
593 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2);
594 }
595
596 static inline void write_cr2(unsigned long x)
597 {
598 PVOP_VCALL1(pv_mmu_ops.write_cr2, x);
599 }
600
601 static inline unsigned long read_cr3(void)
602 {
603 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3);
604 }
605
606 static inline void write_cr3(unsigned long x)
607 {
608 PVOP_VCALL1(pv_mmu_ops.write_cr3, x);
609 }
610
611 static inline unsigned long read_cr4(void)
612 {
613 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4);
614 }
615 static inline unsigned long read_cr4_safe(void)
616 {
617 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe);
618 }
619
620 static inline void write_cr4(unsigned long x)
621 {
622 PVOP_VCALL1(pv_cpu_ops.write_cr4, x);
623 }
624
625 #ifdef CONFIG_X86_64
626 static inline unsigned long read_cr8(void)
627 {
628 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8);
629 }
630
631 static inline void write_cr8(unsigned long x)
632 {
633 PVOP_VCALL1(pv_cpu_ops.write_cr8, x);
634 }
635 #endif
636
637 static inline void raw_safe_halt(void)
638 {
639 PVOP_VCALL0(pv_irq_ops.safe_halt);
640 }
641
642 static inline void halt(void)
643 {
644 PVOP_VCALL0(pv_irq_ops.safe_halt);
645 }
646
647 static inline void wbinvd(void)
648 {
649 PVOP_VCALL0(pv_cpu_ops.wbinvd);
650 }
651
652 #define get_kernel_rpl() (pv_info.kernel_rpl)
653
654 static inline u64 paravirt_read_msr(unsigned msr, int *err)
655 {
656 return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);
657 }
658 static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
659 {
660 return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);
661 }
662
663 /* These should all do BUG_ON(_err), but our headers are too tangled. */
664 #define rdmsr(msr, val1, val2) \
665 do { \
666 int _err; \
667 u64 _l = paravirt_read_msr(msr, &_err); \
668 val1 = (u32)_l; \
669 val2 = _l >> 32; \
670 } while (0)
671
672 #define wrmsr(msr, val1, val2) \
673 do { \
674 paravirt_write_msr(msr, val1, val2); \
675 } while (0)
676
677 #define rdmsrl(msr, val) \
678 do { \
679 int _err; \
680 val = paravirt_read_msr(msr, &_err); \
681 } while (0)
682
683 #define wrmsrl(msr, val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32)
684 #define wrmsr_safe(msr, a, b) paravirt_write_msr(msr, a, b)
685
686 /* rdmsr with exception handling */
687 #define rdmsr_safe(msr, a, b) \
688 ({ \
689 int _err; \
690 u64 _l = paravirt_read_msr(msr, &_err); \
691 (*a) = (u32)_l; \
692 (*b) = _l >> 32; \
693 _err; \
694 })
695
696 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
697 {
698 int err;
699
700 *p = paravirt_read_msr(msr, &err);
701 return err;
702 }
703
704 static inline u64 paravirt_read_tsc(void)
705 {
706 return PVOP_CALL0(u64, pv_cpu_ops.read_tsc);
707 }
708
709 #define rdtscl(low) \
710 do { \
711 u64 _l = paravirt_read_tsc(); \
712 low = (int)_l; \
713 } while (0)
714
715 #define rdtscll(val) (val = paravirt_read_tsc())
716
717 static inline unsigned long long paravirt_sched_clock(void)
718 {
719 return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
720 }
721 #define calculate_cpu_khz() (pv_time_ops.get_cpu_khz())
722
723 static inline unsigned long long paravirt_read_pmc(int counter)
724 {
725 return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter);
726 }
727
728 #define rdpmc(counter, low, high) \
729 do { \
730 u64 _l = paravirt_read_pmc(counter); \
731 low = (u32)_l; \
732 high = _l >> 32; \
733 } while (0)
734
735 static inline unsigned long long paravirt_rdtscp(unsigned int *aux)
736 {
737 return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux);
738 }
739
740 #define rdtscp(low, high, aux) \
741 do { \
742 int __aux; \
743 unsigned long __val = paravirt_rdtscp(&__aux); \
744 (low) = (u32)__val; \
745 (high) = (u32)(__val >> 32); \
746 (aux) = __aux; \
747 } while (0)
748
749 #define rdtscpll(val, aux) \
750 do { \
751 unsigned long __aux; \
752 val = paravirt_rdtscp(&__aux); \
753 (aux) = __aux; \
754 } while (0)
755
756 static inline void load_TR_desc(void)
757 {
758 PVOP_VCALL0(pv_cpu_ops.load_tr_desc);
759 }
760 static inline void load_gdt(const struct desc_ptr *dtr)
761 {
762 PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr);
763 }
764 static inline void load_idt(const struct desc_ptr *dtr)
765 {
766 PVOP_VCALL1(pv_cpu_ops.load_idt, dtr);
767 }
768 static inline void set_ldt(const void *addr, unsigned entries)
769 {
770 PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries);
771 }
772 static inline void store_gdt(struct desc_ptr *dtr)
773 {
774 PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr);
775 }
776 static inline void store_idt(struct desc_ptr *dtr)
777 {
778 PVOP_VCALL1(pv_cpu_ops.store_idt, dtr);
779 }
780 static inline unsigned long paravirt_store_tr(void)
781 {
782 return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr);
783 }
784 #define store_tr(tr) ((tr) = paravirt_store_tr())
785 static inline void load_TLS(struct thread_struct *t, unsigned cpu)
786 {
787 PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu);
788 }
789
790 static inline void write_ldt_entry(struct desc_struct *dt, int entry,
791 const void *desc)
792 {
793 PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc);
794 }
795
796 static inline void write_gdt_entry(struct desc_struct *dt, int entry,
797 void *desc, int type)
798 {
799 PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type);
800 }
801
802 static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
803 {
804 PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g);
805 }
806 static inline void set_iopl_mask(unsigned mask)
807 {
808 PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask);
809 }
810
811 /* The paravirtualized I/O functions */
812 static inline void slow_down_io(void)
813 {
814 pv_cpu_ops.io_delay();
815 #ifdef REALLY_SLOW_IO
816 pv_cpu_ops.io_delay();
817 pv_cpu_ops.io_delay();
818 pv_cpu_ops.io_delay();
819 #endif
820 }
821
822 #ifdef CONFIG_X86_LOCAL_APIC
823 /*
824 * Basic functions accessing APICs.
825 */
826 static inline void apic_write(unsigned long reg, u32 v)
827 {
828 PVOP_VCALL2(pv_apic_ops.apic_write, reg, v);
829 }
830
831 static inline void apic_write_atomic(unsigned long reg, u32 v)
832 {
833 PVOP_VCALL2(pv_apic_ops.apic_write_atomic, reg, v);
834 }
835
836 static inline u32 apic_read(unsigned long reg)
837 {
838 return PVOP_CALL1(unsigned long, pv_apic_ops.apic_read, reg);
839 }
840
841 static inline void setup_boot_clock(void)
842 {
843 PVOP_VCALL0(pv_apic_ops.setup_boot_clock);
844 }
845
846 static inline void setup_secondary_clock(void)
847 {
848 PVOP_VCALL0(pv_apic_ops.setup_secondary_clock);
849 }
850 #endif
851
852 static inline void paravirt_post_allocator_init(void)
853 {
854 if (pv_init_ops.post_allocator_init)
855 (*pv_init_ops.post_allocator_init)();
856 }
857
858 static inline void paravirt_pagetable_setup_start(pgd_t *base)
859 {
860 (*pv_mmu_ops.pagetable_setup_start)(base);
861 }
862
863 static inline void paravirt_pagetable_setup_done(pgd_t *base)
864 {
865 (*pv_mmu_ops.pagetable_setup_done)(base);
866 }
867
868 #ifdef CONFIG_SMP
869 static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip,
870 unsigned long start_esp)
871 {
872 PVOP_VCALL3(pv_apic_ops.startup_ipi_hook,
873 phys_apicid, start_eip, start_esp);
874 }
875 #endif
876
877 static inline void paravirt_activate_mm(struct mm_struct *prev,
878 struct mm_struct *next)
879 {
880 PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next);
881 }
882
883 static inline void arch_dup_mmap(struct mm_struct *oldmm,
884 struct mm_struct *mm)
885 {
886 PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm);
887 }
888
889 static inline void arch_exit_mmap(struct mm_struct *mm)
890 {
891 PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm);
892 }
893
894 static inline void __flush_tlb(void)
895 {
896 PVOP_VCALL0(pv_mmu_ops.flush_tlb_user);
897 }
898 static inline void __flush_tlb_global(void)
899 {
900 PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);
901 }
902 static inline void __flush_tlb_single(unsigned long addr)
903 {
904 PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr);
905 }
906
907 static inline void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
908 unsigned long va)
909 {
910 PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, &cpumask, mm, va);
911 }
912
913 static inline void paravirt_alloc_pt(struct mm_struct *mm, unsigned pfn)
914 {
915 PVOP_VCALL2(pv_mmu_ops.alloc_pt, mm, pfn);
916 }
917 static inline void paravirt_release_pt(unsigned pfn)
918 {
919 PVOP_VCALL1(pv_mmu_ops.release_pt, pfn);
920 }
921
922 static inline void paravirt_alloc_pd(struct mm_struct *mm, unsigned pfn)
923 {
924 PVOP_VCALL2(pv_mmu_ops.alloc_pd, mm, pfn);
925 }
926
927 static inline void paravirt_alloc_pd_clone(unsigned pfn, unsigned clonepfn,
928 unsigned start, unsigned count)
929 {
930 PVOP_VCALL4(pv_mmu_ops.alloc_pd_clone, pfn, clonepfn, start, count);
931 }
932 static inline void paravirt_release_pd(unsigned pfn)
933 {
934 PVOP_VCALL1(pv_mmu_ops.release_pd, pfn);
935 }
936
937 #ifdef CONFIG_HIGHPTE
938 static inline void *kmap_atomic_pte(struct page *page, enum km_type type)
939 {
940 unsigned long ret;
941 ret = PVOP_CALL2(unsigned long, pv_mmu_ops.kmap_atomic_pte, page, type);
942 return (void *)ret;
943 }
944 #endif
945
946 static inline void pte_update(struct mm_struct *mm, unsigned long addr,
947 pte_t *ptep)
948 {
949 PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep);
950 }
951
952 static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr,
953 pte_t *ptep)
954 {
955 PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep);
956 }
957
958 static inline pte_t __pte(pteval_t val)
959 {
960 pteval_t ret;
961
962 if (sizeof(pteval_t) > sizeof(long))
963 ret = PVOP_CALL2(pteval_t,
964 pv_mmu_ops.make_pte,
965 val, (u64)val >> 32);
966 else
967 ret = PVOP_CALL1(pteval_t,
968 pv_mmu_ops.make_pte,
969 val);
970
971 return (pte_t) { .pte = ret };
972 }
973
974 static inline pteval_t pte_val(pte_t pte)
975 {
976 pteval_t ret;
977
978 if (sizeof(pteval_t) > sizeof(long))
979 ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_val,
980 pte.pte, (u64)pte.pte >> 32);
981 else
982 ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_val,
983 pte.pte);
984
985 return ret;
986 }
987
988 static inline pgd_t __pgd(pgdval_t val)
989 {
990 pgdval_t ret;
991
992 if (sizeof(pgdval_t) > sizeof(long))
993 ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.make_pgd,
994 val, (u64)val >> 32);
995 else
996 ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.make_pgd,
997 val);
998
999 return (pgd_t) { ret };
1000 }
1001
1002 static inline pgdval_t pgd_val(pgd_t pgd)
1003 {
1004 pgdval_t ret;
1005
1006 if (sizeof(pgdval_t) > sizeof(long))
1007 ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.pgd_val,
1008 pgd.pgd, (u64)pgd.pgd >> 32);
1009 else
1010 ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.pgd_val,
1011 pgd.pgd);
1012
1013 return ret;
1014 }
1015
1016 static inline void set_pte(pte_t *ptep, pte_t pte)
1017 {
1018 if (sizeof(pteval_t) > sizeof(long))
1019 PVOP_VCALL3(pv_mmu_ops.set_pte, ptep,
1020 pte.pte, (u64)pte.pte >> 32);
1021 else
1022 PVOP_VCALL2(pv_mmu_ops.set_pte, ptep,
1023 pte.pte);
1024 }
1025
1026 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
1027 pte_t *ptep, pte_t pte)
1028 {
1029 if (sizeof(pteval_t) > sizeof(long))
1030 /* 5 arg words */
1031 pv_mmu_ops.set_pte_at(mm, addr, ptep, pte);
1032 else
1033 PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte);
1034 }
1035
1036 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
1037 {
1038 pmdval_t val = native_pmd_val(pmd);
1039
1040 if (sizeof(pmdval_t) > sizeof(long))
1041 PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32);
1042 else
1043 PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val);
1044 }
1045
1046 #if PAGETABLE_LEVELS >= 3
1047 static inline pmd_t __pmd(pmdval_t val)
1048 {
1049 pmdval_t ret;
1050
1051 if (sizeof(pmdval_t) > sizeof(long))
1052 ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.make_pmd,
1053 val, (u64)val >> 32);
1054 else
1055 ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.make_pmd,
1056 val);
1057
1058 return (pmd_t) { ret };
1059 }
1060
1061 static inline pmdval_t pmd_val(pmd_t pmd)
1062 {
1063 pmdval_t ret;
1064
1065 if (sizeof(pmdval_t) > sizeof(long))
1066 ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.pmd_val,
1067 pmd.pmd, (u64)pmd.pmd >> 32);
1068 else
1069 ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.pmd_val,
1070 pmd.pmd);
1071
1072 return ret;
1073 }
1074
1075 static inline void set_pud(pud_t *pudp, pud_t pud)
1076 {
1077 pudval_t val = native_pud_val(pud);
1078
1079 if (sizeof(pudval_t) > sizeof(long))
1080 PVOP_VCALL3(pv_mmu_ops.set_pud, pudp,
1081 val, (u64)val >> 32);
1082 else
1083 PVOP_VCALL2(pv_mmu_ops.set_pud, pudp,
1084 val);
1085 }
1086 #if PAGETABLE_LEVELS == 4
1087 static inline pud_t __pud(pudval_t val)
1088 {
1089 pudval_t ret;
1090
1091 if (sizeof(pudval_t) > sizeof(long))
1092 ret = PVOP_CALL2(pudval_t, pv_mmu_ops.make_pud,
1093 val, (u64)val >> 32);
1094 else
1095 ret = PVOP_CALL1(pudval_t, pv_mmu_ops.make_pud,
1096 val);
1097
1098 return (pud_t) { ret };
1099 }
1100
1101 static inline pudval_t pud_val(pud_t pud)
1102 {
1103 pudval_t ret;
1104
1105 if (sizeof(pudval_t) > sizeof(long))
1106 ret = PVOP_CALL2(pudval_t, pv_mmu_ops.pud_val,
1107 pud.pud, (u64)pud.pud >> 32);
1108 else
1109 ret = PVOP_CALL1(pudval_t, pv_mmu_ops.pud_val,
1110 pud.pud);
1111
1112 return ret;
1113 }
1114
1115 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
1116 {
1117 pgdval_t val = native_pgd_val(pgd);
1118
1119 if (sizeof(pgdval_t) > sizeof(long))
1120 PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp,
1121 val, (u64)val >> 32);
1122 else
1123 PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp,
1124 val);
1125 }
1126
1127 static inline void pgd_clear(pgd_t *pgdp)
1128 {
1129 set_pgd(pgdp, __pgd(0));
1130 }
1131
1132 static inline void pud_clear(pud_t *pudp)
1133 {
1134 set_pud(pudp, __pud(0));
1135 }
1136
1137 #endif /* PAGETABLE_LEVELS == 4 */
1138
1139 #endif /* PAGETABLE_LEVELS >= 3 */
1140
1141 #ifdef CONFIG_X86_PAE
1142 /* Special-case pte-setting operations for PAE, which can't update a
1143 64-bit pte atomically */
1144 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
1145 {
1146 PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep,
1147 pte.pte, pte.pte >> 32);
1148 }
1149
1150 static inline void set_pte_present(struct mm_struct *mm, unsigned long addr,
1151 pte_t *ptep, pte_t pte)
1152 {
1153 /* 5 arg words */
1154 pv_mmu_ops.set_pte_present(mm, addr, ptep, pte);
1155 }
1156
1157 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
1158 pte_t *ptep)
1159 {
1160 PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep);
1161 }
1162
1163 static inline void pmd_clear(pmd_t *pmdp)
1164 {
1165 PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp);
1166 }
1167 #else /* !CONFIG_X86_PAE */
1168 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
1169 {
1170 set_pte(ptep, pte);
1171 }
1172
1173 static inline void set_pte_present(struct mm_struct *mm, unsigned long addr,
1174 pte_t *ptep, pte_t pte)
1175 {
1176 set_pte(ptep, pte);
1177 }
1178
1179 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
1180 pte_t *ptep)
1181 {
1182 set_pte_at(mm, addr, ptep, __pte(0));
1183 }
1184
1185 static inline void pmd_clear(pmd_t *pmdp)
1186 {
1187 set_pmd(pmdp, __pmd(0));
1188 }
1189 #endif /* CONFIG_X86_PAE */
1190
1191 /* Lazy mode for batching updates / context switch */
1192 enum paravirt_lazy_mode {
1193 PARAVIRT_LAZY_NONE,
1194 PARAVIRT_LAZY_MMU,
1195 PARAVIRT_LAZY_CPU,
1196 };
1197
1198 enum paravirt_lazy_mode paravirt_get_lazy_mode(void);
1199 void paravirt_enter_lazy_cpu(void);
1200 void paravirt_leave_lazy_cpu(void);
1201 void paravirt_enter_lazy_mmu(void);
1202 void paravirt_leave_lazy_mmu(void);
1203 void paravirt_leave_lazy(enum paravirt_lazy_mode mode);
1204
1205 #define __HAVE_ARCH_ENTER_LAZY_CPU_MODE
1206 static inline void arch_enter_lazy_cpu_mode(void)
1207 {
1208 PVOP_VCALL0(pv_cpu_ops.lazy_mode.enter);
1209 }
1210
1211 static inline void arch_leave_lazy_cpu_mode(void)
1212 {
1213 PVOP_VCALL0(pv_cpu_ops.lazy_mode.leave);
1214 }
1215
1216 static inline void arch_flush_lazy_cpu_mode(void)
1217 {
1218 if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU)) {
1219 arch_leave_lazy_cpu_mode();
1220 arch_enter_lazy_cpu_mode();
1221 }
1222 }
1223
1224
1225 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
1226 static inline void arch_enter_lazy_mmu_mode(void)
1227 {
1228 PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter);
1229 }
1230
1231 static inline void arch_leave_lazy_mmu_mode(void)
1232 {
1233 PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave);
1234 }
1235
1236 static inline void arch_flush_lazy_mmu_mode(void)
1237 {
1238 if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU)) {
1239 arch_leave_lazy_mmu_mode();
1240 arch_enter_lazy_mmu_mode();
1241 }
1242 }
1243
1244 void _paravirt_nop(void);
1245 #define paravirt_nop ((void *)_paravirt_nop)
1246
1247 /* These all sit in the .parainstructions section to tell us what to patch. */
1248 struct paravirt_patch_site {
1249 u8 *instr; /* original instructions */
1250 u8 instrtype; /* type of this instruction */
1251 u8 len; /* length of original instruction */
1252 u16 clobbers; /* what registers you may clobber */
1253 };
1254
1255 extern struct paravirt_patch_site __parainstructions[],
1256 __parainstructions_end[];
1257
1258 #ifdef CONFIG_X86_32
1259 #define PV_SAVE_REGS "pushl %%ecx; pushl %%edx;"
1260 #define PV_RESTORE_REGS "popl %%edx; popl %%ecx"
1261 #define PV_FLAGS_ARG "0"
1262 #define PV_EXTRA_CLOBBERS
1263 #define PV_VEXTRA_CLOBBERS
1264 #else
1265 /* We save some registers, but all of them, that's too much. We clobber all
1266 * caller saved registers but the argument parameter */
1267 #define PV_SAVE_REGS "pushq %%rdi;"
1268 #define PV_RESTORE_REGS "popq %%rdi;"
1269 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx"
1270 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx"
1271 #define PV_FLAGS_ARG "D"
1272 #endif
1273
1274 static inline unsigned long __raw_local_save_flags(void)
1275 {
1276 unsigned long f;
1277
1278 asm volatile(paravirt_alt(PV_SAVE_REGS
1279 PARAVIRT_CALL
1280 PV_RESTORE_REGS)
1281 : "=a"(f)
1282 : paravirt_type(pv_irq_ops.save_fl),
1283 paravirt_clobber(CLBR_EAX)
1284 : "memory", "cc" PV_VEXTRA_CLOBBERS);
1285 return f;
1286 }
1287
1288 static inline void raw_local_irq_restore(unsigned long f)
1289 {
1290 asm volatile(paravirt_alt(PV_SAVE_REGS
1291 PARAVIRT_CALL
1292 PV_RESTORE_REGS)
1293 : "=a"(f)
1294 : PV_FLAGS_ARG(f),
1295 paravirt_type(pv_irq_ops.restore_fl),
1296 paravirt_clobber(CLBR_EAX)
1297 : "memory", "cc" PV_EXTRA_CLOBBERS);
1298 }
1299
1300 static inline void raw_local_irq_disable(void)
1301 {
1302 asm volatile(paravirt_alt(PV_SAVE_REGS
1303 PARAVIRT_CALL
1304 PV_RESTORE_REGS)
1305 :
1306 : paravirt_type(pv_irq_ops.irq_disable),
1307 paravirt_clobber(CLBR_EAX)
1308 : "memory", "eax", "cc" PV_EXTRA_CLOBBERS);
1309 }
1310
1311 static inline void raw_local_irq_enable(void)
1312 {
1313 asm volatile(paravirt_alt(PV_SAVE_REGS
1314 PARAVIRT_CALL
1315 PV_RESTORE_REGS)
1316 :
1317 : paravirt_type(pv_irq_ops.irq_enable),
1318 paravirt_clobber(CLBR_EAX)
1319 : "memory", "eax", "cc" PV_EXTRA_CLOBBERS);
1320 }
1321
1322 static inline unsigned long __raw_local_irq_save(void)
1323 {
1324 unsigned long f;
1325
1326 f = __raw_local_save_flags();
1327 raw_local_irq_disable();
1328 return f;
1329 }
1330
1331 /* Make sure as little as possible of this mess escapes. */
1332 #undef PARAVIRT_CALL
1333 #undef __PVOP_CALL
1334 #undef __PVOP_VCALL
1335 #undef PVOP_VCALL0
1336 #undef PVOP_CALL0
1337 #undef PVOP_VCALL1
1338 #undef PVOP_CALL1
1339 #undef PVOP_VCALL2
1340 #undef PVOP_CALL2
1341 #undef PVOP_VCALL3
1342 #undef PVOP_CALL3
1343 #undef PVOP_VCALL4
1344 #undef PVOP_CALL4
1345
1346 #else /* __ASSEMBLY__ */
1347
1348 #define _PVSITE(ptype, clobbers, ops, word, algn) \
1349 771:; \
1350 ops; \
1351 772:; \
1352 .pushsection .parainstructions,"a"; \
1353 .align algn; \
1354 word 771b; \
1355 .byte ptype; \
1356 .byte 772b-771b; \
1357 .short clobbers; \
1358 .popsection
1359
1360
1361 #ifdef CONFIG_X86_64
1362 #define PV_SAVE_REGS pushq %rax; pushq %rdi; pushq %rcx; pushq %rdx
1363 #define PV_RESTORE_REGS popq %rdx; popq %rcx; popq %rdi; popq %rax
1364 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8)
1365 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8)
1366 #else
1367 #define PV_SAVE_REGS pushl %eax; pushl %edi; pushl %ecx; pushl %edx
1368 #define PV_RESTORE_REGS popl %edx; popl %ecx; popl %edi; popl %eax
1369 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4)
1370 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4)
1371 #endif
1372
1373 #define INTERRUPT_RETURN \
1374 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \
1375 jmp *%cs:pv_cpu_ops+PV_CPU_iret)
1376
1377 #define DISABLE_INTERRUPTS(clobbers) \
1378 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
1379 PV_SAVE_REGS; \
1380 call *%cs:pv_irq_ops+PV_IRQ_irq_disable; \
1381 PV_RESTORE_REGS;) \
1382
1383 #define ENABLE_INTERRUPTS(clobbers) \
1384 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \
1385 PV_SAVE_REGS; \
1386 call *%cs:pv_irq_ops+PV_IRQ_irq_enable; \
1387 PV_RESTORE_REGS;)
1388
1389 #define ENABLE_INTERRUPTS_SYSCALL_RET \
1390 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_syscall_ret),\
1391 CLBR_NONE, \
1392 jmp *%cs:pv_cpu_ops+PV_CPU_irq_enable_syscall_ret)
1393
1394
1395 #ifdef CONFIG_X86_32
1396 #define GET_CR0_INTO_EAX \
1397 push %ecx; push %edx; \
1398 call *pv_cpu_ops+PV_CPU_read_cr0; \
1399 pop %edx; pop %ecx
1400 #else
1401 #define SWAPGS \
1402 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
1403 PV_SAVE_REGS; \
1404 call *pv_cpu_ops+PV_CPU_swapgs; \
1405 PV_RESTORE_REGS \
1406 )
1407
1408 #define GET_CR2_INTO_RCX \
1409 call *pv_mmu_ops+PV_MMU_read_cr2; \
1410 movq %rax, %rcx; \
1411 xorq %rax, %rax;
1412
1413 #endif
1414
1415 #endif /* __ASSEMBLY__ */
1416 #endif /* CONFIG_PARAVIRT */
1417 #endif /* __ASM_PARAVIRT_H */
Linux with added FPC-III support