include/asm-x86/uv/uv_hub.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV architectural definitions
   7  *
   8  * Copyright (C) 2007 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #ifndef __ASM_X86_UV_HUB_H__
  12 #define __ASM_X86_UV_HUB_H__
  13
  14 #include <linux/numa.h>
  15 #include <linux/percpu.h>
  16 #include <asm/types.h>
  17 #include <asm/percpu.h>
  18
  19
  20 /*
  21  * Addressing Terminology
  22  *
  23  *      NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
  24  *              routers always have low bit of 1, C/MBricks have low bit
  25  *              equal to 0. Most addressing macros that target UV hub chips
  26  *              right shift the NASID by 1 to exclude the always-zero bit.
  27  *
  28  *      SNASID - NASID right shifted by 1 bit.
  29  *
  30  *
  31  *  Memory/UV-HUB Processor Socket Address Format:
  32  *  +--------+---------------+---------------------+
  33  *  |00..0000|    SNASID     |      NodeOffset     |
  34  *  +--------+---------------+---------------------+
  35  *           <--- N bits --->|<--------M bits ----->
  36  *
  37  *      M number of node offset bits (35 .. 40)
  38  *      N number of SNASID bits (0 .. 10)
  39  *
  40  *              Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
  41  *              The actual values are configuration dependent and are set at
  42  *              boot time
  43  *
  44  * APICID format
  45  *      NOTE!!!!!! This is the current format of the APICID. However, code
  46  *      should assume that this will change in the future. Use functions
  47  *      in this file for all APICID bit manipulations and conversion.
  48  *
  49  *              1111110000000000
  50  *              5432109876543210
  51  *              nnnnnnnnnnlc0cch
  52  *              sssssssssss
  53  *
  54  *                      n  = snasid bits
  55  *                      l =  socket number on board
  56  *                      c  = core
  57  *                      h  = hyperthread
  58  *                      s  = bits that are in the socket CSR
  59  *
  60  *      Note: Processor only supports 12 bits in the APICID register. The ACPI
  61  *            tables hold all 16 bits. Software needs to be aware of this.
  62  *
  63  *            Unless otherwise specified, all references to APICID refer to
  64  *            the FULL value contained in ACPI tables, not the subset in the
  65  *            processor APICID register.
  66  */
  67
  68
  69 /*
  70  * Maximum number of bricks in all partitions and in all coherency domains.
  71  * This is the total number of bricks accessible in the numalink fabric. It
  72  * includes all C & M bricks. Routers are NOT included.
  73  *
  74  * This value is also the value of the maximum number of non-router NASIDs
  75  * in the numalink fabric.
  76  *
  77  * NOTE: a brick may be 1 or 2 OS nodes. Don't get these confused.
  78  */
  79 #define UV_MAX_NUMALINK_BLADES  16384
  80
  81 /*
  82  * Maximum number of C/Mbricks within a software SSI (hardware may support
  83  * more).
  84  */
  85 #define UV_MAX_SSI_BLADES       256
  86
  87 /*
  88  * The largest possible NASID of a C or M brick (+ 2)
  89  */
  90 #define UV_MAX_NASID_VALUE      (UV_MAX_NUMALINK_NODES * 2)
  91
  92 /*
  93  * The following defines attributes of the HUB chip. These attributes are
  94  * frequently referenced and are kept in the per-cpu data areas of each cpu.
  95  * They are kept together in a struct to minimize cache misses.
  96  */
  97 struct uv_hub_info_s {
  98         unsigned long   global_mmr_base;
  99         unsigned short  local_nasid;
 100         unsigned short  gnode_upper;
 101         unsigned short  coherency_domain_number;
 102         unsigned short  numa_blade_id;
 103         unsigned char   blade_processor_id;
 104         unsigned char   m_val;
 105         unsigned char   n_val;
 106 };
 107 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 108 #define uv_hub_info             (&__get_cpu_var(__uv_hub_info))
 109 #define uv_cpu_hub_info(cpu)    (&per_cpu(__uv_hub_info, cpu))
 110
 111 /*
 112  * Local & Global MMR space macros.
 113  *      Note: macros are intended to be used ONLY by inline functions
 114  *      in this file - not by other kernel code.
 115  */
 116 #define UV_SNASID(n)                    ((n) >> 1)
 117 #define UV_NASID(n)                     ((n) << 1)
 118
 119 #define UV_LOCAL_MMR_BASE               0xf4000000UL
 120 #define UV_GLOBAL_MMR32_BASE            0xf8000000UL
 121 #define UV_GLOBAL_MMR64_BASE            (uv_hub_info->global_mmr_base)
 122
 123 #define UV_GLOBAL_MMR32_SNASID_MASK     0x3ff
 124 #define UV_GLOBAL_MMR32_SNASID_SHIFT    15
 125 #define UV_GLOBAL_MMR64_SNASID_SHIFT    26
 126
 127 #define UV_GLOBAL_MMR32_NASID_BITS(n)                                   \
 128                 (((UV_SNASID(n) & UV_GLOBAL_MMR32_SNASID_MASK)) <<      \
 129                 (UV_GLOBAL_MMR32_SNASID_SHIFT))
 130
 131 #define UV_GLOBAL_MMR64_NASID_BITS(n)                                   \
 132         ((unsigned long)UV_SNASID(n) << UV_GLOBAL_MMR64_SNASID_SHIFT)
 133
 134 #define UV_APIC_NASID_SHIFT     6
 135
 136 /*
 137  * Extract a NASID from an APICID (full apicid, not processor subset)
 138  */
 139 static inline int uv_apicid_to_nasid(int apicid)
 140 {
 141         return (UV_NASID(apicid >> UV_APIC_NASID_SHIFT));
 142 }
 143
 144 /*
 145  * Access global MMRs using the low memory MMR32 space. This region supports
 146  * faster MMR access but not all MMRs are accessible in this space.
 147  */
 148 static inline unsigned long *uv_global_mmr32_address(int nasid,
 149                                 unsigned long offset)
 150 {
 151         return __va(UV_GLOBAL_MMR32_BASE |
 152                        UV_GLOBAL_MMR32_NASID_BITS(nasid) | offset);
 153 }
 154
 155 static inline void uv_write_global_mmr32(int nasid, unsigned long offset,
 156                                  unsigned long val)
 157 {
 158         *uv_global_mmr32_address(nasid, offset) = val;
 159 }
 160
 161 static inline unsigned long uv_read_global_mmr32(int nasid,
 162                                                  unsigned long offset)
 163 {
 164         return *uv_global_mmr32_address(nasid, offset);
 165 }
 166
 167 /*
 168  * Access Global MMR space using the MMR space located at the top of physical
 169  * memory.
 170  */
 171 static inline unsigned long *uv_global_mmr64_address(int nasid,
 172                                 unsigned long offset)
 173 {
 174         return __va(UV_GLOBAL_MMR64_BASE |
 175                        UV_GLOBAL_MMR64_NASID_BITS(nasid) | offset);
 176 }
 177
 178 static inline void uv_write_global_mmr64(int nasid, unsigned long offset,
 179                                 unsigned long val)
 180 {
 181         *uv_global_mmr64_address(nasid, offset) = val;
 182 }
 183
 184 static inline unsigned long uv_read_global_mmr64(int nasid,
 185                                                  unsigned long offset)
 186 {
 187         return *uv_global_mmr64_address(nasid, offset);
 188 }
 189
 190 /*
 191  * Access node local MMRs. Faster than using global space but only local MMRs
 192  * are accessible.
 193  */
 194 static inline unsigned long *uv_local_mmr_address(unsigned long offset)
 195 {
 196         return __va(UV_LOCAL_MMR_BASE | offset);
 197 }
 198
 199 static inline unsigned long uv_read_local_mmr(unsigned long offset)
 200 {
 201         return *uv_local_mmr_address(offset);
 202 }
 203
 204 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
 205 {
 206         *uv_local_mmr_address(offset) = val;
 207 }
 208
 209 /*
 210  * Structures and definitions for converting between cpu, node, and blade
 211  * numbers.
 212  */
 213 struct uv_blade_info {
 214         unsigned short  nr_posible_cpus;
 215         unsigned short  nr_online_cpus;
 216         unsigned short  nasid;
 217 };
 218 struct uv_blade_info *uv_blade_info;
 219 extern short *uv_node_to_blade;
 220 extern short *uv_cpu_to_blade;
 221 extern short uv_possible_blades;
 222
 223 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
 224 static inline int uv_blade_processor_id(void)
 225 {
 226         return uv_hub_info->blade_processor_id;
 227 }
 228
 229 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
 230 static inline int uv_numa_blade_id(void)
 231 {
 232         return uv_hub_info->numa_blade_id;
 233 }
 234
 235 /* Convert a cpu number to the the UV blade number */
 236 static inline int uv_cpu_to_blade_id(int cpu)
 237 {
 238         return uv_cpu_to_blade[cpu];
 239 }
 240
 241 /* Convert linux node number to the UV blade number */
 242 static inline int uv_node_to_blade_id(int nid)
 243 {
 244         return uv_node_to_blade[nid];
 245 }
 246
 247 /* Convert a blade id to the NASID of the blade */
 248 static inline int uv_blade_to_nasid(int bid)
 249 {
 250         return uv_blade_info[bid].nasid;
 251 }
 252
 253 /* Determine the number of possible cpus on a blade */
 254 static inline int uv_blade_nr_possible_cpus(int bid)
 255 {
 256         return uv_blade_info[bid].nr_posible_cpus;
 257 }
 258
 259 /* Determine the number of online cpus on a blade */
 260 static inline int uv_blade_nr_online_cpus(int bid)
 261 {
 262         return uv_blade_info[bid].nr_online_cpus;
 263 }
 264
 265 /* Convert a cpu id to the NASID of the blade containing the cpu */
 266 static inline int uv_cpu_to_nasid(int cpu)
 267 {
 268         return uv_blade_info[uv_cpu_to_blade_id(cpu)].nasid;
 269 }
 270
 271 /* Convert a node number to the NASID of the blade */
 272 static inline int uv_node_to_nasid(int nid)
 273 {
 274         return uv_blade_info[uv_node_to_blade_id(nid)].nasid;
 275 }
 276
 277 /* Maximum possible number of blades */
 278 static inline int uv_num_possible_blades(void)
 279 {
 280         return uv_possible_blades;
 281 }
 282
 283 #endif /* __ASM_X86_UV_HUB__ */
 284