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Merge branch 'work.regset' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-eg20t.c
blob73f139690e4e547d1db40746c0ae857c9b756e98
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 */
5
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/delay.h>
9 #include <linux/errno.h>
10 #include <linux/i2c.h>
11 #include <linux/fs.h>
12 #include <linux/io.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/jiffies.h>
16 #include <linux/pci.h>
17 #include <linux/mutex.h>
18 #include <linux/ktime.h>
19 #include <linux/slab.h>
20
21 #define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
22 #define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
23 #define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
24 #define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
25 #define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
26
27 #define PCH_I2CSADR 0x00 /* I2C slave address register */
28 #define PCH_I2CCTL 0x04 /* I2C control register */
29 #define PCH_I2CSR 0x08 /* I2C status register */
30 #define PCH_I2CDR 0x0C /* I2C data register */
31 #define PCH_I2CMON 0x10 /* I2C bus monitor register */
32 #define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
33 #define PCH_I2CMOD 0x18 /* I2C mode register */
34 #define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
35 #define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
36 #define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
37 #define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
38 #define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
39 #define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
40 #define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
41 #define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
42 #define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
43 #define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
44 #define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
45 #define PCH_I2CTMR 0x48 /* I2C timer register */
46 #define PCH_I2CSRST 0xFC /* I2C reset register */
47 #define PCH_I2CNF 0xF8 /* I2C noise filter register */
48
49 #define BUS_IDLE_TIMEOUT 20
50 #define PCH_I2CCTL_I2CMEN 0x0080
51 #define TEN_BIT_ADDR_DEFAULT 0xF000
52 #define TEN_BIT_ADDR_MASK 0xF0
53 #define PCH_START 0x0020
54 #define PCH_RESTART 0x0004
55 #define PCH_ESR_START 0x0001
56 #define PCH_BUFF_START 0x1
57 #define PCH_REPSTART 0x0004
58 #define PCH_ACK 0x0008
59 #define PCH_GETACK 0x0001
60 #define CLR_REG 0x0
61 #define I2C_RD 0x1
62 #define I2CMCF_BIT 0x0080
63 #define I2CMIF_BIT 0x0002
64 #define I2CMAL_BIT 0x0010
65 #define I2CBMFI_BIT 0x0001
66 #define I2CBMAL_BIT 0x0002
67 #define I2CBMNA_BIT 0x0004
68 #define I2CBMTO_BIT 0x0008
69 #define I2CBMIS_BIT 0x0010
70 #define I2CESRFI_BIT 0X0001
71 #define I2CESRTO_BIT 0x0002
72 #define I2CESRFIIE_BIT 0x1
73 #define I2CESRTOIE_BIT 0x2
74 #define I2CBMDZ_BIT 0x0040
75 #define I2CBMAG_BIT 0x0020
76 #define I2CMBB_BIT 0x0020
77 #define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
78 I2CBMTO_BIT | I2CBMIS_BIT)
79 #define I2C_ADDR_MSK 0xFF
80 #define I2C_MSB_2B_MSK 0x300
81 #define FAST_MODE_CLK 400
82 #define FAST_MODE_EN 0x0001
83 #define SUB_ADDR_LEN_MAX 4
84 #define BUF_LEN_MAX 32
85 #define PCH_BUFFER_MODE 0x1
86 #define EEPROM_SW_RST_MODE 0x0002
87 #define NORMAL_INTR_ENBL 0x0300
88 #define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
89 #define EEPROM_RST_INTR_DISBL 0x0
90 #define BUFFER_MODE_INTR_ENBL 0x001F
91 #define BUFFER_MODE_INTR_DISBL 0x0
92 #define NORMAL_MODE 0x0
93 #define BUFFER_MODE 0x1
94 #define EEPROM_SR_MODE 0x2
95 #define I2C_TX_MODE 0x0010
96 #define PCH_BUF_TX 0xFFF7
97 #define PCH_BUF_RD 0x0008
98 #define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
99 I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
100 #define I2CMAL_EVENT 0x0001
101 #define I2CMCF_EVENT 0x0002
102 #define I2CBMFI_EVENT 0x0004
103 #define I2CBMAL_EVENT 0x0008
104 #define I2CBMNA_EVENT 0x0010
105 #define I2CBMTO_EVENT 0x0020
106 #define I2CBMIS_EVENT 0x0040
107 #define I2CESRFI_EVENT 0x0080
108 #define I2CESRTO_EVENT 0x0100
109 #define PCI_DEVICE_ID_PCH_I2C 0x8817
110
111 #define pch_dbg(adap, fmt, arg...) \
112 dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
113
114 #define pch_err(adap, fmt, arg...) \
115 dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
116
117 #define pch_pci_err(pdev, fmt, arg...) \
118 dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
119
120 #define pch_pci_dbg(pdev, fmt, arg...) \
121 dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
122
123 /*
124 Set the number of I2C instance max
125 Intel EG20T PCH : 1ch
126 LAPIS Semiconductor ML7213 IOH : 2ch
127 LAPIS Semiconductor ML7831 IOH : 1ch
128 */
129 #define PCH_I2C_MAX_DEV 2
130
131 /**
132 * struct i2c_algo_pch_data - for I2C driver functionalities
133 * @pch_adapter: stores the reference to i2c_adapter structure
134 * @p_adapter_info: stores the reference to adapter_info structure
135 * @pch_base_address: specifies the remapped base address
136 * @pch_buff_mode_en: specifies if buffer mode is enabled
137 * @pch_event_flag: specifies occurrence of interrupt events
138 * @pch_i2c_xfer_in_progress: specifies whether the transfer is completed
139 */
140 struct i2c_algo_pch_data {
141 struct i2c_adapter pch_adapter;
142 struct adapter_info *p_adapter_info;
143 void __iomem *pch_base_address;
144 int pch_buff_mode_en;
145 u32 pch_event_flag;
146 bool pch_i2c_xfer_in_progress;
147 };
148
149 /**
150 * struct adapter_info - This structure holds the adapter information for the
151 PCH i2c controller
152 * @pch_data: stores a list of i2c_algo_pch_data
153 * @pch_i2c_suspended: specifies whether the system is suspended or not
154 * perhaps with more lines and words.
155 * @ch_num: specifies the number of i2c instance
156 *
157 * pch_data has as many elements as maximum I2C channels
158 */
159 struct adapter_info {
160 struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
161 bool pch_i2c_suspended;
162 int ch_num;
163 };
164
165
166 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
167 static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
168 static wait_queue_head_t pch_event;
169 static DEFINE_MUTEX(pch_mutex);
170
171 /* Definition for ML7213 by LAPIS Semiconductor */
172 #define PCI_DEVICE_ID_ML7213_I2C 0x802D
173 #define PCI_DEVICE_ID_ML7223_I2C 0x8010
174 #define PCI_DEVICE_ID_ML7831_I2C 0x8817
175
176 static const struct pci_device_id pch_pcidev_id[] = {
177 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C), 1, },
178 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
179 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
180 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
181 {0,}
182 };
183 MODULE_DEVICE_TABLE(pci, pch_pcidev_id);
184
185 static irqreturn_t pch_i2c_handler(int irq, void *pData);
186
187 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
188 {
189 u32 val;
190 val = ioread32(addr + offset);
191 val |= bitmask;
192 iowrite32(val, addr + offset);
193 }
194
195 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
196 {
197 u32 val;
198 val = ioread32(addr + offset);
199 val &= (~bitmask);
200 iowrite32(val, addr + offset);
201 }
202
203 /**
204 * pch_i2c_init() - hardware initialization of I2C module
205 * @adap: Pointer to struct i2c_algo_pch_data.
206 */
207 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
208 {
209 void __iomem *p = adap->pch_base_address;
210 u32 pch_i2cbc;
211 u32 pch_i2ctmr;
212 u32 reg_value;
213
214 /* reset I2C controller */
215 iowrite32(0x01, p + PCH_I2CSRST);
216 msleep(20);
217 iowrite32(0x0, p + PCH_I2CSRST);
218
219 /* Initialize I2C registers */
220 iowrite32(0x21, p + PCH_I2CNF);
221
222 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
223
224 if (pch_i2c_speed != 400)
225 pch_i2c_speed = 100;
226
227 reg_value = PCH_I2CCTL_I2CMEN;
228 if (pch_i2c_speed == FAST_MODE_CLK) {
229 reg_value |= FAST_MODE_EN;
230 pch_dbg(adap, "Fast mode enabled\n");
231 }
232
233 if (pch_clk > PCH_MAX_CLK)
234 pch_clk = 62500;
235
236 pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
237 /* Set transfer speed in I2CBC */
238 iowrite32(pch_i2cbc, p + PCH_I2CBC);
239
240 pch_i2ctmr = (pch_clk) / 8;
241 iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
242
243 reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
244 iowrite32(reg_value, p + PCH_I2CCTL);
245
246 pch_dbg(adap,
247 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
248 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
249
250 init_waitqueue_head(&pch_event);
251 }
252
253 /**
254 * pch_i2c_wait_for_bus_idle() - check the status of bus.
255 * @adap: Pointer to struct i2c_algo_pch_data.
256 * @timeout: waiting time counter (ms).
257 */
258 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
259 s32 timeout)
260 {
261 void __iomem *p = adap->pch_base_address;
262 int schedule = 0;
263 unsigned long end = jiffies + msecs_to_jiffies(timeout);
264
265 while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
266 if (time_after(jiffies, end)) {
267 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
268 pch_err(adap, "%s: Timeout Error.return%d\n",
269 __func__, -ETIME);
270 pch_i2c_init(adap);
271
272 return -ETIME;
273 }
274
275 if (!schedule)
276 /* Retry after some usecs */
277 udelay(5);
278 else
279 /* Wait a bit more without consuming CPU */
280 usleep_range(20, 1000);
281
282 schedule = 1;
283 }
284
285 return 0;
286 }
287
288 /**
289 * pch_i2c_start() - Generate I2C start condition in normal mode.
290 * @adap: Pointer to struct i2c_algo_pch_data.
291 *
292 * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
293 */
294 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
295 {
296 void __iomem *p = adap->pch_base_address;
297 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
298 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
299 }
300
301 /**
302 * pch_i2c_stop() - generate stop condition in normal mode.
303 * @adap: Pointer to struct i2c_algo_pch_data.
304 */
305 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
306 {
307 void __iomem *p = adap->pch_base_address;
308 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
309 /* clear the start bit */
310 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
311 }
312
313 static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
314 {
315 long ret;
316 void __iomem *p = adap->pch_base_address;
317
318 ret = wait_event_timeout(pch_event,
319 (adap->pch_event_flag != 0), msecs_to_jiffies(1000));
320 if (!ret) {
321 pch_err(adap, "%s:wait-event timeout\n", __func__);
322 adap->pch_event_flag = 0;
323 pch_i2c_stop(adap);
324 pch_i2c_init(adap);
325 return -ETIMEDOUT;
326 }
327
328 if (adap->pch_event_flag & I2C_ERROR_MASK) {
329 pch_err(adap, "Lost Arbitration\n");
330 adap->pch_event_flag = 0;
331 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
332 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
333 pch_i2c_init(adap);
334 return -EAGAIN;
335 }
336
337 adap->pch_event_flag = 0;
338
339 if (ioread32(p + PCH_I2CSR) & PCH_GETACK) {
340 pch_dbg(adap, "Receive NACK for slave address setting\n");
341 return -ENXIO;
342 }
343
344 return 0;
345 }
346
347 /**
348 * pch_i2c_repstart() - generate repeated start condition in normal mode
349 * @adap: Pointer to struct i2c_algo_pch_data.
350 */
351 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
352 {
353 void __iomem *p = adap->pch_base_address;
354 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
355 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
356 }
357
358 /**
359 * pch_i2c_writebytes() - write data to I2C bus in normal mode
360 * @i2c_adap: Pointer to the struct i2c_adapter.
361 * @last: specifies whether last message or not.
362 * In the case of compound mode it will be 1 for last message,
363 * otherwise 0.
364 * @first: specifies whether first message or not.
365 * 1 for first message otherwise 0.
366 */
367 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
368 struct i2c_msg *msgs, u32 last, u32 first)
369 {
370 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
371 u8 *buf;
372 u32 length;
373 u32 addr;
374 u32 addr_2_msb;
375 u32 addr_8_lsb;
376 s32 wrcount;
377 s32 rtn;
378 void __iomem *p = adap->pch_base_address;
379
380 length = msgs->len;
381 buf = msgs->buf;
382 addr = msgs->addr;
383
384 /* enable master tx */
385 pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
386
387 pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
388 length);
389
390 if (first) {
391 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
392 return -ETIME;
393 }
394
395 if (msgs->flags & I2C_M_TEN) {
396 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
397 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
398 if (first)
399 pch_i2c_start(adap);
400
401 rtn = pch_i2c_wait_for_check_xfer(adap);
402 if (rtn)
403 return rtn;
404
405 addr_8_lsb = (addr & I2C_ADDR_MSK);
406 iowrite32(addr_8_lsb, p + PCH_I2CDR);
407 } else {
408 /* set 7 bit slave address and R/W bit as 0 */
409 iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
410 if (first)
411 pch_i2c_start(adap);
412 }
413
414 rtn = pch_i2c_wait_for_check_xfer(adap);
415 if (rtn)
416 return rtn;
417
418 for (wrcount = 0; wrcount < length; ++wrcount) {
419 /* write buffer value to I2C data register */
420 iowrite32(buf[wrcount], p + PCH_I2CDR);
421 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
422
423 rtn = pch_i2c_wait_for_check_xfer(adap);
424 if (rtn)
425 return rtn;
426
427 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT);
428 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
429 }
430
431 /* check if this is the last message */
432 if (last)
433 pch_i2c_stop(adap);
434 else
435 pch_i2c_repstart(adap);
436
437 pch_dbg(adap, "return=%d\n", wrcount);
438
439 return wrcount;
440 }
441
442 /**
443 * pch_i2c_sendack() - send ACK
444 * @adap: Pointer to struct i2c_algo_pch_data.
445 */
446 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
447 {
448 void __iomem *p = adap->pch_base_address;
449 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
450 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
451 }
452
453 /**
454 * pch_i2c_sendnack() - send NACK
455 * @adap: Pointer to struct i2c_algo_pch_data.
456 */
457 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
458 {
459 void __iomem *p = adap->pch_base_address;
460 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
461 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
462 }
463
464 /**
465 * pch_i2c_restart() - Generate I2C restart condition in normal mode.
466 * @adap: Pointer to struct i2c_algo_pch_data.
467 *
468 * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
469 */
470 static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
471 {
472 void __iomem *p = adap->pch_base_address;
473 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
474 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
475 }
476
477 /**
478 * pch_i2c_readbytes() - read data from I2C bus in normal mode.
479 * @i2c_adap: Pointer to the struct i2c_adapter.
480 * @msgs: Pointer to i2c_msg structure.
481 * @last: specifies whether last message or not.
482 * @first: specifies whether first message or not.
483 */
484 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
485 u32 last, u32 first)
486 {
487 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
488
489 u8 *buf;
490 u32 count;
491 u32 length;
492 u32 addr;
493 u32 addr_2_msb;
494 u32 addr_8_lsb;
495 void __iomem *p = adap->pch_base_address;
496 s32 rtn;
497
498 length = msgs->len;
499 buf = msgs->buf;
500 addr = msgs->addr;
501
502 /* enable master reception */
503 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
504
505 if (first) {
506 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
507 return -ETIME;
508 }
509
510 if (msgs->flags & I2C_M_TEN) {
511 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
512 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
513 if (first)
514 pch_i2c_start(adap);
515
516 rtn = pch_i2c_wait_for_check_xfer(adap);
517 if (rtn)
518 return rtn;
519
520 addr_8_lsb = (addr & I2C_ADDR_MSK);
521 iowrite32(addr_8_lsb, p + PCH_I2CDR);
522
523 pch_i2c_restart(adap);
524
525 rtn = pch_i2c_wait_for_check_xfer(adap);
526 if (rtn)
527 return rtn;
528
529 addr_2_msb |= I2C_RD;
530 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
531 } else {
532 /* 7 address bits + R/W bit */
533 iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
534 }
535
536 /* check if it is the first message */
537 if (first)
538 pch_i2c_start(adap);
539
540 rtn = pch_i2c_wait_for_check_xfer(adap);
541 if (rtn)
542 return rtn;
543
544 if (length == 0) {
545 pch_i2c_stop(adap);
546 ioread32(p + PCH_I2CDR); /* Dummy read needs */
547
548 count = length;
549 } else {
550 int read_index;
551 int loop;
552 pch_i2c_sendack(adap);
553
554 /* Dummy read */
555 for (loop = 1, read_index = 0; loop < length; loop++) {
556 buf[read_index] = ioread32(p + PCH_I2CDR);
557
558 if (loop != 1)
559 read_index++;
560
561 rtn = pch_i2c_wait_for_check_xfer(adap);
562 if (rtn)
563 return rtn;
564 } /* end for */
565
566 pch_i2c_sendnack(adap);
567
568 buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
569
570 if (length != 1)
571 read_index++;
572
573 rtn = pch_i2c_wait_for_check_xfer(adap);
574 if (rtn)
575 return rtn;
576
577 if (last)
578 pch_i2c_stop(adap);
579 else
580 pch_i2c_repstart(adap);
581
582 buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
583 count = read_index;
584 }
585
586 return count;
587 }
588
589 /**
590 * pch_i2c_cb() - Interrupt handler Call back function
591 * @adap: Pointer to struct i2c_algo_pch_data.
592 */
593 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
594 {
595 u32 sts;
596 void __iomem *p = adap->pch_base_address;
597
598 sts = ioread32(p + PCH_I2CSR);
599 sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
600 if (sts & I2CMAL_BIT)
601 adap->pch_event_flag |= I2CMAL_EVENT;
602
603 if (sts & I2CMCF_BIT)
604 adap->pch_event_flag |= I2CMCF_EVENT;
605
606 /* clear the applicable bits */
607 pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
608
609 pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
610
611 wake_up(&pch_event);
612 }
613
614 /**
615 * pch_i2c_handler() - interrupt handler for the PCH I2C controller
616 * @irq: irq number.
617 * @pData: cookie passed back to the handler function.
618 */
619 static irqreturn_t pch_i2c_handler(int irq, void *pData)
620 {
621 u32 reg_val;
622 int flag;
623 int i;
624 struct adapter_info *adap_info = pData;
625 void __iomem *p;
626 u32 mode;
627
628 for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
629 p = adap_info->pch_data[i].pch_base_address;
630 mode = ioread32(p + PCH_I2CMOD);
631 mode &= BUFFER_MODE | EEPROM_SR_MODE;
632 if (mode != NORMAL_MODE) {
633 pch_err(adap_info->pch_data,
634 "I2C-%d mode(%d) is not supported\n", mode, i);
635 continue;
636 }
637 reg_val = ioread32(p + PCH_I2CSR);
638 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
639 pch_i2c_cb(&adap_info->pch_data[i]);
640 flag = 1;
641 }
642 }
643
644 return flag ? IRQ_HANDLED : IRQ_NONE;
645 }
646
647 /**
648 * pch_i2c_xfer() - Reading adnd writing data through I2C bus
649 * @i2c_adap: Pointer to the struct i2c_adapter.
650 * @msgs: Pointer to i2c_msg structure.
651 * @num: number of messages.
652 */
653 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
654 struct i2c_msg *msgs, s32 num)
655 {
656 struct i2c_msg *pmsg;
657 u32 i = 0;
658 u32 status;
659 s32 ret;
660
661 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
662
663 ret = mutex_lock_interruptible(&pch_mutex);
664 if (ret)
665 return ret;
666
667 if (adap->p_adapter_info->pch_i2c_suspended) {
668 mutex_unlock(&pch_mutex);
669 return -EBUSY;
670 }
671
672 pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
673 adap->p_adapter_info->pch_i2c_suspended);
674 /* transfer not completed */
675 adap->pch_i2c_xfer_in_progress = true;
676
677 for (i = 0; i < num && ret >= 0; i++) {
678 pmsg = &msgs[i];
679 pmsg->flags |= adap->pch_buff_mode_en;
680 status = pmsg->flags;
681 pch_dbg(adap,
682 "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
683
684 if ((status & (I2C_M_RD)) != false) {
685 ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
686 (i == 0));
687 } else {
688 ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
689 (i == 0));
690 }
691 }
692
693 adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
694
695 mutex_unlock(&pch_mutex);
696
697 return (ret < 0) ? ret : num;
698 }
699
700 /**
701 * pch_i2c_func() - return the functionality of the I2C driver
702 * @adap: Pointer to struct i2c_algo_pch_data.
703 */
704 static u32 pch_i2c_func(struct i2c_adapter *adap)
705 {
706 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
707 }
708
709 static const struct i2c_algorithm pch_algorithm = {
710 .master_xfer = pch_i2c_xfer,
711 .functionality = pch_i2c_func
712 };
713
714 /**
715 * pch_i2c_disbl_int() - Disable PCH I2C interrupts
716 * @adap: Pointer to struct i2c_algo_pch_data.
717 */
718 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
719 {
720 void __iomem *p = adap->pch_base_address;
721
722 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
723
724 iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
725
726 iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
727 }
728
729 static int pch_i2c_probe(struct pci_dev *pdev,
730 const struct pci_device_id *id)
731 {
732 void __iomem *base_addr;
733 int ret;
734 int i, j;
735 struct adapter_info *adap_info;
736 struct i2c_adapter *pch_adap;
737
738 pch_pci_dbg(pdev, "Entered.\n");
739
740 adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
741 if (adap_info == NULL)
742 return -ENOMEM;
743
744 ret = pci_enable_device(pdev);
745 if (ret) {
746 pch_pci_err(pdev, "pci_enable_device FAILED\n");
747 goto err_pci_enable;
748 }
749
750 ret = pci_request_regions(pdev, KBUILD_MODNAME);
751 if (ret) {
752 pch_pci_err(pdev, "pci_request_regions FAILED\n");
753 goto err_pci_req;
754 }
755
756 base_addr = pci_iomap(pdev, 1, 0);
757
758 if (base_addr == NULL) {
759 pch_pci_err(pdev, "pci_iomap FAILED\n");
760 ret = -ENOMEM;
761 goto err_pci_iomap;
762 }
763
764 /* Set the number of I2C channel instance */
765 adap_info->ch_num = id->driver_data;
766
767 for (i = 0; i < adap_info->ch_num; i++) {
768 pch_adap = &adap_info->pch_data[i].pch_adapter;
769 adap_info->pch_i2c_suspended = false;
770
771 adap_info->pch_data[i].p_adapter_info = adap_info;
772
773 pch_adap->owner = THIS_MODULE;
774 pch_adap->class = I2C_CLASS_HWMON;
775 strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
776 pch_adap->algo = &pch_algorithm;
777 pch_adap->algo_data = &adap_info->pch_data[i];
778
779 /* base_addr + offset; */
780 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
781
782 pch_adap->dev.of_node = pdev->dev.of_node;
783 pch_adap->dev.parent = &pdev->dev;
784 }
785
786 ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
787 KBUILD_MODNAME, adap_info);
788 if (ret) {
789 pch_pci_err(pdev, "request_irq FAILED\n");
790 goto err_request_irq;
791 }
792
793 for (i = 0; i < adap_info->ch_num; i++) {
794 pch_adap = &adap_info->pch_data[i].pch_adapter;
795
796 pch_i2c_init(&adap_info->pch_data[i]);
797
798 pch_adap->nr = i;
799 ret = i2c_add_numbered_adapter(pch_adap);
800 if (ret) {
801 pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
802 goto err_add_adapter;
803 }
804 }
805
806 pci_set_drvdata(pdev, adap_info);
807 pch_pci_dbg(pdev, "returns %d.\n", ret);
808 return 0;
809
810 err_add_adapter:
811 for (j = 0; j < i; j++)
812 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
813 free_irq(pdev->irq, adap_info);
814 err_request_irq:
815 pci_iounmap(pdev, base_addr);
816 err_pci_iomap:
817 pci_release_regions(pdev);
818 err_pci_req:
819 pci_disable_device(pdev);
820 err_pci_enable:
821 kfree(adap_info);
822 return ret;
823 }
824
825 static void pch_i2c_remove(struct pci_dev *pdev)
826 {
827 int i;
828 struct adapter_info *adap_info = pci_get_drvdata(pdev);
829
830 free_irq(pdev->irq, adap_info);
831
832 for (i = 0; i < adap_info->ch_num; i++) {
833 pch_i2c_disbl_int(&adap_info->pch_data[i]);
834 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
835 }
836
837 if (adap_info->pch_data[0].pch_base_address)
838 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
839
840 for (i = 0; i < adap_info->ch_num; i++)
841 adap_info->pch_data[i].pch_base_address = NULL;
842
843 pci_release_regions(pdev);
844
845 pci_disable_device(pdev);
846 kfree(adap_info);
847 }
848
849 #ifdef CONFIG_PM
850 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
851 {
852 int ret;
853 int i;
854 struct adapter_info *adap_info = pci_get_drvdata(pdev);
855 void __iomem *p = adap_info->pch_data[0].pch_base_address;
856
857 adap_info->pch_i2c_suspended = true;
858
859 for (i = 0; i < adap_info->ch_num; i++) {
860 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
861 /* Wait until all channel transfers are completed */
862 msleep(20);
863 }
864 }
865
866 /* Disable the i2c interrupts */
867 for (i = 0; i < adap_info->ch_num; i++)
868 pch_i2c_disbl_int(&adap_info->pch_data[i]);
869
870 pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
871 "invoked function pch_i2c_disbl_int successfully\n",
872 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
873 ioread32(p + PCH_I2CESRSTA));
874
875 ret = pci_save_state(pdev);
876
877 if (ret) {
878 pch_pci_err(pdev, "pci_save_state\n");
879 return ret;
880 }
881
882 pci_enable_wake(pdev, PCI_D3hot, 0);
883 pci_disable_device(pdev);
884 pci_set_power_state(pdev, pci_choose_state(pdev, state));
885
886 return 0;
887 }
888
889 static int pch_i2c_resume(struct pci_dev *pdev)
890 {
891 int i;
892 struct adapter_info *adap_info = pci_get_drvdata(pdev);
893
894 pci_set_power_state(pdev, PCI_D0);
895 pci_restore_state(pdev);
896
897 if (pci_enable_device(pdev) < 0) {
898 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
899 return -EIO;
900 }
901
902 pci_enable_wake(pdev, PCI_D3hot, 0);
903
904 for (i = 0; i < adap_info->ch_num; i++)
905 pch_i2c_init(&adap_info->pch_data[i]);
906
907 adap_info->pch_i2c_suspended = false;
908
909 return 0;
910 }
911 #else
912 #define pch_i2c_suspend NULL
913 #define pch_i2c_resume NULL
914 #endif
915
916 static struct pci_driver pch_pcidriver = {
917 .name = KBUILD_MODNAME,
918 .id_table = pch_pcidev_id,
919 .probe = pch_i2c_probe,
920 .remove = pch_i2c_remove,
921 .suspend = pch_i2c_suspend,
922 .resume = pch_i2c_resume
923 };
924
925 module_pci_driver(pch_pcidriver);
926
927 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
928 MODULE_LICENSE("GPL");
929 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
930 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
931 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
Linux with added FPC-III support