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Merge branch 'work.regset' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[linux/fpc-iii.git] / drivers / media / i2c / mt9v032.c
blob5bd3ae82992f35b59339f8283471caed95c3d6c4
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for MT9V022, MT9V024, MT9V032, and MT9V034 CMOS Image Sensors
4 *
5 * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
6 *
7 * Based on the MT9M001 driver,
8 *
9 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
10 */
11
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/log2.h>
17 #include <linux/mutex.h>
18 #include <linux/of.h>
19 #include <linux/of_graph.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
22 #include <linux/videodev2.h>
23 #include <linux/v4l2-mediabus.h>
24 #include <linux/module.h>
25
26 #include <media/i2c/mt9v032.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
30 #include <media/v4l2-subdev.h>
31
32 /* The first four rows are black rows. The active area spans 753x481 pixels. */
33 #define MT9V032_PIXEL_ARRAY_HEIGHT 485
34 #define MT9V032_PIXEL_ARRAY_WIDTH 753
35
36 #define MT9V032_SYSCLK_FREQ_DEF 26600000
37
38 #define MT9V032_CHIP_VERSION 0x00
39 #define MT9V032_CHIP_ID_REV1 0x1311
40 #define MT9V032_CHIP_ID_REV3 0x1313
41 #define MT9V034_CHIP_ID_REV1 0X1324
42 #define MT9V032_COLUMN_START 0x01
43 #define MT9V032_COLUMN_START_MIN 1
44 #define MT9V032_COLUMN_START_DEF 1
45 #define MT9V032_COLUMN_START_MAX 752
46 #define MT9V032_ROW_START 0x02
47 #define MT9V032_ROW_START_MIN 4
48 #define MT9V032_ROW_START_DEF 5
49 #define MT9V032_ROW_START_MAX 482
50 #define MT9V032_WINDOW_HEIGHT 0x03
51 #define MT9V032_WINDOW_HEIGHT_MIN 1
52 #define MT9V032_WINDOW_HEIGHT_DEF 480
53 #define MT9V032_WINDOW_HEIGHT_MAX 480
54 #define MT9V032_WINDOW_WIDTH 0x04
55 #define MT9V032_WINDOW_WIDTH_MIN 1
56 #define MT9V032_WINDOW_WIDTH_DEF 752
57 #define MT9V032_WINDOW_WIDTH_MAX 752
58 #define MT9V032_HORIZONTAL_BLANKING 0x05
59 #define MT9V032_HORIZONTAL_BLANKING_MIN 43
60 #define MT9V034_HORIZONTAL_BLANKING_MIN 61
61 #define MT9V032_HORIZONTAL_BLANKING_DEF 94
62 #define MT9V032_HORIZONTAL_BLANKING_MAX 1023
63 #define MT9V032_VERTICAL_BLANKING 0x06
64 #define MT9V032_VERTICAL_BLANKING_MIN 4
65 #define MT9V034_VERTICAL_BLANKING_MIN 2
66 #define MT9V032_VERTICAL_BLANKING_DEF 45
67 #define MT9V032_VERTICAL_BLANKING_MAX 3000
68 #define MT9V034_VERTICAL_BLANKING_MAX 32288
69 #define MT9V032_CHIP_CONTROL 0x07
70 #define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3)
71 #define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7)
72 #define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8)
73 #define MT9V032_SHUTTER_WIDTH1 0x08
74 #define MT9V032_SHUTTER_WIDTH2 0x09
75 #define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a
76 #define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b
77 #define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1
78 #define MT9V034_TOTAL_SHUTTER_WIDTH_MIN 0
79 #define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480
80 #define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767
81 #define MT9V034_TOTAL_SHUTTER_WIDTH_MAX 32765
82 #define MT9V032_RESET 0x0c
83 #define MT9V032_READ_MODE 0x0d
84 #define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0)
85 #define MT9V032_READ_MODE_ROW_BIN_SHIFT 0
86 #define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2)
87 #define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2
88 #define MT9V032_READ_MODE_ROW_FLIP (1 << 4)
89 #define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5)
90 #define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6)
91 #define MT9V032_READ_MODE_DARK_ROWS (1 << 7)
92 #define MT9V032_READ_MODE_RESERVED 0x0300
93 #define MT9V032_PIXEL_OPERATION_MODE 0x0f
94 #define MT9V034_PIXEL_OPERATION_MODE_HDR (1 << 0)
95 #define MT9V034_PIXEL_OPERATION_MODE_COLOR (1 << 1)
96 #define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2)
97 #define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6)
98 #define MT9V032_ANALOG_GAIN 0x35
99 #define MT9V032_ANALOG_GAIN_MIN 16
100 #define MT9V032_ANALOG_GAIN_DEF 16
101 #define MT9V032_ANALOG_GAIN_MAX 64
102 #define MT9V032_MAX_ANALOG_GAIN 0x36
103 #define MT9V032_MAX_ANALOG_GAIN_MAX 127
104 #define MT9V032_FRAME_DARK_AVERAGE 0x42
105 #define MT9V032_DARK_AVG_THRESH 0x46
106 #define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0)
107 #define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0
108 #define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8)
109 #define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8
110 #define MT9V032_ROW_NOISE_CORR_CONTROL 0x70
111 #define MT9V034_ROW_NOISE_CORR_ENABLE (1 << 0)
112 #define MT9V034_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1)
113 #define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5)
114 #define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7)
115 #define MT9V032_PIXEL_CLOCK 0x74
116 #define MT9V034_PIXEL_CLOCK 0x72
117 #define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0)
118 #define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1)
119 #define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2)
120 #define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3)
121 #define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4)
122 #define MT9V032_TEST_PATTERN 0x7f
123 #define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0)
124 #define MT9V032_TEST_PATTERN_DATA_SHIFT 0
125 #define MT9V032_TEST_PATTERN_USE_DATA (1 << 10)
126 #define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11)
127 #define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11)
128 #define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11)
129 #define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11)
130 #define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11)
131 #define MT9V032_TEST_PATTERN_ENABLE (1 << 13)
132 #define MT9V032_TEST_PATTERN_FLIP (1 << 14)
133 #define MT9V032_AEGC_DESIRED_BIN 0xa5
134 #define MT9V032_AEC_UPDATE_FREQUENCY 0xa6
135 #define MT9V032_AEC_LPF 0xa8
136 #define MT9V032_AGC_UPDATE_FREQUENCY 0xa9
137 #define MT9V032_AGC_LPF 0xaa
138 #define MT9V032_AEC_AGC_ENABLE 0xaf
139 #define MT9V032_AEC_ENABLE (1 << 0)
140 #define MT9V032_AGC_ENABLE (1 << 1)
141 #define MT9V034_AEC_MAX_SHUTTER_WIDTH 0xad
142 #define MT9V032_AEC_MAX_SHUTTER_WIDTH 0xbd
143 #define MT9V032_THERMAL_INFO 0xc1
144
145 enum mt9v032_model {
146 MT9V032_MODEL_V022_COLOR, /* MT9V022IX7ATC */
147 MT9V032_MODEL_V022_MONO, /* MT9V022IX7ATM */
148 MT9V032_MODEL_V024_COLOR, /* MT9V024IA7XTC */
149 MT9V032_MODEL_V024_MONO, /* MT9V024IA7XTM */
150 MT9V032_MODEL_V032_COLOR, /* MT9V032C12STM */
151 MT9V032_MODEL_V032_MONO, /* MT9V032C12STC */
152 MT9V032_MODEL_V034_COLOR,
153 MT9V032_MODEL_V034_MONO,
154 };
155
156 struct mt9v032_model_version {
157 unsigned int version;
158 const char *name;
159 };
160
161 struct mt9v032_model_data {
162 unsigned int min_row_time;
163 unsigned int min_hblank;
164 unsigned int min_vblank;
165 unsigned int max_vblank;
166 unsigned int min_shutter;
167 unsigned int max_shutter;
168 unsigned int pclk_reg;
169 unsigned int aec_max_shutter_reg;
170 const struct v4l2_ctrl_config * const aec_max_shutter_v4l2_ctrl;
171 };
172
173 struct mt9v032_model_info {
174 const struct mt9v032_model_data *data;
175 bool color;
176 };
177
178 static const struct mt9v032_model_version mt9v032_versions[] = {
179 { MT9V032_CHIP_ID_REV1, "MT9V022/MT9V032 rev1/2" },
180 { MT9V032_CHIP_ID_REV3, "MT9V022/MT9V032 rev3" },
181 { MT9V034_CHIP_ID_REV1, "MT9V024/MT9V034 rev1" },
182 };
183
184 struct mt9v032 {
185 struct v4l2_subdev subdev;
186 struct media_pad pad;
187
188 struct v4l2_mbus_framefmt format;
189 struct v4l2_rect crop;
190 unsigned int hratio;
191 unsigned int vratio;
192
193 struct v4l2_ctrl_handler ctrls;
194 struct {
195 struct v4l2_ctrl *link_freq;
196 struct v4l2_ctrl *pixel_rate;
197 };
198
199 struct mutex power_lock;
200 int power_count;
201
202 struct regmap *regmap;
203 struct clk *clk;
204 struct gpio_desc *reset_gpio;
205 struct gpio_desc *standby_gpio;
206
207 struct mt9v032_platform_data *pdata;
208 const struct mt9v032_model_info *model;
209 const struct mt9v032_model_version *version;
210
211 u32 sysclk;
212 u16 aec_agc;
213 u16 hblank;
214 struct {
215 struct v4l2_ctrl *test_pattern;
216 struct v4l2_ctrl *test_pattern_color;
217 };
218 };
219
220 static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd)
221 {
222 return container_of(sd, struct mt9v032, subdev);
223 }
224
225 static int
226 mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable)
227 {
228 struct regmap *map = mt9v032->regmap;
229 u16 value = mt9v032->aec_agc;
230 int ret;
231
232 if (enable)
233 value |= which;
234 else
235 value &= ~which;
236
237 ret = regmap_write(map, MT9V032_AEC_AGC_ENABLE, value);
238 if (ret < 0)
239 return ret;
240
241 mt9v032->aec_agc = value;
242 return 0;
243 }
244
245 static int
246 mt9v032_update_hblank(struct mt9v032 *mt9v032)
247 {
248 struct v4l2_rect *crop = &mt9v032->crop;
249 unsigned int min_hblank = mt9v032->model->data->min_hblank;
250 unsigned int hblank;
251
252 if (mt9v032->version->version == MT9V034_CHIP_ID_REV1)
253 min_hblank += (mt9v032->hratio - 1) * 10;
254 min_hblank = max_t(int, mt9v032->model->data->min_row_time - crop->width,
255 min_hblank);
256 hblank = max_t(unsigned int, mt9v032->hblank, min_hblank);
257
258 return regmap_write(mt9v032->regmap, MT9V032_HORIZONTAL_BLANKING,
259 hblank);
260 }
261
262 static int mt9v032_power_on(struct mt9v032 *mt9v032)
263 {
264 struct regmap *map = mt9v032->regmap;
265 int ret;
266
267 gpiod_set_value_cansleep(mt9v032->reset_gpio, 1);
268
269 ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk);
270 if (ret < 0)
271 return ret;
272
273 /* System clock has to be enabled before releasing the reset */
274 ret = clk_prepare_enable(mt9v032->clk);
275 if (ret)
276 return ret;
277
278 udelay(1);
279
280 if (mt9v032->reset_gpio) {
281 gpiod_set_value_cansleep(mt9v032->reset_gpio, 0);
282
283 /* After releasing reset we need to wait 10 clock cycles
284 * before accessing the sensor over I2C. As the minimum SYSCLK
285 * frequency is 13MHz, waiting 1µs will be enough in the worst
286 * case.
287 */
288 udelay(1);
289 }
290
291 /* Reset the chip and stop data read out */
292 ret = regmap_write(map, MT9V032_RESET, 1);
293 if (ret < 0)
294 goto err;
295
296 ret = regmap_write(map, MT9V032_RESET, 0);
297 if (ret < 0)
298 goto err;
299
300 ret = regmap_write(map, MT9V032_CHIP_CONTROL,
301 MT9V032_CHIP_CONTROL_MASTER_MODE);
302 if (ret < 0)
303 goto err;
304
305 return 0;
306
307 err:
308 clk_disable_unprepare(mt9v032->clk);
309 return ret;
310 }
311
312 static void mt9v032_power_off(struct mt9v032 *mt9v032)
313 {
314 clk_disable_unprepare(mt9v032->clk);
315 }
316
317 static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on)
318 {
319 struct regmap *map = mt9v032->regmap;
320 int ret;
321
322 if (!on) {
323 mt9v032_power_off(mt9v032);
324 return 0;
325 }
326
327 ret = mt9v032_power_on(mt9v032);
328 if (ret < 0)
329 return ret;
330
331 /* Configure the pixel clock polarity */
332 if (mt9v032->pdata && mt9v032->pdata->clk_pol) {
333 ret = regmap_write(map, mt9v032->model->data->pclk_reg,
334 MT9V032_PIXEL_CLOCK_INV_PXL_CLK);
335 if (ret < 0)
336 return ret;
337 }
338
339 /* Disable the noise correction algorithm and restore the controls. */
340 ret = regmap_write(map, MT9V032_ROW_NOISE_CORR_CONTROL, 0);
341 if (ret < 0)
342 return ret;
343
344 return v4l2_ctrl_handler_setup(&mt9v032->ctrls);
345 }
346
347 /* -----------------------------------------------------------------------------
348 * V4L2 subdev video operations
349 */
350
351 static struct v4l2_mbus_framefmt *
352 __mt9v032_get_pad_format(struct mt9v032 *mt9v032, struct v4l2_subdev_pad_config *cfg,
353 unsigned int pad, enum v4l2_subdev_format_whence which)
354 {
355 switch (which) {
356 case V4L2_SUBDEV_FORMAT_TRY:
357 return v4l2_subdev_get_try_format(&mt9v032->subdev, cfg, pad);
358 case V4L2_SUBDEV_FORMAT_ACTIVE:
359 return &mt9v032->format;
360 default:
361 return NULL;
362 }
363 }
364
365 static struct v4l2_rect *
366 __mt9v032_get_pad_crop(struct mt9v032 *mt9v032, struct v4l2_subdev_pad_config *cfg,
367 unsigned int pad, enum v4l2_subdev_format_whence which)
368 {
369 switch (which) {
370 case V4L2_SUBDEV_FORMAT_TRY:
371 return v4l2_subdev_get_try_crop(&mt9v032->subdev, cfg, pad);
372 case V4L2_SUBDEV_FORMAT_ACTIVE:
373 return &mt9v032->crop;
374 default:
375 return NULL;
376 }
377 }
378
379 static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable)
380 {
381 const u16 mode = MT9V032_CHIP_CONTROL_DOUT_ENABLE
382 | MT9V032_CHIP_CONTROL_SEQUENTIAL;
383 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
384 struct v4l2_rect *crop = &mt9v032->crop;
385 struct regmap *map = mt9v032->regmap;
386 unsigned int hbin;
387 unsigned int vbin;
388 int ret;
389
390 if (!enable)
391 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, 0);
392
393 /* Configure the window size and row/column bin */
394 hbin = fls(mt9v032->hratio) - 1;
395 vbin = fls(mt9v032->vratio) - 1;
396 ret = regmap_update_bits(map, MT9V032_READ_MODE,
397 ~MT9V032_READ_MODE_RESERVED,
398 hbin << MT9V032_READ_MODE_COLUMN_BIN_SHIFT |
399 vbin << MT9V032_READ_MODE_ROW_BIN_SHIFT);
400 if (ret < 0)
401 return ret;
402
403 ret = regmap_write(map, MT9V032_COLUMN_START, crop->left);
404 if (ret < 0)
405 return ret;
406
407 ret = regmap_write(map, MT9V032_ROW_START, crop->top);
408 if (ret < 0)
409 return ret;
410
411 ret = regmap_write(map, MT9V032_WINDOW_WIDTH, crop->width);
412 if (ret < 0)
413 return ret;
414
415 ret = regmap_write(map, MT9V032_WINDOW_HEIGHT, crop->height);
416 if (ret < 0)
417 return ret;
418
419 ret = mt9v032_update_hblank(mt9v032);
420 if (ret < 0)
421 return ret;
422
423 /* Switch to master "normal" mode */
424 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, mode);
425 }
426
427 static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev,
428 struct v4l2_subdev_pad_config *cfg,
429 struct v4l2_subdev_mbus_code_enum *code)
430 {
431 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
432
433 if (code->index > 0)
434 return -EINVAL;
435
436 code->code = mt9v032->format.code;
437 return 0;
438 }
439
440 static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev,
441 struct v4l2_subdev_pad_config *cfg,
442 struct v4l2_subdev_frame_size_enum *fse)
443 {
444 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
445
446 if (fse->index >= 3)
447 return -EINVAL;
448 if (mt9v032->format.code != fse->code)
449 return -EINVAL;
450
451 fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index);
452 fse->max_width = fse->min_width;
453 fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / (1 << fse->index);
454 fse->max_height = fse->min_height;
455
456 return 0;
457 }
458
459 static int mt9v032_get_format(struct v4l2_subdev *subdev,
460 struct v4l2_subdev_pad_config *cfg,
461 struct v4l2_subdev_format *format)
462 {
463 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
464
465 format->format = *__mt9v032_get_pad_format(mt9v032, cfg, format->pad,
466 format->which);
467 return 0;
468 }
469
470 static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032)
471 {
472 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
473 int ret;
474
475 ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate,
476 mt9v032->sysclk / mt9v032->hratio);
477 if (ret < 0)
478 dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret);
479 }
480
481 static unsigned int mt9v032_calc_ratio(unsigned int input, unsigned int output)
482 {
483 /* Compute the power-of-two binning factor closest to the input size to
484 * output size ratio. Given that the output size is bounded by input/4
485 * and input, a generic implementation would be an ineffective luxury.
486 */
487 if (output * 3 > input * 2)
488 return 1;
489 if (output * 3 > input)
490 return 2;
491 return 4;
492 }
493
494 static int mt9v032_set_format(struct v4l2_subdev *subdev,
495 struct v4l2_subdev_pad_config *cfg,
496 struct v4l2_subdev_format *format)
497 {
498 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
499 struct v4l2_mbus_framefmt *__format;
500 struct v4l2_rect *__crop;
501 unsigned int width;
502 unsigned int height;
503 unsigned int hratio;
504 unsigned int vratio;
505
506 __crop = __mt9v032_get_pad_crop(mt9v032, cfg, format->pad,
507 format->which);
508
509 /* Clamp the width and height to avoid dividing by zero. */
510 width = clamp(ALIGN(format->format.width, 2),
511 max_t(unsigned int, __crop->width / 4,
512 MT9V032_WINDOW_WIDTH_MIN),
513 __crop->width);
514 height = clamp(ALIGN(format->format.height, 2),
515 max_t(unsigned int, __crop->height / 4,
516 MT9V032_WINDOW_HEIGHT_MIN),
517 __crop->height);
518
519 hratio = mt9v032_calc_ratio(__crop->width, width);
520 vratio = mt9v032_calc_ratio(__crop->height, height);
521
522 __format = __mt9v032_get_pad_format(mt9v032, cfg, format->pad,
523 format->which);
524 __format->width = __crop->width / hratio;
525 __format->height = __crop->height / vratio;
526
527 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
528 mt9v032->hratio = hratio;
529 mt9v032->vratio = vratio;
530 mt9v032_configure_pixel_rate(mt9v032);
531 }
532
533 format->format = *__format;
534
535 return 0;
536 }
537
538 static int mt9v032_get_selection(struct v4l2_subdev *subdev,
539 struct v4l2_subdev_pad_config *cfg,
540 struct v4l2_subdev_selection *sel)
541 {
542 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
543
544 if (sel->target != V4L2_SEL_TGT_CROP)
545 return -EINVAL;
546
547 sel->r = *__mt9v032_get_pad_crop(mt9v032, cfg, sel->pad, sel->which);
548 return 0;
549 }
550
551 static int mt9v032_set_selection(struct v4l2_subdev *subdev,
552 struct v4l2_subdev_pad_config *cfg,
553 struct v4l2_subdev_selection *sel)
554 {
555 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
556 struct v4l2_mbus_framefmt *__format;
557 struct v4l2_rect *__crop;
558 struct v4l2_rect rect;
559
560 if (sel->target != V4L2_SEL_TGT_CROP)
561 return -EINVAL;
562
563 /* Clamp the crop rectangle boundaries and align them to a non multiple
564 * of 2 pixels to ensure a GRBG Bayer pattern.
565 */
566 rect.left = clamp(ALIGN(sel->r.left + 1, 2) - 1,
567 MT9V032_COLUMN_START_MIN,
568 MT9V032_COLUMN_START_MAX);
569 rect.top = clamp(ALIGN(sel->r.top + 1, 2) - 1,
570 MT9V032_ROW_START_MIN,
571 MT9V032_ROW_START_MAX);
572 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2),
573 MT9V032_WINDOW_WIDTH_MIN,
574 MT9V032_WINDOW_WIDTH_MAX);
575 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2),
576 MT9V032_WINDOW_HEIGHT_MIN,
577 MT9V032_WINDOW_HEIGHT_MAX);
578
579 rect.width = min_t(unsigned int,
580 rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left);
581 rect.height = min_t(unsigned int,
582 rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top);
583
584 __crop = __mt9v032_get_pad_crop(mt9v032, cfg, sel->pad, sel->which);
585
586 if (rect.width != __crop->width || rect.height != __crop->height) {
587 /* Reset the output image size if the crop rectangle size has
588 * been modified.
589 */
590 __format = __mt9v032_get_pad_format(mt9v032, cfg, sel->pad,
591 sel->which);
592 __format->width = rect.width;
593 __format->height = rect.height;
594 if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
595 mt9v032->hratio = 1;
596 mt9v032->vratio = 1;
597 mt9v032_configure_pixel_rate(mt9v032);
598 }
599 }
600
601 *__crop = rect;
602 sel->r = rect;
603
604 return 0;
605 }
606
607 /* -----------------------------------------------------------------------------
608 * V4L2 subdev control operations
609 */
610
611 #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
612 /*
613 * Value between 1 and 64 to set the desired bin. This is effectively a measure
614 * of how bright the image is supposed to be. Both AGC and AEC try to reach
615 * this.
616 */
617 #define V4L2_CID_AEGC_DESIRED_BIN (V4L2_CID_USER_BASE | 0x1002)
618 /*
619 * LPF is the low pass filter capability of the chip. Both AEC and AGC have
620 * this setting. This limits the speed in which AGC/AEC adjust their settings.
621 * Possible values are 0-2. 0 means no LPF. For 1 and 2 this equation is used:
622 *
623 * if |(calculated new exp - current exp)| > (current exp / 4)
624 * next exp = calculated new exp
625 * else
626 * next exp = current exp + ((calculated new exp - current exp) / 2^LPF)
627 */
628 #define V4L2_CID_AEC_LPF (V4L2_CID_USER_BASE | 0x1003)
629 #define V4L2_CID_AGC_LPF (V4L2_CID_USER_BASE | 0x1004)
630 /*
631 * Value between 0 and 15. This is the number of frames being skipped before
632 * updating the auto exposure/gain.
633 */
634 #define V4L2_CID_AEC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1005)
635 #define V4L2_CID_AGC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1006)
636 /*
637 * Maximum shutter width used for AEC.
638 */
639 #define V4L2_CID_AEC_MAX_SHUTTER_WIDTH (V4L2_CID_USER_BASE | 0x1007)
640
641 static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
642 {
643 struct mt9v032 *mt9v032 =
644 container_of(ctrl->handler, struct mt9v032, ctrls);
645 struct regmap *map = mt9v032->regmap;
646 u32 freq;
647 u16 data;
648
649 switch (ctrl->id) {
650 case V4L2_CID_AUTOGAIN:
651 return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE,
652 ctrl->val);
653
654 case V4L2_CID_GAIN:
655 return regmap_write(map, MT9V032_ANALOG_GAIN, ctrl->val);
656
657 case V4L2_CID_EXPOSURE_AUTO:
658 return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE,
659 !ctrl->val);
660
661 case V4L2_CID_EXPOSURE:
662 return regmap_write(map, MT9V032_TOTAL_SHUTTER_WIDTH,
663 ctrl->val);
664
665 case V4L2_CID_HBLANK:
666 mt9v032->hblank = ctrl->val;
667 return mt9v032_update_hblank(mt9v032);
668
669 case V4L2_CID_VBLANK:
670 return regmap_write(map, MT9V032_VERTICAL_BLANKING,
671 ctrl->val);
672
673 case V4L2_CID_PIXEL_RATE:
674 case V4L2_CID_LINK_FREQ:
675 if (mt9v032->link_freq == NULL)
676 break;
677
678 freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val];
679 *mt9v032->pixel_rate->p_new.p_s64 = freq;
680 mt9v032->sysclk = freq;
681 break;
682
683 case V4L2_CID_TEST_PATTERN:
684 switch (mt9v032->test_pattern->val) {
685 case 0:
686 data = 0;
687 break;
688 case 1:
689 data = MT9V032_TEST_PATTERN_GRAY_VERTICAL
690 | MT9V032_TEST_PATTERN_ENABLE;
691 break;
692 case 2:
693 data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL
694 | MT9V032_TEST_PATTERN_ENABLE;
695 break;
696 case 3:
697 data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL
698 | MT9V032_TEST_PATTERN_ENABLE;
699 break;
700 default:
701 data = (mt9v032->test_pattern_color->val <<
702 MT9V032_TEST_PATTERN_DATA_SHIFT)
703 | MT9V032_TEST_PATTERN_USE_DATA
704 | MT9V032_TEST_PATTERN_ENABLE
705 | MT9V032_TEST_PATTERN_FLIP;
706 break;
707 }
708 return regmap_write(map, MT9V032_TEST_PATTERN, data);
709
710 case V4L2_CID_AEGC_DESIRED_BIN:
711 return regmap_write(map, MT9V032_AEGC_DESIRED_BIN, ctrl->val);
712
713 case V4L2_CID_AEC_LPF:
714 return regmap_write(map, MT9V032_AEC_LPF, ctrl->val);
715
716 case V4L2_CID_AGC_LPF:
717 return regmap_write(map, MT9V032_AGC_LPF, ctrl->val);
718
719 case V4L2_CID_AEC_UPDATE_INTERVAL:
720 return regmap_write(map, MT9V032_AEC_UPDATE_FREQUENCY,
721 ctrl->val);
722
723 case V4L2_CID_AGC_UPDATE_INTERVAL:
724 return regmap_write(map, MT9V032_AGC_UPDATE_FREQUENCY,
725 ctrl->val);
726
727 case V4L2_CID_AEC_MAX_SHUTTER_WIDTH:
728 return regmap_write(map,
729 mt9v032->model->data->aec_max_shutter_reg,
730 ctrl->val);
731 }
732
733 return 0;
734 }
735
736 static const struct v4l2_ctrl_ops mt9v032_ctrl_ops = {
737 .s_ctrl = mt9v032_s_ctrl,
738 };
739
740 static const char * const mt9v032_test_pattern_menu[] = {
741 "Disabled",
742 "Gray Vertical Shade",
743 "Gray Horizontal Shade",
744 "Gray Diagonal Shade",
745 "Plain",
746 };
747
748 static const struct v4l2_ctrl_config mt9v032_test_pattern_color = {
749 .ops = &mt9v032_ctrl_ops,
750 .id = V4L2_CID_TEST_PATTERN_COLOR,
751 .type = V4L2_CTRL_TYPE_INTEGER,
752 .name = "Test Pattern Color",
753 .min = 0,
754 .max = 1023,
755 .step = 1,
756 .def = 0,
757 .flags = 0,
758 };
759
760 static const struct v4l2_ctrl_config mt9v032_aegc_controls[] = {
761 {
762 .ops = &mt9v032_ctrl_ops,
763 .id = V4L2_CID_AEGC_DESIRED_BIN,
764 .type = V4L2_CTRL_TYPE_INTEGER,
765 .name = "AEC/AGC Desired Bin",
766 .min = 1,
767 .max = 64,
768 .step = 1,
769 .def = 58,
770 .flags = 0,
771 }, {
772 .ops = &mt9v032_ctrl_ops,
773 .id = V4L2_CID_AEC_LPF,
774 .type = V4L2_CTRL_TYPE_INTEGER,
775 .name = "AEC Low Pass Filter",
776 .min = 0,
777 .max = 2,
778 .step = 1,
779 .def = 0,
780 .flags = 0,
781 }, {
782 .ops = &mt9v032_ctrl_ops,
783 .id = V4L2_CID_AGC_LPF,
784 .type = V4L2_CTRL_TYPE_INTEGER,
785 .name = "AGC Low Pass Filter",
786 .min = 0,
787 .max = 2,
788 .step = 1,
789 .def = 2,
790 .flags = 0,
791 }, {
792 .ops = &mt9v032_ctrl_ops,
793 .id = V4L2_CID_AEC_UPDATE_INTERVAL,
794 .type = V4L2_CTRL_TYPE_INTEGER,
795 .name = "AEC Update Interval",
796 .min = 0,
797 .max = 16,
798 .step = 1,
799 .def = 2,
800 .flags = 0,
801 }, {
802 .ops = &mt9v032_ctrl_ops,
803 .id = V4L2_CID_AGC_UPDATE_INTERVAL,
804 .type = V4L2_CTRL_TYPE_INTEGER,
805 .name = "AGC Update Interval",
806 .min = 0,
807 .max = 16,
808 .step = 1,
809 .def = 2,
810 .flags = 0,
811 }
812 };
813
814 static const struct v4l2_ctrl_config mt9v032_aec_max_shutter_width = {
815 .ops = &mt9v032_ctrl_ops,
816 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
817 .type = V4L2_CTRL_TYPE_INTEGER,
818 .name = "AEC Max Shutter Width",
819 .min = 1,
820 .max = 2047,
821 .step = 1,
822 .def = 480,
823 .flags = 0,
824 };
825
826 static const struct v4l2_ctrl_config mt9v034_aec_max_shutter_width = {
827 .ops = &mt9v032_ctrl_ops,
828 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
829 .type = V4L2_CTRL_TYPE_INTEGER,
830 .name = "AEC Max Shutter Width",
831 .min = 1,
832 .max = 32765,
833 .step = 1,
834 .def = 480,
835 .flags = 0,
836 };
837
838 /* -----------------------------------------------------------------------------
839 * V4L2 subdev core operations
840 */
841
842 static int mt9v032_set_power(struct v4l2_subdev *subdev, int on)
843 {
844 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
845 int ret = 0;
846
847 mutex_lock(&mt9v032->power_lock);
848
849 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
850 * update the power state.
851 */
852 if (mt9v032->power_count == !on) {
853 ret = __mt9v032_set_power(mt9v032, !!on);
854 if (ret < 0)
855 goto done;
856 }
857
858 /* Update the power count. */
859 mt9v032->power_count += on ? 1 : -1;
860 WARN_ON(mt9v032->power_count < 0);
861
862 done:
863 mutex_unlock(&mt9v032->power_lock);
864 return ret;
865 }
866
867 /* -----------------------------------------------------------------------------
868 * V4L2 subdev internal operations
869 */
870
871 static int mt9v032_registered(struct v4l2_subdev *subdev)
872 {
873 struct i2c_client *client = v4l2_get_subdevdata(subdev);
874 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
875 unsigned int i;
876 u32 version;
877 int ret;
878
879 dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n",
880 client->addr);
881
882 ret = mt9v032_power_on(mt9v032);
883 if (ret < 0) {
884 dev_err(&client->dev, "MT9V032 power up failed\n");
885 return ret;
886 }
887
888 /* Read and check the sensor version */
889 ret = regmap_read(mt9v032->regmap, MT9V032_CHIP_VERSION, &version);
890
891 mt9v032_power_off(mt9v032);
892
893 if (ret < 0) {
894 dev_err(&client->dev, "Failed reading chip version\n");
895 return ret;
896 }
897
898 for (i = 0; i < ARRAY_SIZE(mt9v032_versions); ++i) {
899 if (mt9v032_versions[i].version == version) {
900 mt9v032->version = &mt9v032_versions[i];
901 break;
902 }
903 }
904
905 if (mt9v032->version == NULL) {
906 dev_err(&client->dev, "Unsupported chip version 0x%04x\n",
907 version);
908 return -ENODEV;
909 }
910
911 dev_info(&client->dev, "%s detected at address 0x%02x\n",
912 mt9v032->version->name, client->addr);
913
914 mt9v032_configure_pixel_rate(mt9v032);
915
916 return ret;
917 }
918
919 static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
920 {
921 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
922 struct v4l2_mbus_framefmt *format;
923 struct v4l2_rect *crop;
924
925 crop = v4l2_subdev_get_try_crop(subdev, fh->pad, 0);
926 crop->left = MT9V032_COLUMN_START_DEF;
927 crop->top = MT9V032_ROW_START_DEF;
928 crop->width = MT9V032_WINDOW_WIDTH_DEF;
929 crop->height = MT9V032_WINDOW_HEIGHT_DEF;
930
931 format = v4l2_subdev_get_try_format(subdev, fh->pad, 0);
932
933 if (mt9v032->model->color)
934 format->code = MEDIA_BUS_FMT_SGRBG10_1X10;
935 else
936 format->code = MEDIA_BUS_FMT_Y10_1X10;
937
938 format->width = MT9V032_WINDOW_WIDTH_DEF;
939 format->height = MT9V032_WINDOW_HEIGHT_DEF;
940 format->field = V4L2_FIELD_NONE;
941 format->colorspace = V4L2_COLORSPACE_SRGB;
942
943 return mt9v032_set_power(subdev, 1);
944 }
945
946 static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
947 {
948 return mt9v032_set_power(subdev, 0);
949 }
950
951 static const struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = {
952 .s_power = mt9v032_set_power,
953 };
954
955 static const struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = {
956 .s_stream = mt9v032_s_stream,
957 };
958
959 static const struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = {
960 .enum_mbus_code = mt9v032_enum_mbus_code,
961 .enum_frame_size = mt9v032_enum_frame_size,
962 .get_fmt = mt9v032_get_format,
963 .set_fmt = mt9v032_set_format,
964 .get_selection = mt9v032_get_selection,
965 .set_selection = mt9v032_set_selection,
966 };
967
968 static const struct v4l2_subdev_ops mt9v032_subdev_ops = {
969 .core = &mt9v032_subdev_core_ops,
970 .video = &mt9v032_subdev_video_ops,
971 .pad = &mt9v032_subdev_pad_ops,
972 };
973
974 static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = {
975 .registered = mt9v032_registered,
976 .open = mt9v032_open,
977 .close = mt9v032_close,
978 };
979
980 static const struct regmap_config mt9v032_regmap_config = {
981 .reg_bits = 8,
982 .val_bits = 16,
983 .max_register = 0xff,
984 .cache_type = REGCACHE_RBTREE,
985 };
986
987 /* -----------------------------------------------------------------------------
988 * Driver initialization and probing
989 */
990
991 static struct mt9v032_platform_data *
992 mt9v032_get_pdata(struct i2c_client *client)
993 {
994 struct mt9v032_platform_data *pdata = NULL;
995 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
996 struct device_node *np;
997 struct property *prop;
998
999 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
1000 return client->dev.platform_data;
1001
1002 np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
1003 if (!np)
1004 return NULL;
1005
1006 if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0)
1007 goto done;
1008
1009 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1010 if (!pdata)
1011 goto done;
1012
1013 prop = of_find_property(np, "link-frequencies", NULL);
1014 if (prop) {
1015 u64 *link_freqs;
1016 size_t size = prop->length / sizeof(*link_freqs);
1017
1018 link_freqs = devm_kcalloc(&client->dev, size,
1019 sizeof(*link_freqs), GFP_KERNEL);
1020 if (!link_freqs)
1021 goto done;
1022
1023 if (of_property_read_u64_array(np, "link-frequencies",
1024 link_freqs, size) < 0)
1025 goto done;
1026
1027 pdata->link_freqs = link_freqs;
1028 pdata->link_def_freq = link_freqs[0];
1029 }
1030
1031 pdata->clk_pol = !!(endpoint.bus.parallel.flags &
1032 V4L2_MBUS_PCLK_SAMPLE_RISING);
1033
1034 done:
1035 of_node_put(np);
1036 return pdata;
1037 }
1038
1039 static int mt9v032_probe(struct i2c_client *client,
1040 const struct i2c_device_id *did)
1041 {
1042 struct mt9v032_platform_data *pdata = mt9v032_get_pdata(client);
1043 struct mt9v032 *mt9v032;
1044 unsigned int i;
1045 int ret;
1046
1047 mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL);
1048 if (!mt9v032)
1049 return -ENOMEM;
1050
1051 mt9v032->regmap = devm_regmap_init_i2c(client, &mt9v032_regmap_config);
1052 if (IS_ERR(mt9v032->regmap))
1053 return PTR_ERR(mt9v032->regmap);
1054
1055 mt9v032->clk = devm_clk_get(&client->dev, NULL);
1056 if (IS_ERR(mt9v032->clk))
1057 return PTR_ERR(mt9v032->clk);
1058
1059 mt9v032->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1060 GPIOD_OUT_HIGH);
1061 if (IS_ERR(mt9v032->reset_gpio))
1062 return PTR_ERR(mt9v032->reset_gpio);
1063
1064 mt9v032->standby_gpio = devm_gpiod_get_optional(&client->dev, "standby",
1065 GPIOD_OUT_LOW);
1066 if (IS_ERR(mt9v032->standby_gpio))
1067 return PTR_ERR(mt9v032->standby_gpio);
1068
1069 mutex_init(&mt9v032->power_lock);
1070 mt9v032->pdata = pdata;
1071 mt9v032->model = (const void *)did->driver_data;
1072
1073 v4l2_ctrl_handler_init(&mt9v032->ctrls, 11 +
1074 ARRAY_SIZE(mt9v032_aegc_controls));
1075
1076 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1077 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1078 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1079 V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN,
1080 MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF);
1081 v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1082 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1083 V4L2_EXPOSURE_AUTO);
1084 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1085 V4L2_CID_EXPOSURE, mt9v032->model->data->min_shutter,
1086 mt9v032->model->data->max_shutter, 1,
1087 MT9V032_TOTAL_SHUTTER_WIDTH_DEF);
1088 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1089 V4L2_CID_HBLANK, mt9v032->model->data->min_hblank,
1090 MT9V032_HORIZONTAL_BLANKING_MAX, 1,
1091 MT9V032_HORIZONTAL_BLANKING_DEF);
1092 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1093 V4L2_CID_VBLANK, mt9v032->model->data->min_vblank,
1094 mt9v032->model->data->max_vblank, 1,
1095 MT9V032_VERTICAL_BLANKING_DEF);
1096 mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls,
1097 &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN,
1098 ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0,
1099 mt9v032_test_pattern_menu);
1100 mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls,
1101 &mt9v032_test_pattern_color, NULL);
1102
1103 v4l2_ctrl_new_custom(&mt9v032->ctrls,
1104 mt9v032->model->data->aec_max_shutter_v4l2_ctrl,
1105 NULL);
1106 for (i = 0; i < ARRAY_SIZE(mt9v032_aegc_controls); ++i)
1107 v4l2_ctrl_new_custom(&mt9v032->ctrls, &mt9v032_aegc_controls[i],
1108 NULL);
1109
1110 v4l2_ctrl_cluster(2, &mt9v032->test_pattern);
1111
1112 mt9v032->pixel_rate =
1113 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1114 V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
1115
1116 if (pdata && pdata->link_freqs) {
1117 unsigned int def = 0;
1118
1119 for (i = 0; pdata->link_freqs[i]; ++i) {
1120 if (pdata->link_freqs[i] == pdata->link_def_freq)
1121 def = i;
1122 }
1123
1124 mt9v032->link_freq =
1125 v4l2_ctrl_new_int_menu(&mt9v032->ctrls,
1126 &mt9v032_ctrl_ops,
1127 V4L2_CID_LINK_FREQ, i - 1, def,
1128 pdata->link_freqs);
1129 v4l2_ctrl_cluster(2, &mt9v032->link_freq);
1130 }
1131
1132
1133 mt9v032->subdev.ctrl_handler = &mt9v032->ctrls;
1134
1135 if (mt9v032->ctrls.error) {
1136 dev_err(&client->dev, "control initialization error %d\n",
1137 mt9v032->ctrls.error);
1138 ret = mt9v032->ctrls.error;
1139 goto err;
1140 }
1141
1142 mt9v032->crop.left = MT9V032_COLUMN_START_DEF;
1143 mt9v032->crop.top = MT9V032_ROW_START_DEF;
1144 mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF;
1145 mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF;
1146
1147 if (mt9v032->model->color)
1148 mt9v032->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1149 else
1150 mt9v032->format.code = MEDIA_BUS_FMT_Y10_1X10;
1151
1152 mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF;
1153 mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF;
1154 mt9v032->format.field = V4L2_FIELD_NONE;
1155 mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB;
1156
1157 mt9v032->hratio = 1;
1158 mt9v032->vratio = 1;
1159
1160 mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE;
1161 mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF;
1162 mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF;
1163
1164 v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops);
1165 mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops;
1166 mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1167
1168 mt9v032->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1169 mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE;
1170 ret = media_entity_pads_init(&mt9v032->subdev.entity, 1, &mt9v032->pad);
1171 if (ret < 0)
1172 goto err;
1173
1174 mt9v032->subdev.dev = &client->dev;
1175 ret = v4l2_async_register_subdev(&mt9v032->subdev);
1176 if (ret < 0)
1177 goto err;
1178
1179 return 0;
1180
1181 err:
1182 media_entity_cleanup(&mt9v032->subdev.entity);
1183 v4l2_ctrl_handler_free(&mt9v032->ctrls);
1184 return ret;
1185 }
1186
1187 static int mt9v032_remove(struct i2c_client *client)
1188 {
1189 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1190 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
1191
1192 v4l2_async_unregister_subdev(subdev);
1193 v4l2_ctrl_handler_free(&mt9v032->ctrls);
1194 media_entity_cleanup(&subdev->entity);
1195
1196 return 0;
1197 }
1198
1199 static const struct mt9v032_model_data mt9v032_model_data[] = {
1200 {
1201 /* MT9V022, MT9V032 revisions 1/2/3 */
1202 .min_row_time = 660,
1203 .min_hblank = MT9V032_HORIZONTAL_BLANKING_MIN,
1204 .min_vblank = MT9V032_VERTICAL_BLANKING_MIN,
1205 .max_vblank = MT9V032_VERTICAL_BLANKING_MAX,
1206 .min_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MIN,
1207 .max_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MAX,
1208 .pclk_reg = MT9V032_PIXEL_CLOCK,
1209 .aec_max_shutter_reg = MT9V032_AEC_MAX_SHUTTER_WIDTH,
1210 .aec_max_shutter_v4l2_ctrl = &mt9v032_aec_max_shutter_width,
1211 }, {
1212 /* MT9V024, MT9V034 */
1213 .min_row_time = 690,
1214 .min_hblank = MT9V034_HORIZONTAL_BLANKING_MIN,
1215 .min_vblank = MT9V034_VERTICAL_BLANKING_MIN,
1216 .max_vblank = MT9V034_VERTICAL_BLANKING_MAX,
1217 .min_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MIN,
1218 .max_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MAX,
1219 .pclk_reg = MT9V034_PIXEL_CLOCK,
1220 .aec_max_shutter_reg = MT9V034_AEC_MAX_SHUTTER_WIDTH,
1221 .aec_max_shutter_v4l2_ctrl = &mt9v034_aec_max_shutter_width,
1222 },
1223 };
1224
1225 static const struct mt9v032_model_info mt9v032_models[] = {
1226 [MT9V032_MODEL_V022_COLOR] = {
1227 .data = &mt9v032_model_data[0],
1228 .color = true,
1229 },
1230 [MT9V032_MODEL_V022_MONO] = {
1231 .data = &mt9v032_model_data[0],
1232 .color = false,
1233 },
1234 [MT9V032_MODEL_V024_COLOR] = {
1235 .data = &mt9v032_model_data[1],
1236 .color = true,
1237 },
1238 [MT9V032_MODEL_V024_MONO] = {
1239 .data = &mt9v032_model_data[1],
1240 .color = false,
1241 },
1242 [MT9V032_MODEL_V032_COLOR] = {
1243 .data = &mt9v032_model_data[0],
1244 .color = true,
1245 },
1246 [MT9V032_MODEL_V032_MONO] = {
1247 .data = &mt9v032_model_data[0],
1248 .color = false,
1249 },
1250 [MT9V032_MODEL_V034_COLOR] = {
1251 .data = &mt9v032_model_data[1],
1252 .color = true,
1253 },
1254 [MT9V032_MODEL_V034_MONO] = {
1255 .data = &mt9v032_model_data[1],
1256 .color = false,
1257 },
1258 };
1259
1260 static const struct i2c_device_id mt9v032_id[] = {
1261 { "mt9v022", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_COLOR] },
1262 { "mt9v022m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_MONO] },
1263 { "mt9v024", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_COLOR] },
1264 { "mt9v024m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_MONO] },
1265 { "mt9v032", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_COLOR] },
1266 { "mt9v032m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_MONO] },
1267 { "mt9v034", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_COLOR] },
1268 { "mt9v034m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_MONO] },
1269 { }
1270 };
1271 MODULE_DEVICE_TABLE(i2c, mt9v032_id);
1272
1273 #if IS_ENABLED(CONFIG_OF)
1274 static const struct of_device_id mt9v032_of_match[] = {
1275 { .compatible = "aptina,mt9v022" },
1276 { .compatible = "aptina,mt9v022m" },
1277 { .compatible = "aptina,mt9v024" },
1278 { .compatible = "aptina,mt9v024m" },
1279 { .compatible = "aptina,mt9v032" },
1280 { .compatible = "aptina,mt9v032m" },
1281 { .compatible = "aptina,mt9v034" },
1282 { .compatible = "aptina,mt9v034m" },
1283 { /* Sentinel */ }
1284 };
1285 MODULE_DEVICE_TABLE(of, mt9v032_of_match);
1286 #endif
1287
1288 static struct i2c_driver mt9v032_driver = {
1289 .driver = {
1290 .name = "mt9v032",
1291 .of_match_table = of_match_ptr(mt9v032_of_match),
1292 },
1293 .probe = mt9v032_probe,
1294 .remove = mt9v032_remove,
1295 .id_table = mt9v032_id,
1296 };
1297
1298 module_i2c_driver(mt9v032_driver);
1299
1300 MODULE_DESCRIPTION("Aptina MT9V032 Camera driver");
1301 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1302 MODULE_LICENSE("GPL");
Linux with added FPC-III support