| blob | ef3cc9965e55a872ddb0d4dc224b4b7e082765b6 |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
3 * Digitizer with Horizontal PLL registers
4 *
5 * Copyright (C) 2009 Texas Instruments Inc
6 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
7 *
8 * This code is partially based upon the TVP5150 driver
9 * written by Mauro Carvalho Chehab <mchehab@kernel.org>,
10 * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
11 * and the TVP7002 driver in the TI LSP 2.10.00.14
12 */
14 /* Naming conventions
15 * ------------------
16 *
17 * FDBK: Feedback
18 * DIV: Divider
19 * CTL: Control
20 * SEL: Select
21 * IN: Input
22 * OUT: Output
23 * R: Red
24 * G: Green
25 * B: Blue
26 * OFF: Offset
27 * THRS: Threshold
28 * DGTL: Digital
29 * LVL: Level
30 * PWR: Power
31 * MVIS: Macrovision
32 * W: Width
33 * H: Height
34 * ALGN: Alignment
35 * CLK: Clocks
36 * TOL: Tolerance
37 * BWTH: Bandwidth
38 * COEF: Coefficient
39 * STAT: Status
40 * AUTO: Automatic
41 * FLD: Field
42 * L: Line
43 */
45 #define TVP7002_CHIP_REV 0x00
46 #define TVP7002_HPLL_FDBK_DIV_MSBS 0x01
47 #define TVP7002_HPLL_FDBK_DIV_LSBS 0x02
48 #define TVP7002_HPLL_CRTL 0x03
49 #define TVP7002_HPLL_PHASE_SEL 0x04
50 #define TVP7002_CLAMP_START 0x05
51 #define TVP7002_CLAMP_W 0x06
52 #define TVP7002_HSYNC_OUT_W 0x07
53 #define TVP7002_B_FINE_GAIN 0x08
54 #define TVP7002_G_FINE_GAIN 0x09
55 #define TVP7002_R_FINE_GAIN 0x0a
56 #define TVP7002_B_FINE_OFF_MSBS 0x0b
57 #define TVP7002_G_FINE_OFF_MSBS 0x0c
58 #define TVP7002_R_FINE_OFF_MSBS 0x0d
59 #define TVP7002_SYNC_CTL_1 0x0e
60 #define TVP7002_HPLL_AND_CLAMP_CTL 0x0f
61 #define TVP7002_SYNC_ON_G_THRS 0x10
62 #define TVP7002_SYNC_SEPARATOR_THRS 0x11
63 #define TVP7002_HPLL_PRE_COAST 0x12
64 #define TVP7002_HPLL_POST_COAST 0x13
65 #define TVP7002_SYNC_DETECT_STAT 0x14
66 #define TVP7002_OUT_FORMATTER 0x15
67 #define TVP7002_MISC_CTL_1 0x16
68 #define TVP7002_MISC_CTL_2 0x17
69 #define TVP7002_MISC_CTL_3 0x18
70 #define TVP7002_IN_MUX_SEL_1 0x19
71 #define TVP7002_IN_MUX_SEL_2 0x1a
72 #define TVP7002_B_AND_G_COARSE_GAIN 0x1b
73 #define TVP7002_R_COARSE_GAIN 0x1c
74 #define TVP7002_FINE_OFF_LSBS 0x1d
75 #define TVP7002_B_COARSE_OFF 0x1e
76 #define TVP7002_G_COARSE_OFF 0x1f
77 #define TVP7002_R_COARSE_OFF 0x20
78 #define TVP7002_HSOUT_OUT_START 0x21
79 #define TVP7002_MISC_CTL_4 0x22
80 #define TVP7002_B_DGTL_ALC_OUT_LSBS 0x23
81 #define TVP7002_G_DGTL_ALC_OUT_LSBS 0x24
82 #define TVP7002_R_DGTL_ALC_OUT_LSBS 0x25
83 #define TVP7002_AUTO_LVL_CTL_ENABLE 0x26
84 #define TVP7002_DGTL_ALC_OUT_MSBS 0x27
85 #define TVP7002_AUTO_LVL_CTL_FILTER 0x28
86 /* Reserved 0x29*/
87 #define TVP7002_FINE_CLAMP_CTL 0x2a
88 #define TVP7002_PWR_CTL 0x2b
89 #define TVP7002_ADC_SETUP 0x2c
90 #define TVP7002_COARSE_CLAMP_CTL 0x2d
91 #define TVP7002_SOG_CLAMP 0x2e
92 #define TVP7002_RGB_COARSE_CLAMP_CTL 0x2f
93 #define TVP7002_SOG_COARSE_CLAMP_CTL 0x30
94 #define TVP7002_ALC_PLACEMENT 0x31
95 /* Reserved 0x32 */
96 /* Reserved 0x33 */
97 #define TVP7002_MVIS_STRIPPER_W 0x34
98 #define TVP7002_VSYNC_ALGN 0x35
99 #define TVP7002_SYNC_BYPASS 0x36
100 #define TVP7002_L_FRAME_STAT_LSBS 0x37
101 #define TVP7002_L_FRAME_STAT_MSBS 0x38
102 #define TVP7002_CLK_L_STAT_LSBS 0x39
103 #define TVP7002_CLK_L_STAT_MSBS 0x3a
104 #define TVP7002_HSYNC_W 0x3b
105 #define TVP7002_VSYNC_W 0x3c
106 #define TVP7002_L_LENGTH_TOL 0x3d
107 /* Reserved 0x3e */
108 #define TVP7002_VIDEO_BWTH_CTL 0x3f
109 #define TVP7002_AVID_START_PIXEL_LSBS 0x40
110 #define TVP7002_AVID_START_PIXEL_MSBS 0x41
111 #define TVP7002_AVID_STOP_PIXEL_LSBS 0x42
112 #define TVP7002_AVID_STOP_PIXEL_MSBS 0x43
113 #define TVP7002_VBLK_F_0_START_L_OFF 0x44
114 #define TVP7002_VBLK_F_1_START_L_OFF 0x45
115 #define TVP7002_VBLK_F_0_DURATION 0x46
116 #define TVP7002_VBLK_F_1_DURATION 0x47
117 #define TVP7002_FBIT_F_0_START_L_OFF 0x48
118 #define TVP7002_FBIT_F_1_START_L_OFF 0x49
119 #define TVP7002_YUV_Y_G_COEF_LSBS 0x4a
120 #define TVP7002_YUV_Y_G_COEF_MSBS 0x4b
121 #define TVP7002_YUV_Y_B_COEF_LSBS 0x4c
122 #define TVP7002_YUV_Y_B_COEF_MSBS 0x4d
123 #define TVP7002_YUV_Y_R_COEF_LSBS 0x4e
124 #define TVP7002_YUV_Y_R_COEF_MSBS 0x4f
125 #define TVP7002_YUV_U_G_COEF_LSBS 0x50
126 #define TVP7002_YUV_U_G_COEF_MSBS 0x51
127 #define TVP7002_YUV_U_B_COEF_LSBS 0x52
128 #define TVP7002_YUV_U_B_COEF_MSBS 0x53
129 #define TVP7002_YUV_U_R_COEF_LSBS 0x54
130 #define TVP7002_YUV_U_R_COEF_MSBS 0x55
131 #define TVP7002_YUV_V_G_COEF_LSBS 0x56
132 #define TVP7002_YUV_V_G_COEF_MSBS 0x57
133 #define TVP7002_YUV_V_B_COEF_LSBS 0x58
134 #define TVP7002_YUV_V_B_COEF_MSBS 0x59
135 #define TVP7002_YUV_V_R_COEF_LSBS 0x5a
136 #define TVP7002_YUV_V_R_COEF_MSBS 0x5b