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Merge branch 'work.regset' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[linux/fpc-iii.git] / drivers / spi / spi-rspi.c
blobcbc2387d450cd4c2161599599e98335510568db6
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SH RSPI driver
4 *
5 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
6 * Copyright (C) 2014 Glider bvba
7 *
8 * Based on spi-sh.c:
9 * Copyright (C) 2011 Renesas Solutions Corp.
10 */
11
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/sched.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/dmaengine.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/of_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/sh_dma.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/rspi.h>
27 #include <linux/spinlock.h>
28
29 #define RSPI_SPCR 0x00 /* Control Register */
30 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
31 #define RSPI_SPPCR 0x02 /* Pin Control Register */
32 #define RSPI_SPSR 0x03 /* Status Register */
33 #define RSPI_SPDR 0x04 /* Data Register */
34 #define RSPI_SPSCR 0x08 /* Sequence Control Register */
35 #define RSPI_SPSSR 0x09 /* Sequence Status Register */
36 #define RSPI_SPBR 0x0a /* Bit Rate Register */
37 #define RSPI_SPDCR 0x0b /* Data Control Register */
38 #define RSPI_SPCKD 0x0c /* Clock Delay Register */
39 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
40 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
41 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
42 #define RSPI_SPCMD0 0x10 /* Command Register 0 */
43 #define RSPI_SPCMD1 0x12 /* Command Register 1 */
44 #define RSPI_SPCMD2 0x14 /* Command Register 2 */
45 #define RSPI_SPCMD3 0x16 /* Command Register 3 */
46 #define RSPI_SPCMD4 0x18 /* Command Register 4 */
47 #define RSPI_SPCMD5 0x1a /* Command Register 5 */
48 #define RSPI_SPCMD6 0x1c /* Command Register 6 */
49 #define RSPI_SPCMD7 0x1e /* Command Register 7 */
50 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
51 #define RSPI_NUM_SPCMD 8
52 #define RSPI_RZ_NUM_SPCMD 4
53 #define QSPI_NUM_SPCMD 4
54
55 /* RSPI on RZ only */
56 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */
57 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
58
59 /* QSPI only */
60 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */
61 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
62 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
63 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
64 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
65 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
66 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
67
68 /* SPCR - Control Register */
69 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
70 #define SPCR_SPE 0x40 /* Function Enable */
71 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
72 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
73 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
74 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
75 /* RSPI on SH only */
76 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
77 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
78 /* QSPI on R-Car Gen2 only */
79 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
80 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
81
82 /* SSLP - Slave Select Polarity Register */
83 #define SSLP_SSLP(i) BIT(i) /* SSLi Signal Polarity Setting */
84
85 /* SPPCR - Pin Control Register */
86 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
87 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
88 #define SPPCR_SPOM 0x04
89 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
90 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
91
92 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
93 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
94
95 /* SPSR - Status Register */
96 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
97 #define SPSR_TEND 0x40 /* Transmit End */
98 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
99 #define SPSR_PERF 0x08 /* Parity Error Flag */
100 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */
101 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
102 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
103
104 /* SPSCR - Sequence Control Register */
105 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
106
107 /* SPSSR - Sequence Status Register */
108 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
109 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
110
111 /* SPDCR - Data Control Register */
112 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
113 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
114 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
115 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
116 #define SPDCR_SPLWORD SPDCR_SPLW1
117 #define SPDCR_SPLBYTE SPDCR_SPLW0
118 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
119 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
120 #define SPDCR_SLSEL1 0x08
121 #define SPDCR_SLSEL0 0x04
122 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
123 #define SPDCR_SPFC1 0x02
124 #define SPDCR_SPFC0 0x01
125 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
126
127 /* SPCKD - Clock Delay Register */
128 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
129
130 /* SSLND - Slave Select Negation Delay Register */
131 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
132
133 /* SPND - Next-Access Delay Register */
134 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
135
136 /* SPCR2 - Control Register 2 */
137 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
138 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
139 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
140 #define SPCR2_SPPE 0x01 /* Parity Enable */
141
142 /* SPCMDn - Command Registers */
143 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
144 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
145 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
146 #define SPCMD_LSBF 0x1000 /* LSB First */
147 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
148 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
149 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
150 #define SPCMD_SPB_16BIT 0x0100
151 #define SPCMD_SPB_20BIT 0x0000
152 #define SPCMD_SPB_24BIT 0x0100
153 #define SPCMD_SPB_32BIT 0x0200
154 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
155 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
156 #define SPCMD_SPIMOD1 0x0040
157 #define SPCMD_SPIMOD0 0x0020
158 #define SPCMD_SPIMOD_SINGLE 0
159 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
160 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
161 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
162 #define SPCMD_SSLA(i) ((i) << 4) /* SSL Assert Signal Setting */
163 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
164 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
165 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
166
167 /* SPBFCR - Buffer Control Register */
168 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
169 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
170 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
171 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
172 /* QSPI on R-Car Gen2 */
173 #define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */
174 #define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */
175 #define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */
176 #define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */
177
178 #define QSPI_BUFFER_SIZE 32u
179
180 struct rspi_data {
181 void __iomem *addr;
182 u32 speed_hz;
183 struct spi_controller *ctlr;
184 struct platform_device *pdev;
185 wait_queue_head_t wait;
186 spinlock_t lock; /* Protects RMW-access to RSPI_SSLP */
187 struct clk *clk;
188 u16 spcmd;
189 u8 spsr;
190 u8 sppcr;
191 int rx_irq, tx_irq;
192 const struct spi_ops *ops;
193
194 unsigned dma_callbacked:1;
195 unsigned byte_access:1;
196 };
197
198 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
199 {
200 iowrite8(data, rspi->addr + offset);
201 }
202
203 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
204 {
205 iowrite16(data, rspi->addr + offset);
206 }
207
208 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
209 {
210 iowrite32(data, rspi->addr + offset);
211 }
212
213 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
214 {
215 return ioread8(rspi->addr + offset);
216 }
217
218 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
219 {
220 return ioread16(rspi->addr + offset);
221 }
222
223 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
224 {
225 if (rspi->byte_access)
226 rspi_write8(rspi, data, RSPI_SPDR);
227 else /* 16 bit */
228 rspi_write16(rspi, data, RSPI_SPDR);
229 }
230
231 static u16 rspi_read_data(const struct rspi_data *rspi)
232 {
233 if (rspi->byte_access)
234 return rspi_read8(rspi, RSPI_SPDR);
235 else /* 16 bit */
236 return rspi_read16(rspi, RSPI_SPDR);
237 }
238
239 /* optional functions */
240 struct spi_ops {
241 int (*set_config_register)(struct rspi_data *rspi, int access_size);
242 int (*transfer_one)(struct spi_controller *ctlr,
243 struct spi_device *spi, struct spi_transfer *xfer);
244 u16 extra_mode_bits;
245 u16 flags;
246 u16 fifo_size;
247 u8 num_hw_ss;
248 };
249
250 /*
251 * functions for RSPI on legacy SH
252 */
253 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
254 {
255 int spbr;
256
257 /* Sets output mode, MOSI signal, and (optionally) loopback */
258 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
259
260 /* Sets transfer bit rate */
261 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->speed_hz) - 1;
262 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
263
264 /* Disable dummy transmission, set 16-bit word access, 1 frame */
265 rspi_write8(rspi, 0, RSPI_SPDCR);
266 rspi->byte_access = 0;
267
268 /* Sets RSPCK, SSL, next-access delay value */
269 rspi_write8(rspi, 0x00, RSPI_SPCKD);
270 rspi_write8(rspi, 0x00, RSPI_SSLND);
271 rspi_write8(rspi, 0x00, RSPI_SPND);
272
273 /* Sets parity, interrupt mask */
274 rspi_write8(rspi, 0x00, RSPI_SPCR2);
275
276 /* Resets sequencer */
277 rspi_write8(rspi, 0, RSPI_SPSCR);
278 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
279 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
280
281 /* Sets RSPI mode */
282 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
283
284 return 0;
285 }
286
287 /*
288 * functions for RSPI on RZ
289 */
290 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
291 {
292 int spbr;
293 int div = 0;
294 unsigned long clksrc;
295
296 /* Sets output mode, MOSI signal, and (optionally) loopback */
297 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
298
299 clksrc = clk_get_rate(rspi->clk);
300 while (div < 3) {
301 if (rspi->speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */
302 break;
303 div++;
304 clksrc /= 2;
305 }
306
307 /* Sets transfer bit rate */
308 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
309 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
310 rspi->spcmd |= div << 2;
311
312 /* Disable dummy transmission, set byte access */
313 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
314 rspi->byte_access = 1;
315
316 /* Sets RSPCK, SSL, next-access delay value */
317 rspi_write8(rspi, 0x00, RSPI_SPCKD);
318 rspi_write8(rspi, 0x00, RSPI_SSLND);
319 rspi_write8(rspi, 0x00, RSPI_SPND);
320
321 /* Resets sequencer */
322 rspi_write8(rspi, 0, RSPI_SPSCR);
323 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
324 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
325
326 /* Sets RSPI mode */
327 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
328
329 return 0;
330 }
331
332 /*
333 * functions for QSPI
334 */
335 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
336 {
337 int spbr;
338
339 /* Sets output mode, MOSI signal, and (optionally) loopback */
340 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
341
342 /* Sets transfer bit rate */
343 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->speed_hz);
344 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
345
346 /* Disable dummy transmission, set byte access */
347 rspi_write8(rspi, 0, RSPI_SPDCR);
348 rspi->byte_access = 1;
349
350 /* Sets RSPCK, SSL, next-access delay value */
351 rspi_write8(rspi, 0x00, RSPI_SPCKD);
352 rspi_write8(rspi, 0x00, RSPI_SSLND);
353 rspi_write8(rspi, 0x00, RSPI_SPND);
354
355 /* Data Length Setting */
356 if (access_size == 8)
357 rspi->spcmd |= SPCMD_SPB_8BIT;
358 else if (access_size == 16)
359 rspi->spcmd |= SPCMD_SPB_16BIT;
360 else
361 rspi->spcmd |= SPCMD_SPB_32BIT;
362
363 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
364
365 /* Resets transfer data length */
366 rspi_write32(rspi, 0, QSPI_SPBMUL0);
367
368 /* Resets transmit and receive buffer */
369 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
370 /* Sets buffer to allow normal operation */
371 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
372
373 /* Resets sequencer */
374 rspi_write8(rspi, 0, RSPI_SPSCR);
375 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
376
377 /* Sets RSPI mode */
378 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
379
380 return 0;
381 }
382
383 static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
384 {
385 u8 data;
386
387 data = rspi_read8(rspi, reg);
388 data &= ~mask;
389 data |= (val & mask);
390 rspi_write8(rspi, data, reg);
391 }
392
393 static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
394 unsigned int len)
395 {
396 unsigned int n;
397
398 n = min(len, QSPI_BUFFER_SIZE);
399
400 if (len >= QSPI_BUFFER_SIZE) {
401 /* sets triggering number to 32 bytes */
402 qspi_update(rspi, SPBFCR_TXTRG_MASK,
403 SPBFCR_TXTRG_32B, QSPI_SPBFCR);
404 } else {
405 /* sets triggering number to 1 byte */
406 qspi_update(rspi, SPBFCR_TXTRG_MASK,
407 SPBFCR_TXTRG_1B, QSPI_SPBFCR);
408 }
409
410 return n;
411 }
412
413 static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
414 {
415 unsigned int n;
416
417 n = min(len, QSPI_BUFFER_SIZE);
418
419 if (len >= QSPI_BUFFER_SIZE) {
420 /* sets triggering number to 32 bytes */
421 qspi_update(rspi, SPBFCR_RXTRG_MASK,
422 SPBFCR_RXTRG_32B, QSPI_SPBFCR);
423 } else {
424 /* sets triggering number to 1 byte */
425 qspi_update(rspi, SPBFCR_RXTRG_MASK,
426 SPBFCR_RXTRG_1B, QSPI_SPBFCR);
427 }
428 return n;
429 }
430
431 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
432 {
433 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
434 }
435
436 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
437 {
438 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
439 }
440
441 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
442 u8 enable_bit)
443 {
444 int ret;
445
446 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
447 if (rspi->spsr & wait_mask)
448 return 0;
449
450 rspi_enable_irq(rspi, enable_bit);
451 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
452 if (ret == 0 && !(rspi->spsr & wait_mask))
453 return -ETIMEDOUT;
454
455 return 0;
456 }
457
458 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
459 {
460 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
461 }
462
463 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
464 {
465 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
466 }
467
468 static int rspi_data_out(struct rspi_data *rspi, u8 data)
469 {
470 int error = rspi_wait_for_tx_empty(rspi);
471 if (error < 0) {
472 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
473 return error;
474 }
475 rspi_write_data(rspi, data);
476 return 0;
477 }
478
479 static int rspi_data_in(struct rspi_data *rspi)
480 {
481 int error;
482 u8 data;
483
484 error = rspi_wait_for_rx_full(rspi);
485 if (error < 0) {
486 dev_err(&rspi->ctlr->dev, "receive timeout\n");
487 return error;
488 }
489 data = rspi_read_data(rspi);
490 return data;
491 }
492
493 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
494 unsigned int n)
495 {
496 while (n-- > 0) {
497 if (tx) {
498 int ret = rspi_data_out(rspi, *tx++);
499 if (ret < 0)
500 return ret;
501 }
502 if (rx) {
503 int ret = rspi_data_in(rspi);
504 if (ret < 0)
505 return ret;
506 *rx++ = ret;
507 }
508 }
509
510 return 0;
511 }
512
513 static void rspi_dma_complete(void *arg)
514 {
515 struct rspi_data *rspi = arg;
516
517 rspi->dma_callbacked = 1;
518 wake_up_interruptible(&rspi->wait);
519 }
520
521 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
522 struct sg_table *rx)
523 {
524 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
525 u8 irq_mask = 0;
526 unsigned int other_irq = 0;
527 dma_cookie_t cookie;
528 int ret;
529
530 /* First prepare and submit the DMA request(s), as this may fail */
531 if (rx) {
532 desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl,
533 rx->nents, DMA_DEV_TO_MEM,
534 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
535 if (!desc_rx) {
536 ret = -EAGAIN;
537 goto no_dma_rx;
538 }
539
540 desc_rx->callback = rspi_dma_complete;
541 desc_rx->callback_param = rspi;
542 cookie = dmaengine_submit(desc_rx);
543 if (dma_submit_error(cookie)) {
544 ret = cookie;
545 goto no_dma_rx;
546 }
547
548 irq_mask |= SPCR_SPRIE;
549 }
550
551 if (tx) {
552 desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl,
553 tx->nents, DMA_MEM_TO_DEV,
554 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
555 if (!desc_tx) {
556 ret = -EAGAIN;
557 goto no_dma_tx;
558 }
559
560 if (rx) {
561 /* No callback */
562 desc_tx->callback = NULL;
563 } else {
564 desc_tx->callback = rspi_dma_complete;
565 desc_tx->callback_param = rspi;
566 }
567 cookie = dmaengine_submit(desc_tx);
568 if (dma_submit_error(cookie)) {
569 ret = cookie;
570 goto no_dma_tx;
571 }
572
573 irq_mask |= SPCR_SPTIE;
574 }
575
576 /*
577 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
578 * called. So, this driver disables the IRQ while DMA transfer.
579 */
580 if (tx)
581 disable_irq(other_irq = rspi->tx_irq);
582 if (rx && rspi->rx_irq != other_irq)
583 disable_irq(rspi->rx_irq);
584
585 rspi_enable_irq(rspi, irq_mask);
586 rspi->dma_callbacked = 0;
587
588 /* Now start DMA */
589 if (rx)
590 dma_async_issue_pending(rspi->ctlr->dma_rx);
591 if (tx)
592 dma_async_issue_pending(rspi->ctlr->dma_tx);
593
594 ret = wait_event_interruptible_timeout(rspi->wait,
595 rspi->dma_callbacked, HZ);
596 if (ret > 0 && rspi->dma_callbacked) {
597 ret = 0;
598 } else {
599 if (!ret) {
600 dev_err(&rspi->ctlr->dev, "DMA timeout\n");
601 ret = -ETIMEDOUT;
602 }
603 if (tx)
604 dmaengine_terminate_all(rspi->ctlr->dma_tx);
605 if (rx)
606 dmaengine_terminate_all(rspi->ctlr->dma_rx);
607 }
608
609 rspi_disable_irq(rspi, irq_mask);
610
611 if (tx)
612 enable_irq(rspi->tx_irq);
613 if (rx && rspi->rx_irq != other_irq)
614 enable_irq(rspi->rx_irq);
615
616 return ret;
617
618 no_dma_tx:
619 if (rx)
620 dmaengine_terminate_all(rspi->ctlr->dma_rx);
621 no_dma_rx:
622 if (ret == -EAGAIN) {
623 dev_warn_once(&rspi->ctlr->dev,
624 "DMA not available, falling back to PIO\n");
625 }
626 return ret;
627 }
628
629 static void rspi_receive_init(const struct rspi_data *rspi)
630 {
631 u8 spsr;
632
633 spsr = rspi_read8(rspi, RSPI_SPSR);
634 if (spsr & SPSR_SPRF)
635 rspi_read_data(rspi); /* dummy read */
636 if (spsr & SPSR_OVRF)
637 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
638 RSPI_SPSR);
639 }
640
641 static void rspi_rz_receive_init(const struct rspi_data *rspi)
642 {
643 rspi_receive_init(rspi);
644 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
645 rspi_write8(rspi, 0, RSPI_SPBFCR);
646 }
647
648 static void qspi_receive_init(const struct rspi_data *rspi)
649 {
650 u8 spsr;
651
652 spsr = rspi_read8(rspi, RSPI_SPSR);
653 if (spsr & SPSR_SPRF)
654 rspi_read_data(rspi); /* dummy read */
655 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
656 rspi_write8(rspi, 0, QSPI_SPBFCR);
657 }
658
659 static bool __rspi_can_dma(const struct rspi_data *rspi,
660 const struct spi_transfer *xfer)
661 {
662 return xfer->len > rspi->ops->fifo_size;
663 }
664
665 static bool rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi,
666 struct spi_transfer *xfer)
667 {
668 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
669
670 return __rspi_can_dma(rspi, xfer);
671 }
672
673 static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
674 struct spi_transfer *xfer)
675 {
676 if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer))
677 return -EAGAIN;
678
679 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
680 return rspi_dma_transfer(rspi, &xfer->tx_sg,
681 xfer->rx_buf ? &xfer->rx_sg : NULL);
682 }
683
684 static int rspi_common_transfer(struct rspi_data *rspi,
685 struct spi_transfer *xfer)
686 {
687 int ret;
688
689 ret = rspi_dma_check_then_transfer(rspi, xfer);
690 if (ret != -EAGAIN)
691 return ret;
692
693 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
694 if (ret < 0)
695 return ret;
696
697 /* Wait for the last transmission */
698 rspi_wait_for_tx_empty(rspi);
699
700 return 0;
701 }
702
703 static int rspi_transfer_one(struct spi_controller *ctlr,
704 struct spi_device *spi, struct spi_transfer *xfer)
705 {
706 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
707 u8 spcr;
708
709 spcr = rspi_read8(rspi, RSPI_SPCR);
710 if (xfer->rx_buf) {
711 rspi_receive_init(rspi);
712 spcr &= ~SPCR_TXMD;
713 } else {
714 spcr |= SPCR_TXMD;
715 }
716 rspi_write8(rspi, spcr, RSPI_SPCR);
717
718 return rspi_common_transfer(rspi, xfer);
719 }
720
721 static int rspi_rz_transfer_one(struct spi_controller *ctlr,
722 struct spi_device *spi,
723 struct spi_transfer *xfer)
724 {
725 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
726
727 rspi_rz_receive_init(rspi);
728
729 return rspi_common_transfer(rspi, xfer);
730 }
731
732 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
733 u8 *rx, unsigned int len)
734 {
735 unsigned int i, n;
736 int ret;
737
738 while (len > 0) {
739 n = qspi_set_send_trigger(rspi, len);
740 qspi_set_receive_trigger(rspi, len);
741 ret = rspi_wait_for_tx_empty(rspi);
742 if (ret < 0) {
743 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
744 return ret;
745 }
746 for (i = 0; i < n; i++)
747 rspi_write_data(rspi, *tx++);
748
749 ret = rspi_wait_for_rx_full(rspi);
750 if (ret < 0) {
751 dev_err(&rspi->ctlr->dev, "receive timeout\n");
752 return ret;
753 }
754 for (i = 0; i < n; i++)
755 *rx++ = rspi_read_data(rspi);
756
757 len -= n;
758 }
759
760 return 0;
761 }
762
763 static int qspi_transfer_out_in(struct rspi_data *rspi,
764 struct spi_transfer *xfer)
765 {
766 int ret;
767
768 qspi_receive_init(rspi);
769
770 ret = rspi_dma_check_then_transfer(rspi, xfer);
771 if (ret != -EAGAIN)
772 return ret;
773
774 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf,
775 xfer->rx_buf, xfer->len);
776 }
777
778 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
779 {
780 const u8 *tx = xfer->tx_buf;
781 unsigned int n = xfer->len;
782 unsigned int i, len;
783 int ret;
784
785 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
786 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
787 if (ret != -EAGAIN)
788 return ret;
789 }
790
791 while (n > 0) {
792 len = qspi_set_send_trigger(rspi, n);
793 ret = rspi_wait_for_tx_empty(rspi);
794 if (ret < 0) {
795 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
796 return ret;
797 }
798 for (i = 0; i < len; i++)
799 rspi_write_data(rspi, *tx++);
800
801 n -= len;
802 }
803
804 /* Wait for the last transmission */
805 rspi_wait_for_tx_empty(rspi);
806
807 return 0;
808 }
809
810 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
811 {
812 u8 *rx = xfer->rx_buf;
813 unsigned int n = xfer->len;
814 unsigned int i, len;
815 int ret;
816
817 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
818 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
819 if (ret != -EAGAIN)
820 return ret;
821 }
822
823 while (n > 0) {
824 len = qspi_set_receive_trigger(rspi, n);
825 ret = rspi_wait_for_rx_full(rspi);
826 if (ret < 0) {
827 dev_err(&rspi->ctlr->dev, "receive timeout\n");
828 return ret;
829 }
830 for (i = 0; i < len; i++)
831 *rx++ = rspi_read_data(rspi);
832
833 n -= len;
834 }
835
836 return 0;
837 }
838
839 static int qspi_transfer_one(struct spi_controller *ctlr,
840 struct spi_device *spi, struct spi_transfer *xfer)
841 {
842 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
843
844 if (spi->mode & SPI_LOOP) {
845 return qspi_transfer_out_in(rspi, xfer);
846 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
847 /* Quad or Dual SPI Write */
848 return qspi_transfer_out(rspi, xfer);
849 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
850 /* Quad or Dual SPI Read */
851 return qspi_transfer_in(rspi, xfer);
852 } else {
853 /* Single SPI Transfer */
854 return qspi_transfer_out_in(rspi, xfer);
855 }
856 }
857
858 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
859 {
860 if (xfer->tx_buf)
861 switch (xfer->tx_nbits) {
862 case SPI_NBITS_QUAD:
863 return SPCMD_SPIMOD_QUAD;
864 case SPI_NBITS_DUAL:
865 return SPCMD_SPIMOD_DUAL;
866 default:
867 return 0;
868 }
869 if (xfer->rx_buf)
870 switch (xfer->rx_nbits) {
871 case SPI_NBITS_QUAD:
872 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
873 case SPI_NBITS_DUAL:
874 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
875 default:
876 return 0;
877 }
878
879 return 0;
880 }
881
882 static int qspi_setup_sequencer(struct rspi_data *rspi,
883 const struct spi_message *msg)
884 {
885 const struct spi_transfer *xfer;
886 unsigned int i = 0, len = 0;
887 u16 current_mode = 0xffff, mode;
888
889 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
890 mode = qspi_transfer_mode(xfer);
891 if (mode == current_mode) {
892 len += xfer->len;
893 continue;
894 }
895
896 /* Transfer mode change */
897 if (i) {
898 /* Set transfer data length of previous transfer */
899 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
900 }
901
902 if (i >= QSPI_NUM_SPCMD) {
903 dev_err(&msg->spi->dev,
904 "Too many different transfer modes");
905 return -EINVAL;
906 }
907
908 /* Program transfer mode for this transfer */
909 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
910 current_mode = mode;
911 len = xfer->len;
912 i++;
913 }
914 if (i) {
915 /* Set final transfer data length and sequence length */
916 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
917 rspi_write8(rspi, i - 1, RSPI_SPSCR);
918 }
919
920 return 0;
921 }
922
923 static int rspi_setup(struct spi_device *spi)
924 {
925 struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
926 u8 sslp;
927
928 if (spi->cs_gpiod)
929 return 0;
930
931 pm_runtime_get_sync(&rspi->pdev->dev);
932 spin_lock_irq(&rspi->lock);
933
934 sslp = rspi_read8(rspi, RSPI_SSLP);
935 if (spi->mode & SPI_CS_HIGH)
936 sslp |= SSLP_SSLP(spi->chip_select);
937 else
938 sslp &= ~SSLP_SSLP(spi->chip_select);
939 rspi_write8(rspi, sslp, RSPI_SSLP);
940
941 spin_unlock_irq(&rspi->lock);
942 pm_runtime_put(&rspi->pdev->dev);
943 return 0;
944 }
945
946 static int rspi_prepare_message(struct spi_controller *ctlr,
947 struct spi_message *msg)
948 {
949 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
950 struct spi_device *spi = msg->spi;
951 const struct spi_transfer *xfer;
952 int ret;
953
954 /*
955 * As the Bit Rate Register must not be changed while the device is
956 * active, all transfers in a message must use the same bit rate.
957 * In theory, the sequencer could be enabled, and each Command Register
958 * could divide the base bit rate by a different value.
959 * However, most RSPI variants do not have Transfer Data Length
960 * Multiplier Setting Registers, so each sequence step would be limited
961 * to a single word, making this feature unsuitable for large
962 * transfers, which would gain most from it.
963 */
964 rspi->speed_hz = spi->max_speed_hz;
965 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
966 if (xfer->speed_hz < rspi->speed_hz)
967 rspi->speed_hz = xfer->speed_hz;
968 }
969
970 rspi->spcmd = SPCMD_SSLKP;
971 if (spi->mode & SPI_CPOL)
972 rspi->spcmd |= SPCMD_CPOL;
973 if (spi->mode & SPI_CPHA)
974 rspi->spcmd |= SPCMD_CPHA;
975 if (spi->mode & SPI_LSB_FIRST)
976 rspi->spcmd |= SPCMD_LSBF;
977
978 /* Configure slave signal to assert */
979 rspi->spcmd |= SPCMD_SSLA(spi->cs_gpiod ? rspi->ctlr->unused_native_cs
980 : spi->chip_select);
981
982 /* CMOS output mode and MOSI signal from previous transfer */
983 rspi->sppcr = 0;
984 if (spi->mode & SPI_LOOP)
985 rspi->sppcr |= SPPCR_SPLP;
986
987 rspi->ops->set_config_register(rspi, 8);
988
989 if (msg->spi->mode &
990 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
991 /* Setup sequencer for messages with multiple transfer modes */
992 ret = qspi_setup_sequencer(rspi, msg);
993 if (ret < 0)
994 return ret;
995 }
996
997 /* Enable SPI function in master mode */
998 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
999 return 0;
1000 }
1001
1002 static int rspi_unprepare_message(struct spi_controller *ctlr,
1003 struct spi_message *msg)
1004 {
1005 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
1006
1007 /* Disable SPI function */
1008 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
1009
1010 /* Reset sequencer for Single SPI Transfers */
1011 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
1012 rspi_write8(rspi, 0, RSPI_SPSCR);
1013 return 0;
1014 }
1015
1016 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
1017 {
1018 struct rspi_data *rspi = _sr;
1019 u8 spsr;
1020 irqreturn_t ret = IRQ_NONE;
1021 u8 disable_irq = 0;
1022
1023 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1024 if (spsr & SPSR_SPRF)
1025 disable_irq |= SPCR_SPRIE;
1026 if (spsr & SPSR_SPTEF)
1027 disable_irq |= SPCR_SPTIE;
1028
1029 if (disable_irq) {
1030 ret = IRQ_HANDLED;
1031 rspi_disable_irq(rspi, disable_irq);
1032 wake_up(&rspi->wait);
1033 }
1034
1035 return ret;
1036 }
1037
1038 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
1039 {
1040 struct rspi_data *rspi = _sr;
1041 u8 spsr;
1042
1043 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1044 if (spsr & SPSR_SPRF) {
1045 rspi_disable_irq(rspi, SPCR_SPRIE);
1046 wake_up(&rspi->wait);
1047 return IRQ_HANDLED;
1048 }
1049
1050 return 0;
1051 }
1052
1053 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
1054 {
1055 struct rspi_data *rspi = _sr;
1056 u8 spsr;
1057
1058 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1059 if (spsr & SPSR_SPTEF) {
1060 rspi_disable_irq(rspi, SPCR_SPTIE);
1061 wake_up(&rspi->wait);
1062 return IRQ_HANDLED;
1063 }
1064
1065 return 0;
1066 }
1067
1068 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
1069 enum dma_transfer_direction dir,
1070 unsigned int id,
1071 dma_addr_t port_addr)
1072 {
1073 dma_cap_mask_t mask;
1074 struct dma_chan *chan;
1075 struct dma_slave_config cfg;
1076 int ret;
1077
1078 dma_cap_zero(mask);
1079 dma_cap_set(DMA_SLAVE, mask);
1080
1081 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1082 (void *)(unsigned long)id, dev,
1083 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1084 if (!chan) {
1085 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1086 return NULL;
1087 }
1088
1089 memset(&cfg, 0, sizeof(cfg));
1090 cfg.direction = dir;
1091 if (dir == DMA_MEM_TO_DEV) {
1092 cfg.dst_addr = port_addr;
1093 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1094 } else {
1095 cfg.src_addr = port_addr;
1096 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1097 }
1098
1099 ret = dmaengine_slave_config(chan, &cfg);
1100 if (ret) {
1101 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1102 dma_release_channel(chan);
1103 return NULL;
1104 }
1105
1106 return chan;
1107 }
1108
1109 static int rspi_request_dma(struct device *dev, struct spi_controller *ctlr,
1110 const struct resource *res)
1111 {
1112 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
1113 unsigned int dma_tx_id, dma_rx_id;
1114
1115 if (dev->of_node) {
1116 /* In the OF case we will get the slave IDs from the DT */
1117 dma_tx_id = 0;
1118 dma_rx_id = 0;
1119 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) {
1120 dma_tx_id = rspi_pd->dma_tx_id;
1121 dma_rx_id = rspi_pd->dma_rx_id;
1122 } else {
1123 /* The driver assumes no error. */
1124 return 0;
1125 }
1126
1127 ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
1128 res->start + RSPI_SPDR);
1129 if (!ctlr->dma_tx)
1130 return -ENODEV;
1131
1132 ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
1133 res->start + RSPI_SPDR);
1134 if (!ctlr->dma_rx) {
1135 dma_release_channel(ctlr->dma_tx);
1136 ctlr->dma_tx = NULL;
1137 return -ENODEV;
1138 }
1139
1140 ctlr->can_dma = rspi_can_dma;
1141 dev_info(dev, "DMA available");
1142 return 0;
1143 }
1144
1145 static void rspi_release_dma(struct spi_controller *ctlr)
1146 {
1147 if (ctlr->dma_tx)
1148 dma_release_channel(ctlr->dma_tx);
1149 if (ctlr->dma_rx)
1150 dma_release_channel(ctlr->dma_rx);
1151 }
1152
1153 static int rspi_remove(struct platform_device *pdev)
1154 {
1155 struct rspi_data *rspi = platform_get_drvdata(pdev);
1156
1157 rspi_release_dma(rspi->ctlr);
1158 pm_runtime_disable(&pdev->dev);
1159
1160 return 0;
1161 }
1162
1163 static const struct spi_ops rspi_ops = {
1164 .set_config_register = rspi_set_config_register,
1165 .transfer_one = rspi_transfer_one,
1166 .flags = SPI_CONTROLLER_MUST_TX,
1167 .fifo_size = 8,
1168 .num_hw_ss = 2,
1169 };
1170
1171 static const struct spi_ops rspi_rz_ops = {
1172 .set_config_register = rspi_rz_set_config_register,
1173 .transfer_one = rspi_rz_transfer_one,
1174 .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
1175 .fifo_size = 8, /* 8 for TX, 32 for RX */
1176 .num_hw_ss = 1,
1177 };
1178
1179 static const struct spi_ops qspi_ops = {
1180 .set_config_register = qspi_set_config_register,
1181 .transfer_one = qspi_transfer_one,
1182 .extra_mode_bits = SPI_TX_DUAL | SPI_TX_QUAD |
1183 SPI_RX_DUAL | SPI_RX_QUAD,
1184 .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
1185 .fifo_size = 32,
1186 .num_hw_ss = 1,
1187 };
1188
1189 #ifdef CONFIG_OF
1190 static const struct of_device_id rspi_of_match[] = {
1191 /* RSPI on legacy SH */
1192 { .compatible = "renesas,rspi", .data = &rspi_ops },
1193 /* RSPI on RZ/A1H */
1194 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1195 /* QSPI on R-Car Gen2 */
1196 { .compatible = "renesas,qspi", .data = &qspi_ops },
1197 { /* sentinel */ }
1198 };
1199
1200 MODULE_DEVICE_TABLE(of, rspi_of_match);
1201
1202 static int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
1203 {
1204 u32 num_cs;
1205 int error;
1206
1207 /* Parse DT properties */
1208 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1209 if (error) {
1210 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1211 return error;
1212 }
1213
1214 ctlr->num_chipselect = num_cs;
1215 return 0;
1216 }
1217 #else
1218 #define rspi_of_match NULL
1219 static inline int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
1220 {
1221 return -EINVAL;
1222 }
1223 #endif /* CONFIG_OF */
1224
1225 static int rspi_request_irq(struct device *dev, unsigned int irq,
1226 irq_handler_t handler, const char *suffix,
1227 void *dev_id)
1228 {
1229 const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
1230 dev_name(dev), suffix);
1231 if (!name)
1232 return -ENOMEM;
1233
1234 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1235 }
1236
1237 static int rspi_probe(struct platform_device *pdev)
1238 {
1239 struct resource *res;
1240 struct spi_controller *ctlr;
1241 struct rspi_data *rspi;
1242 int ret;
1243 const struct rspi_plat_data *rspi_pd;
1244 const struct spi_ops *ops;
1245
1246 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1247 if (ctlr == NULL)
1248 return -ENOMEM;
1249
1250 ops = of_device_get_match_data(&pdev->dev);
1251 if (ops) {
1252 ret = rspi_parse_dt(&pdev->dev, ctlr);
1253 if (ret)
1254 goto error1;
1255 } else {
1256 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1257 rspi_pd = dev_get_platdata(&pdev->dev);
1258 if (rspi_pd && rspi_pd->num_chipselect)
1259 ctlr->num_chipselect = rspi_pd->num_chipselect;
1260 else
1261 ctlr->num_chipselect = 2; /* default */
1262 }
1263
1264 /* ops parameter check */
1265 if (!ops->set_config_register) {
1266 dev_err(&pdev->dev, "there is no set_config_register\n");
1267 ret = -ENODEV;
1268 goto error1;
1269 }
1270
1271 rspi = spi_controller_get_devdata(ctlr);
1272 platform_set_drvdata(pdev, rspi);
1273 rspi->ops = ops;
1274 rspi->ctlr = ctlr;
1275
1276 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1277 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1278 if (IS_ERR(rspi->addr)) {
1279 ret = PTR_ERR(rspi->addr);
1280 goto error1;
1281 }
1282
1283 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1284 if (IS_ERR(rspi->clk)) {
1285 dev_err(&pdev->dev, "cannot get clock\n");
1286 ret = PTR_ERR(rspi->clk);
1287 goto error1;
1288 }
1289
1290 rspi->pdev = pdev;
1291 pm_runtime_enable(&pdev->dev);
1292
1293 init_waitqueue_head(&rspi->wait);
1294 spin_lock_init(&rspi->lock);
1295
1296 ctlr->bus_num = pdev->id;
1297 ctlr->setup = rspi_setup;
1298 ctlr->auto_runtime_pm = true;
1299 ctlr->transfer_one = ops->transfer_one;
1300 ctlr->prepare_message = rspi_prepare_message;
1301 ctlr->unprepare_message = rspi_unprepare_message;
1302 ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1303 SPI_LOOP | ops->extra_mode_bits;
1304 ctlr->flags = ops->flags;
1305 ctlr->dev.of_node = pdev->dev.of_node;
1306 ctlr->use_gpio_descriptors = true;
1307 ctlr->max_native_cs = rspi->ops->num_hw_ss;
1308
1309 ret = platform_get_irq_byname_optional(pdev, "rx");
1310 if (ret < 0) {
1311 ret = platform_get_irq_byname_optional(pdev, "mux");
1312 if (ret < 0)
1313 ret = platform_get_irq(pdev, 0);
1314 if (ret >= 0)
1315 rspi->rx_irq = rspi->tx_irq = ret;
1316 } else {
1317 rspi->rx_irq = ret;
1318 ret = platform_get_irq_byname(pdev, "tx");
1319 if (ret >= 0)
1320 rspi->tx_irq = ret;
1321 }
1322
1323 if (rspi->rx_irq == rspi->tx_irq) {
1324 /* Single multiplexed interrupt */
1325 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1326 "mux", rspi);
1327 } else {
1328 /* Multi-interrupt mode, only SPRI and SPTI are used */
1329 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1330 "rx", rspi);
1331 if (!ret)
1332 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1333 rspi_irq_tx, "tx", rspi);
1334 }
1335 if (ret < 0) {
1336 dev_err(&pdev->dev, "request_irq error\n");
1337 goto error2;
1338 }
1339
1340 ret = rspi_request_dma(&pdev->dev, ctlr, res);
1341 if (ret < 0)
1342 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1343
1344 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1345 if (ret < 0) {
1346 dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1347 goto error3;
1348 }
1349
1350 dev_info(&pdev->dev, "probed\n");
1351
1352 return 0;
1353
1354 error3:
1355 rspi_release_dma(ctlr);
1356 error2:
1357 pm_runtime_disable(&pdev->dev);
1358 error1:
1359 spi_controller_put(ctlr);
1360
1361 return ret;
1362 }
1363
1364 static const struct platform_device_id spi_driver_ids[] = {
1365 { "rspi", (kernel_ulong_t)&rspi_ops },
1366 {},
1367 };
1368
1369 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1370
1371 #ifdef CONFIG_PM_SLEEP
1372 static int rspi_suspend(struct device *dev)
1373 {
1374 struct rspi_data *rspi = dev_get_drvdata(dev);
1375
1376 return spi_controller_suspend(rspi->ctlr);
1377 }
1378
1379 static int rspi_resume(struct device *dev)
1380 {
1381 struct rspi_data *rspi = dev_get_drvdata(dev);
1382
1383 return spi_controller_resume(rspi->ctlr);
1384 }
1385
1386 static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume);
1387 #define DEV_PM_OPS &rspi_pm_ops
1388 #else
1389 #define DEV_PM_OPS NULL
1390 #endif /* CONFIG_PM_SLEEP */
1391
1392 static struct platform_driver rspi_driver = {
1393 .probe = rspi_probe,
1394 .remove = rspi_remove,
1395 .id_table = spi_driver_ids,
1396 .driver = {
1397 .name = "renesas_spi",
1398 .pm = DEV_PM_OPS,
1399 .of_match_table = of_match_ptr(rspi_of_match),
1400 },
1401 };
1402 module_platform_driver(rspi_driver);
1403
1404 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1405 MODULE_LICENSE("GPL v2");
1406 MODULE_AUTHOR("Yoshihiro Shimoda");
1407 MODULE_ALIAS("platform:rspi");
Linux with added FPC-III support