drivers/net/ethernet/intel/igb/igb.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28
  29 /* Linux PRO/1000 Ethernet Driver main header file */
  30
  31 #ifndef _IGB_H_
  32 #define _IGB_H_
  33
  34 #include "e1000_mac.h"
  35 #include "e1000_82575.h"
  36
  37 #include <linux/clocksource.h>
  38 #include <linux/timecompare.h>
  39 #include <linux/net_tstamp.h>
  40 #include <linux/bitops.h>
  41 #include <linux/if_vlan.h>
  42
  43 struct igb_adapter;
  44
  45 /* Interrupt defines */
  46 #define IGB_START_ITR                    648 /* ~6000 ints/sec */
  47 #define IGB_4K_ITR                       980
  48 #define IGB_20K_ITR                      196
  49 #define IGB_70K_ITR                       56
  50
  51 /* TX/RX descriptor defines */
  52 #define IGB_DEFAULT_TXD                  256
  53 #define IGB_DEFAULT_TX_WORK              128
  54 #define IGB_MIN_TXD                       80
  55 #define IGB_MAX_TXD                     4096
  56
  57 #define IGB_DEFAULT_RXD                  256
  58 #define IGB_MIN_RXD                       80
  59 #define IGB_MAX_RXD                     4096
  60
  61 #define IGB_DEFAULT_ITR                    3 /* dynamic */
  62 #define IGB_MAX_ITR_USECS              10000
  63 #define IGB_MIN_ITR_USECS                 10
  64 #define NON_Q_VECTORS                      1
  65 #define MAX_Q_VECTORS                      8
  66
  67 /* Transmit and receive queues */
  68 #define IGB_MAX_RX_QUEUES                  (adapter->vfs_allocated_count ? 2 : \
  69                                            (hw->mac.type > e1000_82575 ? 8 : 4))
  70 #define IGB_MAX_TX_QUEUES                  16
  71
  72 #define IGB_MAX_VF_MC_ENTRIES              30
  73 #define IGB_MAX_VF_FUNCTIONS               8
  74 #define IGB_MAX_VFTA_ENTRIES               128
  75 #define IGB_82576_VF_DEV_ID                0x10CA
  76 #define IGB_I350_VF_DEV_ID                 0x1520
  77
  78 struct vf_data_storage {
  79         unsigned char vf_mac_addresses[ETH_ALEN];
  80         u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
  81         u16 num_vf_mc_hashes;
  82         u16 vlans_enabled;
  83         u32 flags;
  84         unsigned long last_nack;
  85         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
  86         u16 pf_qos;
  87         u16 tx_rate;
  88         struct pci_dev *vfdev;
  89 };
  90
  91 #define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
  92 #define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
  93 #define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
  94 #define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */
  95
  96 /* RX descriptor control thresholds.
  97  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
  98  *           descriptors available in its onboard memory.
  99  *           Setting this to 0 disables RX descriptor prefetch.
 100  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 101  *           available in host memory.
 102  *           If PTHRESH is 0, this should also be 0.
 103  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 104  *           descriptors until either it has this many to write back, or the
 105  *           ITR timer expires.
 106  */
 107 #define IGB_RX_PTHRESH                     8
 108 #define IGB_RX_HTHRESH                     8
 109 #define IGB_TX_PTHRESH                     8
 110 #define IGB_TX_HTHRESH                     1
 111 #define IGB_RX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
 112                                              adapter->msix_entries) ? 1 : 4)
 113 #define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
 114                                              adapter->msix_entries) ? 1 : 16)
 115
 116 /* this is the size past which hardware will drop packets when setting LPE=0 */
 117 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
 118
 119 /* Supported Rx Buffer Sizes */
 120 #define IGB_RXBUFFER_512   512
 121 #define IGB_RXBUFFER_16384 16384
 122 #define IGB_RX_HDR_LEN     IGB_RXBUFFER_512
 123
 124 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
 125 #define IGB_TX_QUEUE_WAKE       16
 126 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 127 #define IGB_RX_BUFFER_WRITE     16      /* Must be power of 2 */
 128
 129 #define AUTO_ALL_MODES            0
 130 #define IGB_EEPROM_APME         0x0400
 131
 132 #ifndef IGB_MASTER_SLAVE
 133 /* Switch to override PHY master/slave setting */
 134 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 135 #endif
 136
 137 #define IGB_MNG_VLAN_NONE -1
 138
 139 #define IGB_TX_FLAGS_CSUM               0x00000001
 140 #define IGB_TX_FLAGS_VLAN               0x00000002
 141 #define IGB_TX_FLAGS_TSO                0x00000004
 142 #define IGB_TX_FLAGS_IPV4               0x00000008
 143 #define IGB_TX_FLAGS_TSTAMP             0x00000010
 144 #define IGB_TX_FLAGS_VLAN_MASK          0xffff0000
 145 #define IGB_TX_FLAGS_VLAN_SHIFT 16
 146
 147 /* wrapper around a pointer to a socket buffer,
 148  * so a DMA handle can be stored along with the buffer */
 149 struct igb_tx_buffer {
 150         union e1000_adv_tx_desc *next_to_watch;
 151         unsigned long time_stamp;
 152         struct sk_buff *skb;
 153         unsigned int bytecount;
 154         u16 gso_segs;
 155         __be16 protocol;
 156         dma_addr_t dma;
 157         u32 length;
 158         u32 tx_flags;
 159 };
 160
 161 struct igb_rx_buffer {
 162         struct sk_buff *skb;
 163         dma_addr_t dma;
 164         struct page *page;
 165         dma_addr_t page_dma;
 166         u32 page_offset;
 167 };
 168
 169 struct igb_tx_queue_stats {
 170         u64 packets;
 171         u64 bytes;
 172         u64 restart_queue;
 173         u64 restart_queue2;
 174 };
 175
 176 struct igb_rx_queue_stats {
 177         u64 packets;
 178         u64 bytes;
 179         u64 drops;
 180         u64 csum_err;
 181         u64 alloc_failed;
 182 };
 183
 184 struct igb_ring_container {
 185         struct igb_ring *ring;          /* pointer to linked list of rings */
 186         unsigned int total_bytes;       /* total bytes processed this int */
 187         unsigned int total_packets;     /* total packets processed this int */
 188         u16 work_limit;                 /* total work allowed per interrupt */
 189         u8 count;                       /* total number of rings in vector */
 190         u8 itr;                         /* current ITR setting for ring */
 191 };
 192
 193 struct igb_q_vector {
 194         struct igb_adapter *adapter;    /* backlink */
 195         int cpu;                        /* CPU for DCA */
 196         u32 eims_value;                 /* EIMS mask value */
 197
 198         struct igb_ring_container rx, tx;
 199
 200         struct napi_struct napi;
 201         int numa_node;
 202
 203         u16 itr_val;
 204         u8 set_itr;
 205         void __iomem *itr_register;
 206
 207         char name[IFNAMSIZ + 9];
 208 };
 209
 210 struct igb_ring {
 211         struct igb_q_vector *q_vector;  /* backlink to q_vector */
 212         struct net_device *netdev;      /* back pointer to net_device */
 213         struct device *dev;             /* device pointer for dma mapping */
 214         union {                         /* array of buffer info structs */
 215                 struct igb_tx_buffer *tx_buffer_info;
 216                 struct igb_rx_buffer *rx_buffer_info;
 217         };
 218         void *desc;                     /* descriptor ring memory */
 219         unsigned long flags;            /* ring specific flags */
 220         void __iomem *tail;             /* pointer to ring tail register */
 221
 222         u16 count;                      /* number of desc. in the ring */
 223         u8 queue_index;                 /* logical index of the ring*/
 224         u8 reg_idx;                     /* physical index of the ring */
 225         u32 size;                       /* length of desc. ring in bytes */
 226
 227         /* everything past this point are written often */
 228         u16 next_to_clean ____cacheline_aligned_in_smp;
 229         u16 next_to_use;
 230
 231         union {
 232                 /* TX */
 233                 struct {
 234                         struct igb_tx_queue_stats tx_stats;
 235                         struct u64_stats_sync tx_syncp;
 236                         struct u64_stats_sync tx_syncp2;
 237                 };
 238                 /* RX */
 239                 struct {
 240                         struct igb_rx_queue_stats rx_stats;
 241                         struct u64_stats_sync rx_syncp;
 242                 };
 243         };
 244         /* Items past this point are only used during ring alloc / free */
 245         dma_addr_t dma;                /* phys address of the ring */
 246         int numa_node;                  /* node to alloc ring memory on */
 247 };
 248
 249 enum e1000_ring_flags_t {
 250         IGB_RING_FLAG_RX_SCTP_CSUM,
 251         IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
 252         IGB_RING_FLAG_TX_CTX_IDX,
 253         IGB_RING_FLAG_TX_DETECT_HANG
 254 };
 255
 256 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
 257
 258 #define IGB_RX_DESC(R, i)           \
 259         (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
 260 #define IGB_TX_DESC(R, i)           \
 261         (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
 262 #define IGB_TX_CTXTDESC(R, i)       \
 263         (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
 264
 265 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */
 266 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
 267                                       const u32 stat_err_bits)
 268 {
 269         return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
 270 }
 271
 272 /* igb_desc_unused - calculate if we have unused descriptors */
 273 static inline int igb_desc_unused(struct igb_ring *ring)
 274 {
 275         if (ring->next_to_clean > ring->next_to_use)
 276                 return ring->next_to_clean - ring->next_to_use - 1;
 277
 278         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 279 }
 280
 281 /* board specific private data structure */
 282 struct igb_adapter {
 283         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 284
 285         struct net_device *netdev;
 286
 287         unsigned long state;
 288         unsigned int flags;
 289
 290         unsigned int num_q_vectors;
 291         struct msix_entry *msix_entries;
 292
 293         /* Interrupt Throttle Rate */
 294         u32 rx_itr_setting;
 295         u32 tx_itr_setting;
 296         u16 tx_itr;
 297         u16 rx_itr;
 298
 299         /* TX */
 300         u16 tx_work_limit;
 301         u32 tx_timeout_count;
 302         int num_tx_queues;
 303         struct igb_ring *tx_ring[16];
 304
 305         /* RX */
 306         int num_rx_queues;
 307         struct igb_ring *rx_ring[16];
 308
 309         u32 max_frame_size;
 310         u32 min_frame_size;
 311
 312         struct timer_list watchdog_timer;
 313         struct timer_list phy_info_timer;
 314
 315         u16 mng_vlan_id;
 316         u32 bd_number;
 317         u32 wol;
 318         u32 en_mng_pt;
 319         u16 link_speed;
 320         u16 link_duplex;
 321
 322         struct work_struct reset_task;
 323         struct work_struct watchdog_task;
 324         bool fc_autoneg;
 325         u8  tx_timeout_factor;
 326         struct timer_list blink_timer;
 327         unsigned long led_status;
 328
 329         /* OS defined structs */
 330         struct pci_dev *pdev;
 331         struct cyclecounter cycles;
 332         struct timecounter clock;
 333         struct timecompare compare;
 334         struct hwtstamp_config hwtstamp_config;
 335
 336         spinlock_t stats64_lock;
 337         struct rtnl_link_stats64 stats64;
 338
 339         /* structs defined in e1000_hw.h */
 340         struct e1000_hw hw;
 341         struct e1000_hw_stats stats;
 342         struct e1000_phy_info phy_info;
 343         struct e1000_phy_stats phy_stats;
 344
 345         u32 test_icr;
 346         struct igb_ring test_tx_ring;
 347         struct igb_ring test_rx_ring;
 348
 349         int msg_enable;
 350
 351         struct igb_q_vector *q_vector[MAX_Q_VECTORS];
 352         u32 eims_enable_mask;
 353         u32 eims_other;
 354
 355         /* to not mess up cache alignment, always add to the bottom */
 356         u32 eeprom_wol;
 357
 358         u16 tx_ring_count;
 359         u16 rx_ring_count;
 360         unsigned int vfs_allocated_count;
 361         struct vf_data_storage *vf_data;
 362         int vf_rate_link_speed;
 363         u32 rss_queues;
 364         u32 wvbr;
 365         int node;
 366         u32 *shadow_vfta;
 367 };
 368
 369 #define IGB_FLAG_HAS_MSI           (1 << 0)
 370 #define IGB_FLAG_DCA_ENABLED       (1 << 1)
 371 #define IGB_FLAG_QUAD_PORT_A       (1 << 2)
 372 #define IGB_FLAG_QUEUE_PAIRS       (1 << 3)
 373 #define IGB_FLAG_DMAC              (1 << 4)
 374
 375 /* DMA Coalescing defines */
 376 #define IGB_MIN_TXPBSIZE           20408
 377 #define IGB_TX_BUF_4096            4096
 378 #define IGB_DMCTLX_DCFLUSH_DIS     0x80000000  /* Disable DMA Coal Flush */
 379
 380 #define IGB_82576_TSYNC_SHIFT 19
 381 #define IGB_82580_TSYNC_SHIFT 24
 382 #define IGB_TS_HDR_LEN        16
 383 enum e1000_state_t {
 384         __IGB_TESTING,
 385         __IGB_RESETTING,
 386         __IGB_DOWN
 387 };
 388
 389 enum igb_boards {
 390         board_82575,
 391 };
 392
 393 extern char igb_driver_name[];
 394 extern char igb_driver_version[];
 395
 396 extern int igb_up(struct igb_adapter *);
 397 extern void igb_down(struct igb_adapter *);
 398 extern void igb_reinit_locked(struct igb_adapter *);
 399 extern void igb_reset(struct igb_adapter *);
 400 extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
 401 extern int igb_setup_tx_resources(struct igb_ring *);
 402 extern int igb_setup_rx_resources(struct igb_ring *);
 403 extern void igb_free_tx_resources(struct igb_ring *);
 404 extern void igb_free_rx_resources(struct igb_ring *);
 405 extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
 406 extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
 407 extern void igb_setup_tctl(struct igb_adapter *);
 408 extern void igb_setup_rctl(struct igb_adapter *);
 409 extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
 410 extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
 411                                            struct igb_tx_buffer *);
 412 extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
 413 extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
 414 extern bool igb_has_link(struct igb_adapter *adapter);
 415 extern void igb_set_ethtool_ops(struct net_device *);
 416 extern void igb_power_up_link(struct igb_adapter *);
 417
 418 static inline s32 igb_reset_phy(struct e1000_hw *hw)
 419 {
 420         if (hw->phy.ops.reset)
 421                 return hw->phy.ops.reset(hw);
 422
 423         return 0;
 424 }
 425
 426 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 427 {
 428         if (hw->phy.ops.read_reg)
 429                 return hw->phy.ops.read_reg(hw, offset, data);
 430
 431         return 0;
 432 }
 433
 434 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 435 {
 436         if (hw->phy.ops.write_reg)
 437                 return hw->phy.ops.write_reg(hw, offset, data);
 438
 439         return 0;
 440 }
 441
 442 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 443 {
 444         if (hw->phy.ops.get_phy_info)
 445                 return hw->phy.ops.get_phy_info(hw);
 446
 447         return 0;
 448 }
 449
 450 static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
 451 {
 452         return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
 453 }
 454
 455 #endif /* _IGB_H_ */