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rt2800: initialize BBP_R104 on proper subroutines
[linux/fpc-iii.git] / drivers / media / i2c / saa7115.c
blob52c717d977c937aff0e39c7194bf9089f0648c19
1 /* saa711x - Philips SAA711x video decoder driver
2 * This driver can work with saa7111, saa7111a, saa7113, saa7114,
3 * saa7115 and saa7118.
4 *
5 * Based on saa7114 driver by Maxim Yevtyushkin, which is based on
6 * the saa7111 driver by Dave Perks.
7 *
8 * Copyright (C) 1998 Dave Perks <dperks@ibm.net>
9 * Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com>
10 *
11 * Slight changes for video timing and attachment output by
12 * Wolfgang Scherr <scherr@net4you.net>
13 *
14 * Moved over to the linux >= 2.4.x i2c protocol (1/1/2003)
15 * by Ronald Bultje <rbultje@ronald.bitfreak.net>
16 *
17 * Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com>
18 * (2/17/2003)
19 *
20 * VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@xs4all.nl>
21 *
22 * Copyright (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
23 * SAA7111, SAA7113 and SAA7118 support
24 *
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
38 */
39
40 #include "saa711x_regs.h"
41
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/slab.h>
45 #include <linux/i2c.h>
46 #include <linux/videodev2.h>
47 #include <media/v4l2-device.h>
48 #include <media/v4l2-ctrls.h>
49 #include <media/v4l2-chip-ident.h>
50 #include <media/saa7115.h>
51 #include <asm/div64.h>
52
53 #define VRES_60HZ (480+16)
54
55 MODULE_DESCRIPTION("Philips SAA7111/SAA7113/SAA7114/SAA7115/SAA7118 video decoder driver");
56 MODULE_AUTHOR( "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, "
57 "Hans Verkuil, Mauro Carvalho Chehab");
58 MODULE_LICENSE("GPL");
59
60 static bool debug;
61 module_param(debug, bool, 0644);
62
63 MODULE_PARM_DESC(debug, "Debug level (0-1)");
64
65
66 struct saa711x_state {
67 struct v4l2_subdev sd;
68 struct v4l2_ctrl_handler hdl;
69
70 struct {
71 /* chroma gain control cluster */
72 struct v4l2_ctrl *agc;
73 struct v4l2_ctrl *gain;
74 };
75
76 v4l2_std_id std;
77 int input;
78 int output;
79 int enable;
80 int radio;
81 int width;
82 int height;
83 u32 ident;
84 u32 audclk_freq;
85 u32 crystal_freq;
86 bool ucgc;
87 u8 cgcdiv;
88 bool apll;
89 bool double_asclk;
90 };
91
92 static inline struct saa711x_state *to_state(struct v4l2_subdev *sd)
93 {
94 return container_of(sd, struct saa711x_state, sd);
95 }
96
97 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
98 {
99 return &container_of(ctrl->handler, struct saa711x_state, hdl)->sd;
100 }
101
102 /* ----------------------------------------------------------------------- */
103
104 static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value)
105 {
106 struct i2c_client *client = v4l2_get_subdevdata(sd);
107
108 return i2c_smbus_write_byte_data(client, reg, value);
109 }
110
111 /* Sanity routine to check if a register is present */
112 static int saa711x_has_reg(const int id, const u8 reg)
113 {
114 if (id == V4L2_IDENT_SAA7111)
115 return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
116 (reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e;
117 if (id == V4L2_IDENT_SAA7111A)
118 return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
119 reg != 0x14 && reg != 0x18 && reg != 0x19 &&
120 reg != 0x1d && reg != 0x1e;
121
122 /* common for saa7113/4/5/8 */
123 if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f ||
124 reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) ||
125 reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) ||
126 reg == 0x82 || (reg >= 0x89 && reg <= 0x8e)))
127 return 0;
128
129 switch (id) {
130 case V4L2_IDENT_SAA7113:
131 return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && (reg < 0x20 || reg > 0x3f) &&
132 reg != 0x5d && reg < 0x63;
133 case V4L2_IDENT_SAA7114:
134 return (reg < 0x1a || reg > 0x1e) && (reg < 0x20 || reg > 0x2f) &&
135 (reg < 0x63 || reg > 0x7f) && reg != 0x33 && reg != 0x37 &&
136 reg != 0x81 && reg < 0xf0;
137 case V4L2_IDENT_SAA7115:
138 return (reg < 0x20 || reg > 0x2f) && reg != 0x65 && (reg < 0xfc || reg > 0xfe);
139 case V4L2_IDENT_SAA7118:
140 return (reg < 0x1a || reg > 0x1d) && (reg < 0x20 || reg > 0x22) &&
141 (reg < 0x26 || reg > 0x28) && reg != 0x33 && reg != 0x37 &&
142 (reg < 0x63 || reg > 0x7f) && reg != 0x81 && reg < 0xf0;
143 }
144 return 1;
145 }
146
147 static int saa711x_writeregs(struct v4l2_subdev *sd, const unsigned char *regs)
148 {
149 struct saa711x_state *state = to_state(sd);
150 unsigned char reg, data;
151
152 while (*regs != 0x00) {
153 reg = *(regs++);
154 data = *(regs++);
155
156 /* According with datasheets, reserved regs should be
157 filled with 0 - seems better not to touch on they */
158 if (saa711x_has_reg(state->ident, reg)) {
159 if (saa711x_write(sd, reg, data) < 0)
160 return -1;
161 } else {
162 v4l2_dbg(1, debug, sd, "tried to access reserved reg 0x%02x\n", reg);
163 }
164 }
165 return 0;
166 }
167
168 static inline int saa711x_read(struct v4l2_subdev *sd, u8 reg)
169 {
170 struct i2c_client *client = v4l2_get_subdevdata(sd);
171
172 return i2c_smbus_read_byte_data(client, reg);
173 }
174
175 /* ----------------------------------------------------------------------- */
176
177 /* SAA7111 initialization table */
178 static const unsigned char saa7111_init[] = {
179 R_01_INC_DELAY, 0x00, /* reserved */
180
181 /*front end */
182 R_02_INPUT_CNTL_1, 0xd0, /* FUSE=3, GUDL=2, MODE=0 */
183 R_03_INPUT_CNTL_2, 0x23, /* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0,
184 * GAFIX=0, GAI1=256, GAI2=256 */
185 R_04_INPUT_CNTL_3, 0x00, /* GAI1=256 */
186 R_05_INPUT_CNTL_4, 0x00, /* GAI2=256 */
187
188 /* decoder */
189 R_06_H_SYNC_START, 0xf3, /* HSB at 13(50Hz) / 17(60Hz)
190 * pixels after end of last line */
191 R_07_H_SYNC_STOP, 0xe8, /* HSS seems to be needed to
192 * work with NTSC, too */
193 R_08_SYNC_CNTL, 0xc8, /* AUFD=1, FSEL=1, EXFIL=0,
194 * VTRC=1, HPLL=0, VNOI=0 */
195 R_09_LUMA_CNTL, 0x01, /* BYPS=0, PREF=0, BPSS=0,
196 * VBLB=0, UPTCV=0, APER=1 */
197 R_0A_LUMA_BRIGHT_CNTL, 0x80,
198 R_0B_LUMA_CONTRAST_CNTL, 0x47, /* 0b - CONT=1.109 */
199 R_0C_CHROMA_SAT_CNTL, 0x40,
200 R_0D_CHROMA_HUE_CNTL, 0x00,
201 R_0E_CHROMA_CNTL_1, 0x01, /* 0e - CDTO=0, CSTD=0, DCCF=0,
202 * FCTC=0, CHBW=1 */
203 R_0F_CHROMA_GAIN_CNTL, 0x00, /* reserved */
204 R_10_CHROMA_CNTL_2, 0x48, /* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */
205 R_11_MODE_DELAY_CNTL, 0x1c, /* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1,
206 * OEYC=1, OEHV=1, VIPB=0, COLO=0 */
207 R_12_RT_SIGNAL_CNTL, 0x00, /* 12 - output control 2 */
208 R_13_RT_X_PORT_OUT_CNTL, 0x00, /* 13 - output control 3 */
209 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
210 R_15_VGATE_START_FID_CHG, 0x00,
211 R_16_VGATE_STOP, 0x00,
212 R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
213
214 0x00, 0x00
215 };
216
217 /* SAA7113 init codes */
218 static const unsigned char saa7113_init[] = {
219 R_01_INC_DELAY, 0x08,
220 R_02_INPUT_CNTL_1, 0xc2,
221 R_03_INPUT_CNTL_2, 0x30,
222 R_04_INPUT_CNTL_3, 0x00,
223 R_05_INPUT_CNTL_4, 0x00,
224 R_06_H_SYNC_START, 0x89,
225 R_07_H_SYNC_STOP, 0x0d,
226 R_08_SYNC_CNTL, 0x88,
227 R_09_LUMA_CNTL, 0x01,
228 R_0A_LUMA_BRIGHT_CNTL, 0x80,
229 R_0B_LUMA_CONTRAST_CNTL, 0x47,
230 R_0C_CHROMA_SAT_CNTL, 0x40,
231 R_0D_CHROMA_HUE_CNTL, 0x00,
232 R_0E_CHROMA_CNTL_1, 0x01,
233 R_0F_CHROMA_GAIN_CNTL, 0x2a,
234 R_10_CHROMA_CNTL_2, 0x08,
235 R_11_MODE_DELAY_CNTL, 0x0c,
236 R_12_RT_SIGNAL_CNTL, 0x07,
237 R_13_RT_X_PORT_OUT_CNTL, 0x00,
238 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
239 R_15_VGATE_START_FID_CHG, 0x00,
240 R_16_VGATE_STOP, 0x00,
241 R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
242
243 0x00, 0x00
244 };
245
246 /* If a value differs from the Hauppauge driver values, then the comment starts with
247 'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the
248 Hauppauge driver sets. */
249
250 /* SAA7114 and SAA7115 initialization table */
251 static const unsigned char saa7115_init_auto_input[] = {
252 /* Front-End Part */
253 R_01_INC_DELAY, 0x48, /* white peak control disabled */
254 R_03_INPUT_CNTL_2, 0x20, /* was 0x30. 0x20: long vertical blanking */
255 R_04_INPUT_CNTL_3, 0x90, /* analog gain set to 0 */
256 R_05_INPUT_CNTL_4, 0x90, /* analog gain set to 0 */
257 /* Decoder Part */
258 R_06_H_SYNC_START, 0xeb, /* horiz sync begin = -21 */
259 R_07_H_SYNC_STOP, 0xe0, /* horiz sync stop = -17 */
260 R_09_LUMA_CNTL, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */
261 R_0A_LUMA_BRIGHT_CNTL, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */
262 R_0B_LUMA_CONTRAST_CNTL, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */
263 R_0C_CHROMA_SAT_CNTL, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */
264 R_0D_CHROMA_HUE_CNTL, 0x00,
265 R_0F_CHROMA_GAIN_CNTL, 0x00, /* use automatic gain */
266 R_10_CHROMA_CNTL_2, 0x06, /* chroma: active adaptive combfilter */
267 R_11_MODE_DELAY_CNTL, 0x00,
268 R_12_RT_SIGNAL_CNTL, 0x9d, /* RTS0 output control: VGATE */
269 R_13_RT_X_PORT_OUT_CNTL, 0x80, /* ITU656 standard mode, RTCO output enable RTCE */
270 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
271 R_18_RAW_DATA_GAIN_CNTL, 0x40, /* gain 0x00 = nominal */
272 R_19_RAW_DATA_OFF_CNTL, 0x80,
273 R_1A_COLOR_KILL_LVL_CNTL, 0x77, /* recommended value */
274 R_1B_MISC_TVVCRDET, 0x42, /* recommended value */
275 R_1C_ENHAN_COMB_CTRL1, 0xa9, /* recommended value */
276 R_1D_ENHAN_COMB_CTRL2, 0x01, /* recommended value */
277
278
279 R_80_GLOBAL_CNTL_1, 0x0, /* No tasks enabled at init */
280
281 /* Power Device Control */
282 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset device */
283 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* set device programmed, all in operational mode */
284 0x00, 0x00
285 };
286
287 /* Used to reset saa7113, saa7114 and saa7115 */
288 static const unsigned char saa7115_cfg_reset_scaler[] = {
289 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* disable I-port output */
290 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
291 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
292 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* enable I-port output */
293 0x00, 0x00
294 };
295
296 /* ============== SAA7715 VIDEO templates ============= */
297
298 static const unsigned char saa7115_cfg_60hz_video[] = {
299 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
300 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
301
302 R_15_VGATE_START_FID_CHG, 0x03,
303 R_16_VGATE_STOP, 0x11,
304 R_17_MISC_VGATE_CONF_AND_MSB, 0x9c,
305
306 R_08_SYNC_CNTL, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */
307 R_0E_CHROMA_CNTL_1, 0x07, /* video autodetection is on */
308
309 R_5A_V_OFF_FOR_SLICER, 0x06, /* standard 60hz value for ITU656 line counting */
310
311 /* Task A */
312 R_90_A_TASK_HANDLING_CNTL, 0x80,
313 R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
314 R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
315 R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
316
317 /* hoffset low (input), 0x0002 is minimum */
318 R_94_A_HORIZ_INPUT_WINDOW_START, 0x01,
319 R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
320
321 /* hsize low (input), 0x02d0 = 720 */
322 R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
323 R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
324
325 R_98_A_VERT_INPUT_WINDOW_START, 0x05,
326 R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
327
328 R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c,
329 R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
330
331 R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
332 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,
333
334 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c,
335 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
336
337 /* Task B */
338 R_C0_B_TASK_HANDLING_CNTL, 0x00,
339 R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
340 R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
341 R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
342
343 /* 0x0002 is minimum */
344 R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02,
345 R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
346
347 /* 0x02d0 = 720 */
348 R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
349 R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
350
351 /* vwindow start 0x12 = 18 */
352 R_C8_B_VERT_INPUT_WINDOW_START, 0x12,
353 R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
354
355 /* vwindow length 0xf8 = 248 */
356 R_CA_B_VERT_INPUT_WINDOW_LENGTH, VRES_60HZ>>1,
357 R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, VRES_60HZ>>9,
358
359 /* hwindow 0x02d0 = 720 */
360 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
361 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
362
363 R_F0_LFCO_PER_LINE, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
364 R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0 */
365 R_F5_PULSGEN_LINE_LENGTH, 0xad,
366 R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
367
368 0x00, 0x00
369 };
370
371 static const unsigned char saa7115_cfg_50hz_video[] = {
372 R_80_GLOBAL_CNTL_1, 0x00,
373 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
374
375 R_15_VGATE_START_FID_CHG, 0x37, /* VGATE start */
376 R_16_VGATE_STOP, 0x16,
377 R_17_MISC_VGATE_CONF_AND_MSB, 0x99,
378
379 R_08_SYNC_CNTL, 0x28, /* 0x28 = PAL */
380 R_0E_CHROMA_CNTL_1, 0x07,
381
382 R_5A_V_OFF_FOR_SLICER, 0x03, /* standard 50hz value */
383
384 /* Task A */
385 R_90_A_TASK_HANDLING_CNTL, 0x81,
386 R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
387 R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
388 R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
389
390 /* This is weird: the datasheet says that you should use 2 as the minimum value, */
391 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
392 /* hoffset low (input), 0x0002 is minimum */
393 R_94_A_HORIZ_INPUT_WINDOW_START, 0x00,
394 R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
395
396 /* hsize low (input), 0x02d0 = 720 */
397 R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
398 R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
399
400 R_98_A_VERT_INPUT_WINDOW_START, 0x03,
401 R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
402
403 /* vsize 0x12 = 18 */
404 R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12,
405 R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
406
407 /* hsize 0x05a0 = 1440 */
408 R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
409 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, /* hsize hi (output) */
410 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12, /* vsize low (output), 0x12 = 18 */
411 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, /* vsize hi (output) */
412
413 /* Task B */
414 R_C0_B_TASK_HANDLING_CNTL, 0x00,
415 R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
416 R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
417 R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
418
419 /* This is weird: the datasheet says that you should use 2 as the minimum value, */
420 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
421 /* hoffset low (input), 0x0002 is minimum. See comment above. */
422 R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00,
423 R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
424
425 /* hsize 0x02d0 = 720 */
426 R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
427 R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
428
429 /* voffset 0x16 = 22 */
430 R_C8_B_VERT_INPUT_WINDOW_START, 0x16,
431 R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
432
433 /* vsize 0x0120 = 288 */
434 R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20,
435 R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01,
436
437 /* hsize 0x02d0 = 720 */
438 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
439 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
440
441 R_F0_LFCO_PER_LINE, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
442 R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0, (was 0x05) */
443 R_F5_PULSGEN_LINE_LENGTH, 0xb0,
444 R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
445
446 0x00, 0x00
447 };
448
449 /* ============== SAA7715 VIDEO templates (end) ======= */
450
451 static const unsigned char saa7115_cfg_vbi_on[] = {
452 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
453 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
454 R_80_GLOBAL_CNTL_1, 0x30, /* Activate both tasks */
455 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
456 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
457
458 0x00, 0x00
459 };
460
461 static const unsigned char saa7115_cfg_vbi_off[] = {
462 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
463 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
464 R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */
465 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
466 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
467
468 0x00, 0x00
469 };
470
471
472 static const unsigned char saa7115_init_misc[] = {
473 R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
474 R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01,
475 R_84_I_PORT_SIGNAL_DEF, 0x20,
476 R_85_I_PORT_SIGNAL_POLAR, 0x21,
477 R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5,
478 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,
479
480 /* Task A */
481 R_A0_A_HORIZ_PRESCALING, 0x01,
482 R_A1_A_ACCUMULATION_LENGTH, 0x00,
483 R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
484
485 /* Configure controls at nominal value*/
486 R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80,
487 R_A5_A_LUMA_CONTRAST_CNTL, 0x40,
488 R_A6_A_CHROMA_SATURATION_CNTL, 0x40,
489
490 /* note: 2 x zoom ensures that VBI lines have same length as video lines. */
491 R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00,
492 R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02,
493
494 R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00,
495
496 /* must be horiz lum scaling / 2 */
497 R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00,
498 R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01,
499
500 /* must be offset luma / 2 */
501 R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00,
502
503 R_B0_A_VERT_LUMA_SCALING_INC, 0x00,
504 R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04,
505
506 R_B2_A_VERT_CHROMA_SCALING_INC, 0x00,
507 R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04,
508
509 R_B4_A_VERT_SCALING_MODE_CNTL, 0x01,
510
511 R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00,
512 R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00,
513 R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00,
514 R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00,
515
516 R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00,
517 R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00,
518 R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00,
519 R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00,
520
521 /* Task B */
522 R_D0_B_HORIZ_PRESCALING, 0x01,
523 R_D1_B_ACCUMULATION_LENGTH, 0x00,
524 R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
525
526 /* Configure controls at nominal value*/
527 R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80,
528 R_D5_B_LUMA_CONTRAST_CNTL, 0x40,
529 R_D6_B_CHROMA_SATURATION_CNTL, 0x40,
530
531 /* hor lum scaling 0x0400 = 1 */
532 R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
533 R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
534
535 R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00,
536
537 /* must be hor lum scaling / 2 */
538 R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
539 R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
540
541 /* must be offset luma / 2 */
542 R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00,
543
544 R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
545 R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
546
547 R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
548 R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
549
550 R_E4_B_VERT_SCALING_MODE_CNTL, 0x01,
551
552 R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00,
553 R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00,
554 R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00,
555 R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00,
556
557 R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00,
558 R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00,
559 R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00,
560 R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00,
561
562 R_F2_NOMINAL_PLL2_DTO, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */
563 R_F3_PLL_INCREMENT, 0x46,
564 R_F4_PLL2_STATUS, 0x00,
565 R_F7_PULSE_A_POS_MSB, 0x4b, /* not the recommended settings! */
566 R_F8_PULSE_B_POS, 0x00,
567 R_F9_PULSE_B_POS_MSB, 0x4b,
568 R_FA_PULSE_C_POS, 0x00,
569 R_FB_PULSE_C_POS_MSB, 0x4b,
570
571 /* PLL2 lock detection settings: 71 lines 50% phase error */
572 R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88,
573
574 /* Turn off VBI */
575 R_40_SLICER_CNTL_1, 0x20, /* No framing code errors allowed. */
576 R_41_LCR_BASE, 0xff,
577 R_41_LCR_BASE+1, 0xff,
578 R_41_LCR_BASE+2, 0xff,
579 R_41_LCR_BASE+3, 0xff,
580 R_41_LCR_BASE+4, 0xff,
581 R_41_LCR_BASE+5, 0xff,
582 R_41_LCR_BASE+6, 0xff,
583 R_41_LCR_BASE+7, 0xff,
584 R_41_LCR_BASE+8, 0xff,
585 R_41_LCR_BASE+9, 0xff,
586 R_41_LCR_BASE+10, 0xff,
587 R_41_LCR_BASE+11, 0xff,
588 R_41_LCR_BASE+12, 0xff,
589 R_41_LCR_BASE+13, 0xff,
590 R_41_LCR_BASE+14, 0xff,
591 R_41_LCR_BASE+15, 0xff,
592 R_41_LCR_BASE+16, 0xff,
593 R_41_LCR_BASE+17, 0xff,
594 R_41_LCR_BASE+18, 0xff,
595 R_41_LCR_BASE+19, 0xff,
596 R_41_LCR_BASE+20, 0xff,
597 R_41_LCR_BASE+21, 0xff,
598 R_41_LCR_BASE+22, 0xff,
599 R_58_PROGRAM_FRAMING_CODE, 0x40,
600 R_59_H_OFF_FOR_SLICER, 0x47,
601 R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83,
602 R_5D_DID, 0xbd,
603 R_5E_SDID, 0x35,
604
605 R_02_INPUT_CNTL_1, 0xc4, /* input tuner -> input 4, amplifier active */
606
607 R_80_GLOBAL_CNTL_1, 0x20, /* enable task B */
608 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,
609 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,
610 0x00, 0x00
611 };
612
613 static int saa711x_odd_parity(u8 c)
614 {
615 c ^= (c >> 4);
616 c ^= (c >> 2);
617 c ^= (c >> 1);
618
619 return c & 1;
620 }
621
622 static int saa711x_decode_vps(u8 *dst, u8 *p)
623 {
624 static const u8 biphase_tbl[] = {
625 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
626 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
627 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
628 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
629 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
630 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
631 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
632 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
633 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
634 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
635 0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
636 0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
637 0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
638 0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
639 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
640 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
641 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
642 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
643 0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
644 0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
645 0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
646 0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
647 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
648 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
649 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
650 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
651 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
652 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
653 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
654 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
655 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
656 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
657 };
658 int i;
659 u8 c, err = 0;
660
661 for (i = 0; i < 2 * 13; i += 2) {
662 err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
663 c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4);
664 dst[i / 2] = c;
665 }
666 return err & 0xf0;
667 }
668
669 static int saa711x_decode_wss(u8 *p)
670 {
671 static const int wss_bits[8] = {
672 0, 0, 0, 1, 0, 1, 1, 1
673 };
674 unsigned char parity;
675 int wss = 0;
676 int i;
677
678 for (i = 0; i < 16; i++) {
679 int b1 = wss_bits[p[i] & 7];
680 int b2 = wss_bits[(p[i] >> 3) & 7];
681
682 if (b1 == b2)
683 return -1;
684 wss |= b2 << i;
685 }
686 parity = wss & 15;
687 parity ^= parity >> 2;
688 parity ^= parity >> 1;
689
690 if (!(parity & 1))
691 return -1;
692
693 return wss;
694 }
695
696 static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
697 {
698 struct saa711x_state *state = to_state(sd);
699 u32 acpf;
700 u32 acni;
701 u32 hz;
702 u64 f;
703 u8 acc = 0; /* reg 0x3a, audio clock control */
704
705 /* Checks for chips that don't have audio clock (saa7111, saa7113) */
706 if (!saa711x_has_reg(state->ident, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD))
707 return 0;
708
709 v4l2_dbg(1, debug, sd, "set audio clock freq: %d\n", freq);
710
711 /* sanity check */
712 if (freq < 32000 || freq > 48000)
713 return -EINVAL;
714
715 /* hz is the refresh rate times 100 */
716 hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000;
717 /* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */
718 acpf = (25600 * freq) / hz;
719 /* acni = (256 * freq * 2^23) / crystal_frequency =
720 (freq * 2^(8+23)) / crystal_frequency =
721 (freq << 31) / crystal_frequency */
722 f = freq;
723 f = f << 31;
724 do_div(f, state->crystal_freq);
725 acni = f;
726 if (state->ucgc) {
727 acpf = acpf * state->cgcdiv / 16;
728 acni = acni * state->cgcdiv / 16;
729 acc = 0x80;
730 if (state->cgcdiv == 3)
731 acc |= 0x40;
732 }
733 if (state->apll)
734 acc |= 0x08;
735
736 if (state->double_asclk) {
737 acpf <<= 1;
738 acni <<= 1;
739 }
740 saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
741 saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10 << state->double_asclk);
742 saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
743
744 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
745 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1,
746 (acpf >> 8) & 0xff);
747 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2,
748 (acpf >> 16) & 0x03);
749
750 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff);
751 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff);
752 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f);
753 state->audclk_freq = freq;
754 return 0;
755 }
756
757 static int saa711x_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
758 {
759 struct v4l2_subdev *sd = to_sd(ctrl);
760 struct saa711x_state *state = to_state(sd);
761
762 switch (ctrl->id) {
763 case V4L2_CID_CHROMA_AGC:
764 /* chroma gain cluster */
765 if (state->agc->val)
766 state->gain->val =
767 saa711x_read(sd, R_0F_CHROMA_GAIN_CNTL) & 0x7f;
768 break;
769 }
770 return 0;
771 }
772
773 static int saa711x_s_ctrl(struct v4l2_ctrl *ctrl)
774 {
775 struct v4l2_subdev *sd = to_sd(ctrl);
776 struct saa711x_state *state = to_state(sd);
777
778 switch (ctrl->id) {
779 case V4L2_CID_BRIGHTNESS:
780 saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, ctrl->val);
781 break;
782
783 case V4L2_CID_CONTRAST:
784 saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, ctrl->val);
785 break;
786
787 case V4L2_CID_SATURATION:
788 saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, ctrl->val);
789 break;
790
791 case V4L2_CID_HUE:
792 saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, ctrl->val);
793 break;
794
795 case V4L2_CID_CHROMA_AGC:
796 /* chroma gain cluster */
797 if (state->agc->val)
798 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val);
799 else
800 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val | 0x80);
801 break;
802
803 default:
804 return -EINVAL;
805 }
806
807 return 0;
808 }
809
810 static int saa711x_set_size(struct v4l2_subdev *sd, int width, int height)
811 {
812 struct saa711x_state *state = to_state(sd);
813 int HPSC, HFSC;
814 int VSCY;
815 int res;
816 int is_50hz = state->std & V4L2_STD_625_50;
817 int Vsrc = is_50hz ? 576 : 480;
818
819 v4l2_dbg(1, debug, sd, "decoder set size to %ix%i\n", width, height);
820
821 /* FIXME need better bounds checking here */
822 if ((width < 1) || (width > 1440))
823 return -EINVAL;
824 if ((height < 1) || (height > Vsrc))
825 return -EINVAL;
826
827 if (!saa711x_has_reg(state->ident, R_D0_B_HORIZ_PRESCALING)) {
828 /* Decoder only supports 720 columns and 480 or 576 lines */
829 if (width != 720)
830 return -EINVAL;
831 if (height != Vsrc)
832 return -EINVAL;
833 }
834
835 state->width = width;
836 state->height = height;
837
838 if (!saa711x_has_reg(state->ident, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH))
839 return 0;
840
841 /* probably have a valid size, let's set it */
842 /* Set output width/height */
843 /* width */
844
845 saa711x_write(sd, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
846 (u8) (width & 0xff));
847 saa711x_write(sd, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
848 (u8) ((width >> 8) & 0xff));
849
850 /* Vertical Scaling uses height/2 */
851 res = height / 2;
852
853 /* On 60Hz, it is using a higher Vertical Output Size */
854 if (!is_50hz)
855 res += (VRES_60HZ - 480) >> 1;
856
857 /* height */
858 saa711x_write(sd, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
859 (u8) (res & 0xff));
860 saa711x_write(sd, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
861 (u8) ((res >> 8) & 0xff));
862
863 /* Scaling settings */
864 /* Hprescaler is floor(inres/outres) */
865 HPSC = (int)(720 / width);
866 /* 0 is not allowed (div. by zero) */
867 HPSC = HPSC ? HPSC : 1;
868 HFSC = (int)((1024 * 720) / (HPSC * width));
869 /* FIXME hardcodes to "Task B"
870 * write H prescaler integer */
871 saa711x_write(sd, R_D0_B_HORIZ_PRESCALING,
872 (u8) (HPSC & 0x3f));
873
874 v4l2_dbg(1, debug, sd, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC);
875 /* write H fine-scaling (luminance) */
876 saa711x_write(sd, R_D8_B_HORIZ_LUMA_SCALING_INC,
877 (u8) (HFSC & 0xff));
878 saa711x_write(sd, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB,
879 (u8) ((HFSC >> 8) & 0xff));
880 /* write H fine-scaling (chrominance)
881 * must be lum/2, so i'll just bitshift :) */
882 saa711x_write(sd, R_DC_B_HORIZ_CHROMA_SCALING,
883 (u8) ((HFSC >> 1) & 0xff));
884 saa711x_write(sd, R_DD_B_HORIZ_CHROMA_SCALING_MSB,
885 (u8) ((HFSC >> 9) & 0xff));
886
887 VSCY = (int)((1024 * Vsrc) / height);
888 v4l2_dbg(1, debug, sd, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
889
890 /* Correct Contrast and Luminance */
891 saa711x_write(sd, R_D5_B_LUMA_CONTRAST_CNTL,
892 (u8) (64 * 1024 / VSCY));
893 saa711x_write(sd, R_D6_B_CHROMA_SATURATION_CNTL,
894 (u8) (64 * 1024 / VSCY));
895
896 /* write V fine-scaling (luminance) */
897 saa711x_write(sd, R_E0_B_VERT_LUMA_SCALING_INC,
898 (u8) (VSCY & 0xff));
899 saa711x_write(sd, R_E1_B_VERT_LUMA_SCALING_INC_MSB,
900 (u8) ((VSCY >> 8) & 0xff));
901 /* write V fine-scaling (chrominance) */
902 saa711x_write(sd, R_E2_B_VERT_CHROMA_SCALING_INC,
903 (u8) (VSCY & 0xff));
904 saa711x_write(sd, R_E3_B_VERT_CHROMA_SCALING_INC_MSB,
905 (u8) ((VSCY >> 8) & 0xff));
906
907 saa711x_writeregs(sd, saa7115_cfg_reset_scaler);
908
909 /* Activates task "B" */
910 saa711x_write(sd, R_80_GLOBAL_CNTL_1,
911 saa711x_read(sd, R_80_GLOBAL_CNTL_1) | 0x20);
912
913 return 0;
914 }
915
916 static void saa711x_set_v4lstd(struct v4l2_subdev *sd, v4l2_std_id std)
917 {
918 struct saa711x_state *state = to_state(sd);
919
920 /* Prevent unnecessary standard changes. During a standard
921 change the I-Port is temporarily disabled. Any devices
922 reading from that port can get confused.
923 Note that s_std is also used to switch from
924 radio to TV mode, so if a s_std is broadcast to
925 all I2C devices then you do not want to have an unwanted
926 side-effect here. */
927 if (std == state->std)
928 return;
929
930 state->std = std;
931
932 // This works for NTSC-M, SECAM-L and the 50Hz PAL variants.
933 if (std & V4L2_STD_525_60) {
934 v4l2_dbg(1, debug, sd, "decoder set standard 60 Hz\n");
935 saa711x_writeregs(sd, saa7115_cfg_60hz_video);
936 saa711x_set_size(sd, 720, 480);
937 } else {
938 v4l2_dbg(1, debug, sd, "decoder set standard 50 Hz\n");
939 saa711x_writeregs(sd, saa7115_cfg_50hz_video);
940 saa711x_set_size(sd, 720, 576);
941 }
942
943 /* Register 0E - Bits D6-D4 on NO-AUTO mode
944 (SAA7111 and SAA7113 doesn't have auto mode)
945 50 Hz / 625 lines 60 Hz / 525 lines
946 000 PAL BGDHI (4.43Mhz) NTSC M (3.58MHz)
947 001 NTSC 4.43 (50 Hz) PAL 4.43 (60 Hz)
948 010 Combination-PAL N (3.58MHz) NTSC 4.43 (60 Hz)
949 011 NTSC N (3.58MHz) PAL M (3.58MHz)
950 100 reserved NTSC-Japan (3.58MHz)
951 */
952 if (state->ident <= V4L2_IDENT_SAA7113) {
953 u8 reg = saa711x_read(sd, R_0E_CHROMA_CNTL_1) & 0x8f;
954
955 if (std == V4L2_STD_PAL_M) {
956 reg |= 0x30;
957 } else if (std == V4L2_STD_PAL_Nc) {
958 reg |= 0x20;
959 } else if (std == V4L2_STD_PAL_60) {
960 reg |= 0x10;
961 } else if (std == V4L2_STD_NTSC_M_JP) {
962 reg |= 0x40;
963 } else if (std & V4L2_STD_SECAM) {
964 reg |= 0x50;
965 }
966 saa711x_write(sd, R_0E_CHROMA_CNTL_1, reg);
967 } else {
968 /* restart task B if needed */
969 int taskb = saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10;
970
971 if (taskb && state->ident == V4L2_IDENT_SAA7114) {
972 saa711x_writeregs(sd, saa7115_cfg_vbi_on);
973 }
974
975 /* switch audio mode too! */
976 saa711x_s_clock_freq(sd, state->audclk_freq);
977 }
978 }
979
980 /* setup the sliced VBI lcr registers according to the sliced VBI format */
981 static void saa711x_set_lcr(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt)
982 {
983 struct saa711x_state *state = to_state(sd);
984 int is_50hz = (state->std & V4L2_STD_625_50);
985 u8 lcr[24];
986 int i, x;
987
988 #if 1
989 /* saa7113/7114/7118 VBI support are experimental */
990 if (!saa711x_has_reg(state->ident, R_41_LCR_BASE))
991 return;
992
993 #else
994 /* SAA7113 and SAA7118 also should support VBI - Need testing */
995 if (state->ident != V4L2_IDENT_SAA7115)
996 return;
997 #endif
998
999 for (i = 0; i <= 23; i++)
1000 lcr[i] = 0xff;
1001
1002 if (fmt == NULL) {
1003 /* raw VBI */
1004 if (is_50hz)
1005 for (i = 6; i <= 23; i++)
1006 lcr[i] = 0xdd;
1007 else
1008 for (i = 10; i <= 21; i++)
1009 lcr[i] = 0xdd;
1010 } else {
1011 /* sliced VBI */
1012 /* first clear lines that cannot be captured */
1013 if (is_50hz) {
1014 for (i = 0; i <= 5; i++)
1015 fmt->service_lines[0][i] =
1016 fmt->service_lines[1][i] = 0;
1017 }
1018 else {
1019 for (i = 0; i <= 9; i++)
1020 fmt->service_lines[0][i] =
1021 fmt->service_lines[1][i] = 0;
1022 for (i = 22; i <= 23; i++)
1023 fmt->service_lines[0][i] =
1024 fmt->service_lines[1][i] = 0;
1025 }
1026
1027 /* Now set the lcr values according to the specified service */
1028 for (i = 6; i <= 23; i++) {
1029 lcr[i] = 0;
1030 for (x = 0; x <= 1; x++) {
1031 switch (fmt->service_lines[1-x][i]) {
1032 case 0:
1033 lcr[i] |= 0xf << (4 * x);
1034 break;
1035 case V4L2_SLICED_TELETEXT_B:
1036 lcr[i] |= 1 << (4 * x);
1037 break;
1038 case V4L2_SLICED_CAPTION_525:
1039 lcr[i] |= 4 << (4 * x);
1040 break;
1041 case V4L2_SLICED_WSS_625:
1042 lcr[i] |= 5 << (4 * x);
1043 break;
1044 case V4L2_SLICED_VPS:
1045 lcr[i] |= 7 << (4 * x);
1046 break;
1047 }
1048 }
1049 }
1050 }
1051
1052 /* write the lcr registers */
1053 for (i = 2; i <= 23; i++) {
1054 saa711x_write(sd, i - 2 + R_41_LCR_BASE, lcr[i]);
1055 }
1056
1057 /* enable/disable raw VBI capturing */
1058 saa711x_writeregs(sd, fmt == NULL ?
1059 saa7115_cfg_vbi_on :
1060 saa7115_cfg_vbi_off);
1061 }
1062
1063 static int saa711x_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *sliced)
1064 {
1065 static u16 lcr2vbi[] = {
1066 0, V4L2_SLICED_TELETEXT_B, 0, /* 1 */
1067 0, V4L2_SLICED_CAPTION_525, /* 4 */
1068 V4L2_SLICED_WSS_625, 0, /* 5 */
1069 V4L2_SLICED_VPS, 0, 0, 0, 0, /* 7 */
1070 0, 0, 0, 0
1071 };
1072 int i;
1073
1074 memset(sliced->service_lines, 0, sizeof(sliced->service_lines));
1075 sliced->service_set = 0;
1076 /* done if using raw VBI */
1077 if (saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10)
1078 return 0;
1079 for (i = 2; i <= 23; i++) {
1080 u8 v = saa711x_read(sd, i - 2 + R_41_LCR_BASE);
1081
1082 sliced->service_lines[0][i] = lcr2vbi[v >> 4];
1083 sliced->service_lines[1][i] = lcr2vbi[v & 0xf];
1084 sliced->service_set |=
1085 sliced->service_lines[0][i] | sliced->service_lines[1][i];
1086 }
1087 return 0;
1088 }
1089
1090 static int saa711x_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
1091 {
1092 saa711x_set_lcr(sd, NULL);
1093 return 0;
1094 }
1095
1096 static int saa711x_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt)
1097 {
1098 saa711x_set_lcr(sd, fmt);
1099 return 0;
1100 }
1101
1102 static int saa711x_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
1103 {
1104 if (fmt->code != V4L2_MBUS_FMT_FIXED)
1105 return -EINVAL;
1106 fmt->field = V4L2_FIELD_INTERLACED;
1107 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1108 return saa711x_set_size(sd, fmt->width, fmt->height);
1109 }
1110
1111 /* Decode the sliced VBI data stream as created by the saa7115.
1112 The format is described in the saa7115 datasheet in Tables 25 and 26
1113 and in Figure 33.
1114 The current implementation uses SAV/EAV codes and not the ancillary data
1115 headers. The vbi->p pointer points to the R_5E_SDID byte right after the SAV
1116 code. */
1117 static int saa711x_decode_vbi_line(struct v4l2_subdev *sd, struct v4l2_decode_vbi_line *vbi)
1118 {
1119 struct saa711x_state *state = to_state(sd);
1120 static const char vbi_no_data_pattern[] = {
1121 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0
1122 };
1123 u8 *p = vbi->p;
1124 u32 wss;
1125 int id1, id2; /* the ID1 and ID2 bytes from the internal header */
1126
1127 vbi->type = 0; /* mark result as a failure */
1128 id1 = p[2];
1129 id2 = p[3];
1130 /* Note: the field bit is inverted for 60 Hz video */
1131 if (state->std & V4L2_STD_525_60)
1132 id1 ^= 0x40;
1133
1134 /* Skip internal header, p now points to the start of the payload */
1135 p += 4;
1136 vbi->p = p;
1137
1138 /* calculate field and line number of the VBI packet (1-23) */
1139 vbi->is_second_field = ((id1 & 0x40) != 0);
1140 vbi->line = (id1 & 0x3f) << 3;
1141 vbi->line |= (id2 & 0x70) >> 4;
1142
1143 /* Obtain data type */
1144 id2 &= 0xf;
1145
1146 /* If the VBI slicer does not detect any signal it will fill up
1147 the payload buffer with 0xa0 bytes. */
1148 if (!memcmp(p, vbi_no_data_pattern, sizeof(vbi_no_data_pattern)))
1149 return 0;
1150
1151 /* decode payloads */
1152 switch (id2) {
1153 case 1:
1154 vbi->type = V4L2_SLICED_TELETEXT_B;
1155 break;
1156 case 4:
1157 if (!saa711x_odd_parity(p[0]) || !saa711x_odd_parity(p[1]))
1158 return 0;
1159 vbi->type = V4L2_SLICED_CAPTION_525;
1160 break;
1161 case 5:
1162 wss = saa711x_decode_wss(p);
1163 if (wss == -1)
1164 return 0;
1165 p[0] = wss & 0xff;
1166 p[1] = wss >> 8;
1167 vbi->type = V4L2_SLICED_WSS_625;
1168 break;
1169 case 7:
1170 if (saa711x_decode_vps(p, p) != 0)
1171 return 0;
1172 vbi->type = V4L2_SLICED_VPS;
1173 break;
1174 default:
1175 break;
1176 }
1177 return 0;
1178 }
1179
1180 /* ============ SAA7115 AUDIO settings (end) ============= */
1181
1182 static int saa711x_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1183 {
1184 struct saa711x_state *state = to_state(sd);
1185 int status;
1186
1187 if (state->radio)
1188 return 0;
1189 status = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1190
1191 v4l2_dbg(1, debug, sd, "status: 0x%02x\n", status);
1192 vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0;
1193 return 0;
1194 }
1195
1196 static int saa711x_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1197 {
1198 struct saa711x_state *state = to_state(sd);
1199
1200 state->radio = 0;
1201 saa711x_set_v4lstd(sd, std);
1202 return 0;
1203 }
1204
1205 static int saa711x_s_radio(struct v4l2_subdev *sd)
1206 {
1207 struct saa711x_state *state = to_state(sd);
1208
1209 state->radio = 1;
1210 return 0;
1211 }
1212
1213 static int saa711x_s_routing(struct v4l2_subdev *sd,
1214 u32 input, u32 output, u32 config)
1215 {
1216 struct saa711x_state *state = to_state(sd);
1217 u8 mask = (state->ident <= V4L2_IDENT_SAA7111A) ? 0xf8 : 0xf0;
1218
1219 v4l2_dbg(1, debug, sd, "decoder set input %d output %d\n",
1220 input, output);
1221
1222 /* saa7111/3 does not have these inputs */
1223 if (state->ident <= V4L2_IDENT_SAA7113 &&
1224 (input == SAA7115_COMPOSITE4 ||
1225 input == SAA7115_COMPOSITE5)) {
1226 return -EINVAL;
1227 }
1228 if (input > SAA7115_SVIDEO3)
1229 return -EINVAL;
1230 if (state->input == input && state->output == output)
1231 return 0;
1232 v4l2_dbg(1, debug, sd, "now setting %s input %s output\n",
1233 (input >= SAA7115_SVIDEO0) ? "S-Video" : "Composite",
1234 (output == SAA7115_IPORT_ON) ? "iport on" : "iport off");
1235 state->input = input;
1236
1237 /* saa7111 has slightly different input numbering */
1238 if (state->ident <= V4L2_IDENT_SAA7111A) {
1239 if (input >= SAA7115_COMPOSITE4)
1240 input -= 2;
1241 /* saa7111 specific */
1242 saa711x_write(sd, R_10_CHROMA_CNTL_2,
1243 (saa711x_read(sd, R_10_CHROMA_CNTL_2) & 0x3f) |
1244 ((output & 0xc0) ^ 0x40));
1245 saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL,
1246 (saa711x_read(sd, R_13_RT_X_PORT_OUT_CNTL) & 0xf0) |
1247 ((output & 2) ? 0x0a : 0));
1248 }
1249
1250 /* select mode */
1251 saa711x_write(sd, R_02_INPUT_CNTL_1,
1252 (saa711x_read(sd, R_02_INPUT_CNTL_1) & mask) |
1253 input);
1254
1255 /* bypass chrominance trap for S-Video modes */
1256 saa711x_write(sd, R_09_LUMA_CNTL,
1257 (saa711x_read(sd, R_09_LUMA_CNTL) & 0x7f) |
1258 (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0));
1259
1260 state->output = output;
1261 if (state->ident == V4L2_IDENT_SAA7114 ||
1262 state->ident == V4L2_IDENT_SAA7115) {
1263 saa711x_write(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK,
1264 (saa711x_read(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK) & 0xfe) |
1265 (state->output & 0x01));
1266 }
1267 if (state->ident > V4L2_IDENT_SAA7111A) {
1268 if (config & SAA7115_IDQ_IS_DEFAULT)
1269 saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x20);
1270 else
1271 saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x21);
1272 }
1273 return 0;
1274 }
1275
1276 static int saa711x_s_gpio(struct v4l2_subdev *sd, u32 val)
1277 {
1278 struct saa711x_state *state = to_state(sd);
1279
1280 if (state->ident > V4L2_IDENT_SAA7111A)
1281 return -EINVAL;
1282 saa711x_write(sd, 0x11, (saa711x_read(sd, 0x11) & 0x7f) |
1283 (val ? 0x80 : 0));
1284 return 0;
1285 }
1286
1287 static int saa711x_s_stream(struct v4l2_subdev *sd, int enable)
1288 {
1289 struct saa711x_state *state = to_state(sd);
1290
1291 v4l2_dbg(1, debug, sd, "%s output\n",
1292 enable ? "enable" : "disable");
1293
1294 if (state->enable == enable)
1295 return 0;
1296 state->enable = enable;
1297 if (!saa711x_has_reg(state->ident, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED))
1298 return 0;
1299 saa711x_write(sd, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, state->enable);
1300 return 0;
1301 }
1302
1303 static int saa711x_s_crystal_freq(struct v4l2_subdev *sd, u32 freq, u32 flags)
1304 {
1305 struct saa711x_state *state = to_state(sd);
1306
1307 if (freq != SAA7115_FREQ_32_11_MHZ && freq != SAA7115_FREQ_24_576_MHZ)
1308 return -EINVAL;
1309 state->crystal_freq = freq;
1310 state->double_asclk = flags & SAA7115_FREQ_FL_DOUBLE_ASCLK;
1311 state->cgcdiv = (flags & SAA7115_FREQ_FL_CGCDIV) ? 3 : 4;
1312 state->ucgc = flags & SAA7115_FREQ_FL_UCGC;
1313 state->apll = flags & SAA7115_FREQ_FL_APLL;
1314 saa711x_s_clock_freq(sd, state->audclk_freq);
1315 return 0;
1316 }
1317
1318 static int saa711x_reset(struct v4l2_subdev *sd, u32 val)
1319 {
1320 v4l2_dbg(1, debug, sd, "decoder RESET\n");
1321 saa711x_writeregs(sd, saa7115_cfg_reset_scaler);
1322 return 0;
1323 }
1324
1325 static int saa711x_g_vbi_data(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_data *data)
1326 {
1327 /* Note: the internal field ID is inverted for NTSC,
1328 so data->field 0 maps to the saa7115 even field,
1329 whereas for PAL it maps to the saa7115 odd field. */
1330 switch (data->id) {
1331 case V4L2_SLICED_WSS_625:
1332 if (saa711x_read(sd, 0x6b) & 0xc0)
1333 return -EIO;
1334 data->data[0] = saa711x_read(sd, 0x6c);
1335 data->data[1] = saa711x_read(sd, 0x6d);
1336 return 0;
1337 case V4L2_SLICED_CAPTION_525:
1338 if (data->field == 0) {
1339 /* CC */
1340 if (saa711x_read(sd, 0x66) & 0x30)
1341 return -EIO;
1342 data->data[0] = saa711x_read(sd, 0x69);
1343 data->data[1] = saa711x_read(sd, 0x6a);
1344 return 0;
1345 }
1346 /* XDS */
1347 if (saa711x_read(sd, 0x66) & 0xc0)
1348 return -EIO;
1349 data->data[0] = saa711x_read(sd, 0x67);
1350 data->data[1] = saa711x_read(sd, 0x68);
1351 return 0;
1352 default:
1353 return -EINVAL;
1354 }
1355 }
1356
1357 static int saa711x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
1358 {
1359 struct saa711x_state *state = to_state(sd);
1360 int reg1f, reg1e;
1361
1362 /*
1363 * The V4L2 core already initializes std with all supported
1364 * Standards. All driver needs to do is to mask it, to remove
1365 * standards that don't apply from the mask
1366 */
1367
1368 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1369
1370 if (state->ident == V4L2_IDENT_SAA7115) {
1371 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
1372
1373 v4l2_dbg(1, debug, sd, "Status byte 1 (0x1e)=0x%02x\n", reg1e);
1374
1375 switch (reg1e & 0x03) {
1376 case 1:
1377 *std &= V4L2_STD_NTSC;
1378 break;
1379 case 2:
1380 /*
1381 * V4L2_STD_PAL just cover the european PAL standards.
1382 * This is wrong, as the device could also be using an
1383 * other PAL standard.
1384 */
1385 *std &= V4L2_STD_PAL | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc |
1386 V4L2_STD_PAL_M | V4L2_STD_PAL_60;
1387 break;
1388 case 3:
1389 *std &= V4L2_STD_SECAM;
1390 break;
1391 default:
1392 /* Can't detect anything */
1393 break;
1394 }
1395 }
1396
1397 v4l2_dbg(1, debug, sd, "Status byte 2 (0x1f)=0x%02x\n", reg1f);
1398
1399 /* horizontal/vertical not locked */
1400 if (reg1f & 0x40)
1401 goto ret;
1402
1403 if (reg1f & 0x20)
1404 *std &= V4L2_STD_525_60;
1405 else
1406 *std &= V4L2_STD_625_50;
1407
1408 ret:
1409 v4l2_dbg(1, debug, sd, "detected std mask = %08Lx\n", *std);
1410
1411 return 0;
1412 }
1413
1414 static int saa711x_g_input_status(struct v4l2_subdev *sd, u32 *status)
1415 {
1416 struct saa711x_state *state = to_state(sd);
1417 int reg1e = 0x80;
1418 int reg1f;
1419
1420 *status = V4L2_IN_ST_NO_SIGNAL;
1421 if (state->ident == V4L2_IDENT_SAA7115)
1422 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
1423 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1424 if ((reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80)
1425 *status = 0;
1426 return 0;
1427 }
1428
1429 #ifdef CONFIG_VIDEO_ADV_DEBUG
1430 static int saa711x_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1431 {
1432 struct i2c_client *client = v4l2_get_subdevdata(sd);
1433
1434 if (!v4l2_chip_match_i2c_client(client, &reg->match))
1435 return -EINVAL;
1436 if (!capable(CAP_SYS_ADMIN))
1437 return -EPERM;
1438 reg->val = saa711x_read(sd, reg->reg & 0xff);
1439 reg->size = 1;
1440 return 0;
1441 }
1442
1443 static int saa711x_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1444 {
1445 struct i2c_client *client = v4l2_get_subdevdata(sd);
1446
1447 if (!v4l2_chip_match_i2c_client(client, &reg->match))
1448 return -EINVAL;
1449 if (!capable(CAP_SYS_ADMIN))
1450 return -EPERM;
1451 saa711x_write(sd, reg->reg & 0xff, reg->val & 0xff);
1452 return 0;
1453 }
1454 #endif
1455
1456 static int saa711x_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
1457 {
1458 struct saa711x_state *state = to_state(sd);
1459 struct i2c_client *client = v4l2_get_subdevdata(sd);
1460
1461 return v4l2_chip_ident_i2c_client(client, chip, state->ident, 0);
1462 }
1463
1464 static int saa711x_log_status(struct v4l2_subdev *sd)
1465 {
1466 struct saa711x_state *state = to_state(sd);
1467 int reg1e, reg1f;
1468 int signalOk;
1469 int vcr;
1470
1471 v4l2_info(sd, "Audio frequency: %d Hz\n", state->audclk_freq);
1472 if (state->ident != V4L2_IDENT_SAA7115) {
1473 /* status for the saa7114 */
1474 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1475 signalOk = (reg1f & 0xc1) == 0x81;
1476 v4l2_info(sd, "Video signal: %s\n", signalOk ? "ok" : "bad");
1477 v4l2_info(sd, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
1478 return 0;
1479 }
1480
1481 /* status for the saa7115 */
1482 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
1483 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1484
1485 signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80;
1486 vcr = !(reg1f & 0x10);
1487
1488 if (state->input >= 6)
1489 v4l2_info(sd, "Input: S-Video %d\n", state->input - 6);
1490 else
1491 v4l2_info(sd, "Input: Composite %d\n", state->input);
1492 v4l2_info(sd, "Video signal: %s\n", signalOk ? (vcr ? "VCR" : "broadcast/DVD") : "bad");
1493 v4l2_info(sd, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
1494
1495 switch (reg1e & 0x03) {
1496 case 1:
1497 v4l2_info(sd, "Detected format: NTSC\n");
1498 break;
1499 case 2:
1500 v4l2_info(sd, "Detected format: PAL\n");
1501 break;
1502 case 3:
1503 v4l2_info(sd, "Detected format: SECAM\n");
1504 break;
1505 default:
1506 v4l2_info(sd, "Detected format: BW/No color\n");
1507 break;
1508 }
1509 v4l2_info(sd, "Width, Height: %d, %d\n", state->width, state->height);
1510 v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
1511 return 0;
1512 }
1513
1514 /* ----------------------------------------------------------------------- */
1515
1516 static const struct v4l2_ctrl_ops saa711x_ctrl_ops = {
1517 .s_ctrl = saa711x_s_ctrl,
1518 .g_volatile_ctrl = saa711x_g_volatile_ctrl,
1519 };
1520
1521 static const struct v4l2_subdev_core_ops saa711x_core_ops = {
1522 .log_status = saa711x_log_status,
1523 .g_chip_ident = saa711x_g_chip_ident,
1524 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1525 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1526 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1527 .g_ctrl = v4l2_subdev_g_ctrl,
1528 .s_ctrl = v4l2_subdev_s_ctrl,
1529 .queryctrl = v4l2_subdev_queryctrl,
1530 .querymenu = v4l2_subdev_querymenu,
1531 .s_std = saa711x_s_std,
1532 .reset = saa711x_reset,
1533 .s_gpio = saa711x_s_gpio,
1534 #ifdef CONFIG_VIDEO_ADV_DEBUG
1535 .g_register = saa711x_g_register,
1536 .s_register = saa711x_s_register,
1537 #endif
1538 };
1539
1540 static const struct v4l2_subdev_tuner_ops saa711x_tuner_ops = {
1541 .s_radio = saa711x_s_radio,
1542 .g_tuner = saa711x_g_tuner,
1543 };
1544
1545 static const struct v4l2_subdev_audio_ops saa711x_audio_ops = {
1546 .s_clock_freq = saa711x_s_clock_freq,
1547 };
1548
1549 static const struct v4l2_subdev_video_ops saa711x_video_ops = {
1550 .s_routing = saa711x_s_routing,
1551 .s_crystal_freq = saa711x_s_crystal_freq,
1552 .s_mbus_fmt = saa711x_s_mbus_fmt,
1553 .s_stream = saa711x_s_stream,
1554 .querystd = saa711x_querystd,
1555 .g_input_status = saa711x_g_input_status,
1556 };
1557
1558 static const struct v4l2_subdev_vbi_ops saa711x_vbi_ops = {
1559 .g_vbi_data = saa711x_g_vbi_data,
1560 .decode_vbi_line = saa711x_decode_vbi_line,
1561 .g_sliced_fmt = saa711x_g_sliced_fmt,
1562 .s_sliced_fmt = saa711x_s_sliced_fmt,
1563 .s_raw_fmt = saa711x_s_raw_fmt,
1564 };
1565
1566 static const struct v4l2_subdev_ops saa711x_ops = {
1567 .core = &saa711x_core_ops,
1568 .tuner = &saa711x_tuner_ops,
1569 .audio = &saa711x_audio_ops,
1570 .video = &saa711x_video_ops,
1571 .vbi = &saa711x_vbi_ops,
1572 };
1573
1574 /* ----------------------------------------------------------------------- */
1575
1576 static int saa711x_probe(struct i2c_client *client,
1577 const struct i2c_device_id *id)
1578 {
1579 struct saa711x_state *state;
1580 struct v4l2_subdev *sd;
1581 struct v4l2_ctrl_handler *hdl;
1582 int i;
1583 char name[17];
1584 char chip_id;
1585 int autodetect = !id || id->driver_data == 1;
1586
1587 /* Check if the adapter supports the needed features */
1588 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1589 return -EIO;
1590
1591 for (i = 0; i < 0x0f; i++) {
1592 i2c_smbus_write_byte_data(client, 0, i);
1593 name[i] = (i2c_smbus_read_byte_data(client, 0) & 0x0f) + '0';
1594 if (name[i] > '9')
1595 name[i] += 'a' - '9' - 1;
1596 }
1597 name[i] = '\0';
1598
1599 chip_id = name[5];
1600
1601 /* Check whether this chip is part of the saa711x series */
1602 if (memcmp(name + 1, "f711", 4)) {
1603 v4l_dbg(1, debug, client, "chip found @ 0x%x (ID %s) does not match a known saa711x chip.\n",
1604 client->addr << 1, name);
1605 return -ENODEV;
1606 }
1607
1608 /* Safety check */
1609 if (!autodetect && id->name[6] != chip_id) {
1610 v4l_warn(client, "found saa711%c while %s was expected\n",
1611 chip_id, id->name);
1612 }
1613 snprintf(client->name, sizeof(client->name), "saa711%c", chip_id);
1614 v4l_info(client, "saa711%c found (%s) @ 0x%x (%s)\n", chip_id, name,
1615 client->addr << 1, client->adapter->name);
1616
1617 state = kzalloc(sizeof(struct saa711x_state), GFP_KERNEL);
1618 if (state == NULL)
1619 return -ENOMEM;
1620 sd = &state->sd;
1621 v4l2_i2c_subdev_init(sd, client, &saa711x_ops);
1622
1623 hdl = &state->hdl;
1624 v4l2_ctrl_handler_init(hdl, 6);
1625 /* add in ascending ID order */
1626 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1627 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1628 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1629 V4L2_CID_CONTRAST, 0, 127, 1, 64);
1630 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1631 V4L2_CID_SATURATION, 0, 127, 1, 64);
1632 v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1633 V4L2_CID_HUE, -128, 127, 1, 0);
1634 state->agc = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1635 V4L2_CID_CHROMA_AGC, 0, 1, 1, 1);
1636 state->gain = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1637 V4L2_CID_CHROMA_GAIN, 0, 127, 1, 40);
1638 sd->ctrl_handler = hdl;
1639 if (hdl->error) {
1640 int err = hdl->error;
1641
1642 v4l2_ctrl_handler_free(hdl);
1643 kfree(state);
1644 return err;
1645 }
1646 v4l2_ctrl_auto_cluster(2, &state->agc, 0, true);
1647
1648 state->input = -1;
1649 state->output = SAA7115_IPORT_ON;
1650 state->enable = 1;
1651 state->radio = 0;
1652 switch (chip_id) {
1653 case '1':
1654 state->ident = V4L2_IDENT_SAA7111;
1655 if (saa711x_read(sd, R_00_CHIP_VERSION) & 0xf0) {
1656 v4l_info(client, "saa7111a variant found\n");
1657 state->ident = V4L2_IDENT_SAA7111A;
1658 }
1659 break;
1660 case '3':
1661 state->ident = V4L2_IDENT_SAA7113;
1662 break;
1663 case '4':
1664 state->ident = V4L2_IDENT_SAA7114;
1665 break;
1666 case '5':
1667 state->ident = V4L2_IDENT_SAA7115;
1668 break;
1669 case '8':
1670 state->ident = V4L2_IDENT_SAA7118;
1671 break;
1672 default:
1673 state->ident = V4L2_IDENT_SAA7111;
1674 v4l2_info(sd, "WARNING: Chip is not known - Falling back to saa7111\n");
1675 break;
1676 }
1677
1678 state->audclk_freq = 48000;
1679
1680 v4l2_dbg(1, debug, sd, "writing init values\n");
1681
1682 /* init to 60hz/48khz */
1683 state->crystal_freq = SAA7115_FREQ_24_576_MHZ;
1684 switch (state->ident) {
1685 case V4L2_IDENT_SAA7111:
1686 case V4L2_IDENT_SAA7111A:
1687 saa711x_writeregs(sd, saa7111_init);
1688 break;
1689 case V4L2_IDENT_SAA7113:
1690 saa711x_writeregs(sd, saa7113_init);
1691 break;
1692 default:
1693 state->crystal_freq = SAA7115_FREQ_32_11_MHZ;
1694 saa711x_writeregs(sd, saa7115_init_auto_input);
1695 }
1696 if (state->ident > V4L2_IDENT_SAA7111A)
1697 saa711x_writeregs(sd, saa7115_init_misc);
1698 saa711x_set_v4lstd(sd, V4L2_STD_NTSC);
1699 v4l2_ctrl_handler_setup(hdl);
1700
1701 v4l2_dbg(1, debug, sd, "status: (1E) 0x%02x, (1F) 0x%02x\n",
1702 saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC),
1703 saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC));
1704 return 0;
1705 }
1706
1707 /* ----------------------------------------------------------------------- */
1708
1709 static int saa711x_remove(struct i2c_client *client)
1710 {
1711 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1712
1713 v4l2_device_unregister_subdev(sd);
1714 v4l2_ctrl_handler_free(sd->ctrl_handler);
1715 kfree(to_state(sd));
1716 return 0;
1717 }
1718
1719 static const struct i2c_device_id saa711x_id[] = {
1720 { "saa7115_auto", 1 }, /* autodetect */
1721 { "saa7111", 0 },
1722 { "saa7113", 0 },
1723 { "saa7114", 0 },
1724 { "saa7115", 0 },
1725 { "saa7118", 0 },
1726 { }
1727 };
1728 MODULE_DEVICE_TABLE(i2c, saa711x_id);
1729
1730 static struct i2c_driver saa711x_driver = {
1731 .driver = {
1732 .owner = THIS_MODULE,
1733 .name = "saa7115",
1734 },
1735 .probe = saa711x_probe,
1736 .remove = saa711x_remove,
1737 .id_table = saa711x_id,
1738 };
1739
1740 module_i2c_driver(saa711x_driver);
Linux with added FPC-III support