drivers/media/pci/cx18/cx18-av-firmware.c

   1 /*
   2  *  cx18 ADEC firmware functions
   3  *
   4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   5  *  Copyright (C) 2008  Andy Walls <awalls@md.metrocast.net>
   6  *
   7  *  This program is free software; you can redistribute it and/or
   8  *  modify it under the terms of the GNU General Public License
   9  *  as published by the Free Software Foundation; either version 2
  10  *  of the License, or (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  *  02110-1301, USA.
  21  */
  22
  23 #include "cx18-driver.h"
  24 #include "cx18-io.h"
  25 #include <linux/firmware.h>
  26
  27 #define CX18_AUDIO_ENABLE    0xc72014
  28 #define CX18_AI1_MUX_MASK    0x30
  29 #define CX18_AI1_MUX_I2S1    0x00
  30 #define CX18_AI1_MUX_I2S2    0x10
  31 #define CX18_AI1_MUX_843_I2S 0x20
  32 #define CX18_AI1_MUX_INVALID 0x30
  33
  34 #define FWFILE "v4l-cx23418-dig.fw"
  35
  36 static int cx18_av_verifyfw(struct cx18 *cx, const struct firmware *fw)
  37 {
  38         struct v4l2_subdev *sd = &cx->av_state.sd;
  39         int ret = 0;
  40         const u8 *data;
  41         u32 size;
  42         int addr;
  43         u32 expected, dl_control;
  44
  45         /* Ensure we put the 8051 in reset and enable firmware upload mode */
  46         dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
  47         do {
  48                 dl_control &= 0x00ffffff;
  49                 dl_control |= 0x0f000000;
  50                 cx18_av_write4_noretry(cx, CXADEC_DL_CTL, dl_control);
  51                 dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
  52         } while ((dl_control & 0xff000000) != 0x0f000000);
  53
  54         /* Read and auto increment until at address 0x0000 */
  55         while (dl_control & 0x3fff)
  56                 dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
  57
  58         data = fw->data;
  59         size = fw->size;
  60         for (addr = 0; addr < size; addr++) {
  61                 dl_control &= 0xffff3fff; /* ignore top 2 bits of address */
  62                 expected = 0x0f000000 | ((u32)data[addr] << 16) | addr;
  63                 if (expected != dl_control) {
  64                         CX18_ERR_DEV(sd, "verification of %s firmware load "
  65                                      "failed: expected %#010x got %#010x\n",
  66                                      FWFILE, expected, dl_control);
  67                         ret = -EIO;
  68                         break;
  69                 }
  70                 dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
  71         }
  72         if (ret == 0)
  73                 CX18_INFO_DEV(sd, "verified load of %s firmware (%d bytes)\n",
  74                               FWFILE, size);
  75         return ret;
  76 }
  77
  78 int cx18_av_loadfw(struct cx18 *cx)
  79 {
  80         struct v4l2_subdev *sd = &cx->av_state.sd;
  81         const struct firmware *fw = NULL;
  82         u32 size;
  83         u32 u, v;
  84         const u8 *ptr;
  85         int i;
  86         int retries1 = 0;
  87
  88         if (request_firmware(&fw, FWFILE, &cx->pci_dev->dev) != 0) {
  89                 CX18_ERR_DEV(sd, "unable to open firmware %s\n", FWFILE);
  90                 return -EINVAL;
  91         }
  92
  93         /* The firmware load often has byte errors, so allow for several
  94            retries, both at byte level and at the firmware load level. */
  95         while (retries1 < 5) {
  96                 cx18_av_write4_expect(cx, CXADEC_CHIP_CTRL, 0x00010000,
  97                                           0x00008430, 0xffffffff); /* cx25843 */
  98                 cx18_av_write_expect(cx, CXADEC_STD_DET_CTL, 0xf6, 0xf6, 0xff);
  99
 100                 /* Reset the Mako core, Register is alias of CXADEC_CHIP_CTRL */
 101                 cx18_av_write4_expect(cx, 0x8100, 0x00010000,
 102                                           0x00008430, 0xffffffff); /* cx25843 */
 103
 104                 /* Put the 8051 in reset and enable firmware upload */
 105                 cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000);
 106
 107                 ptr = fw->data;
 108                 size = fw->size;
 109
 110                 for (i = 0; i < size; i++) {
 111                         u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16);
 112                         u32 value = 0;
 113                         int retries2;
 114                         int unrec_err = 0;
 115
 116                         for (retries2 = 0; retries2 < CX18_MAX_MMIO_WR_RETRIES;
 117                              retries2++) {
 118                                 cx18_av_write4_noretry(cx, CXADEC_DL_CTL,
 119                                                        dl_control);
 120                                 udelay(10);
 121                                 value = cx18_av_read4(cx, CXADEC_DL_CTL);
 122                                 if (value == dl_control)
 123                                         break;
 124                                 /* Check if we can correct the byte by changing
 125                                    the address.  We can only write the lower
 126                                    address byte of the address. */
 127                                 if ((value & 0x3F00) != (dl_control & 0x3F00)) {
 128                                         unrec_err = 1;
 129                                         break;
 130                                 }
 131                         }
 132                         if (unrec_err || retries2 >= CX18_MAX_MMIO_WR_RETRIES)
 133                                 break;
 134                 }
 135                 if (i == size)
 136                         break;
 137                 retries1++;
 138         }
 139         if (retries1 >= 5) {
 140                 CX18_ERR_DEV(sd, "unable to load firmware %s\n", FWFILE);
 141                 release_firmware(fw);
 142                 return -EIO;
 143         }
 144
 145         cx18_av_write4_expect(cx, CXADEC_DL_CTL,
 146                                 0x03000000 | fw->size, 0x03000000, 0x13000000);
 147
 148         CX18_INFO_DEV(sd, "loaded %s firmware (%d bytes)\n", FWFILE, size);
 149
 150         if (cx18_av_verifyfw(cx, fw) == 0)
 151                 cx18_av_write4_expect(cx, CXADEC_DL_CTL,
 152                                 0x13000000 | fw->size, 0x13000000, 0x13000000);
 153
 154         /* Output to the 416 */
 155         cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x78000);
 156
 157         /* Audio input control 1 set to Sony mode */
 158         /* Audio output input 2 is 0 for slave operation input */
 159         /* 0xC4000914[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
 160         /* 0xC4000914[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
 161            after WS transition for first bit of audio word. */
 162         cx18_av_write4(cx, CXADEC_I2S_IN_CTL, 0x000000A0);
 163
 164         /* Audio output control 1 is set to Sony mode */
 165         /* Audio output control 2 is set to 1 for master mode */
 166         /* 0xC4000918[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
 167         /* 0xC4000918[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
 168            after WS transition for first bit of audio word. */
 169         /* 0xC4000918[8]: 0 = slave operation, 1 = master (SCK_OUT and WS_OUT
 170            are generated) */
 171         cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0);
 172
 173         /* set alt I2s master clock to /0x16 and enable alt divider i2s
 174            passthrough */
 175         cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5600B687);
 176
 177         cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6,
 178                                                                   0x3F00FFFF);
 179         /* CxDevWrReg(CXADEC_STD_DET_CTL, 0x000000FF); */
 180
 181         /* Set bit 0 in register 0x9CC to signify that this is MiniMe. */
 182         /* Register 0x09CC is defined by the Merlin firmware, and doesn't
 183            have a name in the spec. */
 184         cx18_av_write4(cx, 0x09CC, 1);
 185
 186         v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
 187         /* If bit 11 is 1, clear bit 10 */
 188         if (v & 0x800)
 189                 cx18_write_reg_expect(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE,
 190                                       0, 0x400);
 191
 192         /* Toggle the AI1 MUX */
 193         v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
 194         u = v & CX18_AI1_MUX_MASK;
 195         v &= ~CX18_AI1_MUX_MASK;
 196         if (u == CX18_AI1_MUX_843_I2S || u == CX18_AI1_MUX_INVALID) {
 197                 /* Switch to I2S1 */
 198                 v |= CX18_AI1_MUX_I2S1;
 199                 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
 200                                       v, CX18_AI1_MUX_MASK);
 201                 /* Switch back to the A/V decoder core I2S output */
 202                 v = (v & ~CX18_AI1_MUX_MASK) | CX18_AI1_MUX_843_I2S;
 203         } else {
 204                 /* Switch to the A/V decoder core I2S output */
 205                 v |= CX18_AI1_MUX_843_I2S;
 206                 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
 207                                       v, CX18_AI1_MUX_MASK);
 208                 /* Switch back to I2S1 or I2S2 */
 209                 v = (v & ~CX18_AI1_MUX_MASK) | u;
 210         }
 211         cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
 212                               v, CX18_AI1_MUX_MASK);
 213
 214         /* Enable WW auto audio standard detection */
 215         v = cx18_av_read4(cx, CXADEC_STD_DET_CTL);
 216         v |= 0xFF;   /* Auto by default */
 217         v |= 0x400;  /* Stereo by default */
 218         v |= 0x14000000;
 219         cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, v, v, 0x3F00FFFF);
 220
 221         release_firmware(fw);
 222         return 0;
 223 }
 224
 225 MODULE_FIRMWARE(FWFILE);