drivers/media/pci/cx23885/cimax2.c

   1 /*
   2  * cimax2.c
   3  *
   4  * CIMax2(R) SP2 driver in conjunction with NetUp Dual DVB-S2 CI card
   5  *
   6  * Copyright (C) 2009 NetUP Inc.
   7  * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
   8  * Copyright (C) 2009 Abylay Ospan <aospan@netup.ru>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include "cx23885.h"
  27 #include "cimax2.h"
  28 #include "dvb_ca_en50221.h"
  29 /**** Bit definitions for MC417_RWD and MC417_OEN registers  ***
  30   bits 31-16
  31 +-----------+
  32 | Reserved  |
  33 +-----------+
  34   bit 15  bit 14  bit 13 bit 12  bit 11  bit 10  bit 9   bit 8
  35 +-------+-------+-------+-------+-------+-------+-------+-------+
  36 |  WR#  |  RD#  |       |  ACK# |  ADHI |  ADLO |  CS1# |  CS0# |
  37 +-------+-------+-------+-------+-------+-------+-------+-------+
  38  bit 7   bit 6   bit 5   bit 4   bit 3   bit 2   bit 1   bit 0
  39 +-------+-------+-------+-------+-------+-------+-------+-------+
  40 |  DATA7|  DATA6|  DATA5|  DATA4|  DATA3|  DATA2|  DATA1|  DATA0|
  41 +-------+-------+-------+-------+-------+-------+-------+-------+
  42 ***/
  43 /* MC417 */
  44 #define NETUP_DATA              0x000000ff
  45 #define NETUP_WR                0x00008000
  46 #define NETUP_RD                0x00004000
  47 #define NETUP_ACK               0x00001000
  48 #define NETUP_ADHI              0x00000800
  49 #define NETUP_ADLO              0x00000400
  50 #define NETUP_CS1               0x00000200
  51 #define NETUP_CS0               0x00000100
  52 #define NETUP_EN_ALL            0x00001000
  53 #define NETUP_CTRL_OFF          (NETUP_CS1 | NETUP_CS0 | NETUP_WR | NETUP_RD)
  54 #define NETUP_CI_CTL            0x04
  55 #define NETUP_CI_RD             1
  56
  57 #define NETUP_IRQ_DETAM         0x1
  58 #define NETUP_IRQ_IRQAM         0x4
  59
  60 static unsigned int ci_dbg;
  61 module_param(ci_dbg, int, 0644);
  62 MODULE_PARM_DESC(ci_dbg, "Enable CI debugging");
  63
  64 static unsigned int ci_irq_enable;
  65 module_param(ci_irq_enable, int, 0644);
  66 MODULE_PARM_DESC(ci_irq_enable, "Enable IRQ from CAM");
  67
  68 #define ci_dbg_print(args...) \
  69         do { \
  70                 if (ci_dbg) \
  71                         printk(KERN_DEBUG args); \
  72         } while (0)
  73
  74 #define ci_irq_flags() (ci_irq_enable ? NETUP_IRQ_IRQAM : 0)
  75
  76 /* stores all private variables for communication with CI */
  77 struct netup_ci_state {
  78         struct dvb_ca_en50221 ca;
  79         struct mutex ca_mutex;
  80         struct i2c_adapter *i2c_adap;
  81         u8 ci_i2c_addr;
  82         int status;
  83         struct work_struct work;
  84         void *priv;
  85         u8 current_irq_mode;
  86         int current_ci_flag;
  87         unsigned long next_status_checked_time;
  88 };
  89
  90
  91 static int netup_read_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg,
  92                                                 u8 *buf, int len)
  93 {
  94         int ret;
  95         struct i2c_msg msg[] = {
  96                 {
  97                         .addr   = addr,
  98                         .flags  = 0,
  99                         .buf    = &reg,
 100                         .len    = 1
 101                 }, {
 102                         .addr   = addr,
 103                         .flags  = I2C_M_RD,
 104                         .buf    = buf,
 105                         .len    = len
 106                 }
 107         };
 108
 109         ret = i2c_transfer(i2c_adap, msg, 2);
 110
 111         if (ret != 2) {
 112                 ci_dbg_print("%s: i2c read error, Reg = 0x%02x, Status = %d\n",
 113                                                 __func__, reg, ret);
 114
 115                 return -1;
 116         }
 117
 118         ci_dbg_print("%s: i2c read Addr=0x%04x, Reg = 0x%02x, data = %02x\n",
 119                                                 __func__, addr, reg, buf[0]);
 120
 121         return 0;
 122 }
 123
 124 static int netup_write_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg,
 125                                                 u8 *buf, int len)
 126 {
 127         int ret;
 128         u8 buffer[len + 1];
 129
 130         struct i2c_msg msg = {
 131                 .addr   = addr,
 132                 .flags  = 0,
 133                 .buf    = &buffer[0],
 134                 .len    = len + 1
 135         };
 136
 137         buffer[0] = reg;
 138         memcpy(&buffer[1], buf, len);
 139
 140         ret = i2c_transfer(i2c_adap, &msg, 1);
 141
 142         if (ret != 1) {
 143                 ci_dbg_print("%s: i2c write error, Reg=[0x%02x], Status=%d\n",
 144                                                 __func__, reg, ret);
 145                 return -1;
 146         }
 147
 148         return 0;
 149 }
 150
 151 static int netup_ci_get_mem(struct cx23885_dev *dev)
 152 {
 153         int mem;
 154         unsigned long timeout = jiffies + msecs_to_jiffies(1);
 155
 156         for (;;) {
 157                 mem = cx_read(MC417_RWD);
 158                 if ((mem & NETUP_ACK) == 0)
 159                         break;
 160                 if (time_after(jiffies, timeout))
 161                         break;
 162                 udelay(1);
 163         }
 164
 165         cx_set(MC417_RWD, NETUP_CTRL_OFF);
 166
 167         return mem & 0xff;
 168 }
 169
 170 static int netup_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot,
 171                                 u8 flag, u8 read, int addr, u8 data)
 172 {
 173         struct netup_ci_state *state = en50221->data;
 174         struct cx23885_tsport *port = state->priv;
 175         struct cx23885_dev *dev = port->dev;
 176
 177         u8 store;
 178         int mem;
 179         int ret;
 180
 181         if (0 != slot)
 182                 return -EINVAL;
 183
 184         if (state->current_ci_flag != flag) {
 185                 ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
 186                                 0, &store, 1);
 187                 if (ret != 0)
 188                         return ret;
 189
 190                 store &= ~0x0c;
 191                 store |= flag;
 192
 193                 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
 194                                 0, &store, 1);
 195                 if (ret != 0)
 196                         return ret;
 197         }
 198         state->current_ci_flag = flag;
 199
 200         mutex_lock(&dev->gpio_lock);
 201
 202         /* write addr */
 203         cx_write(MC417_OEN, NETUP_EN_ALL);
 204         cx_write(MC417_RWD, NETUP_CTRL_OFF |
 205                                 NETUP_ADLO | (0xff & addr));
 206         cx_clear(MC417_RWD, NETUP_ADLO);
 207         cx_write(MC417_RWD, NETUP_CTRL_OFF |
 208                                 NETUP_ADHI | (0xff & (addr >> 8)));
 209         cx_clear(MC417_RWD, NETUP_ADHI);
 210
 211         if (read) { /* data in */
 212                 cx_write(MC417_OEN, NETUP_EN_ALL | NETUP_DATA);
 213         } else /* data out */
 214                 cx_write(MC417_RWD, NETUP_CTRL_OFF | data);
 215
 216         /* choose chip */
 217         cx_clear(MC417_RWD,
 218                         (state->ci_i2c_addr == 0x40) ? NETUP_CS0 : NETUP_CS1);
 219         /* read/write */
 220         cx_clear(MC417_RWD, (read) ? NETUP_RD : NETUP_WR);
 221         mem = netup_ci_get_mem(dev);
 222
 223         mutex_unlock(&dev->gpio_lock);
 224
 225         if (!read)
 226                 if (mem < 0)
 227                         return -EREMOTEIO;
 228
 229         ci_dbg_print("%s: %s: chipaddr=[0x%x] addr=[0x%02x], %s=%x\n", __func__,
 230                         (read) ? "read" : "write", state->ci_i2c_addr, addr,
 231                         (flag == NETUP_CI_CTL) ? "ctl" : "mem",
 232                         (read) ? mem : data);
 233
 234         if (read)
 235                 return mem;
 236
 237         return 0;
 238 }
 239
 240 int netup_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221,
 241                                                 int slot, int addr)
 242 {
 243         return netup_ci_op_cam(en50221, slot, 0, NETUP_CI_RD, addr, 0);
 244 }
 245
 246 int netup_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221,
 247                                                 int slot, int addr, u8 data)
 248 {
 249         return netup_ci_op_cam(en50221, slot, 0, 0, addr, data);
 250 }
 251
 252 int netup_ci_read_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
 253                                  u8 addr)
 254 {
 255         return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL,
 256                                                         NETUP_CI_RD, addr, 0);
 257 }
 258
 259 int netup_ci_write_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
 260                                                         u8 addr, u8 data)
 261 {
 262         return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL, 0, addr, data);
 263 }
 264
 265 int netup_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot)
 266 {
 267         struct netup_ci_state *state = en50221->data;
 268         u8 buf =  0x80;
 269         int ret;
 270
 271         if (0 != slot)
 272                 return -EINVAL;
 273
 274         udelay(500);
 275         ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
 276                                                         0, &buf, 1);
 277
 278         if (ret != 0)
 279                 return ret;
 280
 281         udelay(500);
 282
 283         buf = 0x00;
 284         ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
 285                                                         0, &buf, 1);
 286
 287         msleep(1000);
 288         dvb_ca_en50221_camready_irq(&state->ca, 0);
 289
 290         return 0;
 291
 292 }
 293
 294 int netup_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot)
 295 {
 296         /* not implemented */
 297         return 0;
 298 }
 299
 300 static int netup_ci_set_irq(struct dvb_ca_en50221 *en50221, u8 irq_mode)
 301 {
 302         struct netup_ci_state *state = en50221->data;
 303         int ret;
 304
 305         if (irq_mode == state->current_irq_mode)
 306                 return 0;
 307
 308         ci_dbg_print("%s: chipaddr=[0x%x] setting ci IRQ to [0x%x] \n",
 309                         __func__, state->ci_i2c_addr, irq_mode);
 310         ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
 311                                                         0x1b, &irq_mode, 1);
 312
 313         if (ret != 0)
 314                 return ret;
 315
 316         state->current_irq_mode = irq_mode;
 317
 318         return 0;
 319 }
 320
 321 int netup_ci_slot_ts_ctl(struct dvb_ca_en50221 *en50221, int slot)
 322 {
 323         struct netup_ci_state *state = en50221->data;
 324         u8 buf;
 325
 326         if (0 != slot)
 327                 return -EINVAL;
 328
 329         netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
 330                         0, &buf, 1);
 331         buf |= 0x60;
 332
 333         return netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
 334                                                         0, &buf, 1);
 335 }
 336
 337 /* work handler */
 338 static void netup_read_ci_status(struct work_struct *work)
 339 {
 340         struct netup_ci_state *state =
 341                         container_of(work, struct netup_ci_state, work);
 342         u8 buf[33];
 343         int ret;
 344
 345         /* CAM module IRQ processing. fast operation */
 346         dvb_ca_en50221_frda_irq(&state->ca, 0);
 347
 348         /* CAM module INSERT/REMOVE processing. slow operation because of i2c
 349          * transfers */
 350         if (time_after(jiffies, state->next_status_checked_time)
 351                         || !state->status) {
 352                 ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
 353                                 0, &buf[0], 33);
 354
 355                 state->next_status_checked_time = jiffies
 356                         + msecs_to_jiffies(1000);
 357
 358                 if (ret != 0)
 359                         return;
 360
 361                 ci_dbg_print("%s: Slot Status Addr=[0x%04x], "
 362                                 "Reg=[0x%02x], data=%02x, "
 363                                 "TS config = %02x\n", __func__,
 364                                 state->ci_i2c_addr, 0, buf[0],
 365                                 buf[0]);
 366
 367
 368                 if (buf[0] & 1)
 369                         state->status = DVB_CA_EN50221_POLL_CAM_PRESENT |
 370                                 DVB_CA_EN50221_POLL_CAM_READY;
 371                 else
 372                         state->status = 0;
 373         }
 374 }
 375
 376 /* CI irq handler */
 377 int netup_ci_slot_status(struct cx23885_dev *dev, u32 pci_status)
 378 {
 379         struct cx23885_tsport *port = NULL;
 380         struct netup_ci_state *state = NULL;
 381
 382         ci_dbg_print("%s:\n", __func__);
 383
 384         if (0 == (pci_status & (PCI_MSK_GPIO0 | PCI_MSK_GPIO1)))
 385                 return 0;
 386
 387         if (pci_status & PCI_MSK_GPIO0) {
 388                 port = &dev->ts1;
 389                 state = port->port_priv;
 390                 schedule_work(&state->work);
 391                 ci_dbg_print("%s: Wakeup CI0\n", __func__);
 392         }
 393
 394         if (pci_status & PCI_MSK_GPIO1) {
 395                 port = &dev->ts2;
 396                 state = port->port_priv;
 397                 schedule_work(&state->work);
 398                 ci_dbg_print("%s: Wakeup CI1\n", __func__);
 399         }
 400
 401         return 1;
 402 }
 403
 404 int netup_poll_ci_slot_status(struct dvb_ca_en50221 *en50221,
 405                                      int slot, int open)
 406 {
 407         struct netup_ci_state *state = en50221->data;
 408
 409         if (0 != slot)
 410                 return -EINVAL;
 411
 412         netup_ci_set_irq(en50221, open ? (NETUP_IRQ_DETAM | ci_irq_flags())
 413                         : NETUP_IRQ_DETAM);
 414
 415         return state->status;
 416 }
 417
 418 int netup_ci_init(struct cx23885_tsport *port)
 419 {
 420         struct netup_ci_state *state;
 421         u8 cimax_init[34] = {
 422                 0x00, /* module A control*/
 423                 0x00, /* auto select mask high A */
 424                 0x00, /* auto select mask low A */
 425                 0x00, /* auto select pattern high A */
 426                 0x00, /* auto select pattern low A */
 427                 0x44, /* memory access time A */
 428                 0x00, /* invert input A */
 429                 0x00, /* RFU */
 430                 0x00, /* RFU */
 431                 0x00, /* module B control*/
 432                 0x00, /* auto select mask high B */
 433                 0x00, /* auto select mask low B */
 434                 0x00, /* auto select pattern high B */
 435                 0x00, /* auto select pattern low B */
 436                 0x44, /* memory access time B */
 437                 0x00, /* invert input B */
 438                 0x00, /* RFU */
 439                 0x00, /* RFU */
 440                 0x00, /* auto select mask high Ext */
 441                 0x00, /* auto select mask low Ext */
 442                 0x00, /* auto select pattern high Ext */
 443                 0x00, /* auto select pattern low Ext */
 444                 0x00, /* RFU */
 445                 0x02, /* destination - module A */
 446                 0x01, /* power on (use it like store place) */
 447                 0x00, /* RFU */
 448                 0x00, /* int status read only */
 449                 ci_irq_flags() | NETUP_IRQ_DETAM, /* DETAM, IRQAM unmasked */
 450                 0x05, /* EXTINT=active-high, INT=push-pull */
 451                 0x00, /* USCG1 */
 452                 0x04, /* ack active low */
 453                 0x00, /* LOCK = 0 */
 454                 0x33, /* serial mode, rising in, rising out, MSB first*/
 455                 0x31, /* synchronization */
 456         };
 457         int ret;
 458
 459         ci_dbg_print("%s\n", __func__);
 460         state = kzalloc(sizeof(struct netup_ci_state), GFP_KERNEL);
 461         if (!state) {
 462                 ci_dbg_print("%s: Unable create CI structure!\n", __func__);
 463                 ret = -ENOMEM;
 464                 goto err;
 465         }
 466
 467         port->port_priv = state;
 468
 469         switch (port->nr) {
 470         case 1:
 471                 state->ci_i2c_addr = 0x40;
 472                 break;
 473         case 2:
 474                 state->ci_i2c_addr = 0x41;
 475                 break;
 476         }
 477
 478         state->i2c_adap = &port->dev->i2c_bus[0].i2c_adap;
 479         state->ca.owner = THIS_MODULE;
 480         state->ca.read_attribute_mem = netup_ci_read_attribute_mem;
 481         state->ca.write_attribute_mem = netup_ci_write_attribute_mem;
 482         state->ca.read_cam_control = netup_ci_read_cam_ctl;
 483         state->ca.write_cam_control = netup_ci_write_cam_ctl;
 484         state->ca.slot_reset = netup_ci_slot_reset;
 485         state->ca.slot_shutdown = netup_ci_slot_shutdown;
 486         state->ca.slot_ts_enable = netup_ci_slot_ts_ctl;
 487         state->ca.poll_slot_status = netup_poll_ci_slot_status;
 488         state->ca.data = state;
 489         state->priv = port;
 490         state->current_irq_mode = ci_irq_flags() | NETUP_IRQ_DETAM;
 491
 492         ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
 493                                                 0, &cimax_init[0], 34);
 494         /* lock registers */
 495         ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
 496                                                 0x1f, &cimax_init[0x18], 1);
 497         /* power on slots */
 498         ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
 499                                                 0x18, &cimax_init[0x18], 1);
 500
 501         if (0 != ret)
 502                 goto err;
 503
 504         ret = dvb_ca_en50221_init(&port->frontends.adapter,
 505                                    &state->ca,
 506                                    /* flags */ 0,
 507                                    /* n_slots */ 1);
 508         if (0 != ret)
 509                 goto err;
 510
 511         INIT_WORK(&state->work, netup_read_ci_status);
 512         schedule_work(&state->work);
 513
 514         ci_dbg_print("%s: CI initialized!\n", __func__);
 515
 516         return 0;
 517 err:
 518         ci_dbg_print("%s: Cannot initialize CI: Error %d.\n", __func__, ret);
 519         kfree(state);
 520         return ret;
 521 }
 522
 523 void netup_ci_exit(struct cx23885_tsport *port)
 524 {
 525         struct netup_ci_state *state;
 526
 527         if (NULL == port)
 528                 return;
 529
 530         state = (struct netup_ci_state *)port->port_priv;
 531         if (NULL == state)
 532                 return;
 533
 534         if (NULL == state->ca.data)
 535                 return;
 536
 537         dvb_ca_en50221_release(&state->ca);
 538         kfree(state);
 539 }