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rt2800: initialize BBP_R104 on proper subroutines
[linux/fpc-iii.git] / drivers / media / platform / soc_camera / mx3_camera.c
blob5da337736cd894548a5f281963af0c8c0a5fd193
1 /*
2 * V4L2 Driver for i.MX3x camera host
3 *
4 * Copyright (C) 2008
5 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/videodev2.h>
15 #include <linux/platform_device.h>
16 #include <linux/clk.h>
17 #include <linux/vmalloc.h>
18 #include <linux/interrupt.h>
19 #include <linux/sched.h>
20 #include <linux/dma/ipu-dma.h>
21
22 #include <media/v4l2-common.h>
23 #include <media/v4l2-dev.h>
24 #include <media/videobuf2-dma-contig.h>
25 #include <media/soc_camera.h>
26 #include <media/soc_mediabus.h>
27
28 #include <linux/platform_data/camera-mx3.h>
29 #include <linux/platform_data/dma-imx.h>
30
31 #define MX3_CAM_DRV_NAME "mx3-camera"
32
33 /* CMOS Sensor Interface Registers */
34 #define CSI_REG_START 0x60
35
36 #define CSI_SENS_CONF (0x60 - CSI_REG_START)
37 #define CSI_SENS_FRM_SIZE (0x64 - CSI_REG_START)
38 #define CSI_ACT_FRM_SIZE (0x68 - CSI_REG_START)
39 #define CSI_OUT_FRM_CTRL (0x6C - CSI_REG_START)
40 #define CSI_TST_CTRL (0x70 - CSI_REG_START)
41 #define CSI_CCIR_CODE_1 (0x74 - CSI_REG_START)
42 #define CSI_CCIR_CODE_2 (0x78 - CSI_REG_START)
43 #define CSI_CCIR_CODE_3 (0x7C - CSI_REG_START)
44 #define CSI_FLASH_STROBE_1 (0x80 - CSI_REG_START)
45 #define CSI_FLASH_STROBE_2 (0x84 - CSI_REG_START)
46
47 #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
48 #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
49 #define CSI_SENS_CONF_DATA_POL_SHIFT 2
50 #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
51 #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
52 #define CSI_SENS_CONF_SENS_CLKSRC_SHIFT 7
53 #define CSI_SENS_CONF_DATA_FMT_SHIFT 8
54 #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 10
55 #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
56 #define CSI_SENS_CONF_DIVRATIO_SHIFT 16
57
58 #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 (0UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
59 #define CSI_SENS_CONF_DATA_FMT_YUV422 (2UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
60 #define CSI_SENS_CONF_DATA_FMT_BAYER (3UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
61
62 #define MAX_VIDEO_MEM 16
63
64 struct mx3_camera_buffer {
65 /* common v4l buffer stuff -- must be first */
66 struct vb2_buffer vb;
67 struct list_head queue;
68
69 /* One descriptot per scatterlist (per frame) */
70 struct dma_async_tx_descriptor *txd;
71
72 /* We have to "build" a scatterlist ourselves - one element per frame */
73 struct scatterlist sg;
74 };
75
76 /**
77 * struct mx3_camera_dev - i.MX3x camera (CSI) object
78 * @dev: camera device, to which the coherent buffer is attached
79 * @icd: currently attached camera sensor
80 * @clk: pointer to clock
81 * @base: remapped register base address
82 * @pdata: platform data
83 * @platform_flags: platform flags
84 * @mclk: master clock frequency in Hz
85 * @capture: list of capture videobuffers
86 * @lock: protects video buffer lists
87 * @active: active video buffer
88 * @idmac_channel: array of pointers to IPU DMAC DMA channels
89 * @soc_host: embedded soc_host object
90 */
91 struct mx3_camera_dev {
92 /*
93 * i.MX3x is only supposed to handle one camera on its Camera Sensor
94 * Interface. If anyone ever builds hardware to enable more than one
95 * camera _simultaneously_, they will have to modify this driver too
96 */
97 struct soc_camera_device *icd;
98 struct clk *clk;
99
100 void __iomem *base;
101
102 struct mx3_camera_pdata *pdata;
103
104 unsigned long platform_flags;
105 unsigned long mclk;
106 u16 width_flags; /* max 15 bits */
107
108 struct list_head capture;
109 spinlock_t lock; /* Protects video buffer lists */
110 struct mx3_camera_buffer *active;
111 size_t buf_total;
112 struct vb2_alloc_ctx *alloc_ctx;
113 enum v4l2_field field;
114 int sequence;
115
116 /* IDMAC / dmaengine interface */
117 struct idmac_channel *idmac_channel[1]; /* We need one channel */
118
119 struct soc_camera_host soc_host;
120 };
121
122 struct dma_chan_request {
123 struct mx3_camera_dev *mx3_cam;
124 enum ipu_channel id;
125 };
126
127 static u32 csi_reg_read(struct mx3_camera_dev *mx3, off_t reg)
128 {
129 return __raw_readl(mx3->base + reg);
130 }
131
132 static void csi_reg_write(struct mx3_camera_dev *mx3, u32 value, off_t reg)
133 {
134 __raw_writel(value, mx3->base + reg);
135 }
136
137 static struct mx3_camera_buffer *to_mx3_vb(struct vb2_buffer *vb)
138 {
139 return container_of(vb, struct mx3_camera_buffer, vb);
140 }
141
142 /* Called from the IPU IDMAC ISR */
143 static void mx3_cam_dma_done(void *arg)
144 {
145 struct idmac_tx_desc *desc = to_tx_desc(arg);
146 struct dma_chan *chan = desc->txd.chan;
147 struct idmac_channel *ichannel = to_idmac_chan(chan);
148 struct mx3_camera_dev *mx3_cam = ichannel->client;
149
150 dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n",
151 desc->txd.cookie, mx3_cam->active ? sg_dma_address(&mx3_cam->active->sg) : 0);
152
153 spin_lock(&mx3_cam->lock);
154 if (mx3_cam->active) {
155 struct vb2_buffer *vb = &mx3_cam->active->vb;
156 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
157
158 list_del_init(&buf->queue);
159 v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
160 vb->v4l2_buf.field = mx3_cam->field;
161 vb->v4l2_buf.sequence = mx3_cam->sequence++;
162 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
163 }
164
165 if (list_empty(&mx3_cam->capture)) {
166 mx3_cam->active = NULL;
167 spin_unlock(&mx3_cam->lock);
168
169 /*
170 * stop capture - without further buffers IPU_CHA_BUF0_RDY will
171 * not get updated
172 */
173 return;
174 }
175
176 mx3_cam->active = list_entry(mx3_cam->capture.next,
177 struct mx3_camera_buffer, queue);
178 spin_unlock(&mx3_cam->lock);
179 }
180
181 /*
182 * Videobuf operations
183 */
184
185 /*
186 * Calculate the __buffer__ (not data) size and number of buffers.
187 */
188 static int mx3_videobuf_setup(struct vb2_queue *vq,
189 const struct v4l2_format *fmt,
190 unsigned int *count, unsigned int *num_planes,
191 unsigned int sizes[], void *alloc_ctxs[])
192 {
193 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
194 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
195 struct mx3_camera_dev *mx3_cam = ici->priv;
196
197 if (!mx3_cam->idmac_channel[0])
198 return -EINVAL;
199
200 if (fmt) {
201 const struct soc_camera_format_xlate *xlate = soc_camera_xlate_by_fourcc(icd,
202 fmt->fmt.pix.pixelformat);
203 unsigned int bytes_per_line;
204 int ret;
205
206 if (!xlate)
207 return -EINVAL;
208
209 ret = soc_mbus_bytes_per_line(fmt->fmt.pix.width,
210 xlate->host_fmt);
211 if (ret < 0)
212 return ret;
213
214 bytes_per_line = max_t(u32, fmt->fmt.pix.bytesperline, ret);
215
216 ret = soc_mbus_image_size(xlate->host_fmt, bytes_per_line,
217 fmt->fmt.pix.height);
218 if (ret < 0)
219 return ret;
220
221 sizes[0] = max_t(u32, fmt->fmt.pix.sizeimage, ret);
222 } else {
223 /* Called from VIDIOC_REQBUFS or in compatibility mode */
224 sizes[0] = icd->sizeimage;
225 }
226
227 alloc_ctxs[0] = mx3_cam->alloc_ctx;
228
229 if (!vq->num_buffers)
230 mx3_cam->sequence = 0;
231
232 if (!*count)
233 *count = 2;
234
235 /* If *num_planes != 0, we have already verified *count. */
236 if (!*num_planes &&
237 sizes[0] * *count + mx3_cam->buf_total > MAX_VIDEO_MEM * 1024 * 1024)
238 *count = (MAX_VIDEO_MEM * 1024 * 1024 - mx3_cam->buf_total) /
239 sizes[0];
240
241 *num_planes = 1;
242
243 return 0;
244 }
245
246 static enum pixel_fmt fourcc_to_ipu_pix(__u32 fourcc)
247 {
248 /* Add more formats as need arises and test possibilities appear... */
249 switch (fourcc) {
250 case V4L2_PIX_FMT_RGB24:
251 return IPU_PIX_FMT_RGB24;
252 case V4L2_PIX_FMT_UYVY:
253 case V4L2_PIX_FMT_RGB565:
254 default:
255 return IPU_PIX_FMT_GENERIC;
256 }
257 }
258
259 static void mx3_videobuf_queue(struct vb2_buffer *vb)
260 {
261 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
262 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
263 struct mx3_camera_dev *mx3_cam = ici->priv;
264 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
265 struct scatterlist *sg = &buf->sg;
266 struct dma_async_tx_descriptor *txd;
267 struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
268 struct idmac_video_param *video = &ichan->params.video;
269 const struct soc_mbus_pixelfmt *host_fmt = icd->current_fmt->host_fmt;
270 unsigned long flags;
271 dma_cookie_t cookie;
272 size_t new_size;
273
274 new_size = icd->sizeimage;
275
276 if (vb2_plane_size(vb, 0) < new_size) {
277 dev_err(icd->parent, "Buffer #%d too small (%lu < %zu)\n",
278 vb->v4l2_buf.index, vb2_plane_size(vb, 0), new_size);
279 goto error;
280 }
281
282 if (!buf->txd) {
283 sg_dma_address(sg) = vb2_dma_contig_plane_dma_addr(vb, 0);
284 sg_dma_len(sg) = new_size;
285
286 txd = dmaengine_prep_slave_sg(
287 &ichan->dma_chan, sg, 1, DMA_DEV_TO_MEM,
288 DMA_PREP_INTERRUPT);
289 if (!txd)
290 goto error;
291
292 txd->callback_param = txd;
293 txd->callback = mx3_cam_dma_done;
294
295 buf->txd = txd;
296 } else {
297 txd = buf->txd;
298 }
299
300 vb2_set_plane_payload(vb, 0, new_size);
301
302 /* This is the configuration of one sg-element */
303 video->out_pixel_fmt = fourcc_to_ipu_pix(host_fmt->fourcc);
304
305 if (video->out_pixel_fmt == IPU_PIX_FMT_GENERIC) {
306 /*
307 * If the IPU DMA channel is configured to transfer generic
308 * 8-bit data, we have to set up the geometry parameters
309 * correctly, according to the current pixel format. The DMA
310 * horizontal parameters in this case are expressed in bytes,
311 * not in pixels.
312 */
313 video->out_width = icd->bytesperline;
314 video->out_height = icd->user_height;
315 video->out_stride = icd->bytesperline;
316 } else {
317 /*
318 * For IPU known formats the pixel unit will be managed
319 * successfully by the IPU code
320 */
321 video->out_width = icd->user_width;
322 video->out_height = icd->user_height;
323 video->out_stride = icd->user_width;
324 }
325
326 #ifdef DEBUG
327 /* helps to see what DMA actually has written */
328 if (vb2_plane_vaddr(vb, 0))
329 memset(vb2_plane_vaddr(vb, 0), 0xaa, vb2_get_plane_payload(vb, 0));
330 #endif
331
332 spin_lock_irqsave(&mx3_cam->lock, flags);
333 list_add_tail(&buf->queue, &mx3_cam->capture);
334
335 if (!mx3_cam->active)
336 mx3_cam->active = buf;
337
338 spin_unlock_irq(&mx3_cam->lock);
339
340 cookie = txd->tx_submit(txd);
341 dev_dbg(icd->parent, "Submitted cookie %d DMA 0x%08x\n",
342 cookie, sg_dma_address(&buf->sg));
343
344 if (cookie >= 0)
345 return;
346
347 spin_lock_irq(&mx3_cam->lock);
348
349 /* Submit error */
350 list_del_init(&buf->queue);
351
352 if (mx3_cam->active == buf)
353 mx3_cam->active = NULL;
354
355 spin_unlock_irqrestore(&mx3_cam->lock, flags);
356 error:
357 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
358 }
359
360 static void mx3_videobuf_release(struct vb2_buffer *vb)
361 {
362 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
363 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
364 struct mx3_camera_dev *mx3_cam = ici->priv;
365 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
366 struct dma_async_tx_descriptor *txd = buf->txd;
367 unsigned long flags;
368
369 dev_dbg(icd->parent,
370 "Release%s DMA 0x%08x, queue %sempty\n",
371 mx3_cam->active == buf ? " active" : "", sg_dma_address(&buf->sg),
372 list_empty(&buf->queue) ? "" : "not ");
373
374 spin_lock_irqsave(&mx3_cam->lock, flags);
375
376 if (mx3_cam->active == buf)
377 mx3_cam->active = NULL;
378
379 /* Doesn't hurt also if the list is empty */
380 list_del_init(&buf->queue);
381
382 if (txd) {
383 buf->txd = NULL;
384 if (mx3_cam->idmac_channel[0])
385 async_tx_ack(txd);
386 }
387
388 spin_unlock_irqrestore(&mx3_cam->lock, flags);
389
390 mx3_cam->buf_total -= vb2_plane_size(vb, 0);
391 }
392
393 static int mx3_videobuf_init(struct vb2_buffer *vb)
394 {
395 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
396 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
397 struct mx3_camera_dev *mx3_cam = ici->priv;
398 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
399
400 if (!buf->txd) {
401 /* This is for locking debugging only */
402 INIT_LIST_HEAD(&buf->queue);
403 sg_init_table(&buf->sg, 1);
404
405 mx3_cam->buf_total += vb2_plane_size(vb, 0);
406 }
407
408 return 0;
409 }
410
411 static int mx3_stop_streaming(struct vb2_queue *q)
412 {
413 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
414 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
415 struct mx3_camera_dev *mx3_cam = ici->priv;
416 struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
417 struct mx3_camera_buffer *buf, *tmp;
418 unsigned long flags;
419
420 if (ichan) {
421 struct dma_chan *chan = &ichan->dma_chan;
422 chan->device->device_control(chan, DMA_PAUSE, 0);
423 }
424
425 spin_lock_irqsave(&mx3_cam->lock, flags);
426
427 mx3_cam->active = NULL;
428
429 list_for_each_entry_safe(buf, tmp, &mx3_cam->capture, queue) {
430 list_del_init(&buf->queue);
431 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
432 }
433
434 spin_unlock_irqrestore(&mx3_cam->lock, flags);
435
436 return 0;
437 }
438
439 static struct vb2_ops mx3_videobuf_ops = {
440 .queue_setup = mx3_videobuf_setup,
441 .buf_queue = mx3_videobuf_queue,
442 .buf_cleanup = mx3_videobuf_release,
443 .buf_init = mx3_videobuf_init,
444 .wait_prepare = soc_camera_unlock,
445 .wait_finish = soc_camera_lock,
446 .stop_streaming = mx3_stop_streaming,
447 };
448
449 static int mx3_camera_init_videobuf(struct vb2_queue *q,
450 struct soc_camera_device *icd)
451 {
452 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
453 q->io_modes = VB2_MMAP | VB2_USERPTR;
454 q->drv_priv = icd;
455 q->ops = &mx3_videobuf_ops;
456 q->mem_ops = &vb2_dma_contig_memops;
457 q->buf_struct_size = sizeof(struct mx3_camera_buffer);
458 q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
459
460 return vb2_queue_init(q);
461 }
462
463 /* First part of ipu_csi_init_interface() */
464 static void mx3_camera_activate(struct mx3_camera_dev *mx3_cam,
465 struct soc_camera_device *icd)
466 {
467 u32 conf;
468 long rate;
469
470 /* Set default size: ipu_csi_set_window_size() */
471 csi_reg_write(mx3_cam, (640 - 1) | ((480 - 1) << 16), CSI_ACT_FRM_SIZE);
472 /* ...and position to 0:0: ipu_csi_set_window_pos() */
473 conf = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000;
474 csi_reg_write(mx3_cam, conf, CSI_OUT_FRM_CTRL);
475
476 /* We use only gated clock synchronisation mode so far */
477 conf = 0 << CSI_SENS_CONF_SENS_PRTCL_SHIFT;
478
479 /* Set generic data, platform-biggest bus-width */
480 conf |= CSI_SENS_CONF_DATA_FMT_BAYER;
481
482 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15)
483 conf |= 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
484 else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10)
485 conf |= 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
486 else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8)
487 conf |= 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
488 else/* if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)*/
489 conf |= 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
490
491 if (mx3_cam->platform_flags & MX3_CAMERA_CLK_SRC)
492 conf |= 1 << CSI_SENS_CONF_SENS_CLKSRC_SHIFT;
493 if (mx3_cam->platform_flags & MX3_CAMERA_EXT_VSYNC)
494 conf |= 1 << CSI_SENS_CONF_EXT_VSYNC_SHIFT;
495 if (mx3_cam->platform_flags & MX3_CAMERA_DP)
496 conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT;
497 if (mx3_cam->platform_flags & MX3_CAMERA_PCP)
498 conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT;
499 if (mx3_cam->platform_flags & MX3_CAMERA_HSP)
500 conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT;
501 if (mx3_cam->platform_flags & MX3_CAMERA_VSP)
502 conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT;
503
504 /* ipu_csi_init_interface() */
505 csi_reg_write(mx3_cam, conf, CSI_SENS_CONF);
506
507 clk_prepare_enable(mx3_cam->clk);
508 rate = clk_round_rate(mx3_cam->clk, mx3_cam->mclk);
509 dev_dbg(icd->parent, "Set SENS_CONF to %x, rate %ld\n", conf, rate);
510 if (rate)
511 clk_set_rate(mx3_cam->clk, rate);
512 }
513
514 /* Called with .host_lock held */
515 static int mx3_camera_add_device(struct soc_camera_device *icd)
516 {
517 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
518 struct mx3_camera_dev *mx3_cam = ici->priv;
519
520 if (mx3_cam->icd)
521 return -EBUSY;
522
523 mx3_camera_activate(mx3_cam, icd);
524
525 mx3_cam->buf_total = 0;
526 mx3_cam->icd = icd;
527
528 dev_info(icd->parent, "MX3 Camera driver attached to camera %d\n",
529 icd->devnum);
530
531 return 0;
532 }
533
534 /* Called with .host_lock held */
535 static void mx3_camera_remove_device(struct soc_camera_device *icd)
536 {
537 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
538 struct mx3_camera_dev *mx3_cam = ici->priv;
539 struct idmac_channel **ichan = &mx3_cam->idmac_channel[0];
540
541 BUG_ON(icd != mx3_cam->icd);
542
543 if (*ichan) {
544 dma_release_channel(&(*ichan)->dma_chan);
545 *ichan = NULL;
546 }
547
548 clk_disable_unprepare(mx3_cam->clk);
549
550 mx3_cam->icd = NULL;
551
552 dev_info(icd->parent, "MX3 Camera driver detached from camera %d\n",
553 icd->devnum);
554 }
555
556 static int test_platform_param(struct mx3_camera_dev *mx3_cam,
557 unsigned char buswidth, unsigned long *flags)
558 {
559 /*
560 * If requested data width is supported by the platform, use it or any
561 * possible lower value - i.MX31 is smart enough to shift bits
562 */
563 if (buswidth > fls(mx3_cam->width_flags))
564 return -EINVAL;
565
566 /*
567 * Platform specified synchronization and pixel clock polarities are
568 * only a recommendation and are only used during probing. MX3x
569 * camera interface only works in master mode, i.e., uses HSYNC and
570 * VSYNC signals from the sensor
571 */
572 *flags = V4L2_MBUS_MASTER |
573 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
574 V4L2_MBUS_HSYNC_ACTIVE_LOW |
575 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
576 V4L2_MBUS_VSYNC_ACTIVE_LOW |
577 V4L2_MBUS_PCLK_SAMPLE_RISING |
578 V4L2_MBUS_PCLK_SAMPLE_FALLING |
579 V4L2_MBUS_DATA_ACTIVE_HIGH |
580 V4L2_MBUS_DATA_ACTIVE_LOW;
581
582 return 0;
583 }
584
585 static int mx3_camera_try_bus_param(struct soc_camera_device *icd,
586 const unsigned int depth)
587 {
588 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
589 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
590 struct mx3_camera_dev *mx3_cam = ici->priv;
591 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
592 unsigned long bus_flags, common_flags;
593 int ret = test_platform_param(mx3_cam, depth, &bus_flags);
594
595 dev_dbg(icd->parent, "request bus width %d bit: %d\n", depth, ret);
596
597 if (ret < 0)
598 return ret;
599
600 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
601 if (!ret) {
602 common_flags = soc_mbus_config_compatible(&cfg,
603 bus_flags);
604 if (!common_flags) {
605 dev_warn(icd->parent,
606 "Flags incompatible: camera 0x%x, host 0x%lx\n",
607 cfg.flags, bus_flags);
608 return -EINVAL;
609 }
610 } else if (ret != -ENOIOCTLCMD) {
611 return ret;
612 }
613
614 return 0;
615 }
616
617 static bool chan_filter(struct dma_chan *chan, void *arg)
618 {
619 struct dma_chan_request *rq = arg;
620 struct mx3_camera_pdata *pdata;
621
622 if (!imx_dma_is_ipu(chan))
623 return false;
624
625 if (!rq)
626 return false;
627
628 pdata = rq->mx3_cam->soc_host.v4l2_dev.dev->platform_data;
629
630 return rq->id == chan->chan_id &&
631 pdata->dma_dev == chan->device->dev;
632 }
633
634 static const struct soc_mbus_pixelfmt mx3_camera_formats[] = {
635 {
636 .fourcc = V4L2_PIX_FMT_SBGGR8,
637 .name = "Bayer BGGR (sRGB) 8 bit",
638 .bits_per_sample = 8,
639 .packing = SOC_MBUS_PACKING_NONE,
640 .order = SOC_MBUS_ORDER_LE,
641 .layout = SOC_MBUS_LAYOUT_PACKED,
642 }, {
643 .fourcc = V4L2_PIX_FMT_GREY,
644 .name = "Monochrome 8 bit",
645 .bits_per_sample = 8,
646 .packing = SOC_MBUS_PACKING_NONE,
647 .order = SOC_MBUS_ORDER_LE,
648 .layout = SOC_MBUS_LAYOUT_PACKED,
649 },
650 };
651
652 /* This will be corrected as we get more formats */
653 static bool mx3_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
654 {
655 return fmt->packing == SOC_MBUS_PACKING_NONE ||
656 (fmt->bits_per_sample == 8 &&
657 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
658 (fmt->bits_per_sample > 8 &&
659 fmt->packing == SOC_MBUS_PACKING_EXTEND16);
660 }
661
662 static int mx3_camera_get_formats(struct soc_camera_device *icd, unsigned int idx,
663 struct soc_camera_format_xlate *xlate)
664 {
665 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
666 struct device *dev = icd->parent;
667 int formats = 0, ret;
668 enum v4l2_mbus_pixelcode code;
669 const struct soc_mbus_pixelfmt *fmt;
670
671 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
672 if (ret < 0)
673 /* No more formats */
674 return 0;
675
676 fmt = soc_mbus_get_fmtdesc(code);
677 if (!fmt) {
678 dev_warn(icd->parent,
679 "Unsupported format code #%u: %d\n", idx, code);
680 return 0;
681 }
682
683 /* This also checks support for the requested bits-per-sample */
684 ret = mx3_camera_try_bus_param(icd, fmt->bits_per_sample);
685 if (ret < 0)
686 return 0;
687
688 switch (code) {
689 case V4L2_MBUS_FMT_SBGGR10_1X10:
690 formats++;
691 if (xlate) {
692 xlate->host_fmt = &mx3_camera_formats[0];
693 xlate->code = code;
694 xlate++;
695 dev_dbg(dev, "Providing format %s using code %d\n",
696 mx3_camera_formats[0].name, code);
697 }
698 break;
699 case V4L2_MBUS_FMT_Y10_1X10:
700 formats++;
701 if (xlate) {
702 xlate->host_fmt = &mx3_camera_formats[1];
703 xlate->code = code;
704 xlate++;
705 dev_dbg(dev, "Providing format %s using code %d\n",
706 mx3_camera_formats[1].name, code);
707 }
708 break;
709 default:
710 if (!mx3_camera_packing_supported(fmt))
711 return 0;
712 }
713
714 /* Generic pass-through */
715 formats++;
716 if (xlate) {
717 xlate->host_fmt = fmt;
718 xlate->code = code;
719 dev_dbg(dev, "Providing format %c%c%c%c in pass-through mode\n",
720 (fmt->fourcc >> (0*8)) & 0xFF,
721 (fmt->fourcc >> (1*8)) & 0xFF,
722 (fmt->fourcc >> (2*8)) & 0xFF,
723 (fmt->fourcc >> (3*8)) & 0xFF);
724 xlate++;
725 }
726
727 return formats;
728 }
729
730 static void configure_geometry(struct mx3_camera_dev *mx3_cam,
731 unsigned int width, unsigned int height,
732 const struct soc_mbus_pixelfmt *fmt)
733 {
734 u32 ctrl, width_field, height_field;
735
736 if (fourcc_to_ipu_pix(fmt->fourcc) == IPU_PIX_FMT_GENERIC) {
737 /*
738 * As the CSI will be configured to output BAYER, here
739 * the width parameter count the number of samples to
740 * capture to complete the whole image width.
741 */
742 unsigned int num, den;
743 int ret = soc_mbus_samples_per_pixel(fmt, &num, &den);
744 BUG_ON(ret < 0);
745 width = width * num / den;
746 }
747
748 /* Setup frame size - this cannot be changed on-the-fly... */
749 width_field = width - 1;
750 height_field = height - 1;
751 csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_SENS_FRM_SIZE);
752
753 csi_reg_write(mx3_cam, width_field << 16, CSI_FLASH_STROBE_1);
754 csi_reg_write(mx3_cam, (height_field << 16) | 0x22, CSI_FLASH_STROBE_2);
755
756 csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_ACT_FRM_SIZE);
757
758 /* ...and position */
759 ctrl = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000;
760 /* Sensor does the cropping */
761 csi_reg_write(mx3_cam, ctrl | 0 | (0 << 8), CSI_OUT_FRM_CTRL);
762 }
763
764 static int acquire_dma_channel(struct mx3_camera_dev *mx3_cam)
765 {
766 dma_cap_mask_t mask;
767 struct dma_chan *chan;
768 struct idmac_channel **ichan = &mx3_cam->idmac_channel[0];
769 /* We have to use IDMAC_IC_7 for Bayer / generic data */
770 struct dma_chan_request rq = {.mx3_cam = mx3_cam,
771 .id = IDMAC_IC_7};
772
773 dma_cap_zero(mask);
774 dma_cap_set(DMA_SLAVE, mask);
775 dma_cap_set(DMA_PRIVATE, mask);
776 chan = dma_request_channel(mask, chan_filter, &rq);
777 if (!chan)
778 return -EBUSY;
779
780 *ichan = to_idmac_chan(chan);
781 (*ichan)->client = mx3_cam;
782
783 return 0;
784 }
785
786 /*
787 * FIXME: learn to use stride != width, then we can keep stride properly aligned
788 * and support arbitrary (even) widths.
789 */
790 static inline void stride_align(__u32 *width)
791 {
792 if (ALIGN(*width, 8) < 4096)
793 *width = ALIGN(*width, 8);
794 else
795 *width = *width & ~7;
796 }
797
798 /*
799 * As long as we don't implement host-side cropping and scaling, we can use
800 * default g_crop and cropcap from soc_camera.c
801 */
802 static int mx3_camera_set_crop(struct soc_camera_device *icd,
803 const struct v4l2_crop *a)
804 {
805 struct v4l2_crop a_writable = *a;
806 struct v4l2_rect *rect = &a_writable.c;
807 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
808 struct mx3_camera_dev *mx3_cam = ici->priv;
809 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
810 struct v4l2_mbus_framefmt mf;
811 int ret;
812
813 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
814 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
815
816 ret = v4l2_subdev_call(sd, video, s_crop, a);
817 if (ret < 0)
818 return ret;
819
820 /* The capture device might have changed its output sizes */
821 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
822 if (ret < 0)
823 return ret;
824
825 if (mf.code != icd->current_fmt->code)
826 return -EINVAL;
827
828 if (mf.width & 7) {
829 /* Ouch! We can only handle 8-byte aligned width... */
830 stride_align(&mf.width);
831 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
832 if (ret < 0)
833 return ret;
834 }
835
836 if (mf.width != icd->user_width || mf.height != icd->user_height)
837 configure_geometry(mx3_cam, mf.width, mf.height,
838 icd->current_fmt->host_fmt);
839
840 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
841 mf.width, mf.height);
842
843 icd->user_width = mf.width;
844 icd->user_height = mf.height;
845
846 return ret;
847 }
848
849 static int mx3_camera_set_fmt(struct soc_camera_device *icd,
850 struct v4l2_format *f)
851 {
852 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
853 struct mx3_camera_dev *mx3_cam = ici->priv;
854 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
855 const struct soc_camera_format_xlate *xlate;
856 struct v4l2_pix_format *pix = &f->fmt.pix;
857 struct v4l2_mbus_framefmt mf;
858 int ret;
859
860 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
861 if (!xlate) {
862 dev_warn(icd->parent, "Format %x not found\n",
863 pix->pixelformat);
864 return -EINVAL;
865 }
866
867 stride_align(&pix->width);
868 dev_dbg(icd->parent, "Set format %dx%d\n", pix->width, pix->height);
869
870 /*
871 * Might have to perform a complete interface initialisation like in
872 * ipu_csi_init_interface() in mxc_v4l2_s_param(). Also consider
873 * mxc_v4l2_s_fmt()
874 */
875
876 configure_geometry(mx3_cam, pix->width, pix->height, xlate->host_fmt);
877
878 mf.width = pix->width;
879 mf.height = pix->height;
880 mf.field = pix->field;
881 mf.colorspace = pix->colorspace;
882 mf.code = xlate->code;
883
884 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
885 if (ret < 0)
886 return ret;
887
888 if (mf.code != xlate->code)
889 return -EINVAL;
890
891 if (!mx3_cam->idmac_channel[0]) {
892 ret = acquire_dma_channel(mx3_cam);
893 if (ret < 0)
894 return ret;
895 }
896
897 pix->width = mf.width;
898 pix->height = mf.height;
899 pix->field = mf.field;
900 mx3_cam->field = mf.field;
901 pix->colorspace = mf.colorspace;
902 icd->current_fmt = xlate;
903
904 dev_dbg(icd->parent, "Sensor set %dx%d\n", pix->width, pix->height);
905
906 return ret;
907 }
908
909 static int mx3_camera_try_fmt(struct soc_camera_device *icd,
910 struct v4l2_format *f)
911 {
912 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
913 const struct soc_camera_format_xlate *xlate;
914 struct v4l2_pix_format *pix = &f->fmt.pix;
915 struct v4l2_mbus_framefmt mf;
916 __u32 pixfmt = pix->pixelformat;
917 int ret;
918
919 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
920 if (pixfmt && !xlate) {
921 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
922 return -EINVAL;
923 }
924
925 /* limit to MX3 hardware capabilities */
926 if (pix->height > 4096)
927 pix->height = 4096;
928 if (pix->width > 4096)
929 pix->width = 4096;
930
931 /* limit to sensor capabilities */
932 mf.width = pix->width;
933 mf.height = pix->height;
934 mf.field = pix->field;
935 mf.colorspace = pix->colorspace;
936 mf.code = xlate->code;
937
938 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
939 if (ret < 0)
940 return ret;
941
942 pix->width = mf.width;
943 pix->height = mf.height;
944 pix->colorspace = mf.colorspace;
945
946 switch (mf.field) {
947 case V4L2_FIELD_ANY:
948 pix->field = V4L2_FIELD_NONE;
949 break;
950 case V4L2_FIELD_NONE:
951 break;
952 default:
953 dev_err(icd->parent, "Field type %d unsupported.\n",
954 mf.field);
955 ret = -EINVAL;
956 }
957
958 return ret;
959 }
960
961 static int mx3_camera_reqbufs(struct soc_camera_device *icd,
962 struct v4l2_requestbuffers *p)
963 {
964 return 0;
965 }
966
967 static unsigned int mx3_camera_poll(struct file *file, poll_table *pt)
968 {
969 struct soc_camera_device *icd = file->private_data;
970
971 return vb2_poll(&icd->vb2_vidq, file, pt);
972 }
973
974 static int mx3_camera_querycap(struct soc_camera_host *ici,
975 struct v4l2_capability *cap)
976 {
977 /* cap->name is set by the firendly caller:-> */
978 strlcpy(cap->card, "i.MX3x Camera", sizeof(cap->card));
979 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
980
981 return 0;
982 }
983
984 static int mx3_camera_set_bus_param(struct soc_camera_device *icd)
985 {
986 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
987 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
988 struct mx3_camera_dev *mx3_cam = ici->priv;
989 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
990 u32 pixfmt = icd->current_fmt->host_fmt->fourcc;
991 unsigned long bus_flags, common_flags;
992 u32 dw, sens_conf;
993 const struct soc_mbus_pixelfmt *fmt;
994 int buswidth;
995 int ret;
996 const struct soc_camera_format_xlate *xlate;
997 struct device *dev = icd->parent;
998
999 fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code);
1000 if (!fmt)
1001 return -EINVAL;
1002
1003 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1004 if (!xlate) {
1005 dev_warn(dev, "Format %x not found\n", pixfmt);
1006 return -EINVAL;
1007 }
1008
1009 buswidth = fmt->bits_per_sample;
1010 ret = test_platform_param(mx3_cam, buswidth, &bus_flags);
1011
1012 dev_dbg(dev, "requested bus width %d bit: %d\n", buswidth, ret);
1013
1014 if (ret < 0)
1015 return ret;
1016
1017 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1018 if (!ret) {
1019 common_flags = soc_mbus_config_compatible(&cfg,
1020 bus_flags);
1021 if (!common_flags) {
1022 dev_warn(icd->parent,
1023 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1024 cfg.flags, bus_flags);
1025 return -EINVAL;
1026 }
1027 } else if (ret != -ENOIOCTLCMD) {
1028 return ret;
1029 } else {
1030 common_flags = bus_flags;
1031 }
1032
1033 dev_dbg(dev, "Flags cam: 0x%x host: 0x%lx common: 0x%lx\n",
1034 cfg.flags, bus_flags, common_flags);
1035
1036 /* Make choices, based on platform preferences */
1037 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1038 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1039 if (mx3_cam->platform_flags & MX3_CAMERA_HSP)
1040 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1041 else
1042 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1043 }
1044
1045 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1046 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1047 if (mx3_cam->platform_flags & MX3_CAMERA_VSP)
1048 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1049 else
1050 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1051 }
1052
1053 if ((common_flags & V4L2_MBUS_DATA_ACTIVE_HIGH) &&
1054 (common_flags & V4L2_MBUS_DATA_ACTIVE_LOW)) {
1055 if (mx3_cam->platform_flags & MX3_CAMERA_DP)
1056 common_flags &= ~V4L2_MBUS_DATA_ACTIVE_HIGH;
1057 else
1058 common_flags &= ~V4L2_MBUS_DATA_ACTIVE_LOW;
1059 }
1060
1061 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1062 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1063 if (mx3_cam->platform_flags & MX3_CAMERA_PCP)
1064 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1065 else
1066 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1067 }
1068
1069 cfg.flags = common_flags;
1070 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1071 if (ret < 0 && ret != -ENOIOCTLCMD) {
1072 dev_dbg(dev, "camera s_mbus_config(0x%lx) returned %d\n",
1073 common_flags, ret);
1074 return ret;
1075 }
1076
1077 /*
1078 * So far only gated clock mode is supported. Add a line
1079 * (3 << CSI_SENS_CONF_SENS_PRTCL_SHIFT) |
1080 * below and select the required mode when supporting other
1081 * synchronisation protocols.
1082 */
1083 sens_conf = csi_reg_read(mx3_cam, CSI_SENS_CONF) &
1084 ~((1 << CSI_SENS_CONF_VSYNC_POL_SHIFT) |
1085 (1 << CSI_SENS_CONF_HSYNC_POL_SHIFT) |
1086 (1 << CSI_SENS_CONF_DATA_POL_SHIFT) |
1087 (1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT) |
1088 (3 << CSI_SENS_CONF_DATA_FMT_SHIFT) |
1089 (3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT));
1090
1091 /* TODO: Support RGB and YUV formats */
1092
1093 /* This has been set in mx3_camera_activate(), but we clear it above */
1094 sens_conf |= CSI_SENS_CONF_DATA_FMT_BAYER;
1095
1096 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1097 sens_conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT;
1098 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1099 sens_conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT;
1100 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1101 sens_conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT;
1102 if (common_flags & V4L2_MBUS_DATA_ACTIVE_LOW)
1103 sens_conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT;
1104
1105 /* Just do what we're asked to do */
1106 switch (xlate->host_fmt->bits_per_sample) {
1107 case 4:
1108 dw = 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1109 break;
1110 case 8:
1111 dw = 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1112 break;
1113 case 10:
1114 dw = 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1115 break;
1116 default:
1117 /*
1118 * Actually it can only be 15 now, default is just to silence
1119 * compiler warnings
1120 */
1121 case 15:
1122 dw = 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1123 }
1124
1125 csi_reg_write(mx3_cam, sens_conf | dw, CSI_SENS_CONF);
1126
1127 dev_dbg(dev, "Set SENS_CONF to %x\n", sens_conf | dw);
1128
1129 return 0;
1130 }
1131
1132 static struct soc_camera_host_ops mx3_soc_camera_host_ops = {
1133 .owner = THIS_MODULE,
1134 .add = mx3_camera_add_device,
1135 .remove = mx3_camera_remove_device,
1136 .set_crop = mx3_camera_set_crop,
1137 .set_fmt = mx3_camera_set_fmt,
1138 .try_fmt = mx3_camera_try_fmt,
1139 .get_formats = mx3_camera_get_formats,
1140 .init_videobuf2 = mx3_camera_init_videobuf,
1141 .reqbufs = mx3_camera_reqbufs,
1142 .poll = mx3_camera_poll,
1143 .querycap = mx3_camera_querycap,
1144 .set_bus_param = mx3_camera_set_bus_param,
1145 };
1146
1147 static int mx3_camera_probe(struct platform_device *pdev)
1148 {
1149 struct mx3_camera_dev *mx3_cam;
1150 struct resource *res;
1151 void __iomem *base;
1152 int err = 0;
1153 struct soc_camera_host *soc_host;
1154
1155 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1156 if (!res) {
1157 err = -ENODEV;
1158 goto egetres;
1159 }
1160
1161 mx3_cam = vzalloc(sizeof(*mx3_cam));
1162 if (!mx3_cam) {
1163 dev_err(&pdev->dev, "Could not allocate mx3 camera object\n");
1164 err = -ENOMEM;
1165 goto ealloc;
1166 }
1167
1168 mx3_cam->clk = clk_get(&pdev->dev, NULL);
1169 if (IS_ERR(mx3_cam->clk)) {
1170 err = PTR_ERR(mx3_cam->clk);
1171 goto eclkget;
1172 }
1173
1174 mx3_cam->pdata = pdev->dev.platform_data;
1175 mx3_cam->platform_flags = mx3_cam->pdata->flags;
1176 if (!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_MASK)) {
1177 /*
1178 * Platform hasn't set available data widths. This is bad.
1179 * Warn and use a default.
1180 */
1181 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1182 "data widths, using default 8 bit\n");
1183 mx3_cam->platform_flags |= MX3_CAMERA_DATAWIDTH_8;
1184 }
1185 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)
1186 mx3_cam->width_flags = 1 << 3;
1187 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8)
1188 mx3_cam->width_flags |= 1 << 7;
1189 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10)
1190 mx3_cam->width_flags |= 1 << 9;
1191 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15)
1192 mx3_cam->width_flags |= 1 << 14;
1193
1194 mx3_cam->mclk = mx3_cam->pdata->mclk_10khz * 10000;
1195 if (!mx3_cam->mclk) {
1196 dev_warn(&pdev->dev,
1197 "mclk_10khz == 0! Please, fix your platform data. "
1198 "Using default 20MHz\n");
1199 mx3_cam->mclk = 20000000;
1200 }
1201
1202 /* list of video-buffers */
1203 INIT_LIST_HEAD(&mx3_cam->capture);
1204 spin_lock_init(&mx3_cam->lock);
1205
1206 base = ioremap(res->start, resource_size(res));
1207 if (!base) {
1208 pr_err("Couldn't map %x@%x\n", resource_size(res), res->start);
1209 err = -ENOMEM;
1210 goto eioremap;
1211 }
1212
1213 mx3_cam->base = base;
1214
1215 soc_host = &mx3_cam->soc_host;
1216 soc_host->drv_name = MX3_CAM_DRV_NAME;
1217 soc_host->ops = &mx3_soc_camera_host_ops;
1218 soc_host->priv = mx3_cam;
1219 soc_host->v4l2_dev.dev = &pdev->dev;
1220 soc_host->nr = pdev->id;
1221
1222 mx3_cam->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1223 if (IS_ERR(mx3_cam->alloc_ctx)) {
1224 err = PTR_ERR(mx3_cam->alloc_ctx);
1225 goto eallocctx;
1226 }
1227
1228 err = soc_camera_host_register(soc_host);
1229 if (err)
1230 goto ecamhostreg;
1231
1232 /* IDMAC interface */
1233 dmaengine_get();
1234
1235 return 0;
1236
1237 ecamhostreg:
1238 vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx);
1239 eallocctx:
1240 iounmap(base);
1241 eioremap:
1242 clk_put(mx3_cam->clk);
1243 eclkget:
1244 vfree(mx3_cam);
1245 ealloc:
1246 egetres:
1247 return err;
1248 }
1249
1250 static int mx3_camera_remove(struct platform_device *pdev)
1251 {
1252 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1253 struct mx3_camera_dev *mx3_cam = container_of(soc_host,
1254 struct mx3_camera_dev, soc_host);
1255
1256 clk_put(mx3_cam->clk);
1257
1258 soc_camera_host_unregister(soc_host);
1259
1260 iounmap(mx3_cam->base);
1261
1262 /*
1263 * The channel has either not been allocated,
1264 * or should have been released
1265 */
1266 if (WARN_ON(mx3_cam->idmac_channel[0]))
1267 dma_release_channel(&mx3_cam->idmac_channel[0]->dma_chan);
1268
1269 vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx);
1270
1271 vfree(mx3_cam);
1272
1273 dmaengine_put();
1274
1275 return 0;
1276 }
1277
1278 static struct platform_driver mx3_camera_driver = {
1279 .driver = {
1280 .name = MX3_CAM_DRV_NAME,
1281 },
1282 .probe = mx3_camera_probe,
1283 .remove = mx3_camera_remove,
1284 };
1285
1286 module_platform_driver(mx3_camera_driver);
1287
1288 MODULE_DESCRIPTION("i.MX3x SoC Camera Host driver");
1289 MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1290 MODULE_LICENSE("GPL v2");
1291 MODULE_VERSION("0.2.3");
1292 MODULE_ALIAS("platform:" MX3_CAM_DRV_NAME);
Linux with added FPC-III support