1 /* savage_bci.c -- BCI support for Savage
3 * Copyright 2004 Felix Kuehling
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "savage_drm.h"
27 #include "savage_drv.h"
29 /* Need a long timeout for shadow status updates can take a while
30 * and so can waiting for events when the queue is full. */
31 #define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */
32 #define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */
33 #define SAVAGE_FREELIST_DEBUG 0
35 static int savage_do_cleanup_bci(struct drm_device
*dev
);
38 savage_bci_wait_fifo_shadow(drm_savage_private_t
* dev_priv
, unsigned int n
)
40 uint32_t mask
= dev_priv
->status_used_mask
;
41 uint32_t threshold
= dev_priv
->bci_threshold_hi
;
46 if (n
> dev_priv
->cob_size
+ SAVAGE_BCI_FIFO_SIZE
- threshold
)
47 DRM_ERROR("Trying to emit %d words "
48 "(more than guaranteed space in COB)\n", n
);
51 for (i
= 0; i
< SAVAGE_DEFAULT_USEC_TIMEOUT
; i
++) {
53 status
= dev_priv
->status_ptr
[0];
54 if ((status
& mask
) < threshold
)
60 DRM_ERROR("failed!\n");
61 DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status
, threshold
);
67 savage_bci_wait_fifo_s3d(drm_savage_private_t
* dev_priv
, unsigned int n
)
69 uint32_t maxUsed
= dev_priv
->cob_size
+ SAVAGE_BCI_FIFO_SIZE
- n
;
73 for (i
= 0; i
< SAVAGE_DEFAULT_USEC_TIMEOUT
; i
++) {
74 status
= SAVAGE_READ(SAVAGE_STATUS_WORD0
);
75 if ((status
& SAVAGE_FIFO_USED_MASK_S3D
) <= maxUsed
)
81 DRM_ERROR("failed!\n");
82 DRM_INFO(" status=0x%08x\n", status
);
88 savage_bci_wait_fifo_s4(drm_savage_private_t
* dev_priv
, unsigned int n
)
90 uint32_t maxUsed
= dev_priv
->cob_size
+ SAVAGE_BCI_FIFO_SIZE
- n
;
94 for (i
= 0; i
< SAVAGE_DEFAULT_USEC_TIMEOUT
; i
++) {
95 status
= SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0
);
96 if ((status
& SAVAGE_FIFO_USED_MASK_S4
) <= maxUsed
)
102 DRM_ERROR("failed!\n");
103 DRM_INFO(" status=0x%08x\n", status
);
109 * Waiting for events.
111 * The BIOSresets the event tag to 0 on mode changes. Therefore we
112 * never emit 0 to the event tag. If we find a 0 event tag we know the
113 * BIOS stomped on it and return success assuming that the BIOS waited
116 * Note: if the Xserver uses the event tag it has to follow the same
117 * rule. Otherwise there may be glitches every 2^16 events.
120 savage_bci_wait_event_shadow(drm_savage_private_t
* dev_priv
, uint16_t e
)
125 for (i
= 0; i
< SAVAGE_EVENT_USEC_TIMEOUT
; i
++) {
127 status
= dev_priv
->status_ptr
[1];
128 if ((((status
& 0xffff) - e
) & 0xffff) <= 0x7fff ||
129 (status
& 0xffff) == 0)
135 DRM_ERROR("failed!\n");
136 DRM_INFO(" status=0x%08x, e=0x%04x\n", status
, e
);
143 savage_bci_wait_event_reg(drm_savage_private_t
* dev_priv
, uint16_t e
)
148 for (i
= 0; i
< SAVAGE_EVENT_USEC_TIMEOUT
; i
++) {
149 status
= SAVAGE_READ(SAVAGE_STATUS_WORD1
);
150 if ((((status
& 0xffff) - e
) & 0xffff) <= 0x7fff ||
151 (status
& 0xffff) == 0)
157 DRM_ERROR("failed!\n");
158 DRM_INFO(" status=0x%08x, e=0x%04x\n", status
, e
);
164 uint16_t savage_bci_emit_event(drm_savage_private_t
* dev_priv
,
170 if (dev_priv
->status_ptr
) {
171 /* coordinate with Xserver */
172 count
= dev_priv
->status_ptr
[1023];
173 if (count
< dev_priv
->event_counter
)
174 dev_priv
->event_wrap
++;
176 count
= dev_priv
->event_counter
;
178 count
= (count
+ 1) & 0xffff;
180 count
++; /* See the comment above savage_wait_event_*. */
181 dev_priv
->event_wrap
++;
183 dev_priv
->event_counter
= count
;
184 if (dev_priv
->status_ptr
)
185 dev_priv
->status_ptr
[1023] = (uint32_t) count
;
187 if ((flags
& (SAVAGE_WAIT_2D
| SAVAGE_WAIT_3D
))) {
188 unsigned int wait_cmd
= BCI_CMD_WAIT
;
189 if ((flags
& SAVAGE_WAIT_2D
))
190 wait_cmd
|= BCI_CMD_WAIT_2D
;
191 if ((flags
& SAVAGE_WAIT_3D
))
192 wait_cmd
|= BCI_CMD_WAIT_3D
;
198 BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG
| (uint32_t) count
);
204 * Freelist management
206 static int savage_freelist_init(struct drm_device
* dev
)
208 drm_savage_private_t
*dev_priv
= dev
->dev_private
;
209 struct drm_device_dma
*dma
= dev
->dma
;
211 drm_savage_buf_priv_t
*entry
;
213 DRM_DEBUG("count=%d\n", dma
->buf_count
);
215 dev_priv
->head
.next
= &dev_priv
->tail
;
216 dev_priv
->head
.prev
= NULL
;
217 dev_priv
->head
.buf
= NULL
;
219 dev_priv
->tail
.next
= NULL
;
220 dev_priv
->tail
.prev
= &dev_priv
->head
;
221 dev_priv
->tail
.buf
= NULL
;
223 for (i
= 0; i
< dma
->buf_count
; i
++) {
224 buf
= dma
->buflist
[i
];
225 entry
= buf
->dev_private
;
227 SET_AGE(&entry
->age
, 0, 0);
230 entry
->next
= dev_priv
->head
.next
;
231 entry
->prev
= &dev_priv
->head
;
232 dev_priv
->head
.next
->prev
= entry
;
233 dev_priv
->head
.next
= entry
;
239 static struct drm_buf
*savage_freelist_get(struct drm_device
* dev
)
241 drm_savage_private_t
*dev_priv
= dev
->dev_private
;
242 drm_savage_buf_priv_t
*tail
= dev_priv
->tail
.prev
;
247 UPDATE_EVENT_COUNTER();
248 if (dev_priv
->status_ptr
)
249 event
= dev_priv
->status_ptr
[1] & 0xffff;
251 event
= SAVAGE_READ(SAVAGE_STATUS_WORD1
) & 0xffff;
252 wrap
= dev_priv
->event_wrap
;
253 if (event
> dev_priv
->event_counter
)
254 wrap
--; /* hardware hasn't passed the last wrap yet */
256 DRM_DEBUG(" tail=0x%04x %d\n", tail
->age
.event
, tail
->age
.wrap
);
257 DRM_DEBUG(" head=0x%04x %d\n", event
, wrap
);
259 if (tail
->buf
&& (TEST_AGE(&tail
->age
, event
, wrap
) || event
== 0)) {
260 drm_savage_buf_priv_t
*next
= tail
->next
;
261 drm_savage_buf_priv_t
*prev
= tail
->prev
;
264 tail
->next
= tail
->prev
= NULL
;
268 DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail
->buf
);
272 void savage_freelist_put(struct drm_device
* dev
, struct drm_buf
* buf
)
274 drm_savage_private_t
*dev_priv
= dev
->dev_private
;
275 drm_savage_buf_priv_t
*entry
= buf
->dev_private
, *prev
, *next
;
277 DRM_DEBUG("age=0x%04x wrap=%d\n", entry
->age
.event
, entry
->age
.wrap
);
279 if (entry
->next
!= NULL
|| entry
->prev
!= NULL
) {
280 DRM_ERROR("entry already on freelist.\n");
284 prev
= &dev_priv
->head
;
295 static int savage_dma_init(drm_savage_private_t
* dev_priv
)
299 dev_priv
->nr_dma_pages
= dev_priv
->cmd_dma
->size
/
300 (SAVAGE_DMA_PAGE_SIZE
* 4);
301 dev_priv
->dma_pages
= kmalloc(sizeof(drm_savage_dma_page_t
) *
302 dev_priv
->nr_dma_pages
, GFP_KERNEL
);
303 if (dev_priv
->dma_pages
== NULL
)
306 for (i
= 0; i
< dev_priv
->nr_dma_pages
; ++i
) {
307 SET_AGE(&dev_priv
->dma_pages
[i
].age
, 0, 0);
308 dev_priv
->dma_pages
[i
].used
= 0;
309 dev_priv
->dma_pages
[i
].flushed
= 0;
311 SET_AGE(&dev_priv
->last_dma_age
, 0, 0);
313 dev_priv
->first_dma_page
= 0;
314 dev_priv
->current_dma_page
= 0;
319 void savage_dma_reset(drm_savage_private_t
* dev_priv
)
322 unsigned int wrap
, i
;
323 event
= savage_bci_emit_event(dev_priv
, 0);
324 wrap
= dev_priv
->event_wrap
;
325 for (i
= 0; i
< dev_priv
->nr_dma_pages
; ++i
) {
326 SET_AGE(&dev_priv
->dma_pages
[i
].age
, event
, wrap
);
327 dev_priv
->dma_pages
[i
].used
= 0;
328 dev_priv
->dma_pages
[i
].flushed
= 0;
330 SET_AGE(&dev_priv
->last_dma_age
, event
, wrap
);
331 dev_priv
->first_dma_page
= dev_priv
->current_dma_page
= 0;
334 void savage_dma_wait(drm_savage_private_t
* dev_priv
, unsigned int page
)
339 /* Faked DMA buffer pages don't age. */
340 if (dev_priv
->cmd_dma
== &dev_priv
->fake_dma
)
343 UPDATE_EVENT_COUNTER();
344 if (dev_priv
->status_ptr
)
345 event
= dev_priv
->status_ptr
[1] & 0xffff;
347 event
= SAVAGE_READ(SAVAGE_STATUS_WORD1
) & 0xffff;
348 wrap
= dev_priv
->event_wrap
;
349 if (event
> dev_priv
->event_counter
)
350 wrap
--; /* hardware hasn't passed the last wrap yet */
352 if (dev_priv
->dma_pages
[page
].age
.wrap
> wrap
||
353 (dev_priv
->dma_pages
[page
].age
.wrap
== wrap
&&
354 dev_priv
->dma_pages
[page
].age
.event
> event
)) {
355 if (dev_priv
->wait_evnt(dev_priv
,
356 dev_priv
->dma_pages
[page
].age
.event
)
358 DRM_ERROR("wait_evnt failed!\n");
362 uint32_t *savage_dma_alloc(drm_savage_private_t
* dev_priv
, unsigned int n
)
364 unsigned int cur
= dev_priv
->current_dma_page
;
365 unsigned int rest
= SAVAGE_DMA_PAGE_SIZE
-
366 dev_priv
->dma_pages
[cur
].used
;
367 unsigned int nr_pages
= (n
- rest
+ SAVAGE_DMA_PAGE_SIZE
- 1) /
368 SAVAGE_DMA_PAGE_SIZE
;
372 DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n",
373 cur
, dev_priv
->dma_pages
[cur
].used
, n
, rest
, nr_pages
);
375 if (cur
+ nr_pages
< dev_priv
->nr_dma_pages
) {
376 dma_ptr
= (uint32_t *) dev_priv
->cmd_dma
->handle
+
377 cur
* SAVAGE_DMA_PAGE_SIZE
+ dev_priv
->dma_pages
[cur
].used
;
380 dev_priv
->dma_pages
[cur
].used
+= rest
;
384 dev_priv
->dma_flush(dev_priv
);
386 (n
+ SAVAGE_DMA_PAGE_SIZE
- 1) / SAVAGE_DMA_PAGE_SIZE
;
387 for (i
= cur
; i
< dev_priv
->nr_dma_pages
; ++i
) {
388 dev_priv
->dma_pages
[i
].age
= dev_priv
->last_dma_age
;
389 dev_priv
->dma_pages
[i
].used
= 0;
390 dev_priv
->dma_pages
[i
].flushed
= 0;
392 dma_ptr
= (uint32_t *) dev_priv
->cmd_dma
->handle
;
393 dev_priv
->first_dma_page
= cur
= 0;
395 for (i
= cur
; nr_pages
> 0; ++i
, --nr_pages
) {
397 if (dev_priv
->dma_pages
[i
].used
) {
398 DRM_ERROR("unflushed page %u: used=%u\n",
399 i
, dev_priv
->dma_pages
[i
].used
);
402 if (n
> SAVAGE_DMA_PAGE_SIZE
)
403 dev_priv
->dma_pages
[i
].used
= SAVAGE_DMA_PAGE_SIZE
;
405 dev_priv
->dma_pages
[i
].used
= n
;
406 n
-= SAVAGE_DMA_PAGE_SIZE
;
408 dev_priv
->current_dma_page
= --i
;
410 DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n",
411 i
, dev_priv
->dma_pages
[i
].used
, n
);
413 savage_dma_wait(dev_priv
, dev_priv
->current_dma_page
);
418 static void savage_dma_flush(drm_savage_private_t
* dev_priv
)
420 unsigned int first
= dev_priv
->first_dma_page
;
421 unsigned int cur
= dev_priv
->current_dma_page
;
423 unsigned int wrap
, pad
, align
, len
, i
;
424 unsigned long phys_addr
;
428 dev_priv
->dma_pages
[cur
].used
== dev_priv
->dma_pages
[cur
].flushed
)
431 /* pad length to multiples of 2 entries
432 * align start of next DMA block to multiles of 8 entries */
433 pad
= -dev_priv
->dma_pages
[cur
].used
& 1;
434 align
= -(dev_priv
->dma_pages
[cur
].used
+ pad
) & 7;
436 DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, "
437 "pad=%u, align=%u\n",
438 first
, cur
, dev_priv
->dma_pages
[first
].flushed
,
439 dev_priv
->dma_pages
[cur
].used
, pad
, align
);
443 uint32_t *dma_ptr
= (uint32_t *) dev_priv
->cmd_dma
->handle
+
444 cur
* SAVAGE_DMA_PAGE_SIZE
+ dev_priv
->dma_pages
[cur
].used
;
445 dev_priv
->dma_pages
[cur
].used
+= pad
;
447 *dma_ptr
++ = BCI_CMD_WAIT
;
455 phys_addr
= dev_priv
->cmd_dma
->offset
+
456 (first
* SAVAGE_DMA_PAGE_SIZE
+
457 dev_priv
->dma_pages
[first
].flushed
) * 4;
458 len
= (cur
- first
) * SAVAGE_DMA_PAGE_SIZE
+
459 dev_priv
->dma_pages
[cur
].used
- dev_priv
->dma_pages
[first
].flushed
;
461 DRM_DEBUG("phys_addr=%lx, len=%u\n",
462 phys_addr
| dev_priv
->dma_type
, len
);
465 BCI_SET_REGISTERS(SAVAGE_DMABUFADDR
, 1);
466 BCI_WRITE(phys_addr
| dev_priv
->dma_type
);
469 /* fix alignment of the start of the next block */
470 dev_priv
->dma_pages
[cur
].used
+= align
;
473 event
= savage_bci_emit_event(dev_priv
, 0);
474 wrap
= dev_priv
->event_wrap
;
475 for (i
= first
; i
< cur
; ++i
) {
476 SET_AGE(&dev_priv
->dma_pages
[i
].age
, event
, wrap
);
477 dev_priv
->dma_pages
[i
].used
= 0;
478 dev_priv
->dma_pages
[i
].flushed
= 0;
480 /* age the current page only when it's full */
481 if (dev_priv
->dma_pages
[cur
].used
== SAVAGE_DMA_PAGE_SIZE
) {
482 SET_AGE(&dev_priv
->dma_pages
[cur
].age
, event
, wrap
);
483 dev_priv
->dma_pages
[cur
].used
= 0;
484 dev_priv
->dma_pages
[cur
].flushed
= 0;
485 /* advance to next page */
487 if (cur
== dev_priv
->nr_dma_pages
)
489 dev_priv
->first_dma_page
= dev_priv
->current_dma_page
= cur
;
491 dev_priv
->first_dma_page
= cur
;
492 dev_priv
->dma_pages
[cur
].flushed
= dev_priv
->dma_pages
[i
].used
;
494 SET_AGE(&dev_priv
->last_dma_age
, event
, wrap
);
496 DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur
,
497 dev_priv
->dma_pages
[cur
].used
,
498 dev_priv
->dma_pages
[cur
].flushed
);
501 static void savage_fake_dma_flush(drm_savage_private_t
* dev_priv
)
506 if (dev_priv
->first_dma_page
== dev_priv
->current_dma_page
&&
507 dev_priv
->dma_pages
[dev_priv
->current_dma_page
].used
== 0)
510 DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n",
511 dev_priv
->first_dma_page
, dev_priv
->current_dma_page
,
512 dev_priv
->dma_pages
[dev_priv
->current_dma_page
].used
);
514 for (i
= dev_priv
->first_dma_page
;
515 i
<= dev_priv
->current_dma_page
&& dev_priv
->dma_pages
[i
].used
;
517 uint32_t *dma_ptr
= (uint32_t *) dev_priv
->cmd_dma
->handle
+
518 i
* SAVAGE_DMA_PAGE_SIZE
;
520 /* Sanity check: all pages except the last one must be full. */
521 if (i
< dev_priv
->current_dma_page
&&
522 dev_priv
->dma_pages
[i
].used
!= SAVAGE_DMA_PAGE_SIZE
) {
523 DRM_ERROR("partial DMA page %u: used=%u",
524 i
, dev_priv
->dma_pages
[i
].used
);
527 BEGIN_BCI(dev_priv
->dma_pages
[i
].used
);
528 for (j
= 0; j
< dev_priv
->dma_pages
[i
].used
; ++j
) {
529 BCI_WRITE(dma_ptr
[j
]);
531 dev_priv
->dma_pages
[i
].used
= 0;
534 /* reset to first page */
535 dev_priv
->first_dma_page
= dev_priv
->current_dma_page
= 0;
538 int savage_driver_load(struct drm_device
*dev
, unsigned long chipset
)
540 drm_savage_private_t
*dev_priv
;
542 dev_priv
= kzalloc(sizeof(drm_savage_private_t
), GFP_KERNEL
);
543 if (dev_priv
== NULL
)
546 dev
->dev_private
= (void *)dev_priv
;
548 dev_priv
->chipset
= (enum savage_family
)chipset
;
555 * Initialize mappings. On Savage4 and SavageIX the alignment
556 * and size of the aperture is not suitable for automatic MTRR setup
557 * in drm_addmap. Therefore we add them manually before the maps are
558 * initialized, and tear them down on last close.
560 int savage_driver_firstopen(struct drm_device
*dev
)
562 drm_savage_private_t
*dev_priv
= dev
->dev_private
;
563 unsigned long mmio_base
, fb_base
, fb_size
, aperture_base
;
564 /* fb_rsrc and aper_rsrc aren't really used currently, but still exist
565 * in case we decide we need information on the BAR for BSD in the
568 unsigned int fb_rsrc
, aper_rsrc
;
571 dev_priv
->mtrr
[0].handle
= -1;
572 dev_priv
->mtrr
[1].handle
= -1;
573 dev_priv
->mtrr
[2].handle
= -1;
574 if (S3_SAVAGE3D_SERIES(dev_priv
->chipset
)) {
576 fb_base
= pci_resource_start(dev
->pdev
, 0);
577 fb_size
= SAVAGE_FB_SIZE_S3
;
578 mmio_base
= fb_base
+ SAVAGE_FB_SIZE_S3
;
580 aperture_base
= fb_base
+ SAVAGE_APERTURE_OFFSET
;
581 /* this should always be true */
582 if (pci_resource_len(dev
->pdev
, 0) == 0x08000000) {
583 /* Don't make MMIO write-cobining! We need 3
585 dev_priv
->mtrr
[0].base
= fb_base
;
586 dev_priv
->mtrr
[0].size
= 0x01000000;
587 dev_priv
->mtrr
[0].handle
=
588 drm_mtrr_add(dev_priv
->mtrr
[0].base
,
589 dev_priv
->mtrr
[0].size
, DRM_MTRR_WC
);
590 dev_priv
->mtrr
[1].base
= fb_base
+ 0x02000000;
591 dev_priv
->mtrr
[1].size
= 0x02000000;
592 dev_priv
->mtrr
[1].handle
=
593 drm_mtrr_add(dev_priv
->mtrr
[1].base
,
594 dev_priv
->mtrr
[1].size
, DRM_MTRR_WC
);
595 dev_priv
->mtrr
[2].base
= fb_base
+ 0x04000000;
596 dev_priv
->mtrr
[2].size
= 0x04000000;
597 dev_priv
->mtrr
[2].handle
=
598 drm_mtrr_add(dev_priv
->mtrr
[2].base
,
599 dev_priv
->mtrr
[2].size
, DRM_MTRR_WC
);
601 DRM_ERROR("strange pci_resource_len %08llx\n",
603 pci_resource_len(dev
->pdev
, 0));
605 } else if (dev_priv
->chipset
!= S3_SUPERSAVAGE
&&
606 dev_priv
->chipset
!= S3_SAVAGE2000
) {
607 mmio_base
= pci_resource_start(dev
->pdev
, 0);
609 fb_base
= pci_resource_start(dev
->pdev
, 1);
610 fb_size
= SAVAGE_FB_SIZE_S4
;
612 aperture_base
= fb_base
+ SAVAGE_APERTURE_OFFSET
;
613 /* this should always be true */
614 if (pci_resource_len(dev
->pdev
, 1) == 0x08000000) {
615 /* Can use one MTRR to cover both fb and
617 dev_priv
->mtrr
[0].base
= fb_base
;
618 dev_priv
->mtrr
[0].size
= 0x08000000;
619 dev_priv
->mtrr
[0].handle
=
620 drm_mtrr_add(dev_priv
->mtrr
[0].base
,
621 dev_priv
->mtrr
[0].size
, DRM_MTRR_WC
);
623 DRM_ERROR("strange pci_resource_len %08llx\n",
625 pci_resource_len(dev
->pdev
, 1));
628 mmio_base
= pci_resource_start(dev
->pdev
, 0);
630 fb_base
= pci_resource_start(dev
->pdev
, 1);
631 fb_size
= pci_resource_len(dev
->pdev
, 1);
633 aperture_base
= pci_resource_start(dev
->pdev
, 2);
634 /* Automatic MTRR setup will do the right thing. */
637 ret
= drm_addmap(dev
, mmio_base
, SAVAGE_MMIO_SIZE
, _DRM_REGISTERS
,
638 _DRM_READ_ONLY
, &dev_priv
->mmio
);
642 ret
= drm_addmap(dev
, fb_base
, fb_size
, _DRM_FRAME_BUFFER
,
643 _DRM_WRITE_COMBINING
, &dev_priv
->fb
);
647 ret
= drm_addmap(dev
, aperture_base
, SAVAGE_APERTURE_SIZE
,
648 _DRM_FRAME_BUFFER
, _DRM_WRITE_COMBINING
,
649 &dev_priv
->aperture
);
654 * Delete MTRRs and free device-private data.
656 void savage_driver_lastclose(struct drm_device
*dev
)
658 drm_savage_private_t
*dev_priv
= dev
->dev_private
;
661 for (i
= 0; i
< 3; ++i
)
662 if (dev_priv
->mtrr
[i
].handle
>= 0)
663 drm_mtrr_del(dev_priv
->mtrr
[i
].handle
,
664 dev_priv
->mtrr
[i
].base
,
665 dev_priv
->mtrr
[i
].size
, DRM_MTRR_WC
);
668 int savage_driver_unload(struct drm_device
*dev
)
670 drm_savage_private_t
*dev_priv
= dev
->dev_private
;
677 static int savage_do_init_bci(struct drm_device
* dev
, drm_savage_init_t
* init
)
679 drm_savage_private_t
*dev_priv
= dev
->dev_private
;
681 if (init
->fb_bpp
!= 16 && init
->fb_bpp
!= 32) {
682 DRM_ERROR("invalid frame buffer bpp %d!\n", init
->fb_bpp
);
685 if (init
->depth_bpp
!= 16 && init
->depth_bpp
!= 32) {
686 DRM_ERROR("invalid depth buffer bpp %d!\n", init
->fb_bpp
);
689 if (init
->dma_type
!= SAVAGE_DMA_AGP
&&
690 init
->dma_type
!= SAVAGE_DMA_PCI
) {
691 DRM_ERROR("invalid dma memory type %d!\n", init
->dma_type
);
695 dev_priv
->cob_size
= init
->cob_size
;
696 dev_priv
->bci_threshold_lo
= init
->bci_threshold_lo
;
697 dev_priv
->bci_threshold_hi
= init
->bci_threshold_hi
;
698 dev_priv
->dma_type
= init
->dma_type
;
700 dev_priv
->fb_bpp
= init
->fb_bpp
;
701 dev_priv
->front_offset
= init
->front_offset
;
702 dev_priv
->front_pitch
= init
->front_pitch
;
703 dev_priv
->back_offset
= init
->back_offset
;
704 dev_priv
->back_pitch
= init
->back_pitch
;
705 dev_priv
->depth_bpp
= init
->depth_bpp
;
706 dev_priv
->depth_offset
= init
->depth_offset
;
707 dev_priv
->depth_pitch
= init
->depth_pitch
;
709 dev_priv
->texture_offset
= init
->texture_offset
;
710 dev_priv
->texture_size
= init
->texture_size
;
712 dev_priv
->sarea
= drm_getsarea(dev
);
713 if (!dev_priv
->sarea
) {
714 DRM_ERROR("could not find sarea!\n");
715 savage_do_cleanup_bci(dev
);
718 if (init
->status_offset
!= 0) {
719 dev_priv
->status
= drm_core_findmap(dev
, init
->status_offset
);
720 if (!dev_priv
->status
) {
721 DRM_ERROR("could not find shadow status region!\n");
722 savage_do_cleanup_bci(dev
);
726 dev_priv
->status
= NULL
;
728 if (dev_priv
->dma_type
== SAVAGE_DMA_AGP
&& init
->buffers_offset
) {
729 dev
->agp_buffer_token
= init
->buffers_offset
;
730 dev
->agp_buffer_map
= drm_core_findmap(dev
,
731 init
->buffers_offset
);
732 if (!dev
->agp_buffer_map
) {
733 DRM_ERROR("could not find DMA buffer region!\n");
734 savage_do_cleanup_bci(dev
);
737 drm_core_ioremap(dev
->agp_buffer_map
, dev
);
738 if (!dev
->agp_buffer_map
->handle
) {
739 DRM_ERROR("failed to ioremap DMA buffer region!\n");
740 savage_do_cleanup_bci(dev
);
744 if (init
->agp_textures_offset
) {
745 dev_priv
->agp_textures
=
746 drm_core_findmap(dev
, init
->agp_textures_offset
);
747 if (!dev_priv
->agp_textures
) {
748 DRM_ERROR("could not find agp texture region!\n");
749 savage_do_cleanup_bci(dev
);
753 dev_priv
->agp_textures
= NULL
;
756 if (init
->cmd_dma_offset
) {
757 if (S3_SAVAGE3D_SERIES(dev_priv
->chipset
)) {
758 DRM_ERROR("command DMA not supported on "
759 "Savage3D/MX/IX.\n");
760 savage_do_cleanup_bci(dev
);
763 if (dev
->dma
&& dev
->dma
->buflist
) {
764 DRM_ERROR("command and vertex DMA not supported "
765 "at the same time.\n");
766 savage_do_cleanup_bci(dev
);
769 dev_priv
->cmd_dma
= drm_core_findmap(dev
, init
->cmd_dma_offset
);
770 if (!dev_priv
->cmd_dma
) {
771 DRM_ERROR("could not find command DMA region!\n");
772 savage_do_cleanup_bci(dev
);
775 if (dev_priv
->dma_type
== SAVAGE_DMA_AGP
) {
776 if (dev_priv
->cmd_dma
->type
!= _DRM_AGP
) {
777 DRM_ERROR("AGP command DMA region is not a "
779 savage_do_cleanup_bci(dev
);
782 drm_core_ioremap(dev_priv
->cmd_dma
, dev
);
783 if (!dev_priv
->cmd_dma
->handle
) {
784 DRM_ERROR("failed to ioremap command "
786 savage_do_cleanup_bci(dev
);
789 } else if (dev_priv
->cmd_dma
->type
!= _DRM_CONSISTENT
) {
790 DRM_ERROR("PCI command DMA region is not a "
791 "_DRM_CONSISTENT map!\n");
792 savage_do_cleanup_bci(dev
);
796 dev_priv
->cmd_dma
= NULL
;
799 dev_priv
->dma_flush
= savage_dma_flush
;
800 if (!dev_priv
->cmd_dma
) {
801 DRM_DEBUG("falling back to faked command DMA.\n");
802 dev_priv
->fake_dma
.offset
= 0;
803 dev_priv
->fake_dma
.size
= SAVAGE_FAKE_DMA_SIZE
;
804 dev_priv
->fake_dma
.type
= _DRM_SHM
;
805 dev_priv
->fake_dma
.handle
= kmalloc(SAVAGE_FAKE_DMA_SIZE
,
807 if (!dev_priv
->fake_dma
.handle
) {
808 DRM_ERROR("could not allocate faked DMA buffer!\n");
809 savage_do_cleanup_bci(dev
);
812 dev_priv
->cmd_dma
= &dev_priv
->fake_dma
;
813 dev_priv
->dma_flush
= savage_fake_dma_flush
;
816 dev_priv
->sarea_priv
=
817 (drm_savage_sarea_t
*) ((uint8_t *) dev_priv
->sarea
->handle
+
818 init
->sarea_priv_offset
);
820 /* setup bitmap descriptors */
822 unsigned int color_tile_format
;
823 unsigned int depth_tile_format
;
824 unsigned int front_stride
, back_stride
, depth_stride
;
825 if (dev_priv
->chipset
<= S3_SAVAGE4
) {
826 color_tile_format
= dev_priv
->fb_bpp
== 16 ?
827 SAVAGE_BD_TILE_16BPP
: SAVAGE_BD_TILE_32BPP
;
828 depth_tile_format
= dev_priv
->depth_bpp
== 16 ?
829 SAVAGE_BD_TILE_16BPP
: SAVAGE_BD_TILE_32BPP
;
831 color_tile_format
= SAVAGE_BD_TILE_DEST
;
832 depth_tile_format
= SAVAGE_BD_TILE_DEST
;
834 front_stride
= dev_priv
->front_pitch
/ (dev_priv
->fb_bpp
/ 8);
835 back_stride
= dev_priv
->back_pitch
/ (dev_priv
->fb_bpp
/ 8);
837 dev_priv
->depth_pitch
/ (dev_priv
->depth_bpp
/ 8);
839 dev_priv
->front_bd
= front_stride
| SAVAGE_BD_BW_DISABLE
|
840 (dev_priv
->fb_bpp
<< SAVAGE_BD_BPP_SHIFT
) |
841 (color_tile_format
<< SAVAGE_BD_TILE_SHIFT
);
843 dev_priv
->back_bd
= back_stride
| SAVAGE_BD_BW_DISABLE
|
844 (dev_priv
->fb_bpp
<< SAVAGE_BD_BPP_SHIFT
) |
845 (color_tile_format
<< SAVAGE_BD_TILE_SHIFT
);
847 dev_priv
->depth_bd
= depth_stride
| SAVAGE_BD_BW_DISABLE
|
848 (dev_priv
->depth_bpp
<< SAVAGE_BD_BPP_SHIFT
) |
849 (depth_tile_format
<< SAVAGE_BD_TILE_SHIFT
);
852 /* setup status and bci ptr */
853 dev_priv
->event_counter
= 0;
854 dev_priv
->event_wrap
= 0;
855 dev_priv
->bci_ptr
= (volatile uint32_t *)
856 ((uint8_t *) dev_priv
->mmio
->handle
+ SAVAGE_BCI_OFFSET
);
857 if (S3_SAVAGE3D_SERIES(dev_priv
->chipset
)) {
858 dev_priv
->status_used_mask
= SAVAGE_FIFO_USED_MASK_S3D
;
860 dev_priv
->status_used_mask
= SAVAGE_FIFO_USED_MASK_S4
;
862 if (dev_priv
->status
!= NULL
) {
863 dev_priv
->status_ptr
=
864 (volatile uint32_t *)dev_priv
->status
->handle
;
865 dev_priv
->wait_fifo
= savage_bci_wait_fifo_shadow
;
866 dev_priv
->wait_evnt
= savage_bci_wait_event_shadow
;
867 dev_priv
->status_ptr
[1023] = dev_priv
->event_counter
;
869 dev_priv
->status_ptr
= NULL
;
870 if (S3_SAVAGE3D_SERIES(dev_priv
->chipset
)) {
871 dev_priv
->wait_fifo
= savage_bci_wait_fifo_s3d
;
873 dev_priv
->wait_fifo
= savage_bci_wait_fifo_s4
;
875 dev_priv
->wait_evnt
= savage_bci_wait_event_reg
;
878 /* cliprect functions */
879 if (S3_SAVAGE3D_SERIES(dev_priv
->chipset
))
880 dev_priv
->emit_clip_rect
= savage_emit_clip_rect_s3d
;
882 dev_priv
->emit_clip_rect
= savage_emit_clip_rect_s4
;
884 if (savage_freelist_init(dev
) < 0) {
885 DRM_ERROR("could not initialize freelist\n");
886 savage_do_cleanup_bci(dev
);
890 if (savage_dma_init(dev_priv
) < 0) {
891 DRM_ERROR("could not initialize command DMA\n");
892 savage_do_cleanup_bci(dev
);
899 static int savage_do_cleanup_bci(struct drm_device
* dev
)
901 drm_savage_private_t
*dev_priv
= dev
->dev_private
;
903 if (dev_priv
->cmd_dma
== &dev_priv
->fake_dma
) {
904 kfree(dev_priv
->fake_dma
.handle
);
905 } else if (dev_priv
->cmd_dma
&& dev_priv
->cmd_dma
->handle
&&
906 dev_priv
->cmd_dma
->type
== _DRM_AGP
&&
907 dev_priv
->dma_type
== SAVAGE_DMA_AGP
)
908 drm_core_ioremapfree(dev_priv
->cmd_dma
, dev
);
910 if (dev_priv
->dma_type
== SAVAGE_DMA_AGP
&&
911 dev
->agp_buffer_map
&& dev
->agp_buffer_map
->handle
) {
912 drm_core_ioremapfree(dev
->agp_buffer_map
, dev
);
913 /* make sure the next instance (which may be running
914 * in PCI mode) doesn't try to use an old
916 dev
->agp_buffer_map
= NULL
;
919 kfree(dev_priv
->dma_pages
);
924 static int savage_bci_init(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
926 drm_savage_init_t
*init
= data
;
928 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
930 switch (init
->func
) {
931 case SAVAGE_INIT_BCI
:
932 return savage_do_init_bci(dev
, init
);
933 case SAVAGE_CLEANUP_BCI
:
934 return savage_do_cleanup_bci(dev
);
940 static int savage_bci_event_emit(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
942 drm_savage_private_t
*dev_priv
= dev
->dev_private
;
943 drm_savage_event_emit_t
*event
= data
;
947 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
949 event
->count
= savage_bci_emit_event(dev_priv
, event
->flags
);
950 event
->count
|= dev_priv
->event_wrap
<< 16;
955 static int savage_bci_event_wait(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
957 drm_savage_private_t
*dev_priv
= dev
->dev_private
;
958 drm_savage_event_wait_t
*event
= data
;
959 unsigned int event_e
, hw_e
;
960 unsigned int event_w
, hw_w
;
964 UPDATE_EVENT_COUNTER();
965 if (dev_priv
->status_ptr
)
966 hw_e
= dev_priv
->status_ptr
[1] & 0xffff;
968 hw_e
= SAVAGE_READ(SAVAGE_STATUS_WORD1
) & 0xffff;
969 hw_w
= dev_priv
->event_wrap
;
970 if (hw_e
> dev_priv
->event_counter
)
971 hw_w
--; /* hardware hasn't passed the last wrap yet */
973 event_e
= event
->count
& 0xffff;
974 event_w
= event
->count
>> 16;
976 /* Don't need to wait if
977 * - event counter wrapped since the event was emitted or
978 * - the hardware has advanced up to or over the event to wait for.
980 if (event_w
< hw_w
|| (event_w
== hw_w
&& event_e
<= hw_e
))
983 return dev_priv
->wait_evnt(dev_priv
, event_e
);
987 * DMA buffer management
990 static int savage_bci_get_buffers(struct drm_device
*dev
,
991 struct drm_file
*file_priv
,
997 for (i
= d
->granted_count
; i
< d
->request_count
; i
++) {
998 buf
= savage_freelist_get(dev
);
1002 buf
->file_priv
= file_priv
;
1004 if (DRM_COPY_TO_USER(&d
->request_indices
[i
],
1005 &buf
->idx
, sizeof(buf
->idx
)))
1007 if (DRM_COPY_TO_USER(&d
->request_sizes
[i
],
1008 &buf
->total
, sizeof(buf
->total
)))
1016 int savage_bci_buffers(struct drm_device
*dev
, void *data
, struct drm_file
*file_priv
)
1018 struct drm_device_dma
*dma
= dev
->dma
;
1019 struct drm_dma
*d
= data
;
1022 LOCK_TEST_WITH_RETURN(dev
, file_priv
);
1024 /* Please don't send us buffers.
1026 if (d
->send_count
!= 0) {
1027 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1028 DRM_CURRENTPID
, d
->send_count
);
1032 /* We'll send you buffers.
1034 if (d
->request_count
< 0 || d
->request_count
> dma
->buf_count
) {
1035 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1036 DRM_CURRENTPID
, d
->request_count
, dma
->buf_count
);
1040 d
->granted_count
= 0;
1042 if (d
->request_count
) {
1043 ret
= savage_bci_get_buffers(dev
, file_priv
, d
);
1049 void savage_reclaim_buffers(struct drm_device
*dev
, struct drm_file
*file_priv
)
1051 struct drm_device_dma
*dma
= dev
->dma
;
1052 drm_savage_private_t
*dev_priv
= dev
->dev_private
;
1062 /*i830_flush_queue(dev); */
1064 for (i
= 0; i
< dma
->buf_count
; i
++) {
1065 struct drm_buf
*buf
= dma
->buflist
[i
];
1066 drm_savage_buf_priv_t
*buf_priv
= buf
->dev_private
;
1068 if (buf
->file_priv
== file_priv
&& buf_priv
&&
1069 buf_priv
->next
== NULL
&& buf_priv
->prev
== NULL
) {
1071 DRM_DEBUG("reclaimed from client\n");
1072 event
= savage_bci_emit_event(dev_priv
, SAVAGE_WAIT_3D
);
1073 SET_AGE(&buf_priv
->age
, event
, dev_priv
->event_wrap
);
1074 savage_freelist_put(dev
, buf
);
1078 drm_core_reclaim_buffers(dev
, file_priv
);
1081 struct drm_ioctl_desc savage_ioctls
[] = {
1082 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_INIT
, savage_bci_init
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1083 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_CMDBUF
, savage_bci_cmdbuf
, DRM_AUTH
),
1084 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_EMIT
, savage_bci_event_emit
, DRM_AUTH
),
1085 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_WAIT
, savage_bci_event_wait
, DRM_AUTH
),
1088 int savage_max_ioctl
= DRM_ARRAY_SIZE(savage_ioctls
);