arch/mips/boot/dts/pic32/pic32mzda.dtsi

   1 /*
   2  * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11
  12 #include "pic32mzda-clk.dtsi"
  13
  14 / {
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17         interrupt-parent = <&evic>;
  18
  19         aliases {
  20                 gpio0 = &gpio0;
  21                 gpio1 = &gpio1;
  22                 gpio2 = &gpio2;
  23                 gpio3 = &gpio3;
  24                 gpio4 = &gpio4;
  25                 gpio5 = &gpio5;
  26                 gpio6 = &gpio6;
  27                 gpio7 = &gpio7;
  28                 gpio8 = &gpio8;
  29                 gpio9 = &gpio9;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 serial5 = &uart6;
  36         };
  37
  38         cpus {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 cpu@0 {
  43                         compatible = "mti,mips14KEc";
  44                         device_type = "cpu";
  45                 };
  46         };
  47
  48         soc {
  49                 compatible = "microchip,pic32mzda-infra";
  50                 interrupts = <0 IRQ_TYPE_EDGE_RISING>;
  51         };
  52
  53         evic: interrupt-controller@1f810000 {
  54                 compatible = "microchip,pic32mzda-evic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <2>;
  57                 reg = <0x1f810000 0x1000>;
  58                 microchip,external-irqs = <3 8 13 18 23>;
  59         };
  60
  61         pic32_pinctrl: pinctrl@1f801400{
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 compatible = "microchip,pic32mzda-pinctrl";
  65                 reg = <0x1f801400 0x400>;
  66                 clocks = <&PBCLK1>;
  67         };
  68
  69         /* PORTA */
  70         gpio0: gpio0@1f860000 {
  71                 compatible = "microchip,pic32mzda-gpio";
  72                 reg = <0x1f860000 0x100>;
  73                 interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
  74                 #gpio-cells = <2>;
  75                 gpio-controller;
  76                 interrupt-controller;
  77                 #interrupt-cells = <2>;
  78                 clocks = <&PBCLK4>;
  79                 microchip,gpio-bank = <0>;
  80                 gpio-ranges = <&pic32_pinctrl 0 0 16>;
  81         };
  82
  83         /* PORTB */
  84         gpio1: gpio1@1f860100 {
  85                 compatible = "microchip,pic32mzda-gpio";
  86                 reg = <0x1f860100 0x100>;
  87                 interrupts = <119 IRQ_TYPE_LEVEL_HIGH>;
  88                 #gpio-cells = <2>;
  89                 gpio-controller;
  90                 interrupt-controller;
  91                 #interrupt-cells = <2>;
  92                 clocks = <&PBCLK4>;
  93                 microchip,gpio-bank = <1>;
  94                 gpio-ranges = <&pic32_pinctrl 0 16 16>;
  95         };
  96
  97         /* PORTC */
  98         gpio2: gpio2@1f860200 {
  99                 compatible = "microchip,pic32mzda-gpio";
 100                 reg = <0x1f860200 0x100>;
 101                 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
 102                 #gpio-cells = <2>;
 103                 gpio-controller;
 104                 interrupt-controller;
 105                 #interrupt-cells = <2>;
 106                 clocks = <&PBCLK4>;
 107                 microchip,gpio-bank = <2>;
 108                 gpio-ranges = <&pic32_pinctrl 0 32 16>;
 109         };
 110
 111         /* PORTD */
 112         gpio3: gpio3@1f860300 {
 113                 compatible = "microchip,pic32mzda-gpio";
 114                 reg = <0x1f860300 0x100>;
 115                 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
 116                 #gpio-cells = <2>;
 117                 gpio-controller;
 118                 interrupt-controller;
 119                 #interrupt-cells = <2>;
 120                 clocks = <&PBCLK4>;
 121                 microchip,gpio-bank = <3>;
 122                 gpio-ranges = <&pic32_pinctrl 0 48 16>;
 123         };
 124
 125         /* PORTE */
 126         gpio4: gpio4@1f860400 {
 127                 compatible = "microchip,pic32mzda-gpio";
 128                 reg = <0x1f860400 0x100>;
 129                 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
 130                 #gpio-cells = <2>;
 131                 gpio-controller;
 132                 interrupt-controller;
 133                 #interrupt-cells = <2>;
 134                 clocks = <&PBCLK4>;
 135                 microchip,gpio-bank = <4>;
 136                 gpio-ranges = <&pic32_pinctrl 0 64 16>;
 137         };
 138
 139         /* PORTF */
 140         gpio5: gpio5@1f860500 {
 141                 compatible = "microchip,pic32mzda-gpio";
 142                 reg = <0x1f860500 0x100>;
 143                 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
 144                 #gpio-cells = <2>;
 145                 gpio-controller;
 146                 interrupt-controller;
 147                 #interrupt-cells = <2>;
 148                 clocks = <&PBCLK4>;
 149                 microchip,gpio-bank = <5>;
 150                 gpio-ranges = <&pic32_pinctrl 0 80 16>;
 151         };
 152
 153         /* PORTG */
 154         gpio6: gpio6@1f860600 {
 155                 compatible = "microchip,pic32mzda-gpio";
 156                 reg = <0x1f860600 0x100>;
 157                 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
 158                 #gpio-cells = <2>;
 159                 gpio-controller;
 160                 interrupt-controller;
 161                 #interrupt-cells = <2>;
 162                 clocks = <&PBCLK4>;
 163                 microchip,gpio-bank = <6>;
 164                 gpio-ranges = <&pic32_pinctrl 0 96 16>;
 165         };
 166
 167         /* PORTH */
 168         gpio7: gpio7@1f860700 {
 169                 compatible = "microchip,pic32mzda-gpio";
 170                 reg = <0x1f860700 0x100>;
 171                 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
 172                 #gpio-cells = <2>;
 173                 gpio-controller;
 174                 interrupt-controller;
 175                 #interrupt-cells = <2>;
 176                 clocks = <&PBCLK4>;
 177                 microchip,gpio-bank = <7>;
 178                 gpio-ranges = <&pic32_pinctrl 0 112 16>;
 179         };
 180
 181         /* PORTI does not exist */
 182
 183         /* PORTJ */
 184         gpio8: gpio8@1f860800 {
 185                 compatible = "microchip,pic32mzda-gpio";
 186                 reg = <0x1f860800 0x100>;
 187                 interrupts = <126 IRQ_TYPE_LEVEL_HIGH>;
 188                 #gpio-cells = <2>;
 189                 gpio-controller;
 190                 interrupt-controller;
 191                 #interrupt-cells = <2>;
 192                 clocks = <&PBCLK4>;
 193                 microchip,gpio-bank = <8>;
 194                 gpio-ranges = <&pic32_pinctrl 0 128 16>;
 195         };
 196
 197         /* PORTK */
 198         gpio9: gpio9@1f860900 {
 199                 compatible = "microchip,pic32mzda-gpio";
 200                 reg = <0x1f860900 0x100>;
 201                 interrupts = <127 IRQ_TYPE_LEVEL_HIGH>;
 202                 #gpio-cells = <2>;
 203                 gpio-controller;
 204                 interrupt-controller;
 205                 #interrupt-cells = <2>;
 206                 clocks = <&PBCLK4>;
 207                 microchip,gpio-bank = <9>;
 208                 gpio-ranges = <&pic32_pinctrl 0 144 16>;
 209         };
 210
 211         sdhci: sdhci@1f8ec000 {
 212                 compatible = "microchip,pic32mzda-sdhci";
 213                 reg = <0x1f8ec000 0x100>;
 214                 interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
 215                 clocks = <&REFCLKO4>, <&PBCLK5>;
 216                 clock-names = "base_clk", "sys_clk";
 217                 bus-width = <4>;
 218                 cap-sd-highspeed;
 219                 status = "disabled";
 220         };
 221
 222         uart1: serial@1f822000 {
 223                 compatible = "microchip,pic32mzda-uart";
 224                 reg = <0x1f822000 0x50>;
 225                 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
 226                         <113 IRQ_TYPE_LEVEL_HIGH>,
 227                         <114 IRQ_TYPE_LEVEL_HIGH>;
 228                 clocks = <&PBCLK2>;
 229                 status = "disabled";
 230         };
 231
 232         uart2: serial@1f822200 {
 233                 compatible = "microchip,pic32mzda-uart";
 234                 reg = <0x1f822200 0x50>;
 235                 interrupts = <145 IRQ_TYPE_LEVEL_HIGH>,
 236                         <146 IRQ_TYPE_LEVEL_HIGH>,
 237                         <147 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&PBCLK2>;
 239                 status = "disabled";
 240         };
 241
 242         uart3: serial@1f822400 {
 243                 compatible = "microchip,pic32mzda-uart";
 244                 reg = <0x1f822400 0x50>;
 245                 interrupts = <157 IRQ_TYPE_LEVEL_HIGH>,
 246                         <158 IRQ_TYPE_LEVEL_HIGH>,
 247                         <159 IRQ_TYPE_LEVEL_HIGH>;
 248                 clocks = <&PBCLK2>;
 249                 status = "disabled";
 250         };
 251
 252         uart4: serial@1f822600 {
 253                 compatible = "microchip,pic32mzda-uart";
 254                 reg = <0x1f822600 0x50>;
 255                 interrupts = <170 IRQ_TYPE_LEVEL_HIGH>,
 256                         <171 IRQ_TYPE_LEVEL_HIGH>,
 257                         <172 IRQ_TYPE_LEVEL_HIGH>;
 258                 clocks = <&PBCLK2>;
 259                 status = "disabled";
 260         };
 261
 262         uart5: serial@1f822800 {
 263                 compatible = "microchip,pic32mzda-uart";
 264                 reg = <0x1f822800 0x50>;
 265                 interrupts = <179 IRQ_TYPE_LEVEL_HIGH>,
 266                         <180 IRQ_TYPE_LEVEL_HIGH>,
 267                         <181 IRQ_TYPE_LEVEL_HIGH>;
 268                 clocks = <&PBCLK2>;
 269                 status = "disabled";
 270         };
 271
 272         uart6: serial@1f822A00 {
 273                 compatible = "microchip,pic32mzda-uart";
 274                 reg = <0x1f822A00 0x50>;
 275                 interrupts = <188 IRQ_TYPE_LEVEL_HIGH>,
 276                         <189 IRQ_TYPE_LEVEL_HIGH>,
 277                         <190 IRQ_TYPE_LEVEL_HIGH>;
 278                 clocks = <&PBCLK2>;
 279                 status = "disabled";
 280         };
 281 };