| blob | 80c69472314ea9a2d104be987c4fb1f030b11130 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
22 #include <linux/init.h>
23 #include <asm/processor.h>
24 #include <asm/page.h>
25 #include <asm/mmu.h>
26 #include <asm/cache.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/ptrace.h>
34 /* Macro to make the code more readable. */
35 #ifdef CONFIG_8xx_CPU6
36 #define SPRN_MI_TWC_ADDR 0x2b80
37 #define SPRN_MI_RPN_ADDR 0x2d80
38 #define SPRN_MD_TWC_ADDR 0x3b80
39 #define SPRN_MD_RPN_ADDR 0x3d80
41 #define MTSPR_CPU6(spr, reg, treg) \
42 li treg, spr##_ADDR; \
43 stw treg, 12(r0); \
44 lwz treg, 12(r0); \
45 mtspr spr, reg
46 #else
47 #define MTSPR_CPU6(spr, reg, treg) \
48 mtspr spr, reg
49 #endif
51 /* Macro to test if an address is a kernel address */
52 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
53 #define IS_KERNEL(tmp, addr) \
54 andis. tmp, addr, 0x8000 /* Address >= 0x80000000 */
55 #define BRANCH_UNLESS_KERNEL(label) beq label
56 #else
57 #define IS_KERNEL(tmp, addr) \
58 rlwinm tmp, addr, 16, 16, 31; \
59 cmpli cr0, tmp, PAGE_OFFSET >> 16
60 #define BRANCH_UNLESS_KERNEL(label) blt label
61 #endif
64 /*
65 * Value for the bits that have fixed value in RPN entries.
66 * Also used for tagging DAR for DTLBerror.
67 */
68 #ifdef CONFIG_PPC_16K_PAGES
69 #define RPN_PATTERN (0x00f0 | MD_SPS16K)
70 #else
71 #define RPN_PATTERN 0x00f0
72 #endif
74 __HEAD
75 _ENTRY(_stext);
76 _ENTRY(_start);
78 /* MPC8xx
79 * This port was done on an MBX board with an 860. Right now I only
80 * support an ELF compressed (zImage) boot from EPPC-Bug because the
81 * code there loads up some registers before calling us:
82 * r3: ptr to board info data
83 * r4: initrd_start or if no initrd then 0
84 * r5: initrd_end - unused if r4 is 0
85 * r6: Start of command line string
86 * r7: End of command line string
87 *
88 * I decided to use conditional compilation instead of checking PVR and
89 * adding more processor specific branches around code I don't need.
90 * Since this is an embedded processor, I also appreciate any memory
91 * savings I can get.
92 *
93 * The MPC8xx does not have any BATs, but it supports large page sizes.
94 * We first initialize the MMU to support 8M byte pages, then load one
95 * entry into each of the instruction and data TLBs to map the first
96 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
97 * the "internal" processor registers before MMU_init is called.
98 *
99 * -- Dan
100 */
101 .globl __start
102 __start:
103 mr r31,r3 /* save device tree ptr */
105 /* We have to turn on the MMU right away so we get cache modes
106 * set correctly.
107 */
108 bl initial_mmu
110 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
111 * ready to work.
112 */
114 turn_on_mmu:
115 mfmsr r0
116 ori r0,r0,MSR_DR|MSR_IR
117 mtspr SPRN_SRR1,r0
118 lis r0,start_here@h
119 ori r0,r0,start_here@l
120 mtspr SPRN_SRR0,r0
121 SYNC
122 rfi /* enables MMU */
124 /*
125 * Exception entry code. This code runs with address translation
126 * turned off, i.e. using physical addresses.
127 * We assume sprg3 has the physical address of the current
128 * task's thread_struct.
129 */
130 #define EXCEPTION_PROLOG \
131 EXCEPTION_PROLOG_0; \
132 mfcr r10; \
133 EXCEPTION_PROLOG_1; \
134 EXCEPTION_PROLOG_2
136 #define EXCEPTION_PROLOG_0 \
137 mtspr SPRN_SPRG_SCRATCH0,r10; \
138 mtspr SPRN_SPRG_SCRATCH1,r11
140 #define EXCEPTION_PROLOG_1 \
141 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
142 andi. r11,r11,MSR_PR; \
143 tophys(r11,r1); /* use tophys(r1) if kernel */ \
144 beq 1f; \
145 mfspr r11,SPRN_SPRG_THREAD; \
146 lwz r11,THREAD_INFO-THREAD(r11); \
147 addi r11,r11,THREAD_SIZE; \
148 tophys(r11,r11); \
149 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
152 #define EXCEPTION_PROLOG_2 \
153 CLR_TOP32(r11); \
154 stw r10,_CCR(r11); /* save registers */ \
155 stw r12,GPR12(r11); \
156 stw r9,GPR9(r11); \
157 mfspr r10,SPRN_SPRG_SCRATCH0; \
158 stw r10,GPR10(r11); \
159 mfspr r12,SPRN_SPRG_SCRATCH1; \
160 stw r12,GPR11(r11); \
161 mflr r10; \
162 stw r10,_LINK(r11); \
163 mfspr r12,SPRN_SRR0; \
164 mfspr r9,SPRN_SRR1; \
165 stw r1,GPR1(r11); \
166 stw r1,0(r11); \
167 tovirt(r1,r11); /* set new kernel sp */ \
168 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
169 MTMSRD(r10); /* (except for mach check in rtas) */ \
170 stw r0,GPR0(r11); \
171 SAVE_4GPRS(3, r11); \
172 SAVE_2GPRS(7, r11)
174 /*
175 * Exception exit code.
176 */
177 #define EXCEPTION_EPILOG_0 \
178 mfspr r10,SPRN_SPRG_SCRATCH0; \
179 mfspr r11,SPRN_SPRG_SCRATCH1
181 /*
182 * Note: code which follows this uses cr0.eq (set if from kernel),
183 * r11, r12 (SRR0), and r9 (SRR1).
184 *
185 * Note2: once we have set r1 we are in a position to take exceptions
186 * again, and we could thus set MSR:RI at that point.
187 */
189 /*
190 * Exception vectors.
191 */
192 #define EXCEPTION(n, label, hdlr, xfer) \
193 . = n; \
194 label: \
195 EXCEPTION_PROLOG; \
196 addi r3,r1,STACK_FRAME_OVERHEAD; \
197 xfer(n, hdlr)
199 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
200 li r10,trap; \
201 stw r10,_TRAP(r11); \
202 li r10,MSR_KERNEL; \
203 copyee(r10, r9); \
204 bl tfer; \
205 i##n: \
206 .long hdlr; \
207 .long ret
209 #define COPY_EE(d, s) rlwimi d,s,0,16,16
210 #define NOCOPY(d, s)
212 #define EXC_XFER_STD(n, hdlr) \
213 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
214 ret_from_except_full)
216 #define EXC_XFER_LITE(n, hdlr) \
217 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
218 ret_from_except)
220 #define EXC_XFER_EE(n, hdlr) \
221 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
222 ret_from_except_full)
224 #define EXC_XFER_EE_LITE(n, hdlr) \
225 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
226 ret_from_except)
228 /* System reset */
229 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
231 /* Machine check */
232 . = 0x200
233 MachineCheck:
234 EXCEPTION_PROLOG
235 mfspr r4,SPRN_DAR
236 stw r4,_DAR(r11)
237 li r5,RPN_PATTERN
238 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
239 mfspr r5,SPRN_DSISR
240 stw r5,_DSISR(r11)
241 addi r3,r1,STACK_FRAME_OVERHEAD
242 EXC_XFER_STD(0x200, machine_check_exception)
244 /* Data access exception.
245 * This is "never generated" by the MPC8xx.
246 */
247 . = 0x300
248 DataAccess:
250 /* Instruction access exception.
251 * This is "never generated" by the MPC8xx.
252 */
253 . = 0x400
254 InstructionAccess:
256 /* External interrupt */
257 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
259 /* Alignment exception */
260 . = 0x600
261 Alignment:
262 EXCEPTION_PROLOG
263 mfspr r4,SPRN_DAR
264 stw r4,_DAR(r11)
265 li r5,RPN_PATTERN
266 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
267 mfspr r5,SPRN_DSISR
268 stw r5,_DSISR(r11)
269 addi r3,r1,STACK_FRAME_OVERHEAD
270 EXC_XFER_EE(0x600, alignment_exception)
272 /* Program check exception */
273 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
275 /* No FPU on MPC8xx. This exception is not supposed to happen.
276 */
277 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
279 /* Decrementer */
280 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
282 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
283 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
285 /* System call */
286 . = 0xc00
287 SystemCall:
288 EXCEPTION_PROLOG
289 EXC_XFER_EE_LITE(0xc00, DoSyscall)
291 /* Single step - not used on 601 */
292 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
293 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
294 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
296 /* On the MPC8xx, this is a software emulation interrupt. It occurs
297 * for all unimplemented and illegal instructions.
298 */
299 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
301 . = 0x1100
302 /*
303 * For the MPC8xx, this is a software tablewalk to load the instruction
304 * TLB. The task switch loads the M_TW register with the pointer to the first
305 * level table.
306 * If we discover there is no second level table (value is zero) or if there
307 * is an invalid pte, we load that into the TLB, which causes another fault
308 * into the TLB Error interrupt where we can handle such problems.
309 * We have to use the MD_xxx registers for the tablewalk because the
310 * equivalent MI_xxx registers only perform the attribute functions.
311 */
313 #ifdef CONFIG_8xx_CPU15
314 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \
315 addi tmp, addr, PAGE_SIZE; \
316 tlbie tmp; \
317 addi tmp, addr, -PAGE_SIZE; \
318 tlbie tmp
319 #else
320 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr)
321 #endif
323 InstructionTLBMiss:
324 #ifdef CONFIG_8xx_CPU6
325 mtspr SPRN_SPRG_SCRATCH2, r3
326 #endif
327 EXCEPTION_PROLOG_0
329 /* If we are faulting a kernel address, we have to use the
330 * kernel page tables.
331 */
332 #if defined(CONFIG_MODULES) || defined (CONFIG_DEBUG_PAGEALLOC)
333 /* Only modules will cause ITLB Misses as we always
334 * pin the first 8MB of kernel memory */
335 mfspr r11, SPRN_SRR0 /* Get effective address of fault */
336 INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11)
337 mfcr r10
338 IS_KERNEL(r11, r11)
339 mfspr r11, SPRN_M_TW /* Get level 1 table */
340 BRANCH_UNLESS_KERNEL(3f)
341 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
342 3:
343 mtcr r10
344 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
345 #else
346 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
347 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
348 mfspr r11, SPRN_M_TW /* Get level 1 table base address */
349 #endif
350 /* Insert level 1 index */
351 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
352 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
354 /* Extract level 2 index */
355 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
356 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
357 lwz r10, 0(r10) /* Get the pte */
359 /* Insert the APG into the TWC from the Linux PTE. */
360 rlwimi r11, r10, 0, 25, 26
361 /* Load the MI_TWC with the attributes for this "segment." */
362 MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
364 #ifdef CONFIG_SWAP
365 rlwinm r11, r10, 32-5, _PAGE_PRESENT
366 and r11, r11, r10
367 rlwimi r10, r11, 0, _PAGE_PRESENT
368 #endif
369 li r11, RPN_PATTERN
370 /* The Linux PTE won't go exactly into the MMU TLB.
371 * Software indicator bits 20-23 and 28 must be clear.
372 * Software indicator bits 24, 25, 26, and 27 must be
373 * set. All other Linux PTE bits control the behavior
374 * of the MMU.
375 */
376 rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */
377 MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */
379 /* Restore registers */
380 #ifdef CONFIG_8xx_CPU6
381 mfspr r3, SPRN_SPRG_SCRATCH2
382 #endif
383 EXCEPTION_EPILOG_0
384 rfi
386 . = 0x1200
387 DataStoreTLBMiss:
388 mtspr SPRN_SPRG_SCRATCH2, r3
389 EXCEPTION_PROLOG_0
390 mfcr r3
392 /* If we are faulting a kernel address, we have to use the
393 * kernel page tables.
394 */
395 mfspr r10, SPRN_MD_EPN
396 IS_KERNEL(r11, r10)
397 mfspr r11, SPRN_M_TW /* Get level 1 table */
398 BRANCH_UNLESS_KERNEL(3f)
399 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
400 3:
402 /* Insert level 1 index */
403 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
404 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
405 mtcr r11
406 bt- 28,DTLBMiss8M /* bit 28 = Large page (8M) */
407 mtcr r3
409 /* We have a pte table, so load fetch the pte from the table.
410 */
411 /* Extract level 2 index */
412 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
413 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
414 lwz r10, 0(r10) /* Get the pte */
416 /* Insert the Guarded flag and APG into the TWC from the Linux PTE.
417 * It is bit 26-27 of both the Linux PTE and the TWC (at least
418 * I got that right :-). It will be better when we can put
419 * this into the Linux pgd/pmd and load it in the operation
420 * above.
421 */
422 rlwimi r11, r10, 0, 26, 27
423 /* Insert the WriteThru flag into the TWC from the Linux PTE.
424 * It is bit 25 in the Linux PTE and bit 30 in the TWC
425 */
426 rlwimi r11, r10, 32-5, 30, 30
427 MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
429 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
430 * We also need to know if the insn is a load/store, so:
431 * Clear _PAGE_PRESENT and load that which will
432 * trap into DTLB Error with store bit set accordinly.
433 */
434 /* PRESENT=0x1, ACCESSED=0x20
435 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
436 * r10 = (r10 & ~PRESENT) | r11;
437 */
438 #ifdef CONFIG_SWAP
439 rlwinm r11, r10, 32-5, _PAGE_PRESENT
440 and r11, r11, r10
441 rlwimi r10, r11, 0, _PAGE_PRESENT
442 #endif
443 /* The Linux PTE won't go exactly into the MMU TLB.
444 * Software indicator bits 22 and 28 must be clear.
445 * Software indicator bits 24, 25, 26, and 27 must be
446 * set. All other Linux PTE bits control the behavior
447 * of the MMU.
448 */
449 li r11, RPN_PATTERN
450 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
451 rlwimi r10, r11, 0, 20, 20 /* clear 20 */
452 MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
454 /* Restore registers */
455 mfspr r3, SPRN_SPRG_SCRATCH2
456 mtspr SPRN_DAR, r11 /* Tag DAR */
457 EXCEPTION_EPILOG_0
458 rfi
460 DTLBMiss8M:
461 mtcr r3
462 ori r11, r11, MD_SVALID
463 MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
464 #ifdef CONFIG_PPC_16K_PAGES
465 /*
466 * In 16k pages mode, each PGD entry defines a 64M block.
467 * Here we select the 8M page within the block.
468 */
469 rlwimi r11, r10, 0, 0x03800000
470 #endif
471 rlwinm r10, r11, 0, 0xff800000
472 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
473 _PAGE_PRESENT
474 MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
476 li r11, RPN_PATTERN
477 mfspr r3, SPRN_SPRG_SCRATCH2
478 mtspr SPRN_DAR, r11 /* Tag DAR */
479 EXCEPTION_EPILOG_0
480 rfi
483 /* This is an instruction TLB error on the MPC8xx. This could be due
484 * to many reasons, such as executing guarded memory or illegal instruction
485 * addresses. There is nothing to do but handle a big time error fault.
486 */
487 . = 0x1300
488 InstructionTLBError:
489 EXCEPTION_PROLOG
490 mr r4,r12
491 mr r5,r9
492 andis. r10,r5,0x4000
493 beq+ 1f
494 tlbie r4
495 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
496 1: EXC_XFER_LITE(0x400, handle_page_fault)
498 /* This is the data TLB error on the MPC8xx. This could be due to
499 * many reasons, including a dirty update to a pte. We bail out to
500 * a higher level function that can handle it.
501 */
502 . = 0x1400
503 DataTLBError:
504 EXCEPTION_PROLOG_0
505 mfcr r10
507 mfspr r11, SPRN_DAR
508 cmpwi cr0, r11, RPN_PATTERN
509 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
510 DARFixed:/* Return from dcbx instruction bug workaround */
511 EXCEPTION_PROLOG_1
512 EXCEPTION_PROLOG_2
513 mfspr r5,SPRN_DSISR
514 stw r5,_DSISR(r11)
515 mfspr r4,SPRN_DAR
516 andis. r10,r5,0x4000
517 beq+ 1f
518 tlbie r4
519 1: li r10,RPN_PATTERN
520 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
521 /* 0x300 is DataAccess exception, needed by bad_page_fault() */
522 EXC_XFER_LITE(0x300, handle_page_fault)
524 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
525 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
526 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
527 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
528 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
529 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
530 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
532 /* On the MPC8xx, these next four traps are used for development
533 * support of breakpoints and such. Someday I will get around to
534 * using them.
535 */
536 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
537 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
538 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
539 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
541 . = 0x2000
543 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
544 * by decoding the registers used by the dcbx instruction and adding them.
545 * DAR is set to the calculated address.
546 */
547 /* define if you don't want to use self modifying code */
548 #define NO_SELF_MODIFYING_CODE
549 FixupDAR:/* Entry point for dcbx workaround. */
550 mtspr SPRN_SPRG_SCRATCH2, r10
551 /* fetch instruction from memory. */
552 mfspr r10, SPRN_SRR0
553 IS_KERNEL(r11, r10)
554 mfspr r11, SPRN_M_TW /* Get level 1 table */
555 BRANCH_UNLESS_KERNEL(3f)
556 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
557 /* Insert level 1 index */
558 3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
559 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
560 mtcr r11
561 bt 28,200f /* bit 28 = Large page (8M) */
562 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */
563 /* Insert level 2 index */
564 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
565 lwz r11, 0(r11) /* Get the pte */
566 /* concat physical page address(r11) and page offset(r10) */
567 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
568 201: lwz r11,0(r11)
569 /* Check if it really is a dcbx instruction. */
570 /* dcbt and dcbtst does not generate DTLB Misses/Errors,
571 * no need to include them here */
572 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
573 rlwinm r10, r10, 0, 21, 5
574 cmpwi cr0, r10, 2028 /* Is dcbz? */
575 beq+ 142f
576 cmpwi cr0, r10, 940 /* Is dcbi? */
577 beq+ 142f
578 cmpwi cr0, r10, 108 /* Is dcbst? */
579 beq+ 144f /* Fix up store bit! */
580 cmpwi cr0, r10, 172 /* Is dcbf? */
581 beq+ 142f
582 cmpwi cr0, r10, 1964 /* Is icbi? */
583 beq+ 142f
584 141: mfspr r10,SPRN_SPRG_SCRATCH2
585 b DARFixed /* Nope, go back to normal TLB processing */
587 /* concat physical page address(r11) and page offset(r10) */
588 200: rlwimi r11, r10, 0, 32 - (PAGE_SHIFT << 1), 31
589 b 201b
591 144: mfspr r10, SPRN_DSISR
592 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
593 mtspr SPRN_DSISR, r10
594 142: /* continue, it was a dcbx, dcbi instruction. */
595 #ifndef NO_SELF_MODIFYING_CODE
596 andis. r10,r11,0x1f /* test if reg RA is r0 */
597 li r10,modified_instr@l
598 dcbtst r0,r10 /* touch for store */
599 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
600 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
601 ori r11,r11,532
602 stw r11,0(r10) /* store add/and instruction */
603 dcbf 0,r10 /* flush new instr. to memory. */
604 icbi 0,r10 /* invalidate instr. cache line */
605 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
606 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
607 isync /* Wait until new instr is loaded from memory */
608 modified_instr:
609 .space 4 /* this is where the add instr. is stored */
610 bne+ 143f
611 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
612 143: mtdar r10 /* store faulting EA in DAR */
613 mfspr r10,SPRN_SPRG_SCRATCH2
614 b DARFixed /* Go back to normal TLB handling */
615 #else
616 mfctr r10
617 mtdar r10 /* save ctr reg in DAR */
618 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
619 addi r10, r10, 150f@l /* add start of table */
620 mtctr r10 /* load ctr with jump address */
621 xor r10, r10, r10 /* sum starts at zero */
622 bctr /* jump into table */
623 150:
624 add r10, r10, r0 ;b 151f
625 add r10, r10, r1 ;b 151f
626 add r10, r10, r2 ;b 151f
627 add r10, r10, r3 ;b 151f
628 add r10, r10, r4 ;b 151f
629 add r10, r10, r5 ;b 151f
630 add r10, r10, r6 ;b 151f
631 add r10, r10, r7 ;b 151f
632 add r10, r10, r8 ;b 151f
633 add r10, r10, r9 ;b 151f
634 mtctr r11 ;b 154f /* r10 needs special handling */
635 mtctr r11 ;b 153f /* r11 needs special handling */
636 add r10, r10, r12 ;b 151f
637 add r10, r10, r13 ;b 151f
638 add r10, r10, r14 ;b 151f
639 add r10, r10, r15 ;b 151f
640 add r10, r10, r16 ;b 151f
641 add r10, r10, r17 ;b 151f
642 add r10, r10, r18 ;b 151f
643 add r10, r10, r19 ;b 151f
644 add r10, r10, r20 ;b 151f
645 add r10, r10, r21 ;b 151f
646 add r10, r10, r22 ;b 151f
647 add r10, r10, r23 ;b 151f
648 add r10, r10, r24 ;b 151f
649 add r10, r10, r25 ;b 151f
650 add r10, r10, r26 ;b 151f
651 add r10, r10, r27 ;b 151f
652 add r10, r10, r28 ;b 151f
653 add r10, r10, r29 ;b 151f
654 add r10, r10, r30 ;b 151f
655 add r10, r10, r31
656 151:
657 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
658 beq 152f /* if reg RA is zero, don't add it */
659 addi r11, r11, 150b@l /* add start of table */
660 mtctr r11 /* load ctr with jump address */
661 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
662 bctr /* jump into table */
663 152:
664 mfdar r11
665 mtctr r11 /* restore ctr reg from DAR */
666 mtdar r10 /* save fault EA to DAR */
667 mfspr r10,SPRN_SPRG_SCRATCH2
668 b DARFixed /* Go back to normal TLB handling */
670 /* special handling for r10,r11 since these are modified already */
671 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
672 add r10, r10, r11 /* add it */
673 mfctr r11 /* restore r11 */
674 b 151b
675 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
676 add r10, r10, r11 /* add it */
677 mfctr r11 /* restore r11 */
678 b 151b
679 #endif
681 /*
682 * This is where the main kernel code starts.
683 */
684 start_here:
685 /* ptr to current */
686 lis r2,init_task@h
687 ori r2,r2,init_task@l
689 /* ptr to phys current thread */
690 tophys(r4,r2)
691 addi r4,r4,THREAD /* init task's THREAD */
692 mtspr SPRN_SPRG_THREAD,r4
694 /* stack */
695 lis r1,init_thread_union@ha
696 addi r1,r1,init_thread_union@l
697 li r0,0
698 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
700 bl early_init /* We have to do this with MMU on */
702 /*
703 * Decide what sort of machine this is and initialize the MMU.
704 */
705 li r3,0
706 mr r4,r31
707 bl machine_init
708 bl MMU_init
710 /*
711 * Go back to running unmapped so we can load up new values
712 * and change to using our exception vectors.
713 * On the 8xx, all we have to do is invalidate the TLB to clear
714 * the old 8M byte TLB mappings and load the page table base register.
715 */
716 /* The right way to do this would be to track it down through
717 * init's THREAD like the context switch code does, but this is
718 * easier......until someone changes init's static structures.
719 */
720 lis r6, swapper_pg_dir@ha
721 tophys(r6,r6)
722 #ifdef CONFIG_8xx_CPU6
723 lis r4, cpu6_errata_word@h
724 ori r4, r4, cpu6_errata_word@l
725 li r3, 0x3f80
726 stw r3, 12(r4)
727 lwz r3, 12(r4)
728 #endif
729 mtspr SPRN_M_TW, r6
730 lis r4,2f@h
731 ori r4,r4,2f@l
732 tophys(r4,r4)
733 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
734 mtspr SPRN_SRR0,r4
735 mtspr SPRN_SRR1,r3
736 rfi
737 /* Load up the kernel context */
738 2:
739 SYNC /* Force all PTE updates to finish */
740 tlbia /* Clear all TLB entries */
741 sync /* wait for tlbia/tlbie to finish */
742 TLBSYNC /* ... on all CPUs */
744 /* set up the PTE pointers for the Abatron bdiGDB.
745 */
746 tovirt(r6,r6)
747 lis r5, abatron_pteptrs@h
748 ori r5, r5, abatron_pteptrs@l
749 stw r5, 0xf0(r0) /* Must match your Abatron config file */
750 tophys(r5,r5)
751 stw r6, 0(r5)
753 /* Now turn on the MMU for real! */
754 li r4,MSR_KERNEL
755 lis r3,start_kernel@h
756 ori r3,r3,start_kernel@l
757 mtspr SPRN_SRR0,r3
758 mtspr SPRN_SRR1,r4
759 rfi /* enable MMU and jump to start_kernel */
761 /* Set up the initial MMU state so we can do the first level of
762 * kernel initialization. This maps the first 8 MBytes of memory 1:1
763 * virtual to physical. Also, set the cache mode since that is defined
764 * by TLB entries and perform any additional mapping (like of the IMMR).
765 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
766 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by
767 * these mappings is mapped by page tables.
768 */
769 initial_mmu:
770 tlbia /* Invalidate all TLB entries */
771 /* Always pin the first 8 MB ITLB to prevent ITLB
772 misses while mucking around with SRR0/SRR1 in asm
773 */
774 lis r8, MI_RSV4I@h
775 ori r8, r8, 0x1c00
777 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
779 #ifdef CONFIG_PIN_TLB
780 lis r10, (MD_RSV4I | MD_RESETVAL)@h
781 ori r10, r10, 0x1c00
782 mr r8, r10
783 #else
784 lis r10, MD_RESETVAL@h
785 #endif
786 #ifndef CONFIG_8xx_COPYBACK
787 oris r10, r10, MD_WTDEF@h
788 #endif
789 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
791 /* Now map the lower 8 Meg into the TLBs. For this quick hack,
792 * we can load the instruction and data TLB registers with the
793 * same values.
794 */
795 lis r8, KERNELBASE@h /* Create vaddr for TLB */
796 ori r8, r8, MI_EVALID /* Mark it valid */
797 mtspr SPRN_MI_EPN, r8
798 mtspr SPRN_MD_EPN, r8
799 li r8, MI_PS8MEG | (2 << 5) /* Set 8M byte page, APG 2 */
800 ori r8, r8, MI_SVALID /* Make it valid */
801 mtspr SPRN_MI_TWC, r8
802 li r8, MI_PS8MEG /* Set 8M byte page, APG 0 */
803 ori r8, r8, MI_SVALID /* Make it valid */
804 mtspr SPRN_MD_TWC, r8
805 li r8, MI_BOOTINIT /* Create RPN for address 0 */
806 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
807 mtspr SPRN_MD_RPN, r8
808 lis r8, MI_APG_INIT@h /* Set protection modes */
809 ori r8, r8, MI_APG_INIT@l
810 mtspr SPRN_MI_AP, r8
811 lis r8, MD_APG_INIT@h
812 ori r8, r8, MD_APG_INIT@l
813 mtspr SPRN_MD_AP, r8
815 /* Map another 8 MByte at the IMMR to get the processor
816 * internal registers (among other things).
817 */
818 #ifdef CONFIG_PIN_TLB
819 addi r10, r10, 0x0100
820 mtspr SPRN_MD_CTR, r10
821 #endif
822 mfspr r9, 638 /* Get current IMMR */
823 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
825 mr r8, r9 /* Create vaddr for TLB */
826 ori r8, r8, MD_EVALID /* Mark it valid */
827 mtspr SPRN_MD_EPN, r8
828 li r8, MD_PS8MEG /* Set 8M byte page */
829 ori r8, r8, MD_SVALID /* Make it valid */
830 mtspr SPRN_MD_TWC, r8
831 mr r8, r9 /* Create paddr for TLB */
832 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
833 mtspr SPRN_MD_RPN, r8
835 #ifdef CONFIG_PIN_TLB
836 /* Map two more 8M kernel data pages.
837 */
838 addi r10, r10, 0x0100
839 mtspr SPRN_MD_CTR, r10
841 lis r8, KERNELBASE@h /* Create vaddr for TLB */
842 addis r8, r8, 0x0080 /* Add 8M */
843 ori r8, r8, MI_EVALID /* Mark it valid */
844 mtspr SPRN_MD_EPN, r8
845 li r9, MI_PS8MEG /* Set 8M byte page */
846 ori r9, r9, MI_SVALID /* Make it valid */
847 mtspr SPRN_MD_TWC, r9
848 li r11, MI_BOOTINIT /* Create RPN for address 0 */
849 addis r11, r11, 0x0080 /* Add 8M */
850 mtspr SPRN_MD_RPN, r11
852 addi r10, r10, 0x0100
853 mtspr SPRN_MD_CTR, r10
855 addis r8, r8, 0x0080 /* Add 8M */
856 mtspr SPRN_MD_EPN, r8
857 mtspr SPRN_MD_TWC, r9
858 addis r11, r11, 0x0080 /* Add 8M */
859 mtspr SPRN_MD_RPN, r11
860 #endif
862 /* Since the cache is enabled according to the information we
863 * just loaded into the TLB, invalidate and enable the caches here.
864 * We should probably check/set other modes....later.
865 */
866 lis r8, IDC_INVALL@h
867 mtspr SPRN_IC_CST, r8
868 mtspr SPRN_DC_CST, r8
869 lis r8, IDC_ENABLE@h
870 mtspr SPRN_IC_CST, r8
871 #ifdef CONFIG_8xx_COPYBACK
872 mtspr SPRN_DC_CST, r8
873 #else
874 /* For a debug option, I left this here to easily enable
875 * the write through cache mode
876 */
877 lis r8, DC_SFWT@h
878 mtspr SPRN_DC_CST, r8
879 lis r8, IDC_ENABLE@h
880 mtspr SPRN_DC_CST, r8
881 #endif
882 blr
885 /*
886 * We put a few things here that have to be page-aligned.
887 * This stuff goes at the beginning of the data segment,
888 * which is page-aligned.
889 */
890 .data
891 .globl sdata
892 sdata:
893 .globl empty_zero_page
894 .align PAGE_SHIFT
895 empty_zero_page:
896 .space PAGE_SIZE
898 .globl swapper_pg_dir
899 swapper_pg_dir:
900 .space PGD_TABLE_SIZE
902 /* Room for two PTE table poiners, usually the kernel and current user
903 * pointer to their respective root page table (pgdir).
904 */
905 abatron_pteptrs:
906 .space 8
908 #ifdef CONFIG_8xx_CPU6
909 .globl cpu6_errata_word
910 cpu6_errata_word:
911 .space 16
912 #endif