?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
posix-clock: Fix return code on the poll method's error path
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nvkm / subdev / bios / init.c
bloba7d69ce7abc1ad33b5fd283a5f4b5321feb89f18
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include <subdev/bios.h>
25 #include <subdev/bios/bit.h>
26 #include <subdev/bios/bmp.h>
27 #include <subdev/bios/conn.h>
28 #include <subdev/bios/dcb.h>
29 #include <subdev/bios/dp.h>
30 #include <subdev/bios/gpio.h>
31 #include <subdev/bios/init.h>
32 #include <subdev/bios/ramcfg.h>
33
34 #include <subdev/devinit.h>
35 #include <subdev/gpio.h>
36 #include <subdev/i2c.h>
37 #include <subdev/vga.h>
38
39 #define bioslog(lvl, fmt, args...) do { \
40 nvkm_printk(init->subdev, lvl, info, "0x%04x[%c]: "fmt, \
41 init->offset, init_exec(init) ? \
42 '0' + (init->nested - 1) : ' ', ##args); \
43 } while(0)
44 #define cont(fmt, args...) do { \
45 if (init->subdev->debug >= NV_DBG_TRACE) \
46 printk(fmt, ##args); \
47 } while(0)
48 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
49 #define warn(fmt, args...) bioslog(WARN, fmt, ##args)
50 #define error(fmt, args...) bioslog(ERROR, fmt, ##args)
51
52 /******************************************************************************
53 * init parser control flow helpers
54 *****************************************************************************/
55
56 static inline bool
57 init_exec(struct nvbios_init *init)
58 {
59 return (init->execute == 1) || ((init->execute & 5) == 5);
60 }
61
62 static inline void
63 init_exec_set(struct nvbios_init *init, bool exec)
64 {
65 if (exec) init->execute &= 0xfd;
66 else init->execute |= 0x02;
67 }
68
69 static inline void
70 init_exec_inv(struct nvbios_init *init)
71 {
72 init->execute ^= 0x02;
73 }
74
75 static inline void
76 init_exec_force(struct nvbios_init *init, bool exec)
77 {
78 if (exec) init->execute |= 0x04;
79 else init->execute &= 0xfb;
80 }
81
82 /******************************************************************************
83 * init parser wrappers for normal register/i2c/whatever accessors
84 *****************************************************************************/
85
86 static inline int
87 init_or(struct nvbios_init *init)
88 {
89 if (init_exec(init)) {
90 if (init->outp)
91 return ffs(init->outp->or) - 1;
92 error("script needs OR!!\n");
93 }
94 return 0;
95 }
96
97 static inline int
98 init_link(struct nvbios_init *init)
99 {
100 if (init_exec(init)) {
101 if (init->outp)
102 return !(init->outp->sorconf.link & 1);
103 error("script needs OR link\n");
104 }
105 return 0;
106 }
107
108 static inline int
109 init_crtc(struct nvbios_init *init)
110 {
111 if (init_exec(init)) {
112 if (init->crtc >= 0)
113 return init->crtc;
114 error("script needs crtc\n");
115 }
116 return 0;
117 }
118
119 static u8
120 init_conn(struct nvbios_init *init)
121 {
122 struct nvkm_bios *bios = init->bios;
123 struct nvbios_connE connE;
124 u8 ver, hdr;
125 u32 conn;
126
127 if (init_exec(init)) {
128 if (init->outp) {
129 conn = init->outp->connector;
130 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE);
131 if (conn)
132 return connE.type;
133 }
134
135 error("script needs connector type\n");
136 }
137
138 return 0xff;
139 }
140
141 static inline u32
142 init_nvreg(struct nvbios_init *init, u32 reg)
143 {
144 struct nvkm_devinit *devinit = init->bios->subdev.device->devinit;
145
146 /* C51 (at least) sometimes has the lower bits set which the VBIOS
147 * interprets to mean that access needs to go through certain IO
148 * ports instead. The NVIDIA binary driver has been seen to access
149 * these through the NV register address, so lets assume we can
150 * do the same
151 */
152 reg &= ~0x00000003;
153
154 /* GF8+ display scripts need register addresses mangled a bit to
155 * select a specific CRTC/OR
156 */
157 if (init->bios->subdev.device->card_type >= NV_50) {
158 if (reg & 0x80000000) {
159 reg += init_crtc(init) * 0x800;
160 reg &= ~0x80000000;
161 }
162
163 if (reg & 0x40000000) {
164 reg += init_or(init) * 0x800;
165 reg &= ~0x40000000;
166 if (reg & 0x20000000) {
167 reg += init_link(init) * 0x80;
168 reg &= ~0x20000000;
169 }
170 }
171 }
172
173 if (reg & ~0x00fffffc)
174 warn("unknown bits in register 0x%08x\n", reg);
175
176 return nvkm_devinit_mmio(devinit, reg);
177 }
178
179 static u32
180 init_rd32(struct nvbios_init *init, u32 reg)
181 {
182 struct nvkm_device *device = init->bios->subdev.device;
183 reg = init_nvreg(init, reg);
184 if (reg != ~0 && init_exec(init))
185 return nvkm_rd32(device, reg);
186 return 0x00000000;
187 }
188
189 static void
190 init_wr32(struct nvbios_init *init, u32 reg, u32 val)
191 {
192 struct nvkm_device *device = init->bios->subdev.device;
193 reg = init_nvreg(init, reg);
194 if (reg != ~0 && init_exec(init))
195 nvkm_wr32(device, reg, val);
196 }
197
198 static u32
199 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
200 {
201 struct nvkm_device *device = init->bios->subdev.device;
202 reg = init_nvreg(init, reg);
203 if (reg != ~0 && init_exec(init)) {
204 u32 tmp = nvkm_rd32(device, reg);
205 nvkm_wr32(device, reg, (tmp & ~mask) | val);
206 return tmp;
207 }
208 return 0x00000000;
209 }
210
211 static u8
212 init_rdport(struct nvbios_init *init, u16 port)
213 {
214 if (init_exec(init))
215 return nvkm_rdport(init->subdev->device, init->crtc, port);
216 return 0x00;
217 }
218
219 static void
220 init_wrport(struct nvbios_init *init, u16 port, u8 value)
221 {
222 if (init_exec(init))
223 nvkm_wrport(init->subdev->device, init->crtc, port, value);
224 }
225
226 static u8
227 init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
228 {
229 struct nvkm_subdev *subdev = init->subdev;
230 if (init_exec(init)) {
231 int head = init->crtc < 0 ? 0 : init->crtc;
232 return nvkm_rdvgai(subdev->device, head, port, index);
233 }
234 return 0x00;
235 }
236
237 static void
238 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
239 {
240 struct nvkm_device *device = init->subdev->device;
241
242 /* force head 0 for updates to cr44, it only exists on first head */
243 if (device->card_type < NV_50) {
244 if (port == 0x03d4 && index == 0x44)
245 init->crtc = 0;
246 }
247
248 if (init_exec(init)) {
249 int head = init->crtc < 0 ? 0 : init->crtc;
250 nvkm_wrvgai(device, head, port, index, value);
251 }
252
253 /* select head 1 if cr44 write selected it */
254 if (device->card_type < NV_50) {
255 if (port == 0x03d4 && index == 0x44 && value == 3)
256 init->crtc = 1;
257 }
258 }
259
260 static struct i2c_adapter *
261 init_i2c(struct nvbios_init *init, int index)
262 {
263 struct nvkm_i2c *i2c = init->bios->subdev.device->i2c;
264 struct nvkm_i2c_bus *bus;
265
266 if (index == 0xff) {
267 index = NVKM_I2C_BUS_PRI;
268 if (init->outp && init->outp->i2c_upper_default)
269 index = NVKM_I2C_BUS_SEC;
270 } else
271 if (index == 0x80) {
272 index = NVKM_I2C_BUS_PRI;
273 } else
274 if (index == 0x81) {
275 index = NVKM_I2C_BUS_SEC;
276 }
277
278 bus = nvkm_i2c_bus_find(i2c, index);
279 return bus ? &bus->i2c : NULL;
280 }
281
282 static int
283 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
284 {
285 struct i2c_adapter *adap = init_i2c(init, index);
286 if (adap && init_exec(init))
287 return nvkm_rdi2cr(adap, addr, reg);
288 return -ENODEV;
289 }
290
291 static int
292 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
293 {
294 struct i2c_adapter *adap = init_i2c(init, index);
295 if (adap && init_exec(init))
296 return nvkm_wri2cr(adap, addr, reg, val);
297 return -ENODEV;
298 }
299
300 static struct nvkm_i2c_aux *
301 init_aux(struct nvbios_init *init)
302 {
303 struct nvkm_i2c *i2c = init->bios->subdev.device->i2c;
304 if (!init->outp) {
305 if (init_exec(init))
306 error("script needs output for aux\n");
307 return NULL;
308 }
309 return nvkm_i2c_aux_find(i2c, init->outp->i2c_index);
310 }
311
312 static u8
313 init_rdauxr(struct nvbios_init *init, u32 addr)
314 {
315 struct nvkm_i2c_aux *aux = init_aux(init);
316 u8 data;
317
318 if (aux && init_exec(init)) {
319 int ret = nvkm_rdaux(aux, addr, &data, 1);
320 if (ret == 0)
321 return data;
322 trace("auxch read failed with %d\n", ret);
323 }
324
325 return 0x00;
326 }
327
328 static int
329 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
330 {
331 struct nvkm_i2c_aux *aux = init_aux(init);
332 if (aux && init_exec(init)) {
333 int ret = nvkm_wraux(aux, addr, &data, 1);
334 if (ret)
335 trace("auxch write failed with %d\n", ret);
336 return ret;
337 }
338 return -ENODEV;
339 }
340
341 static void
342 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
343 {
344 struct nvkm_devinit *devinit = init->bios->subdev.device->devinit;
345 if (init_exec(init)) {
346 int ret = nvkm_devinit_pll_set(devinit, id, freq);
347 if (ret)
348 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
349 }
350 }
351
352 /******************************************************************************
353 * parsing of bios structures that are required to execute init tables
354 *****************************************************************************/
355
356 static u16
357 init_table(struct nvkm_bios *bios, u16 *len)
358 {
359 struct bit_entry bit_I;
360
361 if (!bit_entry(bios, 'I', &bit_I)) {
362 *len = bit_I.length;
363 return bit_I.offset;
364 }
365
366 if (bmp_version(bios) >= 0x0510) {
367 *len = 14;
368 return bios->bmp_offset + 75;
369 }
370
371 return 0x0000;
372 }
373
374 static u16
375 init_table_(struct nvbios_init *init, u16 offset, const char *name)
376 {
377 struct nvkm_bios *bios = init->bios;
378 u16 len, data = init_table(bios, &len);
379 if (data) {
380 if (len >= offset + 2) {
381 data = nvbios_rd16(bios, data + offset);
382 if (data)
383 return data;
384
385 warn("%s pointer invalid\n", name);
386 return 0x0000;
387 }
388
389 warn("init data too short for %s pointer", name);
390 return 0x0000;
391 }
392
393 warn("init data not found\n");
394 return 0x0000;
395 }
396
397 #define init_script_table(b) init_table_((b), 0x00, "script table")
398 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
399 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
400 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
401 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
402 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
403 #define init_function_table(b) init_table_((b), 0x0c, "function table")
404 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
405
406 static u16
407 init_script(struct nvkm_bios *bios, int index)
408 {
409 struct nvbios_init init = { .bios = bios };
410 u16 bmp_ver = bmp_version(bios), data;
411
412 if (bmp_ver && bmp_ver < 0x0510) {
413 if (index > 1 || bmp_ver < 0x0100)
414 return 0x0000;
415
416 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
417 return nvbios_rd16(bios, data + (index * 2));
418 }
419
420 data = init_script_table(&init);
421 if (data)
422 return nvbios_rd16(bios, data + (index * 2));
423
424 return 0x0000;
425 }
426
427 static u16
428 init_unknown_script(struct nvkm_bios *bios)
429 {
430 u16 len, data = init_table(bios, &len);
431 if (data && len >= 16)
432 return nvbios_rd16(bios, data + 14);
433 return 0x0000;
434 }
435
436 static u8
437 init_ram_restrict_group_count(struct nvbios_init *init)
438 {
439 return nvbios_ramcfg_count(init->bios);
440 }
441
442 static u8
443 init_ram_restrict(struct nvbios_init *init)
444 {
445 /* This appears to be the behaviour of the VBIOS parser, and *is*
446 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
447 * avoid fucking up the memory controller (somehow) by reading it
448 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
449 *
450 * Preserving the non-caching behaviour on earlier chipsets just
451 * in case *not* re-reading the strap causes similar breakage.
452 */
453 if (!init->ramcfg || init->bios->version.major < 0x70)
454 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev);
455 return (init->ramcfg & 0x7fffffff);
456 }
457
458 static u8
459 init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
460 {
461 struct nvkm_bios *bios = init->bios;
462 u16 table = init_xlat_table(init);
463 if (table) {
464 u16 data = nvbios_rd16(bios, table + (index * 2));
465 if (data)
466 return nvbios_rd08(bios, data + offset);
467 warn("xlat table pointer %d invalid\n", index);
468 }
469 return 0x00;
470 }
471
472 /******************************************************************************
473 * utility functions used by various init opcode handlers
474 *****************************************************************************/
475
476 static bool
477 init_condition_met(struct nvbios_init *init, u8 cond)
478 {
479 struct nvkm_bios *bios = init->bios;
480 u16 table = init_condition_table(init);
481 if (table) {
482 u32 reg = nvbios_rd32(bios, table + (cond * 12) + 0);
483 u32 msk = nvbios_rd32(bios, table + (cond * 12) + 4);
484 u32 val = nvbios_rd32(bios, table + (cond * 12) + 8);
485 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
486 cond, reg, msk, val);
487 return (init_rd32(init, reg) & msk) == val;
488 }
489 return false;
490 }
491
492 static bool
493 init_io_condition_met(struct nvbios_init *init, u8 cond)
494 {
495 struct nvkm_bios *bios = init->bios;
496 u16 table = init_io_condition_table(init);
497 if (table) {
498 u16 port = nvbios_rd16(bios, table + (cond * 5) + 0);
499 u8 index = nvbios_rd08(bios, table + (cond * 5) + 2);
500 u8 mask = nvbios_rd08(bios, table + (cond * 5) + 3);
501 u8 value = nvbios_rd08(bios, table + (cond * 5) + 4);
502 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
503 cond, port, index, mask, value);
504 return (init_rdvgai(init, port, index) & mask) == value;
505 }
506 return false;
507 }
508
509 static bool
510 init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
511 {
512 struct nvkm_bios *bios = init->bios;
513 u16 table = init_io_flag_condition_table(init);
514 if (table) {
515 u16 port = nvbios_rd16(bios, table + (cond * 9) + 0);
516 u8 index = nvbios_rd08(bios, table + (cond * 9) + 2);
517 u8 mask = nvbios_rd08(bios, table + (cond * 9) + 3);
518 u8 shift = nvbios_rd08(bios, table + (cond * 9) + 4);
519 u16 data = nvbios_rd16(bios, table + (cond * 9) + 5);
520 u8 dmask = nvbios_rd08(bios, table + (cond * 9) + 7);
521 u8 value = nvbios_rd08(bios, table + (cond * 9) + 8);
522 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
523 return (nvbios_rd08(bios, data + ioval) & dmask) == value;
524 }
525 return false;
526 }
527
528 static inline u32
529 init_shift(u32 data, u8 shift)
530 {
531 if (shift < 0x80)
532 return data >> shift;
533 return data << (0x100 - shift);
534 }
535
536 static u32
537 init_tmds_reg(struct nvbios_init *init, u8 tmds)
538 {
539 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
540 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
541 * CR58 for CR57 = 0 to index a table of offsets to the basic
542 * 0x6808b0 address.
543 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
544 * CR58 for CR57 = 0 to index a table of offsets to the basic
545 * 0x6808b0 address, and then flip the offset by 8.
546 */
547 const int pramdac_offset[13] = {
548 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
549 const u32 pramdac_table[4] = {
550 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
551
552 if (tmds >= 0x80) {
553 if (init->outp) {
554 u32 dacoffset = pramdac_offset[init->outp->or];
555 if (tmds == 0x81)
556 dacoffset ^= 8;
557 return 0x6808b0 + dacoffset;
558 }
559
560 if (init_exec(init))
561 error("tmds opcodes need dcb\n");
562 } else {
563 if (tmds < ARRAY_SIZE(pramdac_table))
564 return pramdac_table[tmds];
565
566 error("tmds selector 0x%02x unknown\n", tmds);
567 }
568
569 return 0;
570 }
571
572 /******************************************************************************
573 * init opcode handlers
574 *****************************************************************************/
575
576 /**
577 * init_reserved - stub for various unknown/unused single-byte opcodes
578 *
579 */
580 static void
581 init_reserved(struct nvbios_init *init)
582 {
583 u8 opcode = nvbios_rd08(init->bios, init->offset);
584 u8 length, i;
585
586 switch (opcode) {
587 case 0xaa:
588 length = 4;
589 break;
590 default:
591 length = 1;
592 break;
593 }
594
595 trace("RESERVED 0x%02x\t", opcode);
596 for (i = 1; i < length; i++)
597 cont(" 0x%02x", nvbios_rd08(init->bios, init->offset + i));
598 cont("\n");
599 init->offset += length;
600 }
601
602 /**
603 * INIT_DONE - opcode 0x71
604 *
605 */
606 static void
607 init_done(struct nvbios_init *init)
608 {
609 trace("DONE\n");
610 init->offset = 0x0000;
611 }
612
613 /**
614 * INIT_IO_RESTRICT_PROG - opcode 0x32
615 *
616 */
617 static void
618 init_io_restrict_prog(struct nvbios_init *init)
619 {
620 struct nvkm_bios *bios = init->bios;
621 u16 port = nvbios_rd16(bios, init->offset + 1);
622 u8 index = nvbios_rd08(bios, init->offset + 3);
623 u8 mask = nvbios_rd08(bios, init->offset + 4);
624 u8 shift = nvbios_rd08(bios, init->offset + 5);
625 u8 count = nvbios_rd08(bios, init->offset + 6);
626 u32 reg = nvbios_rd32(bios, init->offset + 7);
627 u8 conf, i;
628
629 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
630 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
631 reg, port, index, mask, shift);
632 init->offset += 11;
633
634 conf = (init_rdvgai(init, port, index) & mask) >> shift;
635 for (i = 0; i < count; i++) {
636 u32 data = nvbios_rd32(bios, init->offset);
637
638 if (i == conf) {
639 trace("\t0x%08x *\n", data);
640 init_wr32(init, reg, data);
641 } else {
642 trace("\t0x%08x\n", data);
643 }
644
645 init->offset += 4;
646 }
647 trace("}]\n");
648 }
649
650 /**
651 * INIT_REPEAT - opcode 0x33
652 *
653 */
654 static void
655 init_repeat(struct nvbios_init *init)
656 {
657 struct nvkm_bios *bios = init->bios;
658 u8 count = nvbios_rd08(bios, init->offset + 1);
659 u16 repeat = init->repeat;
660
661 trace("REPEAT\t0x%02x\n", count);
662 init->offset += 2;
663
664 init->repeat = init->offset;
665 init->repend = init->offset;
666 while (count--) {
667 init->offset = init->repeat;
668 nvbios_exec(init);
669 if (count)
670 trace("REPEAT\t0x%02x\n", count);
671 }
672 init->offset = init->repend;
673 init->repeat = repeat;
674 }
675
676 /**
677 * INIT_IO_RESTRICT_PLL - opcode 0x34
678 *
679 */
680 static void
681 init_io_restrict_pll(struct nvbios_init *init)
682 {
683 struct nvkm_bios *bios = init->bios;
684 u16 port = nvbios_rd16(bios, init->offset + 1);
685 u8 index = nvbios_rd08(bios, init->offset + 3);
686 u8 mask = nvbios_rd08(bios, init->offset + 4);
687 u8 shift = nvbios_rd08(bios, init->offset + 5);
688 s8 iofc = nvbios_rd08(bios, init->offset + 6);
689 u8 count = nvbios_rd08(bios, init->offset + 7);
690 u32 reg = nvbios_rd32(bios, init->offset + 8);
691 u8 conf, i;
692
693 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
694 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
695 reg, port, index, mask, shift, iofc);
696 init->offset += 12;
697
698 conf = (init_rdvgai(init, port, index) & mask) >> shift;
699 for (i = 0; i < count; i++) {
700 u32 freq = nvbios_rd16(bios, init->offset) * 10;
701
702 if (i == conf) {
703 trace("\t%dkHz *\n", freq);
704 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
705 freq *= 2;
706 init_prog_pll(init, reg, freq);
707 } else {
708 trace("\t%dkHz\n", freq);
709 }
710
711 init->offset += 2;
712 }
713 trace("}]\n");
714 }
715
716 /**
717 * INIT_END_REPEAT - opcode 0x36
718 *
719 */
720 static void
721 init_end_repeat(struct nvbios_init *init)
722 {
723 trace("END_REPEAT\n");
724 init->offset += 1;
725
726 if (init->repeat) {
727 init->repend = init->offset;
728 init->offset = 0;
729 }
730 }
731
732 /**
733 * INIT_COPY - opcode 0x37
734 *
735 */
736 static void
737 init_copy(struct nvbios_init *init)
738 {
739 struct nvkm_bios *bios = init->bios;
740 u32 reg = nvbios_rd32(bios, init->offset + 1);
741 u8 shift = nvbios_rd08(bios, init->offset + 5);
742 u8 smask = nvbios_rd08(bios, init->offset + 6);
743 u16 port = nvbios_rd16(bios, init->offset + 7);
744 u8 index = nvbios_rd08(bios, init->offset + 9);
745 u8 mask = nvbios_rd08(bios, init->offset + 10);
746 u8 data;
747
748 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
749 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
750 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
751 (shift & 0x80) ? (0x100 - shift) : shift, smask);
752 init->offset += 11;
753
754 data = init_rdvgai(init, port, index) & mask;
755 data |= init_shift(init_rd32(init, reg), shift) & smask;
756 init_wrvgai(init, port, index, data);
757 }
758
759 /**
760 * INIT_NOT - opcode 0x38
761 *
762 */
763 static void
764 init_not(struct nvbios_init *init)
765 {
766 trace("NOT\n");
767 init->offset += 1;
768 init_exec_inv(init);
769 }
770
771 /**
772 * INIT_IO_FLAG_CONDITION - opcode 0x39
773 *
774 */
775 static void
776 init_io_flag_condition(struct nvbios_init *init)
777 {
778 struct nvkm_bios *bios = init->bios;
779 u8 cond = nvbios_rd08(bios, init->offset + 1);
780
781 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
782 init->offset += 2;
783
784 if (!init_io_flag_condition_met(init, cond))
785 init_exec_set(init, false);
786 }
787
788 /**
789 * INIT_DP_CONDITION - opcode 0x3a
790 *
791 */
792 static void
793 init_dp_condition(struct nvbios_init *init)
794 {
795 struct nvkm_bios *bios = init->bios;
796 struct nvbios_dpout info;
797 u8 cond = nvbios_rd08(bios, init->offset + 1);
798 u8 unkn = nvbios_rd08(bios, init->offset + 2);
799 u8 ver, hdr, cnt, len;
800 u16 data;
801
802 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
803 init->offset += 3;
804
805 switch (cond) {
806 case 0:
807 if (init_conn(init) != DCB_CONNECTOR_eDP)
808 init_exec_set(init, false);
809 break;
810 case 1:
811 case 2:
812 if ( init->outp &&
813 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
814 (init->outp->or << 0) |
815 (init->outp->sorconf.link << 6),
816 &ver, &hdr, &cnt, &len, &info)))
817 {
818 if (!(info.flags & cond))
819 init_exec_set(init, false);
820 break;
821 }
822
823 if (init_exec(init))
824 warn("script needs dp output table data\n");
825 break;
826 case 5:
827 if (!(init_rdauxr(init, 0x0d) & 1))
828 init_exec_set(init, false);
829 break;
830 default:
831 warn("unknown dp condition 0x%02x\n", cond);
832 break;
833 }
834 }
835
836 /**
837 * INIT_IO_MASK_OR - opcode 0x3b
838 *
839 */
840 static void
841 init_io_mask_or(struct nvbios_init *init)
842 {
843 struct nvkm_bios *bios = init->bios;
844 u8 index = nvbios_rd08(bios, init->offset + 1);
845 u8 or = init_or(init);
846 u8 data;
847
848 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
849 init->offset += 2;
850
851 data = init_rdvgai(init, 0x03d4, index);
852 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
853 }
854
855 /**
856 * INIT_IO_OR - opcode 0x3c
857 *
858 */
859 static void
860 init_io_or(struct nvbios_init *init)
861 {
862 struct nvkm_bios *bios = init->bios;
863 u8 index = nvbios_rd08(bios, init->offset + 1);
864 u8 or = init_or(init);
865 u8 data;
866
867 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
868 init->offset += 2;
869
870 data = init_rdvgai(init, 0x03d4, index);
871 init_wrvgai(init, 0x03d4, index, data | (1 << or));
872 }
873
874 /**
875 * INIT_ANDN_REG - opcode 0x47
876 *
877 */
878 static void
879 init_andn_reg(struct nvbios_init *init)
880 {
881 struct nvkm_bios *bios = init->bios;
882 u32 reg = nvbios_rd32(bios, init->offset + 1);
883 u32 mask = nvbios_rd32(bios, init->offset + 5);
884
885 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask);
886 init->offset += 9;
887
888 init_mask(init, reg, mask, 0);
889 }
890
891 /**
892 * INIT_OR_REG - opcode 0x48
893 *
894 */
895 static void
896 init_or_reg(struct nvbios_init *init)
897 {
898 struct nvkm_bios *bios = init->bios;
899 u32 reg = nvbios_rd32(bios, init->offset + 1);
900 u32 mask = nvbios_rd32(bios, init->offset + 5);
901
902 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask);
903 init->offset += 9;
904
905 init_mask(init, reg, 0, mask);
906 }
907
908 /**
909 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
910 *
911 */
912 static void
913 init_idx_addr_latched(struct nvbios_init *init)
914 {
915 struct nvkm_bios *bios = init->bios;
916 u32 creg = nvbios_rd32(bios, init->offset + 1);
917 u32 dreg = nvbios_rd32(bios, init->offset + 5);
918 u32 mask = nvbios_rd32(bios, init->offset + 9);
919 u32 data = nvbios_rd32(bios, init->offset + 13);
920 u8 count = nvbios_rd08(bios, init->offset + 17);
921
922 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg);
923 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data);
924 init->offset += 18;
925
926 while (count--) {
927 u8 iaddr = nvbios_rd08(bios, init->offset + 0);
928 u8 idata = nvbios_rd08(bios, init->offset + 1);
929
930 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
931 init->offset += 2;
932
933 init_wr32(init, dreg, idata);
934 init_mask(init, creg, ~mask, data | iaddr);
935 }
936 }
937
938 /**
939 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
940 *
941 */
942 static void
943 init_io_restrict_pll2(struct nvbios_init *init)
944 {
945 struct nvkm_bios *bios = init->bios;
946 u16 port = nvbios_rd16(bios, init->offset + 1);
947 u8 index = nvbios_rd08(bios, init->offset + 3);
948 u8 mask = nvbios_rd08(bios, init->offset + 4);
949 u8 shift = nvbios_rd08(bios, init->offset + 5);
950 u8 count = nvbios_rd08(bios, init->offset + 6);
951 u32 reg = nvbios_rd32(bios, init->offset + 7);
952 u8 conf, i;
953
954 trace("IO_RESTRICT_PLL2\t"
955 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
956 reg, port, index, mask, shift);
957 init->offset += 11;
958
959 conf = (init_rdvgai(init, port, index) & mask) >> shift;
960 for (i = 0; i < count; i++) {
961 u32 freq = nvbios_rd32(bios, init->offset);
962 if (i == conf) {
963 trace("\t%dkHz *\n", freq);
964 init_prog_pll(init, reg, freq);
965 } else {
966 trace("\t%dkHz\n", freq);
967 }
968 init->offset += 4;
969 }
970 trace("}]\n");
971 }
972
973 /**
974 * INIT_PLL2 - opcode 0x4b
975 *
976 */
977 static void
978 init_pll2(struct nvbios_init *init)
979 {
980 struct nvkm_bios *bios = init->bios;
981 u32 reg = nvbios_rd32(bios, init->offset + 1);
982 u32 freq = nvbios_rd32(bios, init->offset + 5);
983
984 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
985 init->offset += 9;
986
987 init_prog_pll(init, reg, freq);
988 }
989
990 /**
991 * INIT_I2C_BYTE - opcode 0x4c
992 *
993 */
994 static void
995 init_i2c_byte(struct nvbios_init *init)
996 {
997 struct nvkm_bios *bios = init->bios;
998 u8 index = nvbios_rd08(bios, init->offset + 1);
999 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
1000 u8 count = nvbios_rd08(bios, init->offset + 3);
1001
1002 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1003 init->offset += 4;
1004
1005 while (count--) {
1006 u8 reg = nvbios_rd08(bios, init->offset + 0);
1007 u8 mask = nvbios_rd08(bios, init->offset + 1);
1008 u8 data = nvbios_rd08(bios, init->offset + 2);
1009 int val;
1010
1011 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
1012 init->offset += 3;
1013
1014 val = init_rdi2cr(init, index, addr, reg);
1015 if (val < 0)
1016 continue;
1017 init_wri2cr(init, index, addr, reg, (val & mask) | data);
1018 }
1019 }
1020
1021 /**
1022 * INIT_ZM_I2C_BYTE - opcode 0x4d
1023 *
1024 */
1025 static void
1026 init_zm_i2c_byte(struct nvbios_init *init)
1027 {
1028 struct nvkm_bios *bios = init->bios;
1029 u8 index = nvbios_rd08(bios, init->offset + 1);
1030 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
1031 u8 count = nvbios_rd08(bios, init->offset + 3);
1032
1033 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1034 init->offset += 4;
1035
1036 while (count--) {
1037 u8 reg = nvbios_rd08(bios, init->offset + 0);
1038 u8 data = nvbios_rd08(bios, init->offset + 1);
1039
1040 trace("\t[0x%02x] = 0x%02x\n", reg, data);
1041 init->offset += 2;
1042
1043 init_wri2cr(init, index, addr, reg, data);
1044 }
1045 }
1046
1047 /**
1048 * INIT_ZM_I2C - opcode 0x4e
1049 *
1050 */
1051 static void
1052 init_zm_i2c(struct nvbios_init *init)
1053 {
1054 struct nvkm_bios *bios = init->bios;
1055 u8 index = nvbios_rd08(bios, init->offset + 1);
1056 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
1057 u8 count = nvbios_rd08(bios, init->offset + 3);
1058 u8 data[256], i;
1059
1060 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
1061 init->offset += 4;
1062
1063 for (i = 0; i < count; i++) {
1064 data[i] = nvbios_rd08(bios, init->offset);
1065 trace("\t0x%02x\n", data[i]);
1066 init->offset++;
1067 }
1068
1069 if (init_exec(init)) {
1070 struct i2c_adapter *adap = init_i2c(init, index);
1071 struct i2c_msg msg = {
1072 .addr = addr, .flags = 0, .len = count, .buf = data,
1073 };
1074 int ret;
1075
1076 if (adap && (ret = i2c_transfer(adap, &msg, 1)) != 1)
1077 warn("i2c wr failed, %d\n", ret);
1078 }
1079 }
1080
1081 /**
1082 * INIT_TMDS - opcode 0x4f
1083 *
1084 */
1085 static void
1086 init_tmds(struct nvbios_init *init)
1087 {
1088 struct nvkm_bios *bios = init->bios;
1089 u8 tmds = nvbios_rd08(bios, init->offset + 1);
1090 u8 addr = nvbios_rd08(bios, init->offset + 2);
1091 u8 mask = nvbios_rd08(bios, init->offset + 3);
1092 u8 data = nvbios_rd08(bios, init->offset + 4);
1093 u32 reg = init_tmds_reg(init, tmds);
1094
1095 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1096 tmds, addr, mask, data);
1097 init->offset += 5;
1098
1099 if (reg == 0)
1100 return;
1101
1102 init_wr32(init, reg + 0, addr | 0x00010000);
1103 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1104 init_wr32(init, reg + 0, addr);
1105 }
1106
1107 /**
1108 * INIT_ZM_TMDS_GROUP - opcode 0x50
1109 *
1110 */
1111 static void
1112 init_zm_tmds_group(struct nvbios_init *init)
1113 {
1114 struct nvkm_bios *bios = init->bios;
1115 u8 tmds = nvbios_rd08(bios, init->offset + 1);
1116 u8 count = nvbios_rd08(bios, init->offset + 2);
1117 u32 reg = init_tmds_reg(init, tmds);
1118
1119 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1120 init->offset += 3;
1121
1122 while (count--) {
1123 u8 addr = nvbios_rd08(bios, init->offset + 0);
1124 u8 data = nvbios_rd08(bios, init->offset + 1);
1125
1126 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1127 init->offset += 2;
1128
1129 init_wr32(init, reg + 4, data);
1130 init_wr32(init, reg + 0, addr);
1131 }
1132 }
1133
1134 /**
1135 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1136 *
1137 */
1138 static void
1139 init_cr_idx_adr_latch(struct nvbios_init *init)
1140 {
1141 struct nvkm_bios *bios = init->bios;
1142 u8 addr0 = nvbios_rd08(bios, init->offset + 1);
1143 u8 addr1 = nvbios_rd08(bios, init->offset + 2);
1144 u8 base = nvbios_rd08(bios, init->offset + 3);
1145 u8 count = nvbios_rd08(bios, init->offset + 4);
1146 u8 save0;
1147
1148 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1149 init->offset += 5;
1150
1151 save0 = init_rdvgai(init, 0x03d4, addr0);
1152 while (count--) {
1153 u8 data = nvbios_rd08(bios, init->offset);
1154
1155 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1156 init->offset += 1;
1157
1158 init_wrvgai(init, 0x03d4, addr0, base++);
1159 init_wrvgai(init, 0x03d4, addr1, data);
1160 }
1161 init_wrvgai(init, 0x03d4, addr0, save0);
1162 }
1163
1164 /**
1165 * INIT_CR - opcode 0x52
1166 *
1167 */
1168 static void
1169 init_cr(struct nvbios_init *init)
1170 {
1171 struct nvkm_bios *bios = init->bios;
1172 u8 addr = nvbios_rd08(bios, init->offset + 1);
1173 u8 mask = nvbios_rd08(bios, init->offset + 2);
1174 u8 data = nvbios_rd08(bios, init->offset + 3);
1175 u8 val;
1176
1177 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1178 init->offset += 4;
1179
1180 val = init_rdvgai(init, 0x03d4, addr) & mask;
1181 init_wrvgai(init, 0x03d4, addr, val | data);
1182 }
1183
1184 /**
1185 * INIT_ZM_CR - opcode 0x53
1186 *
1187 */
1188 static void
1189 init_zm_cr(struct nvbios_init *init)
1190 {
1191 struct nvkm_bios *bios = init->bios;
1192 u8 addr = nvbios_rd08(bios, init->offset + 1);
1193 u8 data = nvbios_rd08(bios, init->offset + 2);
1194
1195 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1196 init->offset += 3;
1197
1198 init_wrvgai(init, 0x03d4, addr, data);
1199 }
1200
1201 /**
1202 * INIT_ZM_CR_GROUP - opcode 0x54
1203 *
1204 */
1205 static void
1206 init_zm_cr_group(struct nvbios_init *init)
1207 {
1208 struct nvkm_bios *bios = init->bios;
1209 u8 count = nvbios_rd08(bios, init->offset + 1);
1210
1211 trace("ZM_CR_GROUP\n");
1212 init->offset += 2;
1213
1214 while (count--) {
1215 u8 addr = nvbios_rd08(bios, init->offset + 0);
1216 u8 data = nvbios_rd08(bios, init->offset + 1);
1217
1218 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1219 init->offset += 2;
1220
1221 init_wrvgai(init, 0x03d4, addr, data);
1222 }
1223 }
1224
1225 /**
1226 * INIT_CONDITION_TIME - opcode 0x56
1227 *
1228 */
1229 static void
1230 init_condition_time(struct nvbios_init *init)
1231 {
1232 struct nvkm_bios *bios = init->bios;
1233 u8 cond = nvbios_rd08(bios, init->offset + 1);
1234 u8 retry = nvbios_rd08(bios, init->offset + 2);
1235 u8 wait = min((u16)retry * 50, 100);
1236
1237 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1238 init->offset += 3;
1239
1240 if (!init_exec(init))
1241 return;
1242
1243 while (wait--) {
1244 if (init_condition_met(init, cond))
1245 return;
1246 mdelay(20);
1247 }
1248
1249 init_exec_set(init, false);
1250 }
1251
1252 /**
1253 * INIT_LTIME - opcode 0x57
1254 *
1255 */
1256 static void
1257 init_ltime(struct nvbios_init *init)
1258 {
1259 struct nvkm_bios *bios = init->bios;
1260 u16 msec = nvbios_rd16(bios, init->offset + 1);
1261
1262 trace("LTIME\t0x%04x\n", msec);
1263 init->offset += 3;
1264
1265 if (init_exec(init))
1266 mdelay(msec);
1267 }
1268
1269 /**
1270 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1271 *
1272 */
1273 static void
1274 init_zm_reg_sequence(struct nvbios_init *init)
1275 {
1276 struct nvkm_bios *bios = init->bios;
1277 u32 base = nvbios_rd32(bios, init->offset + 1);
1278 u8 count = nvbios_rd08(bios, init->offset + 5);
1279
1280 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1281 init->offset += 6;
1282
1283 while (count--) {
1284 u32 data = nvbios_rd32(bios, init->offset);
1285
1286 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1287 init->offset += 4;
1288
1289 init_wr32(init, base, data);
1290 base += 4;
1291 }
1292 }
1293
1294 /**
1295 * INIT_PLL_INDIRECT - opcode 0x59
1296 *
1297 */
1298 static void
1299 init_pll_indirect(struct nvbios_init *init)
1300 {
1301 struct nvkm_bios *bios = init->bios;
1302 u32 reg = nvbios_rd32(bios, init->offset + 1);
1303 u16 addr = nvbios_rd16(bios, init->offset + 5);
1304 u32 freq = (u32)nvbios_rd16(bios, addr) * 1000;
1305
1306 trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n",
1307 reg, addr, freq);
1308 init->offset += 7;
1309
1310 init_prog_pll(init, reg, freq);
1311 }
1312
1313 /**
1314 * INIT_ZM_REG_INDIRECT - opcode 0x5a
1315 *
1316 */
1317 static void
1318 init_zm_reg_indirect(struct nvbios_init *init)
1319 {
1320 struct nvkm_bios *bios = init->bios;
1321 u32 reg = nvbios_rd32(bios, init->offset + 1);
1322 u16 addr = nvbios_rd16(bios, init->offset + 5);
1323 u32 data = nvbios_rd32(bios, addr);
1324
1325 trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n",
1326 reg, addr, data);
1327 init->offset += 7;
1328
1329 init_wr32(init, addr, data);
1330 }
1331
1332 /**
1333 * INIT_SUB_DIRECT - opcode 0x5b
1334 *
1335 */
1336 static void
1337 init_sub_direct(struct nvbios_init *init)
1338 {
1339 struct nvkm_bios *bios = init->bios;
1340 u16 addr = nvbios_rd16(bios, init->offset + 1);
1341 u16 save;
1342
1343 trace("SUB_DIRECT\t0x%04x\n", addr);
1344
1345 if (init_exec(init)) {
1346 save = init->offset;
1347 init->offset = addr;
1348 if (nvbios_exec(init)) {
1349 error("error parsing sub-table\n");
1350 return;
1351 }
1352 init->offset = save;
1353 }
1354
1355 init->offset += 3;
1356 }
1357
1358 /**
1359 * INIT_JUMP - opcode 0x5c
1360 *
1361 */
1362 static void
1363 init_jump(struct nvbios_init *init)
1364 {
1365 struct nvkm_bios *bios = init->bios;
1366 u16 offset = nvbios_rd16(bios, init->offset + 1);
1367
1368 trace("JUMP\t0x%04x\n", offset);
1369
1370 if (init_exec(init))
1371 init->offset = offset;
1372 else
1373 init->offset += 3;
1374 }
1375
1376 /**
1377 * INIT_I2C_IF - opcode 0x5e
1378 *
1379 */
1380 static void
1381 init_i2c_if(struct nvbios_init *init)
1382 {
1383 struct nvkm_bios *bios = init->bios;
1384 u8 index = nvbios_rd08(bios, init->offset + 1);
1385 u8 addr = nvbios_rd08(bios, init->offset + 2);
1386 u8 reg = nvbios_rd08(bios, init->offset + 3);
1387 u8 mask = nvbios_rd08(bios, init->offset + 4);
1388 u8 data = nvbios_rd08(bios, init->offset + 5);
1389 u8 value;
1390
1391 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1392 index, addr, reg, mask, data);
1393 init->offset += 6;
1394 init_exec_force(init, true);
1395
1396 value = init_rdi2cr(init, index, addr, reg);
1397 if ((value & mask) != data)
1398 init_exec_set(init, false);
1399
1400 init_exec_force(init, false);
1401 }
1402
1403 /**
1404 * INIT_COPY_NV_REG - opcode 0x5f
1405 *
1406 */
1407 static void
1408 init_copy_nv_reg(struct nvbios_init *init)
1409 {
1410 struct nvkm_bios *bios = init->bios;
1411 u32 sreg = nvbios_rd32(bios, init->offset + 1);
1412 u8 shift = nvbios_rd08(bios, init->offset + 5);
1413 u32 smask = nvbios_rd32(bios, init->offset + 6);
1414 u32 sxor = nvbios_rd32(bios, init->offset + 10);
1415 u32 dreg = nvbios_rd32(bios, init->offset + 14);
1416 u32 dmask = nvbios_rd32(bios, init->offset + 18);
1417 u32 data;
1418
1419 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1420 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1421 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1422 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1423 init->offset += 22;
1424
1425 data = init_shift(init_rd32(init, sreg), shift);
1426 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1427 }
1428
1429 /**
1430 * INIT_ZM_INDEX_IO - opcode 0x62
1431 *
1432 */
1433 static void
1434 init_zm_index_io(struct nvbios_init *init)
1435 {
1436 struct nvkm_bios *bios = init->bios;
1437 u16 port = nvbios_rd16(bios, init->offset + 1);
1438 u8 index = nvbios_rd08(bios, init->offset + 3);
1439 u8 data = nvbios_rd08(bios, init->offset + 4);
1440
1441 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1442 init->offset += 5;
1443
1444 init_wrvgai(init, port, index, data);
1445 }
1446
1447 /**
1448 * INIT_COMPUTE_MEM - opcode 0x63
1449 *
1450 */
1451 static void
1452 init_compute_mem(struct nvbios_init *init)
1453 {
1454 struct nvkm_devinit *devinit = init->bios->subdev.device->devinit;
1455
1456 trace("COMPUTE_MEM\n");
1457 init->offset += 1;
1458
1459 init_exec_force(init, true);
1460 if (init_exec(init))
1461 nvkm_devinit_meminit(devinit);
1462 init_exec_force(init, false);
1463 }
1464
1465 /**
1466 * INIT_RESET - opcode 0x65
1467 *
1468 */
1469 static void
1470 init_reset(struct nvbios_init *init)
1471 {
1472 struct nvkm_bios *bios = init->bios;
1473 u32 reg = nvbios_rd32(bios, init->offset + 1);
1474 u32 data1 = nvbios_rd32(bios, init->offset + 5);
1475 u32 data2 = nvbios_rd32(bios, init->offset + 9);
1476 u32 savepci19;
1477
1478 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1479 init->offset += 13;
1480 init_exec_force(init, true);
1481
1482 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1483 init_wr32(init, reg, data1);
1484 udelay(10);
1485 init_wr32(init, reg, data2);
1486 init_wr32(init, 0x00184c, savepci19);
1487 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1488
1489 init_exec_force(init, false);
1490 }
1491
1492 /**
1493 * INIT_CONFIGURE_MEM - opcode 0x66
1494 *
1495 */
1496 static u16
1497 init_configure_mem_clk(struct nvbios_init *init)
1498 {
1499 u16 mdata = bmp_mem_init_table(init->bios);
1500 if (mdata)
1501 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1502 return mdata;
1503 }
1504
1505 static void
1506 init_configure_mem(struct nvbios_init *init)
1507 {
1508 struct nvkm_bios *bios = init->bios;
1509 u16 mdata, sdata;
1510 u32 addr, data;
1511
1512 trace("CONFIGURE_MEM\n");
1513 init->offset += 1;
1514
1515 if (bios->version.major > 2) {
1516 init_done(init);
1517 return;
1518 }
1519 init_exec_force(init, true);
1520
1521 mdata = init_configure_mem_clk(init);
1522 sdata = bmp_sdr_seq_table(bios);
1523 if (nvbios_rd08(bios, mdata) & 0x01)
1524 sdata = bmp_ddr_seq_table(bios);
1525 mdata += 6; /* skip to data */
1526
1527 data = init_rdvgai(init, 0x03c4, 0x01);
1528 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1529
1530 for (; (addr = nvbios_rd32(bios, sdata)) != 0xffffffff; sdata += 4) {
1531 switch (addr) {
1532 case 0x10021c: /* CKE_NORMAL */
1533 case 0x1002d0: /* CMD_REFRESH */
1534 case 0x1002d4: /* CMD_PRECHARGE */
1535 data = 0x00000001;
1536 break;
1537 default:
1538 data = nvbios_rd32(bios, mdata);
1539 mdata += 4;
1540 if (data == 0xffffffff)
1541 continue;
1542 break;
1543 }
1544
1545 init_wr32(init, addr, data);
1546 }
1547
1548 init_exec_force(init, false);
1549 }
1550
1551 /**
1552 * INIT_CONFIGURE_CLK - opcode 0x67
1553 *
1554 */
1555 static void
1556 init_configure_clk(struct nvbios_init *init)
1557 {
1558 struct nvkm_bios *bios = init->bios;
1559 u16 mdata, clock;
1560
1561 trace("CONFIGURE_CLK\n");
1562 init->offset += 1;
1563
1564 if (bios->version.major > 2) {
1565 init_done(init);
1566 return;
1567 }
1568 init_exec_force(init, true);
1569
1570 mdata = init_configure_mem_clk(init);
1571
1572 /* NVPLL */
1573 clock = nvbios_rd16(bios, mdata + 4) * 10;
1574 init_prog_pll(init, 0x680500, clock);
1575
1576 /* MPLL */
1577 clock = nvbios_rd16(bios, mdata + 2) * 10;
1578 if (nvbios_rd08(bios, mdata) & 0x01)
1579 clock *= 2;
1580 init_prog_pll(init, 0x680504, clock);
1581
1582 init_exec_force(init, false);
1583 }
1584
1585 /**
1586 * INIT_CONFIGURE_PREINIT - opcode 0x68
1587 *
1588 */
1589 static void
1590 init_configure_preinit(struct nvbios_init *init)
1591 {
1592 struct nvkm_bios *bios = init->bios;
1593 u32 strap;
1594
1595 trace("CONFIGURE_PREINIT\n");
1596 init->offset += 1;
1597
1598 if (bios->version.major > 2) {
1599 init_done(init);
1600 return;
1601 }
1602 init_exec_force(init, true);
1603
1604 strap = init_rd32(init, 0x101000);
1605 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1606 init_wrvgai(init, 0x03d4, 0x3c, strap);
1607
1608 init_exec_force(init, false);
1609 }
1610
1611 /**
1612 * INIT_IO - opcode 0x69
1613 *
1614 */
1615 static void
1616 init_io(struct nvbios_init *init)
1617 {
1618 struct nvkm_bios *bios = init->bios;
1619 u16 port = nvbios_rd16(bios, init->offset + 1);
1620 u8 mask = nvbios_rd16(bios, init->offset + 3);
1621 u8 data = nvbios_rd16(bios, init->offset + 4);
1622 u8 value;
1623
1624 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1625 init->offset += 5;
1626
1627 /* ummm.. yes.. should really figure out wtf this is and why it's
1628 * needed some day.. it's almost certainly wrong, but, it also
1629 * somehow makes things work...
1630 */
1631 if (bios->subdev.device->card_type >= NV_50 &&
1632 port == 0x03c3 && data == 0x01) {
1633 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1634 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1635 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1636 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1637 mdelay(10);
1638 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1639 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1640 init_wr32(init, 0x614100, 0x00800018);
1641 init_wr32(init, 0x614900, 0x00800018);
1642 mdelay(10);
1643 init_wr32(init, 0x614100, 0x10000018);
1644 init_wr32(init, 0x614900, 0x10000018);
1645 }
1646
1647 value = init_rdport(init, port) & mask;
1648 init_wrport(init, port, data | value);
1649 }
1650
1651 /**
1652 * INIT_SUB - opcode 0x6b
1653 *
1654 */
1655 static void
1656 init_sub(struct nvbios_init *init)
1657 {
1658 struct nvkm_bios *bios = init->bios;
1659 u8 index = nvbios_rd08(bios, init->offset + 1);
1660 u16 addr, save;
1661
1662 trace("SUB\t0x%02x\n", index);
1663
1664 addr = init_script(bios, index);
1665 if (addr && init_exec(init)) {
1666 save = init->offset;
1667 init->offset = addr;
1668 if (nvbios_exec(init)) {
1669 error("error parsing sub-table\n");
1670 return;
1671 }
1672 init->offset = save;
1673 }
1674
1675 init->offset += 2;
1676 }
1677
1678 /**
1679 * INIT_RAM_CONDITION - opcode 0x6d
1680 *
1681 */
1682 static void
1683 init_ram_condition(struct nvbios_init *init)
1684 {
1685 struct nvkm_bios *bios = init->bios;
1686 u8 mask = nvbios_rd08(bios, init->offset + 1);
1687 u8 value = nvbios_rd08(bios, init->offset + 2);
1688
1689 trace("RAM_CONDITION\t"
1690 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1691 init->offset += 3;
1692
1693 if ((init_rd32(init, 0x100000) & mask) != value)
1694 init_exec_set(init, false);
1695 }
1696
1697 /**
1698 * INIT_NV_REG - opcode 0x6e
1699 *
1700 */
1701 static void
1702 init_nv_reg(struct nvbios_init *init)
1703 {
1704 struct nvkm_bios *bios = init->bios;
1705 u32 reg = nvbios_rd32(bios, init->offset + 1);
1706 u32 mask = nvbios_rd32(bios, init->offset + 5);
1707 u32 data = nvbios_rd32(bios, init->offset + 9);
1708
1709 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1710 init->offset += 13;
1711
1712 init_mask(init, reg, ~mask, data);
1713 }
1714
1715 /**
1716 * INIT_MACRO - opcode 0x6f
1717 *
1718 */
1719 static void
1720 init_macro(struct nvbios_init *init)
1721 {
1722 struct nvkm_bios *bios = init->bios;
1723 u8 macro = nvbios_rd08(bios, init->offset + 1);
1724 u16 table;
1725
1726 trace("MACRO\t0x%02x\n", macro);
1727
1728 table = init_macro_table(init);
1729 if (table) {
1730 u32 addr = nvbios_rd32(bios, table + (macro * 8) + 0);
1731 u32 data = nvbios_rd32(bios, table + (macro * 8) + 4);
1732 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1733 init_wr32(init, addr, data);
1734 }
1735
1736 init->offset += 2;
1737 }
1738
1739 /**
1740 * INIT_RESUME - opcode 0x72
1741 *
1742 */
1743 static void
1744 init_resume(struct nvbios_init *init)
1745 {
1746 trace("RESUME\n");
1747 init->offset += 1;
1748 init_exec_set(init, true);
1749 }
1750
1751 /**
1752 * INIT_STRAP_CONDITION - opcode 0x73
1753 *
1754 */
1755 static void
1756 init_strap_condition(struct nvbios_init *init)
1757 {
1758 struct nvkm_bios *bios = init->bios;
1759 u32 mask = nvbios_rd32(bios, init->offset + 1);
1760 u32 value = nvbios_rd32(bios, init->offset + 5);
1761
1762 trace("STRAP_CONDITION\t(R[0x101000] & 0x%08x) == 0x%08x\n", mask, value);
1763 init->offset += 9;
1764
1765 if ((init_rd32(init, 0x101000) & mask) != value)
1766 init_exec_set(init, false);
1767 }
1768
1769 /**
1770 * INIT_TIME - opcode 0x74
1771 *
1772 */
1773 static void
1774 init_time(struct nvbios_init *init)
1775 {
1776 struct nvkm_bios *bios = init->bios;
1777 u16 usec = nvbios_rd16(bios, init->offset + 1);
1778
1779 trace("TIME\t0x%04x\n", usec);
1780 init->offset += 3;
1781
1782 if (init_exec(init)) {
1783 if (usec < 1000)
1784 udelay(usec);
1785 else
1786 mdelay((usec + 900) / 1000);
1787 }
1788 }
1789
1790 /**
1791 * INIT_CONDITION - opcode 0x75
1792 *
1793 */
1794 static void
1795 init_condition(struct nvbios_init *init)
1796 {
1797 struct nvkm_bios *bios = init->bios;
1798 u8 cond = nvbios_rd08(bios, init->offset + 1);
1799
1800 trace("CONDITION\t0x%02x\n", cond);
1801 init->offset += 2;
1802
1803 if (!init_condition_met(init, cond))
1804 init_exec_set(init, false);
1805 }
1806
1807 /**
1808 * INIT_IO_CONDITION - opcode 0x76
1809 *
1810 */
1811 static void
1812 init_io_condition(struct nvbios_init *init)
1813 {
1814 struct nvkm_bios *bios = init->bios;
1815 u8 cond = nvbios_rd08(bios, init->offset + 1);
1816
1817 trace("IO_CONDITION\t0x%02x\n", cond);
1818 init->offset += 2;
1819
1820 if (!init_io_condition_met(init, cond))
1821 init_exec_set(init, false);
1822 }
1823
1824 /**
1825 * INIT_ZM_REG16 - opcode 0x77
1826 *
1827 */
1828 static void
1829 init_zm_reg16(struct nvbios_init *init)
1830 {
1831 struct nvkm_bios *bios = init->bios;
1832 u32 addr = nvbios_rd32(bios, init->offset + 1);
1833 u16 data = nvbios_rd16(bios, init->offset + 5);
1834
1835 trace("ZM_REG\tR[0x%06x] = 0x%04x\n", addr, data);
1836 init->offset += 7;
1837
1838 init_wr32(init, addr, data);
1839 }
1840
1841 /**
1842 * INIT_INDEX_IO - opcode 0x78
1843 *
1844 */
1845 static void
1846 init_index_io(struct nvbios_init *init)
1847 {
1848 struct nvkm_bios *bios = init->bios;
1849 u16 port = nvbios_rd16(bios, init->offset + 1);
1850 u8 index = nvbios_rd16(bios, init->offset + 3);
1851 u8 mask = nvbios_rd08(bios, init->offset + 4);
1852 u8 data = nvbios_rd08(bios, init->offset + 5);
1853 u8 value;
1854
1855 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1856 port, index, mask, data);
1857 init->offset += 6;
1858
1859 value = init_rdvgai(init, port, index) & mask;
1860 init_wrvgai(init, port, index, data | value);
1861 }
1862
1863 /**
1864 * INIT_PLL - opcode 0x79
1865 *
1866 */
1867 static void
1868 init_pll(struct nvbios_init *init)
1869 {
1870 struct nvkm_bios *bios = init->bios;
1871 u32 reg = nvbios_rd32(bios, init->offset + 1);
1872 u32 freq = nvbios_rd16(bios, init->offset + 5) * 10;
1873
1874 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1875 init->offset += 7;
1876
1877 init_prog_pll(init, reg, freq);
1878 }
1879
1880 /**
1881 * INIT_ZM_REG - opcode 0x7a
1882 *
1883 */
1884 static void
1885 init_zm_reg(struct nvbios_init *init)
1886 {
1887 struct nvkm_bios *bios = init->bios;
1888 u32 addr = nvbios_rd32(bios, init->offset + 1);
1889 u32 data = nvbios_rd32(bios, init->offset + 5);
1890
1891 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1892 init->offset += 9;
1893
1894 if (addr == 0x000200)
1895 data |= 0x00000001;
1896
1897 init_wr32(init, addr, data);
1898 }
1899
1900 /**
1901 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1902 *
1903 */
1904 static void
1905 init_ram_restrict_pll(struct nvbios_init *init)
1906 {
1907 struct nvkm_bios *bios = init->bios;
1908 u8 type = nvbios_rd08(bios, init->offset + 1);
1909 u8 count = init_ram_restrict_group_count(init);
1910 u8 strap = init_ram_restrict(init);
1911 u8 cconf;
1912
1913 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1914 init->offset += 2;
1915
1916 for (cconf = 0; cconf < count; cconf++) {
1917 u32 freq = nvbios_rd32(bios, init->offset);
1918
1919 if (cconf == strap) {
1920 trace("%dkHz *\n", freq);
1921 init_prog_pll(init, type, freq);
1922 } else {
1923 trace("%dkHz\n", freq);
1924 }
1925
1926 init->offset += 4;
1927 }
1928 }
1929
1930 /**
1931 * INIT_GPIO - opcode 0x8e
1932 *
1933 */
1934 static void
1935 init_gpio(struct nvbios_init *init)
1936 {
1937 struct nvkm_gpio *gpio = init->bios->subdev.device->gpio;
1938
1939 trace("GPIO\n");
1940 init->offset += 1;
1941
1942 if (init_exec(init))
1943 nvkm_gpio_reset(gpio, DCB_GPIO_UNUSED);
1944 }
1945
1946 /**
1947 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1948 *
1949 */
1950 static void
1951 init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1952 {
1953 struct nvkm_bios *bios = init->bios;
1954 u32 addr = nvbios_rd32(bios, init->offset + 1);
1955 u8 incr = nvbios_rd08(bios, init->offset + 5);
1956 u8 num = nvbios_rd08(bios, init->offset + 6);
1957 u8 count = init_ram_restrict_group_count(init);
1958 u8 index = init_ram_restrict(init);
1959 u8 i, j;
1960
1961 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1962 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
1963 init->offset += 7;
1964
1965 for (i = 0; i < num; i++) {
1966 trace("\tR[0x%06x] = {\n", addr);
1967 for (j = 0; j < count; j++) {
1968 u32 data = nvbios_rd32(bios, init->offset);
1969
1970 if (j == index) {
1971 trace("\t\t0x%08x *\n", data);
1972 init_wr32(init, addr, data);
1973 } else {
1974 trace("\t\t0x%08x\n", data);
1975 }
1976
1977 init->offset += 4;
1978 }
1979 trace("\t}\n");
1980 addr += incr;
1981 }
1982 }
1983
1984 /**
1985 * INIT_COPY_ZM_REG - opcode 0x90
1986 *
1987 */
1988 static void
1989 init_copy_zm_reg(struct nvbios_init *init)
1990 {
1991 struct nvkm_bios *bios = init->bios;
1992 u32 sreg = nvbios_rd32(bios, init->offset + 1);
1993 u32 dreg = nvbios_rd32(bios, init->offset + 5);
1994
1995 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
1996 init->offset += 9;
1997
1998 init_wr32(init, dreg, init_rd32(init, sreg));
1999 }
2000
2001 /**
2002 * INIT_ZM_REG_GROUP - opcode 0x91
2003 *
2004 */
2005 static void
2006 init_zm_reg_group(struct nvbios_init *init)
2007 {
2008 struct nvkm_bios *bios = init->bios;
2009 u32 addr = nvbios_rd32(bios, init->offset + 1);
2010 u8 count = nvbios_rd08(bios, init->offset + 5);
2011
2012 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
2013 init->offset += 6;
2014
2015 while (count--) {
2016 u32 data = nvbios_rd32(bios, init->offset);
2017 trace("\t0x%08x\n", data);
2018 init_wr32(init, addr, data);
2019 init->offset += 4;
2020 }
2021 }
2022
2023 /**
2024 * INIT_XLAT - opcode 0x96
2025 *
2026 */
2027 static void
2028 init_xlat(struct nvbios_init *init)
2029 {
2030 struct nvkm_bios *bios = init->bios;
2031 u32 saddr = nvbios_rd32(bios, init->offset + 1);
2032 u8 sshift = nvbios_rd08(bios, init->offset + 5);
2033 u8 smask = nvbios_rd08(bios, init->offset + 6);
2034 u8 index = nvbios_rd08(bios, init->offset + 7);
2035 u32 daddr = nvbios_rd32(bios, init->offset + 8);
2036 u32 dmask = nvbios_rd32(bios, init->offset + 12);
2037 u8 shift = nvbios_rd08(bios, init->offset + 16);
2038 u32 data;
2039
2040 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
2041 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
2042 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
2043 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
2044 init->offset += 17;
2045
2046 data = init_shift(init_rd32(init, saddr), sshift) & smask;
2047 data = init_xlat_(init, index, data) << shift;
2048 init_mask(init, daddr, ~dmask, data);
2049 }
2050
2051 /**
2052 * INIT_ZM_MASK_ADD - opcode 0x97
2053 *
2054 */
2055 static void
2056 init_zm_mask_add(struct nvbios_init *init)
2057 {
2058 struct nvkm_bios *bios = init->bios;
2059 u32 addr = nvbios_rd32(bios, init->offset + 1);
2060 u32 mask = nvbios_rd32(bios, init->offset + 5);
2061 u32 add = nvbios_rd32(bios, init->offset + 9);
2062 u32 data;
2063
2064 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
2065 init->offset += 13;
2066
2067 data = init_rd32(init, addr);
2068 data = (data & mask) | ((data + add) & ~mask);
2069 init_wr32(init, addr, data);
2070 }
2071
2072 /**
2073 * INIT_AUXCH - opcode 0x98
2074 *
2075 */
2076 static void
2077 init_auxch(struct nvbios_init *init)
2078 {
2079 struct nvkm_bios *bios = init->bios;
2080 u32 addr = nvbios_rd32(bios, init->offset + 1);
2081 u8 count = nvbios_rd08(bios, init->offset + 5);
2082
2083 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2084 init->offset += 6;
2085
2086 while (count--) {
2087 u8 mask = nvbios_rd08(bios, init->offset + 0);
2088 u8 data = nvbios_rd08(bios, init->offset + 1);
2089 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
2090 mask = init_rdauxr(init, addr) & mask;
2091 init_wrauxr(init, addr, mask | data);
2092 init->offset += 2;
2093 }
2094 }
2095
2096 /**
2097 * INIT_AUXCH - opcode 0x99
2098 *
2099 */
2100 static void
2101 init_zm_auxch(struct nvbios_init *init)
2102 {
2103 struct nvkm_bios *bios = init->bios;
2104 u32 addr = nvbios_rd32(bios, init->offset + 1);
2105 u8 count = nvbios_rd08(bios, init->offset + 5);
2106
2107 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2108 init->offset += 6;
2109
2110 while (count--) {
2111 u8 data = nvbios_rd08(bios, init->offset + 0);
2112 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
2113 init_wrauxr(init, addr, data);
2114 init->offset += 1;
2115 }
2116 }
2117
2118 /**
2119 * INIT_I2C_LONG_IF - opcode 0x9a
2120 *
2121 */
2122 static void
2123 init_i2c_long_if(struct nvbios_init *init)
2124 {
2125 struct nvkm_bios *bios = init->bios;
2126 u8 index = nvbios_rd08(bios, init->offset + 1);
2127 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
2128 u8 reglo = nvbios_rd08(bios, init->offset + 3);
2129 u8 reghi = nvbios_rd08(bios, init->offset + 4);
2130 u8 mask = nvbios_rd08(bios, init->offset + 5);
2131 u8 data = nvbios_rd08(bios, init->offset + 6);
2132 struct i2c_adapter *adap;
2133
2134 trace("I2C_LONG_IF\t"
2135 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2136 index, addr, reglo, reghi, mask, data);
2137 init->offset += 7;
2138
2139 adap = init_i2c(init, index);
2140 if (adap) {
2141 u8 i[2] = { reghi, reglo };
2142 u8 o[1] = {};
2143 struct i2c_msg msg[] = {
2144 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2145 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2146 };
2147 int ret;
2148
2149 ret = i2c_transfer(adap, msg, 2);
2150 if (ret == 2 && ((o[0] & mask) == data))
2151 return;
2152 }
2153
2154 init_exec_set(init, false);
2155 }
2156
2157 /**
2158 * INIT_GPIO_NE - opcode 0xa9
2159 *
2160 */
2161 static void
2162 init_gpio_ne(struct nvbios_init *init)
2163 {
2164 struct nvkm_bios *bios = init->bios;
2165 struct nvkm_gpio *gpio = bios->subdev.device->gpio;
2166 struct dcb_gpio_func func;
2167 u8 count = nvbios_rd08(bios, init->offset + 1);
2168 u8 idx = 0, ver, len;
2169 u16 data, i;
2170
2171 trace("GPIO_NE\t");
2172 init->offset += 2;
2173
2174 for (i = init->offset; i < init->offset + count; i++)
2175 cont("0x%02x ", nvbios_rd08(bios, i));
2176 cont("\n");
2177
2178 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2179 if (func.func != DCB_GPIO_UNUSED) {
2180 for (i = init->offset; i < init->offset + count; i++) {
2181 if (func.func == nvbios_rd08(bios, i))
2182 break;
2183 }
2184
2185 trace("\tFUNC[0x%02x]", func.func);
2186 if (i == (init->offset + count)) {
2187 cont(" *");
2188 if (init_exec(init))
2189 nvkm_gpio_reset(gpio, func.func);
2190 }
2191 cont("\n");
2192 }
2193 }
2194
2195 init->offset += count;
2196 }
2197
2198 static struct nvbios_init_opcode {
2199 void (*exec)(struct nvbios_init *);
2200 } init_opcode[] = {
2201 [0x32] = { init_io_restrict_prog },
2202 [0x33] = { init_repeat },
2203 [0x34] = { init_io_restrict_pll },
2204 [0x36] = { init_end_repeat },
2205 [0x37] = { init_copy },
2206 [0x38] = { init_not },
2207 [0x39] = { init_io_flag_condition },
2208 [0x3a] = { init_dp_condition },
2209 [0x3b] = { init_io_mask_or },
2210 [0x3c] = { init_io_or },
2211 [0x47] = { init_andn_reg },
2212 [0x48] = { init_or_reg },
2213 [0x49] = { init_idx_addr_latched },
2214 [0x4a] = { init_io_restrict_pll2 },
2215 [0x4b] = { init_pll2 },
2216 [0x4c] = { init_i2c_byte },
2217 [0x4d] = { init_zm_i2c_byte },
2218 [0x4e] = { init_zm_i2c },
2219 [0x4f] = { init_tmds },
2220 [0x50] = { init_zm_tmds_group },
2221 [0x51] = { init_cr_idx_adr_latch },
2222 [0x52] = { init_cr },
2223 [0x53] = { init_zm_cr },
2224 [0x54] = { init_zm_cr_group },
2225 [0x56] = { init_condition_time },
2226 [0x57] = { init_ltime },
2227 [0x58] = { init_zm_reg_sequence },
2228 [0x59] = { init_pll_indirect },
2229 [0x5a] = { init_zm_reg_indirect },
2230 [0x5b] = { init_sub_direct },
2231 [0x5c] = { init_jump },
2232 [0x5e] = { init_i2c_if },
2233 [0x5f] = { init_copy_nv_reg },
2234 [0x62] = { init_zm_index_io },
2235 [0x63] = { init_compute_mem },
2236 [0x65] = { init_reset },
2237 [0x66] = { init_configure_mem },
2238 [0x67] = { init_configure_clk },
2239 [0x68] = { init_configure_preinit },
2240 [0x69] = { init_io },
2241 [0x6b] = { init_sub },
2242 [0x6d] = { init_ram_condition },
2243 [0x6e] = { init_nv_reg },
2244 [0x6f] = { init_macro },
2245 [0x71] = { init_done },
2246 [0x72] = { init_resume },
2247 [0x73] = { init_strap_condition },
2248 [0x74] = { init_time },
2249 [0x75] = { init_condition },
2250 [0x76] = { init_io_condition },
2251 [0x77] = { init_zm_reg16 },
2252 [0x78] = { init_index_io },
2253 [0x79] = { init_pll },
2254 [0x7a] = { init_zm_reg },
2255 [0x87] = { init_ram_restrict_pll },
2256 [0x8c] = { init_reserved },
2257 [0x8d] = { init_reserved },
2258 [0x8e] = { init_gpio },
2259 [0x8f] = { init_ram_restrict_zm_reg_group },
2260 [0x90] = { init_copy_zm_reg },
2261 [0x91] = { init_zm_reg_group },
2262 [0x92] = { init_reserved },
2263 [0x96] = { init_xlat },
2264 [0x97] = { init_zm_mask_add },
2265 [0x98] = { init_auxch },
2266 [0x99] = { init_zm_auxch },
2267 [0x9a] = { init_i2c_long_if },
2268 [0xa9] = { init_gpio_ne },
2269 [0xaa] = { init_reserved },
2270 };
2271
2272 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2273
2274 int
2275 nvbios_exec(struct nvbios_init *init)
2276 {
2277 init->nested++;
2278 while (init->offset) {
2279 u8 opcode = nvbios_rd08(init->bios, init->offset);
2280 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2281 error("unknown opcode 0x%02x\n", opcode);
2282 return -EINVAL;
2283 }
2284
2285 init_opcode[opcode].exec(init);
2286 }
2287 init->nested--;
2288 return 0;
2289 }
2290
2291 int
2292 nvbios_init(struct nvkm_subdev *subdev, bool execute)
2293 {
2294 struct nvkm_bios *bios = subdev->device->bios;
2295 int ret = 0;
2296 int i = -1;
2297 u16 data;
2298
2299 if (execute)
2300 nvkm_debug(subdev, "running init tables\n");
2301 while (!ret && (data = (init_script(bios, ++i)))) {
2302 struct nvbios_init init = {
2303 .subdev = subdev,
2304 .bios = bios,
2305 .offset = data,
2306 .outp = NULL,
2307 .crtc = -1,
2308 .execute = execute ? 1 : 0,
2309 };
2310
2311 ret = nvbios_exec(&init);
2312 }
2313
2314 /* the vbios parser will run this right after the normal init
2315 * tables, whereas the binary driver appears to run it later.
2316 */
2317 if (!ret && (data = init_unknown_script(bios))) {
2318 struct nvbios_init init = {
2319 .subdev = subdev,
2320 .bios = bios,
2321 .offset = data,
2322 .outp = NULL,
2323 .crtc = -1,
2324 .execute = execute ? 1 : 0,
2325 };
2326
2327 ret = nvbios_exec(&init);
2328 }
2329
2330 return ret;
2331 }
Linux with added FPC-III support