drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv50.h"
  25
  26 #include <subdev/bios.h>
  27 #include <subdev/bios/dcb.h>
  28 #include <subdev/bios/disp.h>
  29 #include <subdev/bios/init.h>
  30 #include <subdev/bios/pll.h>
  31 #include <subdev/clk/pll.h>
  32 #include <subdev/vga.h>
  33
  34 int
  35 nv50_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq)
  36 {
  37         struct nvkm_subdev *subdev = &init->subdev;
  38         struct nvkm_device *device = subdev->device;
  39         struct nvkm_bios *bios = device->bios;
  40         struct nvbios_pll info;
  41         int N1, M1, N2, M2, P;
  42         int ret;
  43
  44         ret = nvbios_pll_parse(bios, type, &info);
  45         if (ret) {
  46                 nvkm_error(subdev, "failed to retrieve pll data, %d\n", ret);
  47                 return ret;
  48         }
  49
  50         ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
  51         if (!ret) {
  52                 nvkm_error(subdev, "failed pll calculation\n");
  53                 return ret;
  54         }
  55
  56         switch (info.type) {
  57         case PLL_VPLL0:
  58         case PLL_VPLL1:
  59                 nvkm_wr32(device, info.reg + 0, 0x10000611);
  60                 nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
  61                 nvkm_mask(device, info.reg + 8, 0x7fff00ff, (P  << 28) |
  62                                                             (M2 << 16) | N2);
  63                 break;
  64         case PLL_MEMORY:
  65                 nvkm_mask(device, info.reg + 0, 0x01ff0000,
  66                                                 (P << 22) |
  67                                                 (info.bias_p << 19) |
  68                                                 (P << 16));
  69                 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1);
  70                 break;
  71         default:
  72                 nvkm_mask(device, info.reg + 0, 0x00070000, (P << 16));
  73                 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1);
  74                 break;
  75         }
  76
  77         return 0;
  78 }
  79
  80 static u64
  81 nv50_devinit_disable(struct nvkm_devinit *init)
  82 {
  83         struct nvkm_device *device = init->subdev.device;
  84         u32 r001540 = nvkm_rd32(device, 0x001540);
  85         u64 disable = 0ULL;
  86
  87         if (!(r001540 & 0x40000000))
  88                 disable |= (1ULL << NVKM_ENGINE_MPEG);
  89
  90         return disable;
  91 }
  92
  93 void
  94 nv50_devinit_preinit(struct nvkm_devinit *base)
  95 {
  96         struct nv50_devinit *init = nv50_devinit(base);
  97         struct nvkm_subdev *subdev = &init->base.subdev;
  98         struct nvkm_device *device = subdev->device;
  99
 100         /* our heuristics can't detect whether the board has had its
 101          * devinit scripts executed or not if the display engine is
 102          * missing, assume it's a secondary gpu which requires post
 103          */
 104         if (!init->base.post) {
 105                 u64 disable = nvkm_devinit_disable(&init->base);
 106                 if (disable & (1ULL << NVKM_ENGINE_DISP))
 107                         init->base.post = true;
 108         }
 109
 110         /* magic to detect whether or not x86 vbios code has executed
 111          * the devinit scripts to initialise the board
 112          */
 113         if (!init->base.post) {
 114                 if (!nvkm_rdvgac(device, 0, 0x00) &&
 115                     !nvkm_rdvgac(device, 0, 0x1a)) {
 116                         nvkm_debug(subdev, "adaptor not initialised\n");
 117                         init->base.post = true;
 118                 }
 119         }
 120 }
 121
 122 void
 123 nv50_devinit_init(struct nvkm_devinit *base)
 124 {
 125         struct nv50_devinit *init = nv50_devinit(base);
 126         struct nvkm_subdev *subdev = &init->base.subdev;
 127         struct nvkm_device *device = subdev->device;
 128         struct nvkm_bios *bios = device->bios;
 129         struct nvbios_outp info;
 130         struct dcb_output outp;
 131         u8  ver = 0xff, hdr, cnt, len;
 132         int i = 0;
 133
 134         /* if we ran the init tables, we have to execute the first script
 135          * pointer of each dcb entry's display encoder table in order
 136          * to properly initialise each encoder.
 137          */
 138         while (init->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) {
 139                 if (nvbios_outp_match(bios, outp.hasht, outp.hashm,
 140                                       &ver, &hdr, &cnt, &len, &info)) {
 141                         struct nvbios_init exec = {
 142                                 .subdev = subdev,
 143                                 .bios = bios,
 144                                 .offset = info.script[0],
 145                                 .outp = &outp,
 146                                 .crtc = -1,
 147                                 .execute = 1,
 148                         };
 149
 150                         nvbios_exec(&exec);
 151                 }
 152                 i++;
 153         }
 154 }
 155
 156 int
 157 nv50_devinit_new_(const struct nvkm_devinit_func *func,
 158                   struct nvkm_device *device, int index,
 159                   struct nvkm_devinit **pinit)
 160 {
 161         struct nv50_devinit *init;
 162
 163         if (!(init = kzalloc(sizeof(*init), GFP_KERNEL)))
 164                 return -ENOMEM;
 165         *pinit = &init->base;
 166
 167         nvkm_devinit_ctor(func, device, index, &init->base);
 168         return 0;
 169 }
 170
 171 static const struct nvkm_devinit_func
 172 nv50_devinit = {
 173         .preinit = nv50_devinit_preinit,
 174         .init = nv50_devinit_init,
 175         .post = nv04_devinit_post,
 176         .pll_set = nv50_devinit_pll_set,
 177         .disable = nv50_devinit_disable,
 178 };
 179
 180 int
 181 nv50_devinit_new(struct nvkm_device *device, int index,
 182                  struct nvkm_devinit **pinit)
 183 {
 184         return nv50_devinit_new_(&nv50_devinit, device, index, pinit);
 185 }