drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "priv.h"
  25
  26 static const struct nvkm_mc_intr
  27 g98_mc_intr[] = {
  28         { 0x04000000, NVKM_ENGINE_DISP },  /* DISP first, so pageflip timestamps work */
  29         { 0x00000001, NVKM_ENGINE_MSPPP },
  30         { 0x00000100, NVKM_ENGINE_FIFO },
  31         { 0x00001000, NVKM_ENGINE_GR },
  32         { 0x00004000, NVKM_ENGINE_SEC },        /* NV84:NVA3 */
  33         { 0x00008000, NVKM_ENGINE_MSVLD },
  34         { 0x00020000, NVKM_ENGINE_MSPDEC },
  35         { 0x00040000, NVKM_SUBDEV_PMU },        /* NVA3:NVC0 */
  36         { 0x00080000, NVKM_SUBDEV_THERM },      /* NVA3:NVC0 */
  37         { 0x00100000, NVKM_SUBDEV_TIMER },
  38         { 0x00200000, NVKM_SUBDEV_GPIO },       /* PMGR->GPIO */
  39         { 0x00200000, NVKM_SUBDEV_I2C },        /* PMGR->I2C/AUX */
  40         { 0x00400000, NVKM_ENGINE_CE0 },        /* NVA3-     */
  41         { 0x10000000, NVKM_SUBDEV_BUS },
  42         { 0x80000000, NVKM_ENGINE_SW },
  43         { 0x0042d101, NVKM_SUBDEV_FB },
  44         {},
  45 };
  46
  47 static const struct nvkm_mc_func
  48 g98_mc = {
  49         .init = nv50_mc_init,
  50         .intr = g98_mc_intr,
  51         .intr_unarm = nv04_mc_intr_unarm,
  52         .intr_rearm = nv04_mc_intr_rearm,
  53         .intr_mask = nv04_mc_intr_mask,
  54 };
  55
  56 int
  57 g98_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
  58 {
  59         return nvkm_mc_new_(&g98_mc, device, index, pmc);
  60 }