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[SCSI] drivers/scsi/dpt_i2o.c: fix compile warnings
[linux/fpc-iii.git] / drivers / parport / parport_pc.c
blobc5774e7855d0362acbea8c7c5eb32049e0332612
1 /* Low-level parallel-port routines for 8255-based PC-style hardware.
2 *
3 * Authors: Phil Blundell <philb@gnu.org>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
6 * David Campbell <campbell@torque.net>
7 * Andrea Arcangeli
8 *
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
10 *
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
17 */
18
19 /* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
22 * layout is:
23 *
24 * base+0 data
25 * base+1 status
26 * base+2 control
27 *
28 * In addition, there are some optional registers:
29 *
30 * base+3 EPP address
31 * base+4 EPP data
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
35 *
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
39 * accommodate this.
40 *
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
43 */
44
45 #include <linux/config.h>
46 #include <linux/module.h>
47 #include <linux/init.h>
48 #include <linux/sched.h>
49 #include <linux/delay.h>
50 #include <linux/errno.h>
51 #include <linux/interrupt.h>
52 #include <linux/ioport.h>
53 #include <linux/kernel.h>
54 #include <linux/slab.h>
55 #include <linux/pci.h>
56 #include <linux/pnp.h>
57 #include <linux/sysctl.h>
58
59 #include <asm/io.h>
60 #include <asm/dma.h>
61 #include <asm/uaccess.h>
62
63 #include <linux/parport.h>
64 #include <linux/parport_pc.h>
65 #include <linux/via.h>
66 #include <asm/parport.h>
67
68 #define PARPORT_PC_MAX_PORTS PARPORT_MAX
69
70 /* ECR modes */
71 #define ECR_SPP 00
72 #define ECR_PS2 01
73 #define ECR_PPF 02
74 #define ECR_ECP 03
75 #define ECR_EPP 04
76 #define ECR_VND 05
77 #define ECR_TST 06
78 #define ECR_CNF 07
79 #define ECR_MODE_MASK 0xe0
80 #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v))
81
82 #undef DEBUG
83
84 #ifdef DEBUG
85 #define DPRINTK printk
86 #else
87 #define DPRINTK(stuff...)
88 #endif
89
90
91 #define NR_SUPERIOS 3
92 static struct superio_struct { /* For Super-IO chips autodetection */
93 int io;
94 int irq;
95 int dma;
96 } superios[NR_SUPERIOS] __devinitdata = { {0,},};
97
98 static int user_specified;
99 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
100 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
101 static int verbose_probing;
102 #endif
103 static int pci_registered_parport;
104 static int pnp_registered_parport;
105
106 /* frob_control, but for ECR */
107 static void frob_econtrol (struct parport *pb, unsigned char m,
108 unsigned char v)
109 {
110 unsigned char ectr = 0;
111
112 if (m != 0xff)
113 ectr = inb (ECONTROL (pb));
114
115 DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
116 m, v, ectr, (ectr & ~m) ^ v);
117
118 outb ((ectr & ~m) ^ v, ECONTROL (pb));
119 }
120
121 static __inline__ void frob_set_mode (struct parport *p, int mode)
122 {
123 frob_econtrol (p, ECR_MODE_MASK, mode << 5);
124 }
125
126 #ifdef CONFIG_PARPORT_PC_FIFO
127 /* Safely change the mode bits in the ECR
128 Returns:
129 0 : Success
130 -EBUSY: Could not drain FIFO in some finite amount of time,
131 mode not changed!
132 */
133 static int change_mode(struct parport *p, int m)
134 {
135 const struct parport_pc_private *priv = p->physport->private_data;
136 unsigned char oecr;
137 int mode;
138
139 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m);
140
141 if (!priv->ecr) {
142 printk (KERN_DEBUG "change_mode: but there's no ECR!\n");
143 return 0;
144 }
145
146 /* Bits <7:5> contain the mode. */
147 oecr = inb (ECONTROL (p));
148 mode = (oecr >> 5) & 0x7;
149 if (mode == m) return 0;
150
151 if (mode >= 2 && !(priv->ctr & 0x20)) {
152 /* This mode resets the FIFO, so we may
153 * have to wait for it to drain first. */
154 unsigned long expire = jiffies + p->physport->cad->timeout;
155 int counter;
156 switch (mode) {
157 case ECR_PPF: /* Parallel Port FIFO mode */
158 case ECR_ECP: /* ECP Parallel Port mode */
159 /* Busy wait for 200us */
160 for (counter = 0; counter < 40; counter++) {
161 if (inb (ECONTROL (p)) & 0x01)
162 break;
163 if (signal_pending (current)) break;
164 udelay (5);
165 }
166
167 /* Poll slowly. */
168 while (!(inb (ECONTROL (p)) & 0x01)) {
169 if (time_after_eq (jiffies, expire))
170 /* The FIFO is stuck. */
171 return -EBUSY;
172 __set_current_state (TASK_INTERRUPTIBLE);
173 schedule_timeout ((HZ + 99) / 100);
174 if (signal_pending (current))
175 break;
176 }
177 }
178 }
179
180 if (mode >= 2 && m >= 2) {
181 /* We have to go through mode 001 */
182 oecr &= ~(7 << 5);
183 oecr |= ECR_PS2 << 5;
184 ECR_WRITE (p, oecr);
185 }
186
187 /* Set the mode. */
188 oecr &= ~(7 << 5);
189 oecr |= m << 5;
190 ECR_WRITE (p, oecr);
191 return 0;
192 }
193
194 #ifdef CONFIG_PARPORT_1284
195 /* Find FIFO lossage; FIFO is reset */
196 #if 0
197 static int get_fifo_residue (struct parport *p)
198 {
199 int residue;
200 int cnfga;
201 const struct parport_pc_private *priv = p->physport->private_data;
202
203 /* Adjust for the contents of the FIFO. */
204 for (residue = priv->fifo_depth; ; residue--) {
205 if (inb (ECONTROL (p)) & 0x2)
206 /* Full up. */
207 break;
208
209 outb (0, FIFO (p));
210 }
211
212 printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name,
213 residue);
214
215 /* Reset the FIFO. */
216 frob_set_mode (p, ECR_PS2);
217
218 /* Now change to config mode and clean up. FIXME */
219 frob_set_mode (p, ECR_CNF);
220 cnfga = inb (CONFIGA (p));
221 printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga);
222
223 if (!(cnfga & (1<<2))) {
224 printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name);
225 residue++;
226 }
227
228 /* Don't care about partial PWords until support is added for
229 * PWord != 1 byte. */
230
231 /* Back to PS2 mode. */
232 frob_set_mode (p, ECR_PS2);
233
234 DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p)));
235 return residue;
236 }
237 #endif /* 0 */
238 #endif /* IEEE 1284 support */
239 #endif /* FIFO support */
240
241 /*
242 * Clear TIMEOUT BIT in EPP MODE
243 *
244 * This is also used in SPP detection.
245 */
246 static int clear_epp_timeout(struct parport *pb)
247 {
248 unsigned char r;
249
250 if (!(parport_pc_read_status(pb) & 0x01))
251 return 1;
252
253 /* To clear timeout some chips require double read */
254 parport_pc_read_status(pb);
255 r = parport_pc_read_status(pb);
256 outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */
257 outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */
258 r = parport_pc_read_status(pb);
259
260 return !(r & 0x01);
261 }
262
263 /*
264 * Access functions.
265 *
266 * Most of these aren't static because they may be used by the
267 * parport_xxx_yyy macros. extern __inline__ versions of several
268 * of these are in parport_pc.h.
269 */
270
271 static irqreturn_t parport_pc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
272 {
273 parport_generic_irq(irq, (struct parport *) dev_id, regs);
274 /* FIXME! Was it really ours? */
275 return IRQ_HANDLED;
276 }
277
278 static void parport_pc_init_state(struct pardevice *dev, struct parport_state *s)
279 {
280 s->u.pc.ctr = 0xc;
281 if (dev->irq_func &&
282 dev->port->irq != PARPORT_IRQ_NONE)
283 /* Set ackIntEn */
284 s->u.pc.ctr |= 0x10;
285
286 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
287 * D.Gruszka VScom */
288 }
289
290 static void parport_pc_save_state(struct parport *p, struct parport_state *s)
291 {
292 const struct parport_pc_private *priv = p->physport->private_data;
293 s->u.pc.ctr = priv->ctr;
294 if (priv->ecr)
295 s->u.pc.ecr = inb (ECONTROL (p));
296 }
297
298 static void parport_pc_restore_state(struct parport *p, struct parport_state *s)
299 {
300 struct parport_pc_private *priv = p->physport->private_data;
301 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
302 outb (c, CONTROL (p));
303 priv->ctr = c;
304 if (priv->ecr)
305 ECR_WRITE (p, s->u.pc.ecr);
306 }
307
308 #ifdef CONFIG_PARPORT_1284
309 static size_t parport_pc_epp_read_data (struct parport *port, void *buf,
310 size_t length, int flags)
311 {
312 size_t got = 0;
313
314 if (flags & PARPORT_W91284PIC) {
315 unsigned char status;
316 size_t left = length;
317
318 /* use knowledge about data lines..:
319 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
320 * pError is 1 if there are 16 bytes in the Warp's FIFO
321 */
322 status = inb (STATUS (port));
323
324 while (!(status & 0x08) && (got < length)) {
325 if ((left >= 16) && (status & 0x20) && !(status & 0x08)) {
326 /* can grab 16 bytes from warp fifo */
327 if (!((long)buf & 0x03)) {
328 insl (EPPDATA (port), buf, 4);
329 } else {
330 insb (EPPDATA (port), buf, 16);
331 }
332 buf += 16;
333 got += 16;
334 left -= 16;
335 } else {
336 /* grab single byte from the warp fifo */
337 *((char *)buf) = inb (EPPDATA (port));
338 buf++;
339 got++;
340 left--;
341 }
342 status = inb (STATUS (port));
343 if (status & 0x01) {
344 /* EPP timeout should never occur... */
345 printk (KERN_DEBUG "%s: EPP timeout occurred while talking to "
346 "w91284pic (should not have done)\n", port->name);
347 clear_epp_timeout (port);
348 }
349 }
350 return got;
351 }
352 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
353 if (!(((long)buf | length) & 0x03)) {
354 insl (EPPDATA (port), buf, (length >> 2));
355 } else {
356 insb (EPPDATA (port), buf, length);
357 }
358 if (inb (STATUS (port)) & 0x01) {
359 clear_epp_timeout (port);
360 return -EIO;
361 }
362 return length;
363 }
364 for (; got < length; got++) {
365 *((char*)buf) = inb (EPPDATA(port));
366 buf++;
367 if (inb (STATUS (port)) & 0x01) {
368 /* EPP timeout */
369 clear_epp_timeout (port);
370 break;
371 }
372 }
373
374 return got;
375 }
376
377 static size_t parport_pc_epp_write_data (struct parport *port, const void *buf,
378 size_t length, int flags)
379 {
380 size_t written = 0;
381
382 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
383 if (!(((long)buf | length) & 0x03)) {
384 outsl (EPPDATA (port), buf, (length >> 2));
385 } else {
386 outsb (EPPDATA (port), buf, length);
387 }
388 if (inb (STATUS (port)) & 0x01) {
389 clear_epp_timeout (port);
390 return -EIO;
391 }
392 return length;
393 }
394 for (; written < length; written++) {
395 outb (*((char*)buf), EPPDATA(port));
396 buf++;
397 if (inb (STATUS(port)) & 0x01) {
398 clear_epp_timeout (port);
399 break;
400 }
401 }
402
403 return written;
404 }
405
406 static size_t parport_pc_epp_read_addr (struct parport *port, void *buf,
407 size_t length, int flags)
408 {
409 size_t got = 0;
410
411 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
412 insb (EPPADDR (port), buf, length);
413 if (inb (STATUS (port)) & 0x01) {
414 clear_epp_timeout (port);
415 return -EIO;
416 }
417 return length;
418 }
419 for (; got < length; got++) {
420 *((char*)buf) = inb (EPPADDR (port));
421 buf++;
422 if (inb (STATUS (port)) & 0x01) {
423 clear_epp_timeout (port);
424 break;
425 }
426 }
427
428 return got;
429 }
430
431 static size_t parport_pc_epp_write_addr (struct parport *port,
432 const void *buf, size_t length,
433 int flags)
434 {
435 size_t written = 0;
436
437 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
438 outsb (EPPADDR (port), buf, length);
439 if (inb (STATUS (port)) & 0x01) {
440 clear_epp_timeout (port);
441 return -EIO;
442 }
443 return length;
444 }
445 for (; written < length; written++) {
446 outb (*((char*)buf), EPPADDR (port));
447 buf++;
448 if (inb (STATUS (port)) & 0x01) {
449 clear_epp_timeout (port);
450 break;
451 }
452 }
453
454 return written;
455 }
456
457 static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf,
458 size_t length, int flags)
459 {
460 size_t got;
461
462 frob_set_mode (port, ECR_EPP);
463 parport_pc_data_reverse (port);
464 parport_pc_write_control (port, 0x4);
465 got = parport_pc_epp_read_data (port, buf, length, flags);
466 frob_set_mode (port, ECR_PS2);
467
468 return got;
469 }
470
471 static size_t parport_pc_ecpepp_write_data (struct parport *port,
472 const void *buf, size_t length,
473 int flags)
474 {
475 size_t written;
476
477 frob_set_mode (port, ECR_EPP);
478 parport_pc_write_control (port, 0x4);
479 parport_pc_data_forward (port);
480 written = parport_pc_epp_write_data (port, buf, length, flags);
481 frob_set_mode (port, ECR_PS2);
482
483 return written;
484 }
485
486 static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf,
487 size_t length, int flags)
488 {
489 size_t got;
490
491 frob_set_mode (port, ECR_EPP);
492 parport_pc_data_reverse (port);
493 parport_pc_write_control (port, 0x4);
494 got = parport_pc_epp_read_addr (port, buf, length, flags);
495 frob_set_mode (port, ECR_PS2);
496
497 return got;
498 }
499
500 static size_t parport_pc_ecpepp_write_addr (struct parport *port,
501 const void *buf, size_t length,
502 int flags)
503 {
504 size_t written;
505
506 frob_set_mode (port, ECR_EPP);
507 parport_pc_write_control (port, 0x4);
508 parport_pc_data_forward (port);
509 written = parport_pc_epp_write_addr (port, buf, length, flags);
510 frob_set_mode (port, ECR_PS2);
511
512 return written;
513 }
514 #endif /* IEEE 1284 support */
515
516 #ifdef CONFIG_PARPORT_PC_FIFO
517 static size_t parport_pc_fifo_write_block_pio (struct parport *port,
518 const void *buf, size_t length)
519 {
520 int ret = 0;
521 const unsigned char *bufp = buf;
522 size_t left = length;
523 unsigned long expire = jiffies + port->physport->cad->timeout;
524 const int fifo = FIFO (port);
525 int poll_for = 8; /* 80 usecs */
526 const struct parport_pc_private *priv = port->physport->private_data;
527 const int fifo_depth = priv->fifo_depth;
528
529 port = port->physport;
530
531 /* We don't want to be interrupted every character. */
532 parport_pc_disable_irq (port);
533 /* set nErrIntrEn and serviceIntr */
534 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
535
536 /* Forward mode. */
537 parport_pc_data_forward (port); /* Must be in PS2 mode */
538
539 while (left) {
540 unsigned char byte;
541 unsigned char ecrval = inb (ECONTROL (port));
542 int i = 0;
543
544 if (need_resched() && time_before (jiffies, expire))
545 /* Can't yield the port. */
546 schedule ();
547
548 /* Anyone else waiting for the port? */
549 if (port->waithead) {
550 printk (KERN_DEBUG "Somebody wants the port\n");
551 break;
552 }
553
554 if (ecrval & 0x02) {
555 /* FIFO is full. Wait for interrupt. */
556
557 /* Clear serviceIntr */
558 ECR_WRITE (port, ecrval & ~(1<<2));
559 false_alarm:
560 ret = parport_wait_event (port, HZ);
561 if (ret < 0) break;
562 ret = 0;
563 if (!time_before (jiffies, expire)) {
564 /* Timed out. */
565 printk (KERN_DEBUG "FIFO write timed out\n");
566 break;
567 }
568 ecrval = inb (ECONTROL (port));
569 if (!(ecrval & (1<<2))) {
570 if (need_resched() &&
571 time_before (jiffies, expire))
572 schedule ();
573
574 goto false_alarm;
575 }
576
577 continue;
578 }
579
580 /* Can't fail now. */
581 expire = jiffies + port->cad->timeout;
582
583 poll:
584 if (signal_pending (current))
585 break;
586
587 if (ecrval & 0x01) {
588 /* FIFO is empty. Blast it full. */
589 const int n = left < fifo_depth ? left : fifo_depth;
590 outsb (fifo, bufp, n);
591 bufp += n;
592 left -= n;
593
594 /* Adjust the poll time. */
595 if (i < (poll_for - 2)) poll_for--;
596 continue;
597 } else if (i++ < poll_for) {
598 udelay (10);
599 ecrval = inb (ECONTROL (port));
600 goto poll;
601 }
602
603 /* Half-full (call me an optimist) */
604 byte = *bufp++;
605 outb (byte, fifo);
606 left--;
607 }
608
609 dump_parport_state ("leave fifo_write_block_pio", port);
610 return length - left;
611 }
612
613 static size_t parport_pc_fifo_write_block_dma (struct parport *port,
614 const void *buf, size_t length)
615 {
616 int ret = 0;
617 unsigned long dmaflag;
618 size_t left = length;
619 const struct parport_pc_private *priv = port->physport->private_data;
620 dma_addr_t dma_addr, dma_handle;
621 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
622 unsigned long start = (unsigned long) buf;
623 unsigned long end = (unsigned long) buf + length - 1;
624
625 dump_parport_state ("enter fifo_write_block_dma", port);
626 if (end < MAX_DMA_ADDRESS) {
627 /* If it would cross a 64k boundary, cap it at the end. */
628 if ((start ^ end) & ~0xffffUL)
629 maxlen = 0x10000 - (start & 0xffff);
630
631 dma_addr = dma_handle = pci_map_single(priv->dev, (void *)buf, length,
632 PCI_DMA_TODEVICE);
633 } else {
634 /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */
635 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
636 dma_addr = priv->dma_handle;
637 dma_handle = 0;
638 }
639
640 port = port->physport;
641
642 /* We don't want to be interrupted every character. */
643 parport_pc_disable_irq (port);
644 /* set nErrIntrEn and serviceIntr */
645 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
646
647 /* Forward mode. */
648 parport_pc_data_forward (port); /* Must be in PS2 mode */
649
650 while (left) {
651 unsigned long expire = jiffies + port->physport->cad->timeout;
652
653 size_t count = left;
654
655 if (count > maxlen)
656 count = maxlen;
657
658 if (!dma_handle) /* bounce buffer ! */
659 memcpy(priv->dma_buf, buf, count);
660
661 dmaflag = claim_dma_lock();
662 disable_dma(port->dma);
663 clear_dma_ff(port->dma);
664 set_dma_mode(port->dma, DMA_MODE_WRITE);
665 set_dma_addr(port->dma, dma_addr);
666 set_dma_count(port->dma, count);
667
668 /* Set DMA mode */
669 frob_econtrol (port, 1<<3, 1<<3);
670
671 /* Clear serviceIntr */
672 frob_econtrol (port, 1<<2, 0);
673
674 enable_dma(port->dma);
675 release_dma_lock(dmaflag);
676
677 /* assume DMA will be successful */
678 left -= count;
679 buf += count;
680 if (dma_handle) dma_addr += count;
681
682 /* Wait for interrupt. */
683 false_alarm:
684 ret = parport_wait_event (port, HZ);
685 if (ret < 0) break;
686 ret = 0;
687 if (!time_before (jiffies, expire)) {
688 /* Timed out. */
689 printk (KERN_DEBUG "DMA write timed out\n");
690 break;
691 }
692 /* Is serviceIntr set? */
693 if (!(inb (ECONTROL (port)) & (1<<2))) {
694 cond_resched();
695
696 goto false_alarm;
697 }
698
699 dmaflag = claim_dma_lock();
700 disable_dma(port->dma);
701 clear_dma_ff(port->dma);
702 count = get_dma_residue(port->dma);
703 release_dma_lock(dmaflag);
704
705 cond_resched(); /* Can't yield the port. */
706
707 /* Anyone else waiting for the port? */
708 if (port->waithead) {
709 printk (KERN_DEBUG "Somebody wants the port\n");
710 break;
711 }
712
713 /* update for possible DMA residue ! */
714 buf -= count;
715 left += count;
716 if (dma_handle) dma_addr -= count;
717 }
718
719 /* Maybe got here through break, so adjust for DMA residue! */
720 dmaflag = claim_dma_lock();
721 disable_dma(port->dma);
722 clear_dma_ff(port->dma);
723 left += get_dma_residue(port->dma);
724 release_dma_lock(dmaflag);
725
726 /* Turn off DMA mode */
727 frob_econtrol (port, 1<<3, 0);
728
729 if (dma_handle)
730 pci_unmap_single(priv->dev, dma_handle, length, PCI_DMA_TODEVICE);
731
732 dump_parport_state ("leave fifo_write_block_dma", port);
733 return length - left;
734 }
735
736 /* Parallel Port FIFO mode (ECP chipsets) */
737 static size_t parport_pc_compat_write_block_pio (struct parport *port,
738 const void *buf, size_t length,
739 int flags)
740 {
741 size_t written;
742 int r;
743 unsigned long expire;
744 const struct parport_pc_private *priv = port->physport->private_data;
745
746 /* Special case: a timeout of zero means we cannot call schedule().
747 * Also if O_NONBLOCK is set then use the default implementation. */
748 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
749 return parport_ieee1284_write_compat (port, buf,
750 length, flags);
751
752 /* Set up parallel port FIFO mode.*/
753 parport_pc_data_forward (port); /* Must be in PS2 mode */
754 parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0);
755 r = change_mode (port, ECR_PPF); /* Parallel port FIFO */
756 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name);
757
758 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
759
760 /* Write the data to the FIFO. */
761 if (port->dma != PARPORT_DMA_NONE)
762 written = parport_pc_fifo_write_block_dma (port, buf, length);
763 else
764 written = parport_pc_fifo_write_block_pio (port, buf, length);
765
766 /* Finish up. */
767 /* For some hardware we don't want to touch the mode until
768 * the FIFO is empty, so allow 4 seconds for each position
769 * in the fifo.
770 */
771 expire = jiffies + (priv->fifo_depth * HZ * 4);
772 do {
773 /* Wait for the FIFO to empty */
774 r = change_mode (port, ECR_PS2);
775 if (r != -EBUSY) {
776 break;
777 }
778 } while (time_before (jiffies, expire));
779 if (r == -EBUSY) {
780
781 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
782
783 /* Prevent further data transfer. */
784 frob_set_mode (port, ECR_TST);
785
786 /* Adjust for the contents of the FIFO. */
787 for (written -= priv->fifo_depth; ; written++) {
788 if (inb (ECONTROL (port)) & 0x2) {
789 /* Full up. */
790 break;
791 }
792 outb (0, FIFO (port));
793 }
794
795 /* Reset the FIFO and return to PS2 mode. */
796 frob_set_mode (port, ECR_PS2);
797 }
798
799 r = parport_wait_peripheral (port,
800 PARPORT_STATUS_BUSY,
801 PARPORT_STATUS_BUSY);
802 if (r)
803 printk (KERN_DEBUG
804 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
805 port->name, r);
806
807 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
808
809 return written;
810 }
811
812 /* ECP */
813 #ifdef CONFIG_PARPORT_1284
814 static size_t parport_pc_ecp_write_block_pio (struct parport *port,
815 const void *buf, size_t length,
816 int flags)
817 {
818 size_t written;
819 int r;
820 unsigned long expire;
821 const struct parport_pc_private *priv = port->physport->private_data;
822
823 /* Special case: a timeout of zero means we cannot call schedule().
824 * Also if O_NONBLOCK is set then use the default implementation. */
825 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
826 return parport_ieee1284_ecp_write_data (port, buf,
827 length, flags);
828
829 /* Switch to forward mode if necessary. */
830 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
831 /* Event 47: Set nInit high. */
832 parport_frob_control (port,
833 PARPORT_CONTROL_INIT
834 | PARPORT_CONTROL_AUTOFD,
835 PARPORT_CONTROL_INIT
836 | PARPORT_CONTROL_AUTOFD);
837
838 /* Event 49: PError goes high. */
839 r = parport_wait_peripheral (port,
840 PARPORT_STATUS_PAPEROUT,
841 PARPORT_STATUS_PAPEROUT);
842 if (r) {
843 printk (KERN_DEBUG "%s: PError timeout (%d) "
844 "in ecp_write_block_pio\n", port->name, r);
845 }
846 }
847
848 /* Set up ECP parallel port mode.*/
849 parport_pc_data_forward (port); /* Must be in PS2 mode */
850 parport_pc_frob_control (port,
851 PARPORT_CONTROL_STROBE |
852 PARPORT_CONTROL_AUTOFD,
853 0);
854 r = change_mode (port, ECR_ECP); /* ECP FIFO */
855 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
856 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
857
858 /* Write the data to the FIFO. */
859 if (port->dma != PARPORT_DMA_NONE)
860 written = parport_pc_fifo_write_block_dma (port, buf, length);
861 else
862 written = parport_pc_fifo_write_block_pio (port, buf, length);
863
864 /* Finish up. */
865 /* For some hardware we don't want to touch the mode until
866 * the FIFO is empty, so allow 4 seconds for each position
867 * in the fifo.
868 */
869 expire = jiffies + (priv->fifo_depth * (HZ * 4));
870 do {
871 /* Wait for the FIFO to empty */
872 r = change_mode (port, ECR_PS2);
873 if (r != -EBUSY) {
874 break;
875 }
876 } while (time_before (jiffies, expire));
877 if (r == -EBUSY) {
878
879 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
880
881 /* Prevent further data transfer. */
882 frob_set_mode (port, ECR_TST);
883
884 /* Adjust for the contents of the FIFO. */
885 for (written -= priv->fifo_depth; ; written++) {
886 if (inb (ECONTROL (port)) & 0x2) {
887 /* Full up. */
888 break;
889 }
890 outb (0, FIFO (port));
891 }
892
893 /* Reset the FIFO and return to PS2 mode. */
894 frob_set_mode (port, ECR_PS2);
895
896 /* Host transfer recovery. */
897 parport_pc_data_reverse (port); /* Must be in PS2 mode */
898 udelay (5);
899 parport_frob_control (port, PARPORT_CONTROL_INIT, 0);
900 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
901 if (r)
902 printk (KERN_DEBUG "%s: PE,1 timeout (%d) "
903 "in ecp_write_block_pio\n", port->name, r);
904
905 parport_frob_control (port,
906 PARPORT_CONTROL_INIT,
907 PARPORT_CONTROL_INIT);
908 r = parport_wait_peripheral (port,
909 PARPORT_STATUS_PAPEROUT,
910 PARPORT_STATUS_PAPEROUT);
911 if (r)
912 printk (KERN_DEBUG "%s: PE,2 timeout (%d) "
913 "in ecp_write_block_pio\n", port->name, r);
914 }
915
916 r = parport_wait_peripheral (port,
917 PARPORT_STATUS_BUSY,
918 PARPORT_STATUS_BUSY);
919 if(r)
920 printk (KERN_DEBUG
921 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
922 port->name, r);
923
924 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
925
926 return written;
927 }
928
929 #if 0
930 static size_t parport_pc_ecp_read_block_pio (struct parport *port,
931 void *buf, size_t length,
932 int flags)
933 {
934 size_t left = length;
935 size_t fifofull;
936 int r;
937 const int fifo = FIFO(port);
938 const struct parport_pc_private *priv = port->physport->private_data;
939 const int fifo_depth = priv->fifo_depth;
940 char *bufp = buf;
941
942 port = port->physport;
943 DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n");
944 dump_parport_state ("enter fcn", port);
945
946 /* Special case: a timeout of zero means we cannot call schedule().
947 * Also if O_NONBLOCK is set then use the default implementation. */
948 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
949 return parport_ieee1284_ecp_read_data (port, buf,
950 length, flags);
951
952 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) {
953 /* If the peripheral is allowed to send RLE compressed
954 * data, it is possible for a byte to expand to 128
955 * bytes in the FIFO. */
956 fifofull = 128;
957 } else {
958 fifofull = fifo_depth;
959 }
960
961 /* If the caller wants less than a full FIFO's worth of data,
962 * go through software emulation. Otherwise we may have to throw
963 * away data. */
964 if (length < fifofull)
965 return parport_ieee1284_ecp_read_data (port, buf,
966 length, flags);
967
968 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) {
969 /* change to reverse-idle phase (must be in forward-idle) */
970
971 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */
972 parport_frob_control (port,
973 PARPORT_CONTROL_AUTOFD
974 | PARPORT_CONTROL_STROBE,
975 PARPORT_CONTROL_AUTOFD);
976 parport_pc_data_reverse (port); /* Must be in PS2 mode */
977 udelay (5);
978 /* Event 39: Set nInit low to initiate bus reversal */
979 parport_frob_control (port,
980 PARPORT_CONTROL_INIT,
981 0);
982 /* Event 40: Wait for nAckReverse (PError) to go low */
983 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
984 if (r) {
985 printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) "
986 "in ecp_read_block_pio\n", port->name, r);
987 return 0;
988 }
989 }
990
991 /* Set up ECP FIFO mode.*/
992 /* parport_pc_frob_control (port,
993 PARPORT_CONTROL_STROBE |
994 PARPORT_CONTROL_AUTOFD,
995 PARPORT_CONTROL_AUTOFD); */
996 r = change_mode (port, ECR_ECP); /* ECP FIFO */
997 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
998
999 port->ieee1284.phase = IEEE1284_PH_REV_DATA;
1000
1001 /* the first byte must be collected manually */
1002 dump_parport_state ("pre 43", port);
1003 /* Event 43: Wait for nAck to go low */
1004 r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0);
1005 if (r) {
1006 /* timed out while reading -- no data */
1007 printk (KERN_DEBUG "PIO read timed out (initial byte)\n");
1008 goto out_no_data;
1009 }
1010 /* read byte */
1011 *bufp++ = inb (DATA (port));
1012 left--;
1013 dump_parport_state ("43-44", port);
1014 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */
1015 parport_pc_frob_control (port,
1016 PARPORT_CONTROL_AUTOFD,
1017 0);
1018 dump_parport_state ("pre 45", port);
1019 /* Event 45: Wait for nAck to go high */
1020 /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */
1021 dump_parport_state ("post 45", port);
1022 r = 0;
1023 if (r) {
1024 /* timed out while waiting for peripheral to respond to ack */
1025 printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n");
1026
1027 /* keep hold of the byte we've got already */
1028 goto out_no_data;
1029 }
1030 /* Event 46: nAutoFd (HostAck) goes low to accept more data */
1031 parport_pc_frob_control (port,
1032 PARPORT_CONTROL_AUTOFD,
1033 PARPORT_CONTROL_AUTOFD);
1034
1035
1036 dump_parport_state ("rev idle", port);
1037 /* Do the transfer. */
1038 while (left > fifofull) {
1039 int ret;
1040 unsigned long expire = jiffies + port->cad->timeout;
1041 unsigned char ecrval = inb (ECONTROL (port));
1042
1043 if (need_resched() && time_before (jiffies, expire))
1044 /* Can't yield the port. */
1045 schedule ();
1046
1047 /* At this point, the FIFO may already be full. In
1048 * that case ECP is already holding back the
1049 * peripheral (assuming proper design) with a delayed
1050 * handshake. Work fast to avoid a peripheral
1051 * timeout. */
1052
1053 if (ecrval & 0x01) {
1054 /* FIFO is empty. Wait for interrupt. */
1055 dump_parport_state ("FIFO empty", port);
1056
1057 /* Anyone else waiting for the port? */
1058 if (port->waithead) {
1059 printk (KERN_DEBUG "Somebody wants the port\n");
1060 break;
1061 }
1062
1063 /* Clear serviceIntr */
1064 ECR_WRITE (port, ecrval & ~(1<<2));
1065 false_alarm:
1066 dump_parport_state ("waiting", port);
1067 ret = parport_wait_event (port, HZ);
1068 DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret);
1069 if (ret < 0)
1070 break;
1071 ret = 0;
1072 if (!time_before (jiffies, expire)) {
1073 /* Timed out. */
1074 dump_parport_state ("timeout", port);
1075 printk (KERN_DEBUG "PIO read timed out\n");
1076 break;
1077 }
1078 ecrval = inb (ECONTROL (port));
1079 if (!(ecrval & (1<<2))) {
1080 if (need_resched() &&
1081 time_before (jiffies, expire)) {
1082 schedule ();
1083 }
1084 goto false_alarm;
1085 }
1086
1087 /* Depending on how the FIFO threshold was
1088 * set, how long interrupt service took, and
1089 * how fast the peripheral is, we might be
1090 * lucky and have a just filled FIFO. */
1091 continue;
1092 }
1093
1094 if (ecrval & 0x02) {
1095 /* FIFO is full. */
1096 dump_parport_state ("FIFO full", port);
1097 insb (fifo, bufp, fifo_depth);
1098 bufp += fifo_depth;
1099 left -= fifo_depth;
1100 continue;
1101 }
1102
1103 DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n");
1104
1105 /* FIFO not filled. We will cycle this loop for a while
1106 * and either the peripheral will fill it faster,
1107 * tripping a fast empty with insb, or we empty it. */
1108 *bufp++ = inb (fifo);
1109 left--;
1110 }
1111
1112 /* scoop up anything left in the FIFO */
1113 while (left && !(inb (ECONTROL (port) & 0x01))) {
1114 *bufp++ = inb (fifo);
1115 left--;
1116 }
1117
1118 port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
1119 dump_parport_state ("rev idle2", port);
1120
1121 out_no_data:
1122
1123 /* Go to forward idle mode to shut the peripheral up (event 47). */
1124 parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT);
1125
1126 /* event 49: PError goes high */
1127 r = parport_wait_peripheral (port,
1128 PARPORT_STATUS_PAPEROUT,
1129 PARPORT_STATUS_PAPEROUT);
1130 if (r) {
1131 printk (KERN_DEBUG
1132 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n",
1133 port->name, r);
1134 }
1135
1136 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1137
1138 /* Finish up. */
1139 {
1140 int lost = get_fifo_residue (port);
1141 if (lost)
1142 /* Shouldn't happen with compliant peripherals. */
1143 printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n",
1144 port->name, lost);
1145 }
1146
1147 dump_parport_state ("fwd idle", port);
1148 return length - left;
1149 }
1150 #endif /* 0 */
1151 #endif /* IEEE 1284 support */
1152 #endif /* Allowed to use FIFO/DMA */
1153
1154
1155 /*
1156 * ******************************************
1157 * INITIALISATION AND MODULE STUFF BELOW HERE
1158 * ******************************************
1159 */
1160
1161 /* GCC is not inlining extern inline function later overwriten to non-inline,
1162 so we use outlined_ variants here. */
1163 static struct parport_operations parport_pc_ops =
1164 {
1165 .write_data = parport_pc_write_data,
1166 .read_data = parport_pc_read_data,
1167
1168 .write_control = parport_pc_write_control,
1169 .read_control = parport_pc_read_control,
1170 .frob_control = parport_pc_frob_control,
1171
1172 .read_status = parport_pc_read_status,
1173
1174 .enable_irq = parport_pc_enable_irq,
1175 .disable_irq = parport_pc_disable_irq,
1176
1177 .data_forward = parport_pc_data_forward,
1178 .data_reverse = parport_pc_data_reverse,
1179
1180 .init_state = parport_pc_init_state,
1181 .save_state = parport_pc_save_state,
1182 .restore_state = parport_pc_restore_state,
1183
1184 .epp_write_data = parport_ieee1284_epp_write_data,
1185 .epp_read_data = parport_ieee1284_epp_read_data,
1186 .epp_write_addr = parport_ieee1284_epp_write_addr,
1187 .epp_read_addr = parport_ieee1284_epp_read_addr,
1188
1189 .ecp_write_data = parport_ieee1284_ecp_write_data,
1190 .ecp_read_data = parport_ieee1284_ecp_read_data,
1191 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
1192
1193 .compat_write_data = parport_ieee1284_write_compat,
1194 .nibble_read_data = parport_ieee1284_read_nibble,
1195 .byte_read_data = parport_ieee1284_read_byte,
1196
1197 .owner = THIS_MODULE,
1198 };
1199
1200 #ifdef CONFIG_PARPORT_PC_SUPERIO
1201 /* Super-IO chipset detection, Winbond, SMSC */
1202 static void __devinit show_parconfig_smsc37c669(int io, int key)
1203 {
1204 int cr1,cr4,cra,cr23,cr26,cr27,i=0;
1205 static const char *modes[]={ "SPP and Bidirectional (PS/2)",
1206 "EPP and SPP",
1207 "ECP",
1208 "ECP and EPP" };
1209
1210 outb(key,io);
1211 outb(key,io);
1212 outb(1,io);
1213 cr1=inb(io+1);
1214 outb(4,io);
1215 cr4=inb(io+1);
1216 outb(0x0a,io);
1217 cra=inb(io+1);
1218 outb(0x23,io);
1219 cr23=inb(io+1);
1220 outb(0x26,io);
1221 cr26=inb(io+1);
1222 outb(0x27,io);
1223 cr27=inb(io+1);
1224 outb(0xaa,io);
1225
1226 if (verbose_probing) {
1227 printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1228 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
1229 cr1,cr4,cra,cr23,cr26,cr27);
1230
1231 /* The documentation calls DMA and IRQ-Lines by letters, so
1232 the board maker can/will wire them
1233 appropriately/randomly... G=reserved H=IDE-irq, */
1234 printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, "
1235 "fifo threshold=%d\n", cr23*4,
1236 (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-',
1237 (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f);
1238 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
1239 (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no");
1240 printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1241 (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03],
1242 (cr4 & 0x40) ? "1.7" : "1.9");
1243 }
1244
1245 /* Heuristics ! BIOS setup for this mainboard device limits
1246 the choices to standard settings, i.e. io-address and IRQ
1247 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1248 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1249 if(cr23*4 >=0x100) { /* if active */
1250 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1251 i++;
1252 if(i==NR_SUPERIOS)
1253 printk(KERN_INFO "Super-IO: too many chips!\n");
1254 else {
1255 int d;
1256 switch (cr23*4) {
1257 case 0x3bc:
1258 superios[i].io = 0x3bc;
1259 superios[i].irq = 7;
1260 break;
1261 case 0x378:
1262 superios[i].io = 0x378;
1263 superios[i].irq = 7;
1264 break;
1265 case 0x278:
1266 superios[i].io = 0x278;
1267 superios[i].irq = 5;
1268 }
1269 d=(cr26 &0x0f);
1270 if((d==1) || (d==3))
1271 superios[i].dma= d;
1272 else
1273 superios[i].dma= PARPORT_DMA_NONE;
1274 }
1275 }
1276 }
1277
1278
1279 static void __devinit show_parconfig_winbond(int io, int key)
1280 {
1281 int cr30,cr60,cr61,cr70,cr74,crf0,i=0;
1282 static const char *modes[] = {
1283 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1284 "EPP-1.9 and SPP",
1285 "ECP",
1286 "ECP and EPP-1.9",
1287 "Standard (SPP)",
1288 "EPP-1.7 and SPP", /* 5 */
1289 "undefined!",
1290 "ECP and EPP-1.7" };
1291 static char *irqtypes[] = { "pulsed low, high-Z", "follows nACK" };
1292
1293 /* The registers are called compatible-PnP because the
1294 register layout is modelled after ISA-PnP, the access
1295 method is just another ... */
1296 outb(key,io);
1297 outb(key,io);
1298 outb(0x07,io); /* Register 7: Select Logical Device */
1299 outb(0x01,io+1); /* LD1 is Parallel Port */
1300 outb(0x30,io);
1301 cr30=inb(io+1);
1302 outb(0x60,io);
1303 cr60=inb(io+1);
1304 outb(0x61,io);
1305 cr61=inb(io+1);
1306 outb(0x70,io);
1307 cr70=inb(io+1);
1308 outb(0x74,io);
1309 cr74=inb(io+1);
1310 outb(0xf0,io);
1311 crf0=inb(io+1);
1312 outb(0xaa,io);
1313
1314 if (verbose_probing) {
1315 printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x "
1316 "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0);
1317 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1318 (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f );
1319 if ((cr74 & 0x07) > 3)
1320 printk("dma=none\n");
1321 else
1322 printk("dma=%d\n",cr74 & 0x07);
1323 printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1324 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1325 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]);
1326 }
1327
1328 if(cr30 & 0x01) { /* the settings can be interrogated later ... */
1329 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1330 i++;
1331 if(i==NR_SUPERIOS)
1332 printk(KERN_INFO "Super-IO: too many chips!\n");
1333 else {
1334 superios[i].io = (cr60<<8)|cr61;
1335 superios[i].irq = cr70&0x0f;
1336 superios[i].dma = (((cr74 & 0x07) > 3) ?
1337 PARPORT_DMA_NONE : (cr74 & 0x07));
1338 }
1339 }
1340 }
1341
1342 static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1343 {
1344 const char *type = "unknown";
1345 int id,progif=2;
1346
1347 if (devid == devrev)
1348 /* simple heuristics, we happened to read some
1349 non-winbond register */
1350 return;
1351
1352 id=(devid<<8) | devrev;
1353
1354 /* Values are from public data sheets pdf files, I can just
1355 confirm 83977TF is correct :-) */
1356 if (id == 0x9771) type="83977F/AF";
1357 else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x";
1358 else if (id == 0x9774) type="83977ATF";
1359 else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x";
1360 else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x";
1361 else if ((id & ~0x0f) == 0x5210) type="83627";
1362 else if ((id & ~0x0f) == 0x6010) type="83697HF";
1363 else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;}
1364 else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;}
1365 else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;}
1366 else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;}
1367 else progif=0;
1368
1369 if (verbose_probing)
1370 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1371 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1372 efer, key, devid, devrev, oldid, type);
1373
1374 if (progif == 2)
1375 show_parconfig_winbond(efer,key);
1376 }
1377
1378 static void __devinit decode_smsc(int efer, int key, int devid, int devrev)
1379 {
1380 const char *type = "unknown";
1381 void (*func)(int io, int key);
1382 int id;
1383
1384 if (devid == devrev)
1385 /* simple heuristics, we happened to read some
1386 non-smsc register */
1387 return;
1388
1389 func=NULL;
1390 id=(devid<<8) | devrev;
1391
1392 if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;}
1393 else if (id==0x6582) type="37c665IR";
1394 else if (devid==0x65) type="37c665GT";
1395 else if (devid==0x66) type="37c666GT";
1396
1397 if (verbose_probing)
1398 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1399 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1400 efer, key, devid, devrev, type);
1401
1402 if (func)
1403 func(efer,key);
1404 }
1405
1406
1407 static void __devinit winbond_check(int io, int key)
1408 {
1409 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1410
1411 if (!request_region(io, 3, __FUNCTION__))
1412 return;
1413
1414 /* First probe without key */
1415 outb(0x20,io);
1416 x_devid=inb(io+1);
1417 outb(0x21,io);
1418 x_devrev=inb(io+1);
1419 outb(0x09,io);
1420 x_oldid=inb(io+1);
1421
1422 outb(key,io);
1423 outb(key,io); /* Write Magic Sequence to EFER, extended
1424 funtion enable register */
1425 outb(0x20,io); /* Write EFIR, extended function index register */
1426 devid=inb(io+1); /* Read EFDR, extended function data register */
1427 outb(0x21,io);
1428 devrev=inb(io+1);
1429 outb(0x09,io);
1430 oldid=inb(io+1);
1431 outb(0xaa,io); /* Magic Seal */
1432
1433 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1434 goto out; /* protection against false positives */
1435
1436 decode_winbond(io,key,devid,devrev,oldid);
1437 out:
1438 release_region(io, 3);
1439 }
1440
1441 static void __devinit winbond_check2(int io,int key)
1442 {
1443 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1444
1445 if (!request_region(io, 3, __FUNCTION__))
1446 return;
1447
1448 /* First probe without the key */
1449 outb(0x20,io+2);
1450 x_devid=inb(io+2);
1451 outb(0x21,io+1);
1452 x_devrev=inb(io+2);
1453 outb(0x09,io+1);
1454 x_oldid=inb(io+2);
1455
1456 outb(key,io); /* Write Magic Byte to EFER, extended
1457 funtion enable register */
1458 outb(0x20,io+2); /* Write EFIR, extended function index register */
1459 devid=inb(io+2); /* Read EFDR, extended function data register */
1460 outb(0x21,io+1);
1461 devrev=inb(io+2);
1462 outb(0x09,io+1);
1463 oldid=inb(io+2);
1464 outb(0xaa,io); /* Magic Seal */
1465
1466 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1467 goto out; /* protection against false positives */
1468
1469 decode_winbond(io,key,devid,devrev,oldid);
1470 out:
1471 release_region(io, 3);
1472 }
1473
1474 static void __devinit smsc_check(int io, int key)
1475 {
1476 int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev;
1477
1478 if (!request_region(io, 3, __FUNCTION__))
1479 return;
1480
1481 /* First probe without the key */
1482 outb(0x0d,io);
1483 x_oldid=inb(io+1);
1484 outb(0x0e,io);
1485 x_oldrev=inb(io+1);
1486 outb(0x20,io);
1487 x_id=inb(io+1);
1488 outb(0x21,io);
1489 x_rev=inb(io+1);
1490
1491 outb(key,io);
1492 outb(key,io); /* Write Magic Sequence to EFER, extended
1493 funtion enable register */
1494 outb(0x0d,io); /* Write EFIR, extended function index register */
1495 oldid=inb(io+1); /* Read EFDR, extended function data register */
1496 outb(0x0e,io);
1497 oldrev=inb(io+1);
1498 outb(0x20,io);
1499 id=inb(io+1);
1500 outb(0x21,io);
1501 rev=inb(io+1);
1502 outb(0xaa,io); /* Magic Seal */
1503
1504 if ((x_id == id) && (x_oldrev == oldrev) &&
1505 (x_oldid == oldid) && (x_rev == rev))
1506 goto out; /* protection against false positives */
1507
1508 decode_smsc(io,key,oldid,oldrev);
1509 out:
1510 release_region(io, 3);
1511 }
1512
1513
1514 static void __devinit detect_and_report_winbond (void)
1515 {
1516 if (verbose_probing)
1517 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1518 winbond_check(0x3f0,0x87);
1519 winbond_check(0x370,0x87);
1520 winbond_check(0x2e ,0x87);
1521 winbond_check(0x4e ,0x87);
1522 winbond_check(0x3f0,0x86);
1523 winbond_check2(0x250,0x88);
1524 winbond_check2(0x250,0x89);
1525 }
1526
1527 static void __devinit detect_and_report_smsc (void)
1528 {
1529 if (verbose_probing)
1530 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1531 smsc_check(0x3f0,0x55);
1532 smsc_check(0x370,0x55);
1533 smsc_check(0x3f0,0x44);
1534 smsc_check(0x370,0x44);
1535 }
1536 #endif /* CONFIG_PARPORT_PC_SUPERIO */
1537
1538 static int __devinit get_superio_dma (struct parport *p)
1539 {
1540 int i=0;
1541 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1542 i++;
1543 if (i!=NR_SUPERIOS)
1544 return superios[i].dma;
1545 return PARPORT_DMA_NONE;
1546 }
1547
1548 static int __devinit get_superio_irq (struct parport *p)
1549 {
1550 int i=0;
1551 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1552 i++;
1553 if (i!=NR_SUPERIOS)
1554 return superios[i].irq;
1555 return PARPORT_IRQ_NONE;
1556 }
1557
1558
1559 /* --- Mode detection ------------------------------------- */
1560
1561 /*
1562 * Checks for port existence, all ports support SPP MODE
1563 * Returns:
1564 * 0 : No parallel port at this address
1565 * PARPORT_MODE_PCSPP : SPP port detected
1566 * (if the user specified an ioport himself,
1567 * this shall always be the case!)
1568 *
1569 */
1570 static int __devinit parport_SPP_supported(struct parport *pb)
1571 {
1572 unsigned char r, w;
1573
1574 /*
1575 * first clear an eventually pending EPP timeout
1576 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1577 * that does not even respond to SPP cycles if an EPP
1578 * timeout is pending
1579 */
1580 clear_epp_timeout(pb);
1581
1582 /* Do a simple read-write test to make sure the port exists. */
1583 w = 0xc;
1584 outb (w, CONTROL (pb));
1585
1586 /* Is there a control register that we can read from? Some
1587 * ports don't allow reads, so read_control just returns a
1588 * software copy. Some ports _do_ allow reads, so bypass the
1589 * software copy here. In addition, some bits aren't
1590 * writable. */
1591 r = inb (CONTROL (pb));
1592 if ((r & 0xf) == w) {
1593 w = 0xe;
1594 outb (w, CONTROL (pb));
1595 r = inb (CONTROL (pb));
1596 outb (0xc, CONTROL (pb));
1597 if ((r & 0xf) == w)
1598 return PARPORT_MODE_PCSPP;
1599 }
1600
1601 if (user_specified)
1602 /* That didn't work, but the user thinks there's a
1603 * port here. */
1604 printk (KERN_INFO "parport 0x%lx (WARNING): CTR: "
1605 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1606
1607 /* Try the data register. The data lines aren't tri-stated at
1608 * this stage, so we expect back what we wrote. */
1609 w = 0xaa;
1610 parport_pc_write_data (pb, w);
1611 r = parport_pc_read_data (pb);
1612 if (r == w) {
1613 w = 0x55;
1614 parport_pc_write_data (pb, w);
1615 r = parport_pc_read_data (pb);
1616 if (r == w)
1617 return PARPORT_MODE_PCSPP;
1618 }
1619
1620 if (user_specified) {
1621 /* Didn't work, but the user is convinced this is the
1622 * place. */
1623 printk (KERN_INFO "parport 0x%lx (WARNING): DATA: "
1624 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1625 printk (KERN_INFO "parport 0x%lx: You gave this address, "
1626 "but there is probably no parallel port there!\n",
1627 pb->base);
1628 }
1629
1630 /* It's possible that we can't read the control register or
1631 * the data register. In that case just believe the user. */
1632 if (user_specified)
1633 return PARPORT_MODE_PCSPP;
1634
1635 return 0;
1636 }
1637
1638 /* Check for ECR
1639 *
1640 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1641 * on these cards actually accesses the CTR.
1642 *
1643 * Modern cards don't do this but reading from ECR will return 0xff
1644 * regardless of what is written here if the card does NOT support
1645 * ECP.
1646 *
1647 * We first check to see if ECR is the same as CTR. If not, the low
1648 * two bits of ECR aren't writable, so we check by writing ECR and
1649 * reading it back to see if it's what we expect.
1650 */
1651 static int __devinit parport_ECR_present(struct parport *pb)
1652 {
1653 struct parport_pc_private *priv = pb->private_data;
1654 unsigned char r = 0xc;
1655
1656 outb (r, CONTROL (pb));
1657 if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) {
1658 outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */
1659
1660 r = inb (CONTROL (pb));
1661 if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2))
1662 goto no_reg; /* Sure that no ECR register exists */
1663 }
1664
1665 if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1)
1666 goto no_reg;
1667
1668 ECR_WRITE (pb, 0x34);
1669 if (inb (ECONTROL (pb)) != 0x35)
1670 goto no_reg;
1671
1672 priv->ecr = 1;
1673 outb (0xc, CONTROL (pb));
1674
1675 /* Go to mode 000 */
1676 frob_set_mode (pb, ECR_SPP);
1677
1678 return 1;
1679
1680 no_reg:
1681 outb (0xc, CONTROL (pb));
1682 return 0;
1683 }
1684
1685 #ifdef CONFIG_PARPORT_1284
1686 /* Detect PS/2 support.
1687 *
1688 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1689 * allows us to read data from the data lines. In theory we would get back
1690 * 0xff but any peripheral attached to the port may drag some or all of the
1691 * lines down to zero. So if we get back anything that isn't the contents
1692 * of the data register we deem PS/2 support to be present.
1693 *
1694 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1695 * drivers, but an external peripheral with sufficiently beefy drivers of
1696 * its own can overpower them and assert its own levels onto the bus, from
1697 * where they can then be read back as normal. Ports with this property
1698 * and the right type of device attached are likely to fail the SPP test,
1699 * (as they will appear to have stuck bits) and so the fact that they might
1700 * be misdetected here is rather academic.
1701 */
1702
1703 static int __devinit parport_PS2_supported(struct parport *pb)
1704 {
1705 int ok = 0;
1706
1707 clear_epp_timeout(pb);
1708
1709 /* try to tri-state the buffer */
1710 parport_pc_data_reverse (pb);
1711
1712 parport_pc_write_data(pb, 0x55);
1713 if (parport_pc_read_data(pb) != 0x55) ok++;
1714
1715 parport_pc_write_data(pb, 0xaa);
1716 if (parport_pc_read_data(pb) != 0xaa) ok++;
1717
1718 /* cancel input mode */
1719 parport_pc_data_forward (pb);
1720
1721 if (ok) {
1722 pb->modes |= PARPORT_MODE_TRISTATE;
1723 } else {
1724 struct parport_pc_private *priv = pb->private_data;
1725 priv->ctr_writable &= ~0x20;
1726 }
1727
1728 return ok;
1729 }
1730
1731 #ifdef CONFIG_PARPORT_PC_FIFO
1732 static int __devinit parport_ECP_supported(struct parport *pb)
1733 {
1734 int i;
1735 int config, configb;
1736 int pword;
1737 struct parport_pc_private *priv = pb->private_data;
1738 /* Translate ECP intrLine to ISA irq value */
1739 static const int intrline[]= { 0, 7, 9, 10, 11, 14, 15, 5 };
1740
1741 /* If there is no ECR, we have no hope of supporting ECP. */
1742 if (!priv->ecr)
1743 return 0;
1744
1745 /* Find out FIFO depth */
1746 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1747 ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */
1748 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++)
1749 outb (0xaa, FIFO (pb));
1750
1751 /*
1752 * Using LGS chipset it uses ECR register, but
1753 * it doesn't support ECP or FIFO MODE
1754 */
1755 if (i == 1024) {
1756 ECR_WRITE (pb, ECR_SPP << 5);
1757 return 0;
1758 }
1759
1760 priv->fifo_depth = i;
1761 if (verbose_probing)
1762 printk (KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1763
1764 /* Find out writeIntrThreshold */
1765 frob_econtrol (pb, 1<<2, 1<<2);
1766 frob_econtrol (pb, 1<<2, 0);
1767 for (i = 1; i <= priv->fifo_depth; i++) {
1768 inb (FIFO (pb));
1769 udelay (50);
1770 if (inb (ECONTROL (pb)) & (1<<2))
1771 break;
1772 }
1773
1774 if (i <= priv->fifo_depth) {
1775 if (verbose_probing)
1776 printk (KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1777 pb->base, i);
1778 } else
1779 /* Number of bytes we know we can write if we get an
1780 interrupt. */
1781 i = 0;
1782
1783 priv->writeIntrThreshold = i;
1784
1785 /* Find out readIntrThreshold */
1786 frob_set_mode (pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1787 parport_pc_data_reverse (pb); /* Must be in PS2 mode */
1788 frob_set_mode (pb, ECR_TST); /* Test FIFO */
1789 frob_econtrol (pb, 1<<2, 1<<2);
1790 frob_econtrol (pb, 1<<2, 0);
1791 for (i = 1; i <= priv->fifo_depth; i++) {
1792 outb (0xaa, FIFO (pb));
1793 if (inb (ECONTROL (pb)) & (1<<2))
1794 break;
1795 }
1796
1797 if (i <= priv->fifo_depth) {
1798 if (verbose_probing)
1799 printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1800 pb->base, i);
1801 } else
1802 /* Number of bytes we can read if we get an interrupt. */
1803 i = 0;
1804
1805 priv->readIntrThreshold = i;
1806
1807 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1808 ECR_WRITE (pb, 0xf4); /* Configuration mode */
1809 config = inb (CONFIGA (pb));
1810 pword = (config >> 4) & 0x7;
1811 switch (pword) {
1812 case 0:
1813 pword = 2;
1814 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1815 pb->base);
1816 break;
1817 case 2:
1818 pword = 4;
1819 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1820 pb->base);
1821 break;
1822 default:
1823 printk (KERN_WARNING "0x%lx: Unknown implementation ID\n",
1824 pb->base);
1825 /* Assume 1 */
1826 case 1:
1827 pword = 1;
1828 }
1829 priv->pword = pword;
1830
1831 if (verbose_probing) {
1832 printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword);
1833
1834 printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1835 config & 0x80 ? "Level" : "Pulses");
1836
1837 configb = inb (CONFIGB (pb));
1838 printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1839 pb->base, config, configb);
1840 printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1841 if ((configb >>3) & 0x07)
1842 printk("%d",intrline[(configb >>3) & 0x07]);
1843 else
1844 printk("<none or set by other means>");
1845 printk (" dma=");
1846 if( (configb & 0x03 ) == 0x00)
1847 printk("<none or set by other means>\n");
1848 else
1849 printk("%d\n",configb & 0x07);
1850 }
1851
1852 /* Go back to mode 000 */
1853 frob_set_mode (pb, ECR_SPP);
1854
1855 return 1;
1856 }
1857 #endif
1858
1859 static int __devinit parport_ECPPS2_supported(struct parport *pb)
1860 {
1861 const struct parport_pc_private *priv = pb->private_data;
1862 int result;
1863 unsigned char oecr;
1864
1865 if (!priv->ecr)
1866 return 0;
1867
1868 oecr = inb (ECONTROL (pb));
1869 ECR_WRITE (pb, ECR_PS2 << 5);
1870 result = parport_PS2_supported(pb);
1871 ECR_WRITE (pb, oecr);
1872 return result;
1873 }
1874
1875 /* EPP mode detection */
1876
1877 static int __devinit parport_EPP_supported(struct parport *pb)
1878 {
1879 const struct parport_pc_private *priv = pb->private_data;
1880
1881 /*
1882 * Theory:
1883 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1884 * when EPP is possible and is set high when an EPP timeout
1885 * occurs (EPP uses the HALT line to stop the CPU while it does
1886 * the byte transfer, an EPP timeout occurs if the attached
1887 * device fails to respond after 10 micro seconds).
1888 *
1889 * This bit is cleared by either reading it (National Semi)
1890 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1891 * This bit is always high in non EPP modes.
1892 */
1893
1894 /* If EPP timeout bit clear then EPP available */
1895 if (!clear_epp_timeout(pb)) {
1896 return 0; /* No way to clear timeout */
1897 }
1898
1899 /* Check for Intel bug. */
1900 if (priv->ecr) {
1901 unsigned char i;
1902 for (i = 0x00; i < 0x80; i += 0x20) {
1903 ECR_WRITE (pb, i);
1904 if (clear_epp_timeout (pb)) {
1905 /* Phony EPP in ECP. */
1906 return 0;
1907 }
1908 }
1909 }
1910
1911 pb->modes |= PARPORT_MODE_EPP;
1912
1913 /* Set up access functions to use EPP hardware. */
1914 pb->ops->epp_read_data = parport_pc_epp_read_data;
1915 pb->ops->epp_write_data = parport_pc_epp_write_data;
1916 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1917 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1918
1919 return 1;
1920 }
1921
1922 static int __devinit parport_ECPEPP_supported(struct parport *pb)
1923 {
1924 struct parport_pc_private *priv = pb->private_data;
1925 int result;
1926 unsigned char oecr;
1927
1928 if (!priv->ecr) {
1929 return 0;
1930 }
1931
1932 oecr = inb (ECONTROL (pb));
1933 /* Search for SMC style EPP+ECP mode */
1934 ECR_WRITE (pb, 0x80);
1935 outb (0x04, CONTROL (pb));
1936 result = parport_EPP_supported(pb);
1937
1938 ECR_WRITE (pb, oecr);
1939
1940 if (result) {
1941 /* Set up access functions to use ECP+EPP hardware. */
1942 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1943 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1944 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1945 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1946 }
1947
1948 return result;
1949 }
1950
1951 #else /* No IEEE 1284 support */
1952
1953 /* Don't bother probing for modes we know we won't use. */
1954 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
1955 #ifdef CONFIG_PARPORT_PC_FIFO
1956 static int __devinit parport_ECP_supported(struct parport *pb) { return 0; }
1957 #endif
1958 static int __devinit parport_EPP_supported(struct parport *pb) { return 0; }
1959 static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;}
1960 static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;}
1961
1962 #endif /* No IEEE 1284 support */
1963
1964 /* --- IRQ detection -------------------------------------- */
1965
1966 /* Only if supports ECP mode */
1967 static int __devinit programmable_irq_support(struct parport *pb)
1968 {
1969 int irq, intrLine;
1970 unsigned char oecr = inb (ECONTROL (pb));
1971 static const int lookup[8] = {
1972 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1973 };
1974
1975 ECR_WRITE (pb, ECR_CNF << 5); /* Configuration MODE */
1976
1977 intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07;
1978 irq = lookup[intrLine];
1979
1980 ECR_WRITE (pb, oecr);
1981 return irq;
1982 }
1983
1984 static int __devinit irq_probe_ECP(struct parport *pb)
1985 {
1986 int i;
1987 unsigned long irqs;
1988
1989 irqs = probe_irq_on();
1990
1991 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1992 ECR_WRITE (pb, (ECR_TST << 5) | 0x04);
1993 ECR_WRITE (pb, ECR_TST << 5);
1994
1995 /* If Full FIFO sure that writeIntrThreshold is generated */
1996 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++)
1997 outb (0xaa, FIFO (pb));
1998
1999 pb->irq = probe_irq_off(irqs);
2000 ECR_WRITE (pb, ECR_SPP << 5);
2001
2002 if (pb->irq <= 0)
2003 pb->irq = PARPORT_IRQ_NONE;
2004
2005 return pb->irq;
2006 }
2007
2008 /*
2009 * This detection seems that only works in National Semiconductors
2010 * This doesn't work in SMC, LGS, and Winbond
2011 */
2012 static int __devinit irq_probe_EPP(struct parport *pb)
2013 {
2014 #ifndef ADVANCED_DETECT
2015 return PARPORT_IRQ_NONE;
2016 #else
2017 int irqs;
2018 unsigned char oecr;
2019
2020 if (pb->modes & PARPORT_MODE_PCECR)
2021 oecr = inb (ECONTROL (pb));
2022
2023 irqs = probe_irq_on();
2024
2025 if (pb->modes & PARPORT_MODE_PCECR)
2026 frob_econtrol (pb, 0x10, 0x10);
2027
2028 clear_epp_timeout(pb);
2029 parport_pc_frob_control (pb, 0x20, 0x20);
2030 parport_pc_frob_control (pb, 0x10, 0x10);
2031 clear_epp_timeout(pb);
2032
2033 /* Device isn't expecting an EPP read
2034 * and generates an IRQ.
2035 */
2036 parport_pc_read_epp(pb);
2037 udelay(20);
2038
2039 pb->irq = probe_irq_off (irqs);
2040 if (pb->modes & PARPORT_MODE_PCECR)
2041 ECR_WRITE (pb, oecr);
2042 parport_pc_write_control(pb, 0xc);
2043
2044 if (pb->irq <= 0)
2045 pb->irq = PARPORT_IRQ_NONE;
2046
2047 return pb->irq;
2048 #endif /* Advanced detection */
2049 }
2050
2051 static int __devinit irq_probe_SPP(struct parport *pb)
2052 {
2053 /* Don't even try to do this. */
2054 return PARPORT_IRQ_NONE;
2055 }
2056
2057 /* We will attempt to share interrupt requests since other devices
2058 * such as sound cards and network cards seem to like using the
2059 * printer IRQs.
2060 *
2061 * When ECP is available we can autoprobe for IRQs.
2062 * NOTE: If we can autoprobe it, we can register the IRQ.
2063 */
2064 static int __devinit parport_irq_probe(struct parport *pb)
2065 {
2066 struct parport_pc_private *priv = pb->private_data;
2067
2068 if (priv->ecr) {
2069 pb->irq = programmable_irq_support(pb);
2070
2071 if (pb->irq == PARPORT_IRQ_NONE)
2072 pb->irq = irq_probe_ECP(pb);
2073 }
2074
2075 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
2076 (pb->modes & PARPORT_MODE_EPP))
2077 pb->irq = irq_probe_EPP(pb);
2078
2079 clear_epp_timeout(pb);
2080
2081 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
2082 pb->irq = irq_probe_EPP(pb);
2083
2084 clear_epp_timeout(pb);
2085
2086 if (pb->irq == PARPORT_IRQ_NONE)
2087 pb->irq = irq_probe_SPP(pb);
2088
2089 if (pb->irq == PARPORT_IRQ_NONE)
2090 pb->irq = get_superio_irq(pb);
2091
2092 return pb->irq;
2093 }
2094
2095 /* --- DMA detection -------------------------------------- */
2096
2097 /* Only if chipset conforms to ECP ISA Interface Standard */
2098 static int __devinit programmable_dma_support (struct parport *p)
2099 {
2100 unsigned char oecr = inb (ECONTROL (p));
2101 int dma;
2102
2103 frob_set_mode (p, ECR_CNF);
2104
2105 dma = inb (CONFIGB(p)) & 0x07;
2106 /* 000: Indicates jumpered 8-bit DMA if read-only.
2107 100: Indicates jumpered 16-bit DMA if read-only. */
2108 if ((dma & 0x03) == 0)
2109 dma = PARPORT_DMA_NONE;
2110
2111 ECR_WRITE (p, oecr);
2112 return dma;
2113 }
2114
2115 static int __devinit parport_dma_probe (struct parport *p)
2116 {
2117 const struct parport_pc_private *priv = p->private_data;
2118 if (priv->ecr)
2119 p->dma = programmable_dma_support(p); /* ask ECP chipset first */
2120 if (p->dma == PARPORT_DMA_NONE) {
2121 /* ask known Super-IO chips proper, although these
2122 claim ECP compatible, some don't report their DMA
2123 conforming to ECP standards */
2124 p->dma = get_superio_dma(p);
2125 }
2126
2127 return p->dma;
2128 }
2129
2130 /* --- Initialisation code -------------------------------- */
2131
2132 static LIST_HEAD(ports_list);
2133 static DEFINE_SPINLOCK(ports_lock);
2134
2135 struct parport *parport_pc_probe_port (unsigned long int base,
2136 unsigned long int base_hi,
2137 int irq, int dma,
2138 struct pci_dev *dev)
2139 {
2140 struct parport_pc_private *priv;
2141 struct parport_operations *ops;
2142 struct parport *p;
2143 int probedirq = PARPORT_IRQ_NONE;
2144 struct resource *base_res;
2145 struct resource *ECR_res = NULL;
2146 struct resource *EPP_res = NULL;
2147
2148 ops = kmalloc(sizeof (struct parport_operations), GFP_KERNEL);
2149 if (!ops)
2150 goto out1;
2151
2152 priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
2153 if (!priv)
2154 goto out2;
2155
2156 /* a misnomer, actually - it's allocate and reserve parport number */
2157 p = parport_register_port(base, irq, dma, ops);
2158 if (!p)
2159 goto out3;
2160
2161 base_res = request_region(base, 3, p->name);
2162 if (!base_res)
2163 goto out4;
2164
2165 memcpy(ops, &parport_pc_ops, sizeof (struct parport_operations));
2166 priv->ctr = 0xc;
2167 priv->ctr_writable = ~0x10;
2168 priv->ecr = 0;
2169 priv->fifo_depth = 0;
2170 priv->dma_buf = NULL;
2171 priv->dma_handle = 0;
2172 priv->dev = dev;
2173 INIT_LIST_HEAD(&priv->list);
2174 priv->port = p;
2175 p->base_hi = base_hi;
2176 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2177 p->private_data = priv;
2178
2179 if (base_hi) {
2180 ECR_res = request_region(base_hi, 3, p->name);
2181 if (ECR_res)
2182 parport_ECR_present(p);
2183 }
2184
2185 if (base != 0x3bc) {
2186 EPP_res = request_region(base+0x3, 5, p->name);
2187 if (EPP_res)
2188 if (!parport_EPP_supported(p))
2189 parport_ECPEPP_supported(p);
2190 }
2191 if (!parport_SPP_supported (p))
2192 /* No port. */
2193 goto out5;
2194 if (priv->ecr)
2195 parport_ECPPS2_supported(p);
2196 else
2197 parport_PS2_supported(p);
2198
2199 p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
2200
2201 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2202 if (p->base_hi && priv->ecr)
2203 printk(" (0x%lx)", p->base_hi);
2204 if (p->irq == PARPORT_IRQ_AUTO) {
2205 p->irq = PARPORT_IRQ_NONE;
2206 parport_irq_probe(p);
2207 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2208 p->irq = PARPORT_IRQ_NONE;
2209 parport_irq_probe(p);
2210 probedirq = p->irq;
2211 p->irq = PARPORT_IRQ_NONE;
2212 }
2213 if (p->irq != PARPORT_IRQ_NONE) {
2214 printk(", irq %d", p->irq);
2215 priv->ctr_writable |= 0x10;
2216
2217 if (p->dma == PARPORT_DMA_AUTO) {
2218 p->dma = PARPORT_DMA_NONE;
2219 parport_dma_probe(p);
2220 }
2221 }
2222 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2223 is mandatory (see above) */
2224 p->dma = PARPORT_DMA_NONE;
2225
2226 #ifdef CONFIG_PARPORT_PC_FIFO
2227 if (parport_ECP_supported(p) &&
2228 p->dma != PARPORT_DMA_NOFIFO &&
2229 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2230 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2231 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2232 #ifdef CONFIG_PARPORT_1284
2233 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2234 /* currently broken, but working on it.. (FB) */
2235 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2236 #endif /* IEEE 1284 support */
2237 if (p->dma != PARPORT_DMA_NONE) {
2238 printk(", dma %d", p->dma);
2239 p->modes |= PARPORT_MODE_DMA;
2240 }
2241 else printk(", using FIFO");
2242 }
2243 else
2244 /* We can't use the DMA channel after all. */
2245 p->dma = PARPORT_DMA_NONE;
2246 #endif /* Allowed to use FIFO/DMA */
2247
2248 printk(" [");
2249 #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}}
2250 {
2251 int f = 0;
2252 printmode(PCSPP);
2253 printmode(TRISTATE);
2254 printmode(COMPAT)
2255 printmode(EPP);
2256 printmode(ECP);
2257 printmode(DMA);
2258 }
2259 #undef printmode
2260 #ifndef CONFIG_PARPORT_1284
2261 printk ("(,...)");
2262 #endif /* CONFIG_PARPORT_1284 */
2263 printk("]\n");
2264 if (probedirq != PARPORT_IRQ_NONE)
2265 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2266
2267 /* If No ECP release the ports grabbed above. */
2268 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2269 release_region(base_hi, 3);
2270 ECR_res = NULL;
2271 }
2272 /* Likewise for EEP ports */
2273 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2274 release_region(base+3, 5);
2275 EPP_res = NULL;
2276 }
2277 if (p->irq != PARPORT_IRQ_NONE) {
2278 if (request_irq (p->irq, parport_pc_interrupt,
2279 0, p->name, p)) {
2280 printk (KERN_WARNING "%s: irq %d in use, "
2281 "resorting to polled operation\n",
2282 p->name, p->irq);
2283 p->irq = PARPORT_IRQ_NONE;
2284 p->dma = PARPORT_DMA_NONE;
2285 }
2286
2287 #ifdef CONFIG_PARPORT_PC_FIFO
2288 if (p->dma != PARPORT_DMA_NONE) {
2289 if (request_dma (p->dma, p->name)) {
2290 printk (KERN_WARNING "%s: dma %d in use, "
2291 "resorting to PIO operation\n",
2292 p->name, p->dma);
2293 p->dma = PARPORT_DMA_NONE;
2294 } else {
2295 priv->dma_buf =
2296 pci_alloc_consistent(priv->dev,
2297 PAGE_SIZE,
2298 &priv->dma_handle);
2299 if (! priv->dma_buf) {
2300 printk (KERN_WARNING "%s: "
2301 "cannot get buffer for DMA, "
2302 "resorting to PIO operation\n",
2303 p->name);
2304 free_dma(p->dma);
2305 p->dma = PARPORT_DMA_NONE;
2306 }
2307 }
2308 }
2309 #endif /* CONFIG_PARPORT_PC_FIFO */
2310 }
2311
2312 /* Done probing. Now put the port into a sensible start-up state. */
2313 if (priv->ecr)
2314 /*
2315 * Put the ECP detected port in PS2 mode.
2316 * Do this also for ports that have ECR but don't do ECP.
2317 */
2318 ECR_WRITE (p, 0x34);
2319
2320 parport_pc_write_data(p, 0);
2321 parport_pc_data_forward (p);
2322
2323 /* Now that we've told the sharing engine about the port, and
2324 found out its characteristics, let the high-level drivers
2325 know about it. */
2326 spin_lock(&ports_lock);
2327 list_add(&priv->list, &ports_list);
2328 spin_unlock(&ports_lock);
2329 parport_announce_port (p);
2330
2331 return p;
2332
2333 out5:
2334 if (ECR_res)
2335 release_region(base_hi, 3);
2336 if (EPP_res)
2337 release_region(base+0x3, 5);
2338 release_region(base, 3);
2339 out4:
2340 parport_put_port(p);
2341 out3:
2342 kfree (priv);
2343 out2:
2344 kfree (ops);
2345 out1:
2346 return NULL;
2347 }
2348
2349 EXPORT_SYMBOL (parport_pc_probe_port);
2350
2351 void parport_pc_unregister_port (struct parport *p)
2352 {
2353 struct parport_pc_private *priv = p->private_data;
2354 struct parport_operations *ops = p->ops;
2355
2356 parport_remove_port(p);
2357 spin_lock(&ports_lock);
2358 list_del_init(&priv->list);
2359 spin_unlock(&ports_lock);
2360 if (p->dma != PARPORT_DMA_NONE)
2361 free_dma(p->dma);
2362 if (p->irq != PARPORT_IRQ_NONE)
2363 free_irq(p->irq, p);
2364 release_region(p->base, 3);
2365 if (p->size > 3)
2366 release_region(p->base + 3, p->size - 3);
2367 if (p->modes & PARPORT_MODE_ECP)
2368 release_region(p->base_hi, 3);
2369 #ifdef CONFIG_PARPORT_PC_FIFO
2370 if (priv->dma_buf)
2371 pci_free_consistent(priv->dev, PAGE_SIZE,
2372 priv->dma_buf,
2373 priv->dma_handle);
2374 #endif /* CONFIG_PARPORT_PC_FIFO */
2375 kfree (p->private_data);
2376 parport_put_port(p);
2377 kfree (ops); /* hope no-one cached it */
2378 }
2379
2380 EXPORT_SYMBOL (parport_pc_unregister_port);
2381
2382 #ifdef CONFIG_PCI
2383
2384 /* ITE support maintained by Rich Liu <richliu@poorman.org> */
2385 static int __devinit sio_ite_8872_probe (struct pci_dev *pdev, int autoirq,
2386 int autodma, struct parport_pc_via_data *via)
2387 {
2388 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2389 struct resource *base_res;
2390 u32 ite8872set;
2391 u32 ite8872_lpt, ite8872_lpthi;
2392 u8 ite8872_irq, type;
2393 char *fake_name = "parport probe";
2394 int irq;
2395 int i;
2396
2397 DPRINTK (KERN_DEBUG "sio_ite_8872_probe()\n");
2398
2399 // make sure which one chip
2400 for(i = 0; i < 5; i++) {
2401 base_res = request_region(inta_addr[i], 0x8, fake_name);
2402 if (base_res) {
2403 int test;
2404 pci_write_config_dword (pdev, 0x60,
2405 0xe7000000 | inta_addr[i]);
2406 pci_write_config_dword (pdev, 0x78,
2407 0x00000000 | inta_addr[i]);
2408 test = inb (inta_addr[i]);
2409 if (test != 0xff) break;
2410 release_region(inta_addr[i], 0x8);
2411 }
2412 }
2413 if(i >= 5) {
2414 printk (KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2415 return 0;
2416 }
2417
2418 type = inb (inta_addr[i] + 0x18);
2419 type &= 0x0f;
2420
2421 switch (type) {
2422 case 0x2:
2423 printk (KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2424 ite8872set = 0x64200000;
2425 break;
2426 case 0xa:
2427 printk (KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2428 ite8872set = 0x64200000;
2429 break;
2430 case 0xe:
2431 printk (KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2432 ite8872set = 0x64e00000;
2433 break;
2434 case 0x6:
2435 printk (KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2436 return 0;
2437 case 0x8:
2438 DPRINTK (KERN_DEBUG "parport_pc: ITE8874 found (2S)\n");
2439 return 0;
2440 default:
2441 printk (KERN_INFO "parport_pc: unknown ITE887x\n");
2442 printk (KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2443 "output to Rich.Liu@ite.com.tw\n");
2444 return 0;
2445 }
2446
2447 pci_read_config_byte (pdev, 0x3c, &ite8872_irq);
2448 pci_read_config_dword (pdev, 0x1c, &ite8872_lpt);
2449 ite8872_lpt &= 0x0000ff00;
2450 pci_read_config_dword (pdev, 0x20, &ite8872_lpthi);
2451 ite8872_lpthi &= 0x0000ff00;
2452 pci_write_config_dword (pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2453 pci_write_config_dword (pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2454 pci_write_config_dword (pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2455 // SET SPP&EPP , Parallel Port NO DMA , Enable All Function
2456 // SET Parallel IRQ
2457 pci_write_config_dword (pdev, 0x9c,
2458 ite8872set | (ite8872_irq * 0x11111));
2459
2460 DPRINTK (KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2461 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2462 ite8872_lpt);
2463 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2464 ite8872_lpthi);
2465
2466 /* Let the user (or defaults) steer us away from interrupts */
2467 irq = ite8872_irq;
2468 if (autoirq != PARPORT_IRQ_AUTO)
2469 irq = PARPORT_IRQ_NONE;
2470
2471 /*
2472 * Release the resource so that parport_pc_probe_port can get it.
2473 */
2474 release_resource(base_res);
2475 if (parport_pc_probe_port (ite8872_lpt, ite8872_lpthi,
2476 irq, PARPORT_DMA_NONE, NULL)) {
2477 printk (KERN_INFO
2478 "parport_pc: ITE 8872 parallel port: io=0x%X",
2479 ite8872_lpt);
2480 if (irq != PARPORT_IRQ_NONE)
2481 printk (", irq=%d", irq);
2482 printk ("\n");
2483 return 1;
2484 }
2485
2486 return 0;
2487 }
2488
2489 /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2490 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2491 static int __devinitdata parport_init_mode = 0;
2492
2493 /* Data for two known VIA chips */
2494 static struct parport_pc_via_data via_686a_data __devinitdata = {
2495 0x51,
2496 0x50,
2497 0x85,
2498 0x02,
2499 0xE2,
2500 0xF0,
2501 0xE6
2502 };
2503 static struct parport_pc_via_data via_8231_data __devinitdata = {
2504 0x45,
2505 0x44,
2506 0x50,
2507 0x04,
2508 0xF2,
2509 0xFA,
2510 0xF6
2511 };
2512
2513 static int __devinit sio_via_probe (struct pci_dev *pdev, int autoirq,
2514 int autodma, struct parport_pc_via_data *via)
2515 {
2516 u8 tmp, tmp2, siofunc;
2517 u8 ppcontrol = 0;
2518 int dma, irq;
2519 unsigned port1, port2;
2520 unsigned have_epp = 0;
2521
2522 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2523
2524 switch(parport_init_mode)
2525 {
2526 case 1:
2527 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2528 siofunc = VIA_FUNCTION_PARPORT_SPP;
2529 break;
2530 case 2:
2531 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2532 siofunc = VIA_FUNCTION_PARPORT_SPP;
2533 ppcontrol = VIA_PARPORT_BIDIR;
2534 break;
2535 case 3:
2536 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2537 siofunc = VIA_FUNCTION_PARPORT_EPP;
2538 ppcontrol = VIA_PARPORT_BIDIR;
2539 have_epp = 1;
2540 break;
2541 case 4:
2542 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2543 siofunc = VIA_FUNCTION_PARPORT_ECP;
2544 ppcontrol = VIA_PARPORT_BIDIR;
2545 break;
2546 case 5:
2547 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2548 siofunc = VIA_FUNCTION_PARPORT_ECP;
2549 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2550 have_epp = 1;
2551 break;
2552 default:
2553 printk(KERN_DEBUG "parport_pc: probing current configuration\n");
2554 siofunc = VIA_FUNCTION_PROBE;
2555 break;
2556 }
2557 /*
2558 * unlock super i/o configuration
2559 */
2560 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2561 tmp |= via->via_pci_superio_config_data;
2562 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2563
2564 /* Bits 1-0: Parallel Port Mode / Enable */
2565 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2566 tmp = inb (VIA_CONFIG_DATA);
2567 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2568 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2569 tmp2 = inb (VIA_CONFIG_DATA);
2570 if (siofunc == VIA_FUNCTION_PROBE)
2571 {
2572 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2573 ppcontrol = tmp2;
2574 }
2575 else
2576 {
2577 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2578 tmp |= siofunc;
2579 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2580 outb(tmp, VIA_CONFIG_DATA);
2581 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2582 tmp2 |= ppcontrol;
2583 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2584 outb(tmp2, VIA_CONFIG_DATA);
2585 }
2586
2587 /* Parallel Port I/O Base Address, bits 9-2 */
2588 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2589 port1 = inb(VIA_CONFIG_DATA) << 2;
2590
2591 printk (KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",port1);
2592 if ((port1 == 0x3BC) && have_epp)
2593 {
2594 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2595 outb((0x378 >> 2), VIA_CONFIG_DATA);
2596 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n");
2597 port1 = 0x378;
2598 }
2599
2600 /*
2601 * lock super i/o configuration
2602 */
2603 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2604 tmp &= ~via->via_pci_superio_config_data;
2605 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2606
2607 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2608 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n");
2609 return 0;
2610 }
2611
2612 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2613 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2614 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2615
2616 if (siofunc == VIA_FUNCTION_PARPORT_ECP)
2617 {
2618 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2619 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2620 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2621 }
2622 else
2623 /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */
2624 dma = PARPORT_DMA_NONE;
2625
2626 /* Let the user (or defaults) steer us away from interrupts and DMA */
2627 if (autoirq == PARPORT_IRQ_NONE) {
2628 irq = PARPORT_IRQ_NONE;
2629 dma = PARPORT_DMA_NONE;
2630 }
2631 if (autodma == PARPORT_DMA_NONE)
2632 dma = PARPORT_DMA_NONE;
2633
2634 switch (port1) {
2635 case 0x3bc: port2 = 0x7bc; break;
2636 case 0x378: port2 = 0x778; break;
2637 case 0x278: port2 = 0x678; break;
2638 default:
2639 printk(KERN_INFO "parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2640 port1);
2641 return 0;
2642 }
2643
2644 /* filter bogus IRQs */
2645 switch (irq) {
2646 case 0:
2647 case 2:
2648 case 8:
2649 case 13:
2650 irq = PARPORT_IRQ_NONE;
2651 break;
2652
2653 default: /* do nothing */
2654 break;
2655 }
2656
2657 /* finally, do the probe with values obtained */
2658 if (parport_pc_probe_port (port1, port2, irq, dma, NULL)) {
2659 printk (KERN_INFO
2660 "parport_pc: VIA parallel port: io=0x%X", port1);
2661 if (irq != PARPORT_IRQ_NONE)
2662 printk (", irq=%d", irq);
2663 if (dma != PARPORT_DMA_NONE)
2664 printk (", dma=%d", dma);
2665 printk ("\n");
2666 return 1;
2667 }
2668
2669 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2670 port1, irq, dma);
2671 return 0;
2672 }
2673
2674
2675 enum parport_pc_sio_types {
2676 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2677 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
2678 sio_ite_8872,
2679 last_sio
2680 };
2681
2682 /* each element directly indexed from enum list, above */
2683 static struct parport_pc_superio {
2684 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma, struct parport_pc_via_data *via);
2685 struct parport_pc_via_data *via;
2686 } parport_pc_superio_info[] __devinitdata = {
2687 { sio_via_probe, &via_686a_data, },
2688 { sio_via_probe, &via_8231_data, },
2689 { sio_ite_8872_probe, NULL, },
2690 };
2691
2692 enum parport_pc_pci_cards {
2693 siig_1p_10x = last_sio,
2694 siig_2p_10x,
2695 siig_1p_20x,
2696 siig_2p_20x,
2697 lava_parallel,
2698 lava_parallel_dual_a,
2699 lava_parallel_dual_b,
2700 boca_ioppar,
2701 plx_9050,
2702 timedia_4078a,
2703 timedia_4079h,
2704 timedia_4085h,
2705 timedia_4088a,
2706 timedia_4089a,
2707 timedia_4095a,
2708 timedia_4096a,
2709 timedia_4078u,
2710 timedia_4079a,
2711 timedia_4085u,
2712 timedia_4079r,
2713 timedia_4079s,
2714 timedia_4079d,
2715 timedia_4079e,
2716 timedia_4079f,
2717 timedia_9079a,
2718 timedia_9079b,
2719 timedia_9079c,
2720 timedia_4006a,
2721 timedia_4014,
2722 timedia_4008a,
2723 timedia_4018,
2724 timedia_9018a,
2725 syba_2p_epp,
2726 syba_1p_ecp,
2727 titan_010l,
2728 titan_1284p2,
2729 avlab_1p,
2730 avlab_2p,
2731 oxsemi_954,
2732 oxsemi_840,
2733 aks_0100,
2734 mobility_pp,
2735 netmos_9705,
2736 netmos_9715,
2737 netmos_9755,
2738 netmos_9805,
2739 netmos_9815,
2740 netmos_9855,
2741 };
2742
2743
2744 /* each element directly indexed from enum list, above
2745 * (but offset by last_sio) */
2746 static struct parport_pc_pci {
2747 int numports;
2748 struct { /* BAR (base address registers) numbers in the config
2749 space header */
2750 int lo;
2751 int hi; /* -1 if not there, >6 for offset-method (max
2752 BAR is 6) */
2753 } addr[4];
2754
2755 /* If set, this is called immediately after pci_enable_device.
2756 * If it returns non-zero, no probing will take place and the
2757 * ports will not be used. */
2758 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2759
2760 /* If set, this is called after probing for ports. If 'failed'
2761 * is non-zero we couldn't use any of the ports. */
2762 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2763 } cards[] __devinitdata = {
2764 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2765 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2766 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2767 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2768 /* lava_parallel */ { 1, { { 0, -1 }, } },
2769 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2770 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2771 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2772 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2773 /* timedia_4078a */ { 1, { { 2, -1 }, } },
2774 /* timedia_4079h */ { 1, { { 2, 3 }, } },
2775 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
2776 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2777 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2778 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2779 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2780 /* timedia_4078u */ { 1, { { 2, -1 }, } },
2781 /* timedia_4079a */ { 1, { { 2, 3 }, } },
2782 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
2783 /* timedia_4079r */ { 1, { { 2, 3 }, } },
2784 /* timedia_4079s */ { 1, { { 2, 3 }, } },
2785 /* timedia_4079d */ { 1, { { 2, 3 }, } },
2786 /* timedia_4079e */ { 1, { { 2, 3 }, } },
2787 /* timedia_4079f */ { 1, { { 2, 3 }, } },
2788 /* timedia_9079a */ { 1, { { 2, 3 }, } },
2789 /* timedia_9079b */ { 1, { { 2, 3 }, } },
2790 /* timedia_9079c */ { 1, { { 2, 3 }, } },
2791 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2792 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2793 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2794 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2795 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2796 /* SYBA uses fixed offsets in
2797 a 1K io window */
2798 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2799 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2800 /* titan_010l */ { 1, { { 3, -1 }, } },
2801 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2802 /* avlab_1p */ { 1, { { 0, 1}, } },
2803 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2804 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2805 * and 840 locks up if you write 1 to bit 2! */
2806 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2807 /* oxsemi_840 */ { 1, { { 0, -1 }, } },
2808 /* aks_0100 */ { 1, { { 0, -1 }, } },
2809 /* mobility_pp */ { 1, { { 0, 1 }, } },
2810 /* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */
2811 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */
2812 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */
2813 /* netmos_9805 */ { 1, { { 0, -1 }, } }, /* untested */
2814 /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */
2815 /* netmos_9855 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */
2816 };
2817
2818 static struct pci_device_id parport_pc_pci_tbl[] = {
2819 /* Super-IO onboard chips */
2820 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2821 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2822 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2823 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2824
2825 /* PCI cards */
2826 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2827 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2828 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2829 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2830 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2831 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2832 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2833 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2834 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2835 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2836 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2837 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2838 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2839 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2840 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2841 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2842 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2843 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 },
2844 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2845 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
2846 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
2847 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
2848 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
2849 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
2850 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
2851 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
2852 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
2853 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
2854 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
2855 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
2856 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
2857 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
2858 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
2859 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
2860 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
2861 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
2862 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
2863 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2864 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2865 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2866 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2867 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2868 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2869 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2870 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2871 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2872 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2873 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2874 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2875 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
2876 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2877 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, /* AFAVLAB_TK9902 */
2878 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2879 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2880 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2881 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2882 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2883 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2884 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2885 /* NetMos communication controllers */
2886 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2887 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2888 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2889 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2890 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2891 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2892 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2893 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2894 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2895 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2896 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
2897 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9855 },
2898 { 0, } /* terminate list */
2899 };
2900 MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl);
2901
2902 struct pci_parport_data {
2903 int num;
2904 struct parport *ports[2];
2905 };
2906
2907 static int parport_pc_pci_probe (struct pci_dev *dev,
2908 const struct pci_device_id *id)
2909 {
2910 int err, count, n, i = id->driver_data;
2911 struct pci_parport_data *data;
2912
2913 if (i < last_sio)
2914 /* This is an onboard Super-IO and has already been probed */
2915 return 0;
2916
2917 /* This is a PCI card */
2918 i -= last_sio;
2919 count = 0;
2920 if ((err = pci_enable_device (dev)) != 0)
2921 return err;
2922
2923 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
2924 if (!data)
2925 return -ENOMEM;
2926
2927 if (cards[i].preinit_hook &&
2928 cards[i].preinit_hook (dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
2929 kfree(data);
2930 return -ENODEV;
2931 }
2932
2933 for (n = 0; n < cards[i].numports; n++) {
2934 int lo = cards[i].addr[n].lo;
2935 int hi = cards[i].addr[n].hi;
2936 unsigned long io_lo, io_hi;
2937 io_lo = pci_resource_start (dev, lo);
2938 io_hi = 0;
2939 if ((hi >= 0) && (hi <= 6))
2940 io_hi = pci_resource_start (dev, hi);
2941 else if (hi > 6)
2942 io_lo += hi; /* Reinterpret the meaning of
2943 "hi" as an offset (see SYBA
2944 def.) */
2945 /* TODO: test if sharing interrupts works */
2946 printk (KERN_DEBUG "PCI parallel port detected: %04x:%04x, "
2947 "I/O at %#lx(%#lx)\n",
2948 parport_pc_pci_tbl[i + last_sio].vendor,
2949 parport_pc_pci_tbl[i + last_sio].device, io_lo, io_hi);
2950 data->ports[count] =
2951 parport_pc_probe_port (io_lo, io_hi, PARPORT_IRQ_NONE,
2952 PARPORT_DMA_NONE, dev);
2953 if (data->ports[count])
2954 count++;
2955 }
2956
2957 data->num = count;
2958
2959 if (cards[i].postinit_hook)
2960 cards[i].postinit_hook (dev, count == 0);
2961
2962 if (count) {
2963 pci_set_drvdata(dev, data);
2964 return 0;
2965 }
2966
2967 kfree(data);
2968
2969 return -ENODEV;
2970 }
2971
2972 static void __devexit parport_pc_pci_remove(struct pci_dev *dev)
2973 {
2974 struct pci_parport_data *data = pci_get_drvdata(dev);
2975 int i;
2976
2977 pci_set_drvdata(dev, NULL);
2978
2979 if (data) {
2980 for (i = data->num - 1; i >= 0; i--)
2981 parport_pc_unregister_port(data->ports[i]);
2982
2983 kfree(data);
2984 }
2985 }
2986
2987 static struct pci_driver parport_pc_pci_driver = {
2988 .name = "parport_pc",
2989 .id_table = parport_pc_pci_tbl,
2990 .probe = parport_pc_pci_probe,
2991 .remove = __devexit_p(parport_pc_pci_remove),
2992 };
2993
2994 static int __init parport_pc_init_superio (int autoirq, int autodma)
2995 {
2996 const struct pci_device_id *id;
2997 struct pci_dev *pdev = NULL;
2998 int ret = 0;
2999
3000 while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) {
3001 id = pci_match_device (parport_pc_pci_tbl, pdev);
3002 if (id == NULL || id->driver_data >= last_sio)
3003 continue;
3004
3005 if (parport_pc_superio_info[id->driver_data].probe
3006 (pdev, autoirq, autodma,parport_pc_superio_info[id->driver_data].via)) {
3007 ret++;
3008 }
3009 }
3010
3011 return ret; /* number of devices found */
3012 }
3013 #else
3014 static struct pci_driver parport_pc_pci_driver;
3015 static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;}
3016 #endif /* CONFIG_PCI */
3017
3018
3019 static const struct pnp_device_id parport_pc_pnp_tbl[] = {
3020 /* Standard LPT Printer Port */
3021 {.id = "PNP0400", .driver_data = 0},
3022 /* ECP Printer Port */
3023 {.id = "PNP0401", .driver_data = 0},
3024 { }
3025 };
3026
3027 MODULE_DEVICE_TABLE(pnp,parport_pc_pnp_tbl);
3028
3029 static int parport_pc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id)
3030 {
3031 struct parport *pdata;
3032 unsigned long io_lo, io_hi;
3033 int dma, irq;
3034
3035 if (pnp_port_valid(dev,0) &&
3036 !(pnp_port_flags(dev,0) & IORESOURCE_DISABLED)) {
3037 io_lo = pnp_port_start(dev,0);
3038 } else
3039 return -EINVAL;
3040
3041 if (pnp_port_valid(dev,1) &&
3042 !(pnp_port_flags(dev,1) & IORESOURCE_DISABLED)) {
3043 io_hi = pnp_port_start(dev,1);
3044 } else
3045 io_hi = 0;
3046
3047 if (pnp_irq_valid(dev,0) &&
3048 !(pnp_irq_flags(dev,0) & IORESOURCE_DISABLED)) {
3049 irq = pnp_irq(dev,0);
3050 } else
3051 irq = PARPORT_IRQ_NONE;
3052
3053 if (pnp_dma_valid(dev,0) &&
3054 !(pnp_dma_flags(dev,0) & IORESOURCE_DISABLED)) {
3055 dma = pnp_dma(dev,0);
3056 } else
3057 dma = PARPORT_DMA_NONE;
3058
3059 printk(KERN_INFO "parport: PnPBIOS parport detected.\n");
3060 if (!(pdata = parport_pc_probe_port (io_lo, io_hi, irq, dma, NULL)))
3061 return -ENODEV;
3062
3063 pnp_set_drvdata(dev,pdata);
3064 return 0;
3065 }
3066
3067 static void parport_pc_pnp_remove(struct pnp_dev *dev)
3068 {
3069 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
3070 if (!pdata)
3071 return;
3072
3073 parport_pc_unregister_port(pdata);
3074 }
3075
3076 /* we only need the pnp layer to activate the device, at least for now */
3077 static struct pnp_driver parport_pc_pnp_driver = {
3078 .name = "parport_pc",
3079 .id_table = parport_pc_pnp_tbl,
3080 .probe = parport_pc_pnp_probe,
3081 .remove = parport_pc_pnp_remove,
3082 };
3083
3084
3085 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3086 static int __devinit __attribute__((unused))
3087 parport_pc_find_isa_ports (int autoirq, int autodma)
3088 {
3089 int count = 0;
3090
3091 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL))
3092 count++;
3093 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL))
3094 count++;
3095 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL))
3096 count++;
3097
3098 return count;
3099 }
3100
3101 /* This function is called by parport_pc_init if the user didn't
3102 * specify any ports to probe. Its job is to find some ports. Order
3103 * is important here -- we want ISA ports to be registered first,
3104 * followed by PCI cards (for least surprise), but before that we want
3105 * to do chipset-specific tests for some onboard ports that we know
3106 * about.
3107 *
3108 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3109 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3110 */
3111 static int __init parport_pc_find_ports (int autoirq, int autodma)
3112 {
3113 int count = 0, r;
3114
3115 #ifdef CONFIG_PARPORT_PC_SUPERIO
3116 detect_and_report_winbond ();
3117 detect_and_report_smsc ();
3118 #endif
3119
3120 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3121 count += parport_pc_init_superio (autoirq, autodma);
3122
3123 /* PnP ports, skip detection if SuperIO already found them */
3124 if (!count) {
3125 r = pnp_register_driver (&parport_pc_pnp_driver);
3126 if (r >= 0) {
3127 pnp_registered_parport = 1;
3128 count += r;
3129 }
3130 }
3131
3132 /* ISA ports and whatever (see asm/parport.h). */
3133 count += parport_pc_find_nonpci_ports (autoirq, autodma);
3134
3135 r = pci_register_driver (&parport_pc_pci_driver);
3136 if (r)
3137 return r;
3138 pci_registered_parport = 1;
3139 count += 1;
3140
3141 return count;
3142 }
3143
3144 /*
3145 * Piles of crap below pretend to be a parser for module and kernel
3146 * parameters. Say "thank you" to whoever had come up with that
3147 * syntax and keep in mind that code below is a cleaned up version.
3148 */
3149
3150 static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 };
3151 static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] =
3152 { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO };
3153 static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE };
3154 static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY };
3155
3156 static int __init parport_parse_param(const char *s, int *val,
3157 int automatic, int none, int nofifo)
3158 {
3159 if (!s)
3160 return 0;
3161 if (!strncmp(s, "auto", 4))
3162 *val = automatic;
3163 else if (!strncmp(s, "none", 4))
3164 *val = none;
3165 else if (nofifo && !strncmp(s, "nofifo", 4))
3166 *val = nofifo;
3167 else {
3168 char *ep;
3169 unsigned long r = simple_strtoul(s, &ep, 0);
3170 if (ep != s)
3171 *val = r;
3172 else {
3173 printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3174 return -1;
3175 }
3176 }
3177 return 0;
3178 }
3179
3180 static int __init parport_parse_irq(const char *irqstr, int *val)
3181 {
3182 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3183 PARPORT_IRQ_NONE, 0);
3184 }
3185
3186 static int __init parport_parse_dma(const char *dmastr, int *val)
3187 {
3188 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3189 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3190 }
3191
3192 #ifdef CONFIG_PCI
3193 static int __init parport_init_mode_setup(char *str)
3194 {
3195 printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n", str);
3196
3197 if (!strcmp (str, "spp"))
3198 parport_init_mode=1;
3199 if (!strcmp (str, "ps2"))
3200 parport_init_mode=2;
3201 if (!strcmp (str, "epp"))
3202 parport_init_mode=3;
3203 if (!strcmp (str, "ecp"))
3204 parport_init_mode=4;
3205 if (!strcmp (str, "ecpepp"))
3206 parport_init_mode=5;
3207 return 1;
3208 }
3209 #endif
3210
3211 #ifdef MODULE
3212 static const char *irq[PARPORT_PC_MAX_PORTS];
3213 static const char *dma[PARPORT_PC_MAX_PORTS];
3214
3215 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3216 module_param_array(io, int, NULL, 0);
3217 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3218 module_param_array(io_hi, int, NULL, 0);
3219 MODULE_PARM_DESC(irq, "IRQ line");
3220 module_param_array(irq, charp, NULL, 0);
3221 MODULE_PARM_DESC(dma, "DMA channel");
3222 module_param_array(dma, charp, NULL, 0);
3223 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3224 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3225 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3226 module_param(verbose_probing, int, 0644);
3227 #endif
3228 #ifdef CONFIG_PCI
3229 static char *init_mode;
3230 MODULE_PARM_DESC(init_mode, "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3231 module_param(init_mode, charp, 0);
3232 #endif
3233
3234 static int __init parse_parport_params(void)
3235 {
3236 unsigned int i;
3237 int val;
3238
3239 #ifdef CONFIG_PCI
3240 if (init_mode)
3241 parport_init_mode_setup(init_mode);
3242 #endif
3243
3244 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3245 if (parport_parse_irq(irq[i], &val))
3246 return 1;
3247 irqval[i] = val;
3248 if (parport_parse_dma(dma[i], &val))
3249 return 1;
3250 dmaval[i] = val;
3251 }
3252 if (!io[0]) {
3253 /* The user can make us use any IRQs or DMAs we find. */
3254 if (irq[0] && !parport_parse_irq(irq[0], &val))
3255 switch (val) {
3256 case PARPORT_IRQ_NONE:
3257 case PARPORT_IRQ_AUTO:
3258 irqval[0] = val;
3259 break;
3260 default:
3261 printk (KERN_WARNING
3262 "parport_pc: irq specified "
3263 "without base address. Use 'io=' "
3264 "to specify one\n");
3265 }
3266
3267 if (dma[0] && !parport_parse_dma(dma[0], &val))
3268 switch (val) {
3269 case PARPORT_DMA_NONE:
3270 case PARPORT_DMA_AUTO:
3271 dmaval[0] = val;
3272 break;
3273 default:
3274 printk (KERN_WARNING
3275 "parport_pc: dma specified "
3276 "without base address. Use 'io=' "
3277 "to specify one\n");
3278 }
3279 }
3280 return 0;
3281 }
3282
3283 #else
3284
3285 static int parport_setup_ptr __initdata = 0;
3286
3287 /*
3288 * Acceptable parameters:
3289 *
3290 * parport=0
3291 * parport=auto
3292 * parport=0xBASE[,IRQ[,DMA]]
3293 *
3294 * IRQ/DMA may be numeric or 'auto' or 'none'
3295 */
3296 static int __init parport_setup (char *str)
3297 {
3298 char *endptr;
3299 char *sep;
3300 int val;
3301
3302 if (!str || !*str || (*str == '0' && !*(str+1))) {
3303 /* Disable parport if "parport=0" in cmdline */
3304 io[0] = PARPORT_DISABLE;
3305 return 1;
3306 }
3307
3308 if (!strncmp (str, "auto", 4)) {
3309 irqval[0] = PARPORT_IRQ_AUTO;
3310 dmaval[0] = PARPORT_DMA_AUTO;
3311 return 1;
3312 }
3313
3314 val = simple_strtoul (str, &endptr, 0);
3315 if (endptr == str) {
3316 printk (KERN_WARNING "parport=%s not understood\n", str);
3317 return 1;
3318 }
3319
3320 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3321 printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3322 return 1;
3323 }
3324
3325 io[parport_setup_ptr] = val;
3326 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3327 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3328
3329 sep = strchr(str, ',');
3330 if (sep++) {
3331 if (parport_parse_irq(sep, &val))
3332 return 1;
3333 irqval[parport_setup_ptr] = val;
3334 sep = strchr(sep, ',');
3335 if (sep++) {
3336 if (parport_parse_dma(sep, &val))
3337 return 1;
3338 dmaval[parport_setup_ptr] = val;
3339 }
3340 }
3341 parport_setup_ptr++;
3342 return 1;
3343 }
3344
3345 static int __init parse_parport_params(void)
3346 {
3347 return io[0] == PARPORT_DISABLE;
3348 }
3349
3350 __setup ("parport=", parport_setup);
3351
3352 /*
3353 * Acceptable parameters:
3354 *
3355 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3356 */
3357 #ifdef CONFIG_PCI
3358 __setup("parport_init_mode=",parport_init_mode_setup);
3359 #endif
3360 #endif
3361
3362 /* "Parser" ends here */
3363
3364 static int __init parport_pc_init(void)
3365 {
3366 int count = 0;
3367
3368 if (parse_parport_params())
3369 return -EINVAL;
3370
3371 if (io[0]) {
3372 int i;
3373 /* Only probe the ports we were given. */
3374 user_specified = 1;
3375 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3376 if (!io[i])
3377 break;
3378 if ((io_hi[i]) == PARPORT_IOHI_AUTO)
3379 io_hi[i] = 0x400 + io[i];
3380 if (parport_pc_probe_port(io[i], io_hi[i],
3381 irqval[i], dmaval[i], NULL))
3382 count++;
3383 }
3384 } else
3385 count += parport_pc_find_ports (irqval[0], dmaval[0]);
3386
3387 return 0;
3388 }
3389
3390 static void __exit parport_pc_exit(void)
3391 {
3392 if (pci_registered_parport)
3393 pci_unregister_driver (&parport_pc_pci_driver);
3394 if (pnp_registered_parport)
3395 pnp_unregister_driver (&parport_pc_pnp_driver);
3396
3397 spin_lock(&ports_lock);
3398 while (!list_empty(&ports_list)) {
3399 struct parport_pc_private *priv;
3400 struct parport *port;
3401 priv = list_entry(ports_list.next,
3402 struct parport_pc_private, list);
3403 port = priv->port;
3404 spin_unlock(&ports_lock);
3405 parport_pc_unregister_port(port);
3406 spin_lock(&ports_lock);
3407 }
3408 spin_unlock(&ports_lock);
3409 }
3410
3411 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3412 MODULE_DESCRIPTION("PC-style parallel port driver");
3413 MODULE_LICENSE("GPL");
3414 module_init(parport_pc_init)
3415 module_exit(parport_pc_exit)
Linux with added FPC-III support