drivers/ata/ahci_xgene.c

   1 /*
   2  * AppliedMicro X-Gene SoC SATA Host Controller Driver
   3  *
   4  * Copyright (c) 2014, Applied Micro Circuits Corporation
   5  * Author: Loc Ho <lho@apm.com>
   6  *         Tuan Phan <tphan@apm.com>
   7  *         Suman Tripathi <stripathi@apm.com>
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * NOTE: PM support is not currently available.
  23  *
  24  */
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/ahci_platform.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_irq.h>
  30 #include <linux/phy/phy.h>
  31 #include "ahci.h"
  32
  33 /* Max # of disk per a controller */
  34 #define MAX_AHCI_CHN_PERCTR             2
  35
  36 /* MUX CSR */
  37 #define SATA_ENET_CONFIG_REG            0x00000000
  38 #define  CFG_SATA_ENET_SELECT_MASK      0x00000001
  39
  40 /* SATA core host controller CSR */
  41 #define SLVRDERRATTRIBUTES              0x00000000
  42 #define SLVWRERRATTRIBUTES              0x00000004
  43 #define MSTRDERRATTRIBUTES              0x00000008
  44 #define MSTWRERRATTRIBUTES              0x0000000c
  45 #define BUSCTLREG                       0x00000014
  46 #define IOFMSTRWAUX                     0x00000018
  47 #define INTSTATUSMASK                   0x0000002c
  48 #define ERRINTSTATUS                    0x00000030
  49 #define ERRINTSTATUSMASK                0x00000034
  50
  51 /* SATA host AHCI CSR */
  52 #define PORTCFG                         0x000000a4
  53 #define  PORTADDR_SET(dst, src) \
  54                 (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))
  55 #define PORTPHY1CFG             0x000000a8
  56 #define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \
  57                 (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))
  58 #define PORTPHY2CFG                     0x000000ac
  59 #define PORTPHY3CFG                     0x000000b0
  60 #define PORTPHY4CFG                     0x000000b4
  61 #define PORTPHY5CFG                     0x000000b8
  62 #define SCTL0                           0x0000012C
  63 #define PORTPHY5CFG_RTCHG_SET(dst, src) \
  64                 (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))
  65 #define PORTAXICFG_EN_CONTEXT_SET(dst, src) \
  66                 (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))
  67 #define PORTAXICFG                      0x000000bc
  68 #define PORTAXICFG_OUTTRANS_SET(dst, src) \
  69                 (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
  70 #define PORTRANSCFG                     0x000000c8
  71 #define PORTRANSCFG_RXWM_SET(dst, src)          \
  72                 (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f))
  73
  74 /* SATA host controller AXI CSR */
  75 #define INT_SLV_TMOMASK                 0x00000010
  76
  77 /* SATA diagnostic CSR */
  78 #define CFG_MEM_RAM_SHUTDOWN            0x00000070
  79 #define BLOCK_MEM_RDY                   0x00000074
  80
  81 /* Max retry for link down */
  82 #define MAX_LINK_DOWN_RETRY 3
  83
  84 struct xgene_ahci_context {
  85         struct ahci_host_priv *hpriv;
  86         struct device *dev;
  87         u8 last_cmd[MAX_AHCI_CHN_PERCTR]; /* tracking the last command issued*/
  88         void __iomem *csr_core;         /* Core CSR address of IP */
  89         void __iomem *csr_diag;         /* Diag CSR address of IP */
  90         void __iomem *csr_axi;          /* AXI CSR address of IP */
  91         void __iomem *csr_mux;          /* MUX CSR address of IP */
  92 };
  93
  94 static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
  95 {
  96         dev_dbg(ctx->dev, "Release memory from shutdown\n");
  97         writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);
  98         readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
  99         msleep(1);      /* reset may take up to 1ms */
 100         if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {
 101                 dev_err(ctx->dev, "failed to release memory from shutdown\n");
 102                 return -ENODEV;
 103         }
 104         return 0;
 105 }
 106
 107 /**
 108  * xgene_ahci_restart_engine - Restart the dma engine.
 109  * @ap : ATA port of interest
 110  *
 111  * Restarts the dma engine inside the controller.
 112  */
 113 static int xgene_ahci_restart_engine(struct ata_port *ap)
 114 {
 115         struct ahci_host_priv *hpriv = ap->host->private_data;
 116
 117         ahci_stop_engine(ap);
 118         ahci_start_fis_rx(ap);
 119         hpriv->start_engine(ap);
 120
 121         return 0;
 122 }
 123
 124 /**
 125  * xgene_ahci_qc_issue - Issue commands to the device
 126  * @qc: Command to issue
 127  *
 128  * Due to Hardware errata for IDENTIFY DEVICE command, the controller cannot
 129  * clear the BSY bit after receiving the PIO setup FIS. This results in the dma
 130  * state machine goes into the CMFatalErrorUpdate state and locks up. By
 131  * restarting the dma engine, it removes the controller out of lock up state.
 132  */
 133 static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc)
 134 {
 135         struct ata_port *ap = qc->ap;
 136         struct ahci_host_priv *hpriv = ap->host->private_data;
 137         struct xgene_ahci_context *ctx = hpriv->plat_data;
 138         int rc = 0;
 139
 140         if (unlikely(ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA))
 141                 xgene_ahci_restart_engine(ap);
 142
 143         rc = ahci_qc_issue(qc);
 144
 145         /* Save the last command issued */
 146         ctx->last_cmd[ap->port_no] = qc->tf.command;
 147
 148         return rc;
 149 }
 150
 151 static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context *ctx)
 152 {
 153         void __iomem *diagcsr = ctx->csr_diag;
 154
 155         return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 &&
 156                 readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF);
 157 }
 158
 159 /**
 160  * xgene_ahci_read_id - Read ID data from the specified device
 161  * @dev: device
 162  * @tf: proposed taskfile
 163  * @id: data buffer
 164  *
 165  * This custom read ID function is required due to the fact that the HW
 166  * does not support DEVSLP.
 167  */
 168 static unsigned int xgene_ahci_read_id(struct ata_device *dev,
 169                                        struct ata_taskfile *tf, u16 *id)
 170 {
 171         u32 err_mask;
 172
 173         err_mask = ata_do_dev_read_id(dev, tf, id);
 174         if (err_mask)
 175                 return err_mask;
 176
 177         /*
 178          * Mask reserved area. Word78 spec of Link Power Management
 179          * bit15-8: reserved
 180          * bit7: NCQ autosence
 181          * bit6: Software settings preservation supported
 182          * bit5: reserved
 183          * bit4: In-order sata delivery supported
 184          * bit3: DIPM requests supported
 185          * bit2: DMA Setup FIS Auto-Activate optimization supported
 186          * bit1: DMA Setup FIX non-Zero buffer offsets supported
 187          * bit0: Reserved
 188          *
 189          * Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP
 190          */
 191         id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8));
 192
 193         return 0;
 194 }
 195
 196 static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
 197 {
 198         void __iomem *mmio = ctx->hpriv->mmio;
 199         u32 val;
 200
 201         dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
 202                 mmio, channel);
 203         val = readl(mmio + PORTCFG);
 204         val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
 205         writel(val, mmio + PORTCFG);
 206         readl(mmio + PORTCFG);  /* Force a barrier */
 207         /* Disable fix rate */
 208         writel(0x0001fffe, mmio + PORTPHY1CFG);
 209         readl(mmio + PORTPHY1CFG); /* Force a barrier */
 210         writel(0x28183219, mmio + PORTPHY2CFG);
 211         readl(mmio + PORTPHY2CFG); /* Force a barrier */
 212         writel(0x13081008, mmio + PORTPHY3CFG);
 213         readl(mmio + PORTPHY3CFG); /* Force a barrier */
 214         writel(0x00480815, mmio + PORTPHY4CFG);
 215         readl(mmio + PORTPHY4CFG); /* Force a barrier */
 216         /* Set window negotiation */
 217         val = readl(mmio + PORTPHY5CFG);
 218         val = PORTPHY5CFG_RTCHG_SET(val, 0x300);
 219         writel(val, mmio + PORTPHY5CFG);
 220         readl(mmio + PORTPHY5CFG); /* Force a barrier */
 221         val = readl(mmio + PORTAXICFG);
 222         val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */
 223         val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */
 224         writel(val, mmio + PORTAXICFG);
 225         readl(mmio + PORTAXICFG); /* Force a barrier */
 226         /* Set the watermark threshold of the receive FIFO */
 227         val = readl(mmio + PORTRANSCFG);
 228         val = PORTRANSCFG_RXWM_SET(val, 0x30);
 229         writel(val, mmio + PORTRANSCFG);
 230 }
 231
 232 /**
 233  * xgene_ahci_do_hardreset - Issue the actual COMRESET
 234  * @link: link to reset
 235  * @deadline: deadline jiffies for the operation
 236  * @online: Return value to indicate if device online
 237  *
 238  * Due to the limitation of the hardware PHY, a difference set of setting is
 239  * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps),
 240  * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will
 241  * report disparity error and etc. In addition, during COMRESET, there can
 242  * be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and
 243  * SERR_10B_8B_ERR, the PHY receiver line must be reseted. Also during long
 244  * reboot cycle regression, sometimes the PHY reports link down even if the
 245  * device is present because of speed negotiation failure. so need to retry
 246  * the COMRESET to get the link up. The following algorithm is followed to
 247  * proper configure the hardware PHY during COMRESET:
 248  *
 249  * Alg Part 1:
 250  * 1. Start the PHY at Gen3 speed (default setting)
 251  * 2. Issue the COMRESET
 252  * 3. If no link, go to Alg Part 3
 253  * 4. If link up, determine if the negotiated speed matches the PHY
 254  *    configured speed
 255  * 5. If they matched, go to Alg Part 2
 256  * 6. If they do not matched and first time, configure the PHY for the linked
 257  *    up disk speed and repeat step 2
 258  * 7. Go to Alg Part 2
 259  *
 260  * Alg Part 2:
 261  * 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error
 262  *    reported in the register PORT_SCR_ERR, then reset the PHY receiver line
 263  * 2. Go to Alg Part 4
 264  *
 265  * Alg Part 3:
 266  * 1. Check the PORT_SCR_STAT to see whether device presence detected but PHY
 267  *    communication establishment failed and maximum link down attempts are
 268  *    less than Max attempts 3 then goto Alg Part 1.
 269  * 2. Go to Alg Part 4.
 270  *
 271  * Alg Part 4:
 272  * 1. Clear any pending from register PORT_SCR_ERR.
 273  *
 274  * NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition
 275  *       and until the underlying PHY supports an method to reset the receiver
 276  *       line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors,
 277  *       an warning message will be printed.
 278  */
 279 static int xgene_ahci_do_hardreset(struct ata_link *link,
 280                                    unsigned long deadline, bool *online)
 281 {
 282         const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
 283         struct ata_port *ap = link->ap;
 284         struct ahci_host_priv *hpriv = ap->host->private_data;
 285         struct xgene_ahci_context *ctx = hpriv->plat_data;
 286         struct ahci_port_priv *pp = ap->private_data;
 287         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
 288         void __iomem *port_mmio = ahci_port_base(ap);
 289         struct ata_taskfile tf;
 290         int link_down_retry = 0;
 291         int rc;
 292         u32 val, sstatus;
 293
 294         do {
 295                 /* clear D2H reception area to properly wait for D2H FIS */
 296                 ata_tf_init(link->device, &tf);
 297                 tf.command = ATA_BUSY;
 298                 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 299                 rc = sata_link_hardreset(link, timing, deadline, online,
 300                                  ahci_check_ready);
 301                 if (*online) {
 302                         val = readl(port_mmio + PORT_SCR_ERR);
 303                         if (val & (SERR_DISPARITY | SERR_10B_8B_ERR))
 304                                 dev_warn(ctx->dev, "link has error\n");
 305                         break;
 306                 }
 307
 308                 sata_scr_read(link, SCR_STATUS, &sstatus);
 309         } while (link_down_retry++ < MAX_LINK_DOWN_RETRY &&
 310                  (sstatus & 0xff) == 0x1);
 311
 312         /* clear all errors if any pending */
 313         val = readl(port_mmio + PORT_SCR_ERR);
 314         writel(val, port_mmio + PORT_SCR_ERR);
 315
 316         return rc;
 317 }
 318
 319 static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class,
 320                                 unsigned long deadline)
 321 {
 322         struct ata_port *ap = link->ap;
 323         struct ahci_host_priv *hpriv = ap->host->private_data;
 324         void __iomem *port_mmio = ahci_port_base(ap);
 325         bool online;
 326         int rc;
 327         u32 portcmd_saved;
 328         u32 portclb_saved;
 329         u32 portclbhi_saved;
 330         u32 portrxfis_saved;
 331         u32 portrxfishi_saved;
 332
 333         /* As hardreset resets these CSR, save it to restore later */
 334         portcmd_saved = readl(port_mmio + PORT_CMD);
 335         portclb_saved = readl(port_mmio + PORT_LST_ADDR);
 336         portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);
 337         portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);
 338         portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);
 339
 340         ahci_stop_engine(ap);
 341
 342         rc = xgene_ahci_do_hardreset(link, deadline, &online);
 343
 344         /* As controller hardreset clears them, restore them */
 345         writel(portcmd_saved, port_mmio + PORT_CMD);
 346         writel(portclb_saved, port_mmio + PORT_LST_ADDR);
 347         writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI);
 348         writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR);
 349         writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI);
 350
 351         hpriv->start_engine(ap);
 352
 353         if (online)
 354                 *class = ahci_dev_classify(ap);
 355
 356         return rc;
 357 }
 358
 359 static void xgene_ahci_host_stop(struct ata_host *host)
 360 {
 361         struct ahci_host_priv *hpriv = host->private_data;
 362
 363         ahci_platform_disable_resources(hpriv);
 364 }
 365
 366 static struct ata_port_operations xgene_ahci_ops = {
 367         .inherits = &ahci_ops,
 368         .host_stop = xgene_ahci_host_stop,
 369         .hardreset = xgene_ahci_hardreset,
 370         .read_id = xgene_ahci_read_id,
 371         .qc_issue = xgene_ahci_qc_issue,
 372 };
 373
 374 static const struct ata_port_info xgene_ahci_port_info = {
 375         .flags = AHCI_FLAG_COMMON,
 376         .pio_mask = ATA_PIO4,
 377         .udma_mask = ATA_UDMA6,
 378         .port_ops = &xgene_ahci_ops,
 379 };
 380
 381 static int xgene_ahci_hw_init(struct ahci_host_priv *hpriv)
 382 {
 383         struct xgene_ahci_context *ctx = hpriv->plat_data;
 384         int i;
 385         int rc;
 386         u32 val;
 387
 388         /* Remove IP RAM out of shutdown */
 389         rc = xgene_ahci_init_memram(ctx);
 390         if (rc)
 391                 return rc;
 392
 393         for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++)
 394                 xgene_ahci_set_phy_cfg(ctx, i);
 395
 396         /* AXI disable Mask */
 397         writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);
 398         readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */
 399         writel(0, ctx->csr_core + INTSTATUSMASK);
 400         val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */
 401         dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n",
 402                 INTSTATUSMASK, val);
 403
 404         writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);
 405         readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */
 406         writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);
 407         readl(ctx->csr_axi + INT_SLV_TMOMASK);
 408
 409         /* Enable AXI Interrupt */
 410         writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);
 411         writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);
 412         writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);
 413         writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);
 414
 415         /* Enable coherency */
 416         val = readl(ctx->csr_core + BUSCTLREG);
 417         val &= ~0x00000002;     /* Enable write coherency */
 418         val &= ~0x00000001;     /* Enable read coherency */
 419         writel(val, ctx->csr_core + BUSCTLREG);
 420
 421         val = readl(ctx->csr_core + IOFMSTRWAUX);
 422         val |= (1 << 3);        /* Enable read coherency */
 423         val |= (1 << 9);        /* Enable write coherency */
 424         writel(val, ctx->csr_core + IOFMSTRWAUX);
 425         val = readl(ctx->csr_core + IOFMSTRWAUX);
 426         dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n",
 427                 IOFMSTRWAUX, val);
 428
 429         return rc;
 430 }
 431
 432 static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
 433 {
 434         u32 val;
 435
 436         /* Check for optional MUX resource */
 437         if (!ctx->csr_mux)
 438                 return 0;
 439
 440         val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
 441         val &= ~CFG_SATA_ENET_SELECT_MASK;
 442         writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);
 443         val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
 444         return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0;
 445 }
 446
 447 static int xgene_ahci_probe(struct platform_device *pdev)
 448 {
 449         struct device *dev = &pdev->dev;
 450         struct ahci_host_priv *hpriv;
 451         struct xgene_ahci_context *ctx;
 452         struct resource *res;
 453         int rc;
 454
 455         hpriv = ahci_platform_get_resources(pdev);
 456         if (IS_ERR(hpriv))
 457                 return PTR_ERR(hpriv);
 458
 459         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 460         if (!ctx)
 461                 return -ENOMEM;
 462
 463         hpriv->plat_data = ctx;
 464         ctx->hpriv = hpriv;
 465         ctx->dev = dev;
 466
 467         /* Retrieve the IP core resource */
 468         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 469         ctx->csr_core = devm_ioremap_resource(dev, res);
 470         if (IS_ERR(ctx->csr_core))
 471                 return PTR_ERR(ctx->csr_core);
 472
 473         /* Retrieve the IP diagnostic resource */
 474         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 475         ctx->csr_diag = devm_ioremap_resource(dev, res);
 476         if (IS_ERR(ctx->csr_diag))
 477                 return PTR_ERR(ctx->csr_diag);
 478
 479         /* Retrieve the IP AXI resource */
 480         res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
 481         ctx->csr_axi = devm_ioremap_resource(dev, res);
 482         if (IS_ERR(ctx->csr_axi))
 483                 return PTR_ERR(ctx->csr_axi);
 484
 485         /* Retrieve the optional IP mux resource */
 486         res = platform_get_resource(pdev, IORESOURCE_MEM, 4);
 487         if (res) {
 488                 void __iomem *csr = devm_ioremap_resource(dev, res);
 489                 if (IS_ERR(csr))
 490                         return PTR_ERR(csr);
 491
 492                 ctx->csr_mux = csr;
 493         }
 494
 495         dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,
 496                 hpriv->mmio);
 497
 498         /* Select ATA */
 499         if ((rc = xgene_ahci_mux_select(ctx))) {
 500                 dev_err(dev, "SATA mux selection failed error %d\n", rc);
 501                 return -ENODEV;
 502         }
 503
 504         if (xgene_ahci_is_memram_inited(ctx)) {
 505                 dev_info(dev, "skip clock and PHY initialization\n");
 506                 goto skip_clk_phy;
 507         }
 508
 509         /* Due to errata, HW requires full toggle transition */
 510         rc = ahci_platform_enable_clks(hpriv);
 511         if (rc)
 512                 goto disable_resources;
 513         ahci_platform_disable_clks(hpriv);
 514
 515         rc = ahci_platform_enable_resources(hpriv);
 516         if (rc)
 517                 goto disable_resources;
 518
 519         /* Configure the host controller */
 520         xgene_ahci_hw_init(hpriv);
 521 skip_clk_phy:
 522         hpriv->flags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_NCQ;
 523
 524         rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info);
 525         if (rc)
 526                 goto disable_resources;
 527
 528         dev_dbg(dev, "X-Gene SATA host controller initialized\n");
 529         return 0;
 530
 531 disable_resources:
 532         ahci_platform_disable_resources(hpriv);
 533         return rc;
 534 }
 535
 536 static const struct of_device_id xgene_ahci_of_match[] = {
 537         {.compatible = "apm,xgene-ahci"},
 538         {},
 539 };
 540 MODULE_DEVICE_TABLE(of, xgene_ahci_of_match);
 541
 542 static struct platform_driver xgene_ahci_driver = {
 543         .probe = xgene_ahci_probe,
 544         .remove = ata_platform_remove_one,
 545         .driver = {
 546                 .name = "xgene-ahci",
 547                 .owner = THIS_MODULE,
 548                 .of_match_table = xgene_ahci_of_match,
 549         },
 550 };
 551
 552 module_platform_driver(xgene_ahci_driver);
 553
 554 MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver");
 555 MODULE_AUTHOR("Loc Ho <lho@apm.com>");
 556 MODULE_LICENSE("GPL");
 557 MODULE_VERSION("0.4");