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Linux 3.18.86
[linux/fpc-iii.git] / drivers / crypto / atmel-sha.c
blob60e8376666b0615648a210d39f02089f3c3dea6a
1 /*
2 * Cryptographic API.
3 *
4 * Support for ATMEL SHA1/SHA256 HW acceleration.
5 *
6 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
7 * Author: Nicolas Royer <nicolas@eukrea.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 *
13 * Some ideas are from omap-sham.c drivers.
14 */
15
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/hw_random.h>
24 #include <linux/platform_device.h>
25
26 #include <linux/device.h>
27 #include <linux/init.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/scatterlist.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/of_device.h>
34 #include <linux/delay.h>
35 #include <linux/crypto.h>
36 #include <linux/cryptohash.h>
37 #include <crypto/scatterwalk.h>
38 #include <crypto/algapi.h>
39 #include <crypto/sha.h>
40 #include <crypto/hash.h>
41 #include <crypto/internal/hash.h>
42 #include <linux/platform_data/crypto-atmel.h>
43 #include "atmel-sha-regs.h"
44
45 /* SHA flags */
46 #define SHA_FLAGS_BUSY BIT(0)
47 #define SHA_FLAGS_FINAL BIT(1)
48 #define SHA_FLAGS_DMA_ACTIVE BIT(2)
49 #define SHA_FLAGS_OUTPUT_READY BIT(3)
50 #define SHA_FLAGS_INIT BIT(4)
51 #define SHA_FLAGS_CPU BIT(5)
52 #define SHA_FLAGS_DMA_READY BIT(6)
53
54 #define SHA_FLAGS_FINUP BIT(16)
55 #define SHA_FLAGS_SG BIT(17)
56 #define SHA_FLAGS_SHA1 BIT(18)
57 #define SHA_FLAGS_SHA224 BIT(19)
58 #define SHA_FLAGS_SHA256 BIT(20)
59 #define SHA_FLAGS_SHA384 BIT(21)
60 #define SHA_FLAGS_SHA512 BIT(22)
61 #define SHA_FLAGS_ERROR BIT(23)
62 #define SHA_FLAGS_PAD BIT(24)
63
64 #define SHA_OP_UPDATE 1
65 #define SHA_OP_FINAL 2
66
67 #define SHA_BUFFER_LEN PAGE_SIZE
68
69 #define ATMEL_SHA_DMA_THRESHOLD 56
70
71 struct atmel_sha_caps {
72 bool has_dma;
73 bool has_dualbuff;
74 bool has_sha224;
75 bool has_sha_384_512;
76 };
77
78 struct atmel_sha_dev;
79
80 struct atmel_sha_reqctx {
81 struct atmel_sha_dev *dd;
82 unsigned long flags;
83 unsigned long op;
84
85 u8 digest[SHA512_DIGEST_SIZE] __aligned(sizeof(u32));
86 u64 digcnt[2];
87 size_t bufcnt;
88 size_t buflen;
89 dma_addr_t dma_addr;
90
91 /* walk state */
92 struct scatterlist *sg;
93 unsigned int offset; /* offset in current sg */
94 unsigned int total; /* total request */
95
96 size_t block_size;
97
98 u8 buffer[0] __aligned(sizeof(u32));
99 };
100
101 struct atmel_sha_ctx {
102 struct atmel_sha_dev *dd;
103
104 unsigned long flags;
105
106 /* fallback stuff */
107 struct crypto_shash *fallback;
108
109 };
110
111 #define ATMEL_SHA_QUEUE_LENGTH 50
112
113 struct atmel_sha_dma {
114 struct dma_chan *chan;
115 struct dma_slave_config dma_conf;
116 };
117
118 struct atmel_sha_dev {
119 struct list_head list;
120 unsigned long phys_base;
121 struct device *dev;
122 struct clk *iclk;
123 int irq;
124 void __iomem *io_base;
125
126 spinlock_t lock;
127 int err;
128 struct tasklet_struct done_task;
129
130 unsigned long flags;
131 struct crypto_queue queue;
132 struct ahash_request *req;
133
134 struct atmel_sha_dma dma_lch_in;
135
136 struct atmel_sha_caps caps;
137
138 u32 hw_version;
139 };
140
141 struct atmel_sha_drv {
142 struct list_head dev_list;
143 spinlock_t lock;
144 };
145
146 static struct atmel_sha_drv atmel_sha = {
147 .dev_list = LIST_HEAD_INIT(atmel_sha.dev_list),
148 .lock = __SPIN_LOCK_UNLOCKED(atmel_sha.lock),
149 };
150
151 static inline u32 atmel_sha_read(struct atmel_sha_dev *dd, u32 offset)
152 {
153 return readl_relaxed(dd->io_base + offset);
154 }
155
156 static inline void atmel_sha_write(struct atmel_sha_dev *dd,
157 u32 offset, u32 value)
158 {
159 writel_relaxed(value, dd->io_base + offset);
160 }
161
162 static size_t atmel_sha_append_sg(struct atmel_sha_reqctx *ctx)
163 {
164 size_t count;
165
166 while ((ctx->bufcnt < ctx->buflen) && ctx->total) {
167 count = min(ctx->sg->length - ctx->offset, ctx->total);
168 count = min(count, ctx->buflen - ctx->bufcnt);
169
170 if (count <= 0)
171 break;
172
173 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, ctx->sg,
174 ctx->offset, count, 0);
175
176 ctx->bufcnt += count;
177 ctx->offset += count;
178 ctx->total -= count;
179
180 if (ctx->offset == ctx->sg->length) {
181 ctx->sg = sg_next(ctx->sg);
182 if (ctx->sg)
183 ctx->offset = 0;
184 else
185 ctx->total = 0;
186 }
187 }
188
189 return 0;
190 }
191
192 /*
193 * The purpose of this padding is to ensure that the padded message is a
194 * multiple of 512 bits (SHA1/SHA224/SHA256) or 1024 bits (SHA384/SHA512).
195 * The bit "1" is appended at the end of the message followed by
196 * "padlen-1" zero bits. Then a 64 bits block (SHA1/SHA224/SHA256) or
197 * 128 bits block (SHA384/SHA512) equals to the message length in bits
198 * is appended.
199 *
200 * For SHA1/SHA224/SHA256, padlen is calculated as followed:
201 * - if message length < 56 bytes then padlen = 56 - message length
202 * - else padlen = 64 + 56 - message length
203 *
204 * For SHA384/SHA512, padlen is calculated as followed:
205 * - if message length < 112 bytes then padlen = 112 - message length
206 * - else padlen = 128 + 112 - message length
207 */
208 static void atmel_sha_fill_padding(struct atmel_sha_reqctx *ctx, int length)
209 {
210 unsigned int index, padlen;
211 u64 bits[2];
212 u64 size[2];
213
214 size[0] = ctx->digcnt[0];
215 size[1] = ctx->digcnt[1];
216
217 size[0] += ctx->bufcnt;
218 if (size[0] < ctx->bufcnt)
219 size[1]++;
220
221 size[0] += length;
222 if (size[0] < length)
223 size[1]++;
224
225 bits[1] = cpu_to_be64(size[0] << 3);
226 bits[0] = cpu_to_be64(size[1] << 3 | size[0] >> 61);
227
228 if (ctx->flags & (SHA_FLAGS_SHA384 | SHA_FLAGS_SHA512)) {
229 index = ctx->bufcnt & 0x7f;
230 padlen = (index < 112) ? (112 - index) : ((128+112) - index);
231 *(ctx->buffer + ctx->bufcnt) = 0x80;
232 memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
233 memcpy(ctx->buffer + ctx->bufcnt + padlen, bits, 16);
234 ctx->bufcnt += padlen + 16;
235 ctx->flags |= SHA_FLAGS_PAD;
236 } else {
237 index = ctx->bufcnt & 0x3f;
238 padlen = (index < 56) ? (56 - index) : ((64+56) - index);
239 *(ctx->buffer + ctx->bufcnt) = 0x80;
240 memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
241 memcpy(ctx->buffer + ctx->bufcnt + padlen, &bits[1], 8);
242 ctx->bufcnt += padlen + 8;
243 ctx->flags |= SHA_FLAGS_PAD;
244 }
245 }
246
247 static int atmel_sha_init(struct ahash_request *req)
248 {
249 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
250 struct atmel_sha_ctx *tctx = crypto_ahash_ctx(tfm);
251 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
252 struct atmel_sha_dev *dd = NULL;
253 struct atmel_sha_dev *tmp;
254
255 spin_lock_bh(&atmel_sha.lock);
256 if (!tctx->dd) {
257 list_for_each_entry(tmp, &atmel_sha.dev_list, list) {
258 dd = tmp;
259 break;
260 }
261 tctx->dd = dd;
262 } else {
263 dd = tctx->dd;
264 }
265
266 spin_unlock_bh(&atmel_sha.lock);
267
268 ctx->dd = dd;
269
270 ctx->flags = 0;
271
272 dev_dbg(dd->dev, "init: digest size: %d\n",
273 crypto_ahash_digestsize(tfm));
274
275 switch (crypto_ahash_digestsize(tfm)) {
276 case SHA1_DIGEST_SIZE:
277 ctx->flags |= SHA_FLAGS_SHA1;
278 ctx->block_size = SHA1_BLOCK_SIZE;
279 break;
280 case SHA224_DIGEST_SIZE:
281 ctx->flags |= SHA_FLAGS_SHA224;
282 ctx->block_size = SHA224_BLOCK_SIZE;
283 break;
284 case SHA256_DIGEST_SIZE:
285 ctx->flags |= SHA_FLAGS_SHA256;
286 ctx->block_size = SHA256_BLOCK_SIZE;
287 break;
288 case SHA384_DIGEST_SIZE:
289 ctx->flags |= SHA_FLAGS_SHA384;
290 ctx->block_size = SHA384_BLOCK_SIZE;
291 break;
292 case SHA512_DIGEST_SIZE:
293 ctx->flags |= SHA_FLAGS_SHA512;
294 ctx->block_size = SHA512_BLOCK_SIZE;
295 break;
296 default:
297 return -EINVAL;
298 break;
299 }
300
301 ctx->bufcnt = 0;
302 ctx->digcnt[0] = 0;
303 ctx->digcnt[1] = 0;
304 ctx->buflen = SHA_BUFFER_LEN;
305
306 return 0;
307 }
308
309 static void atmel_sha_write_ctrl(struct atmel_sha_dev *dd, int dma)
310 {
311 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
312 u32 valcr = 0, valmr = SHA_MR_MODE_AUTO;
313
314 if (likely(dma)) {
315 if (!dd->caps.has_dma)
316 atmel_sha_write(dd, SHA_IER, SHA_INT_TXBUFE);
317 valmr = SHA_MR_MODE_PDC;
318 if (dd->caps.has_dualbuff)
319 valmr |= SHA_MR_DUALBUFF;
320 } else {
321 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
322 }
323
324 if (ctx->flags & SHA_FLAGS_SHA1)
325 valmr |= SHA_MR_ALGO_SHA1;
326 else if (ctx->flags & SHA_FLAGS_SHA224)
327 valmr |= SHA_MR_ALGO_SHA224;
328 else if (ctx->flags & SHA_FLAGS_SHA256)
329 valmr |= SHA_MR_ALGO_SHA256;
330 else if (ctx->flags & SHA_FLAGS_SHA384)
331 valmr |= SHA_MR_ALGO_SHA384;
332 else if (ctx->flags & SHA_FLAGS_SHA512)
333 valmr |= SHA_MR_ALGO_SHA512;
334
335 /* Setting CR_FIRST only for the first iteration */
336 if (!(ctx->digcnt[0] || ctx->digcnt[1]))
337 valcr = SHA_CR_FIRST;
338
339 atmel_sha_write(dd, SHA_CR, valcr);
340 atmel_sha_write(dd, SHA_MR, valmr);
341 }
342
343 static int atmel_sha_xmit_cpu(struct atmel_sha_dev *dd, const u8 *buf,
344 size_t length, int final)
345 {
346 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
347 int count, len32;
348 const u32 *buffer = (const u32 *)buf;
349
350 dev_dbg(dd->dev, "xmit_cpu: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n",
351 ctx->digcnt[1], ctx->digcnt[0], length, final);
352
353 atmel_sha_write_ctrl(dd, 0);
354
355 /* should be non-zero before next lines to disable clocks later */
356 ctx->digcnt[0] += length;
357 if (ctx->digcnt[0] < length)
358 ctx->digcnt[1]++;
359
360 if (final)
361 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
362
363 len32 = DIV_ROUND_UP(length, sizeof(u32));
364
365 dd->flags |= SHA_FLAGS_CPU;
366
367 for (count = 0; count < len32; count++)
368 atmel_sha_write(dd, SHA_REG_DIN(count), buffer[count]);
369
370 return -EINPROGRESS;
371 }
372
373 static int atmel_sha_xmit_pdc(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
374 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
375 {
376 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
377 int len32;
378
379 dev_dbg(dd->dev, "xmit_pdc: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n",
380 ctx->digcnt[1], ctx->digcnt[0], length1, final);
381
382 len32 = DIV_ROUND_UP(length1, sizeof(u32));
383 atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTDIS);
384 atmel_sha_write(dd, SHA_TPR, dma_addr1);
385 atmel_sha_write(dd, SHA_TCR, len32);
386
387 len32 = DIV_ROUND_UP(length2, sizeof(u32));
388 atmel_sha_write(dd, SHA_TNPR, dma_addr2);
389 atmel_sha_write(dd, SHA_TNCR, len32);
390
391 atmel_sha_write_ctrl(dd, 1);
392
393 /* should be non-zero before next lines to disable clocks later */
394 ctx->digcnt[0] += length1;
395 if (ctx->digcnt[0] < length1)
396 ctx->digcnt[1]++;
397
398 if (final)
399 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
400
401 dd->flags |= SHA_FLAGS_DMA_ACTIVE;
402
403 /* Start DMA transfer */
404 atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTEN);
405
406 return -EINPROGRESS;
407 }
408
409 static void atmel_sha_dma_callback(void *data)
410 {
411 struct atmel_sha_dev *dd = data;
412
413 /* dma_lch_in - completed - wait DATRDY */
414 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
415 }
416
417 static int atmel_sha_xmit_dma(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
418 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
419 {
420 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
421 struct dma_async_tx_descriptor *in_desc;
422 struct scatterlist sg[2];
423
424 dev_dbg(dd->dev, "xmit_dma: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n",
425 ctx->digcnt[1], ctx->digcnt[0], length1, final);
426
427 if (ctx->flags & (SHA_FLAGS_SHA1 | SHA_FLAGS_SHA224 |
428 SHA_FLAGS_SHA256)) {
429 dd->dma_lch_in.dma_conf.src_maxburst = 16;
430 dd->dma_lch_in.dma_conf.dst_maxburst = 16;
431 } else {
432 dd->dma_lch_in.dma_conf.src_maxburst = 32;
433 dd->dma_lch_in.dma_conf.dst_maxburst = 32;
434 }
435
436 dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf);
437
438 if (length2) {
439 sg_init_table(sg, 2);
440 sg_dma_address(&sg[0]) = dma_addr1;
441 sg_dma_len(&sg[0]) = length1;
442 sg_dma_address(&sg[1]) = dma_addr2;
443 sg_dma_len(&sg[1]) = length2;
444 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 2,
445 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
446 } else {
447 sg_init_table(sg, 1);
448 sg_dma_address(&sg[0]) = dma_addr1;
449 sg_dma_len(&sg[0]) = length1;
450 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 1,
451 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
452 }
453 if (!in_desc)
454 return -EINVAL;
455
456 in_desc->callback = atmel_sha_dma_callback;
457 in_desc->callback_param = dd;
458
459 atmel_sha_write_ctrl(dd, 1);
460
461 /* should be non-zero before next lines to disable clocks later */
462 ctx->digcnt[0] += length1;
463 if (ctx->digcnt[0] < length1)
464 ctx->digcnt[1]++;
465
466 if (final)
467 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
468
469 dd->flags |= SHA_FLAGS_DMA_ACTIVE;
470
471 /* Start DMA transfer */
472 dmaengine_submit(in_desc);
473 dma_async_issue_pending(dd->dma_lch_in.chan);
474
475 return -EINPROGRESS;
476 }
477
478 static int atmel_sha_xmit_start(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
479 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
480 {
481 if (dd->caps.has_dma)
482 return atmel_sha_xmit_dma(dd, dma_addr1, length1,
483 dma_addr2, length2, final);
484 else
485 return atmel_sha_xmit_pdc(dd, dma_addr1, length1,
486 dma_addr2, length2, final);
487 }
488
489 static int atmel_sha_update_cpu(struct atmel_sha_dev *dd)
490 {
491 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
492 int bufcnt;
493
494 atmel_sha_append_sg(ctx);
495 atmel_sha_fill_padding(ctx, 0);
496 bufcnt = ctx->bufcnt;
497 ctx->bufcnt = 0;
498
499 return atmel_sha_xmit_cpu(dd, ctx->buffer, bufcnt, 1);
500 }
501
502 static int atmel_sha_xmit_dma_map(struct atmel_sha_dev *dd,
503 struct atmel_sha_reqctx *ctx,
504 size_t length, int final)
505 {
506 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer,
507 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
508 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
509 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen +
510 ctx->block_size);
511 return -EINVAL;
512 }
513
514 ctx->flags &= ~SHA_FLAGS_SG;
515
516 /* next call does not fail... so no unmap in the case of error */
517 return atmel_sha_xmit_start(dd, ctx->dma_addr, length, 0, 0, final);
518 }
519
520 static int atmel_sha_update_dma_slow(struct atmel_sha_dev *dd)
521 {
522 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
523 unsigned int final;
524 size_t count;
525
526 atmel_sha_append_sg(ctx);
527
528 final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total;
529
530 dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: 0x%llx 0x%llx, final: %d\n",
531 ctx->bufcnt, ctx->digcnt[1], ctx->digcnt[0], final);
532
533 if (final)
534 atmel_sha_fill_padding(ctx, 0);
535
536 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
537 count = ctx->bufcnt;
538 ctx->bufcnt = 0;
539 return atmel_sha_xmit_dma_map(dd, ctx, count, final);
540 }
541
542 return 0;
543 }
544
545 static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd)
546 {
547 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
548 unsigned int length, final, tail;
549 struct scatterlist *sg;
550 unsigned int count;
551
552 if (!ctx->total)
553 return 0;
554
555 if (ctx->bufcnt || ctx->offset)
556 return atmel_sha_update_dma_slow(dd);
557
558 dev_dbg(dd->dev, "fast: digcnt: 0x%llx 0x%llx, bufcnt: %u, total: %u\n",
559 ctx->digcnt[1], ctx->digcnt[0], ctx->bufcnt, ctx->total);
560
561 sg = ctx->sg;
562
563 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
564 return atmel_sha_update_dma_slow(dd);
565
566 if (!sg_is_last(sg) && !IS_ALIGNED(sg->length, ctx->block_size))
567 /* size is not ctx->block_size aligned */
568 return atmel_sha_update_dma_slow(dd);
569
570 length = min(ctx->total, sg->length);
571
572 if (sg_is_last(sg)) {
573 if (!(ctx->flags & SHA_FLAGS_FINUP)) {
574 /* not last sg must be ctx->block_size aligned */
575 tail = length & (ctx->block_size - 1);
576 length -= tail;
577 }
578 }
579
580 ctx->total -= length;
581 ctx->offset = length; /* offset where to start slow */
582
583 final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total;
584
585 /* Add padding */
586 if (final) {
587 tail = length & (ctx->block_size - 1);
588 length -= tail;
589 ctx->total += tail;
590 ctx->offset = length; /* offset where to start slow */
591
592 sg = ctx->sg;
593 atmel_sha_append_sg(ctx);
594
595 atmel_sha_fill_padding(ctx, length);
596
597 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer,
598 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
599 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
600 dev_err(dd->dev, "dma %u bytes error\n",
601 ctx->buflen + ctx->block_size);
602 return -EINVAL;
603 }
604
605 if (length == 0) {
606 ctx->flags &= ~SHA_FLAGS_SG;
607 count = ctx->bufcnt;
608 ctx->bufcnt = 0;
609 return atmel_sha_xmit_start(dd, ctx->dma_addr, count, 0,
610 0, final);
611 } else {
612 ctx->sg = sg;
613 if (!dma_map_sg(dd->dev, ctx->sg, 1,
614 DMA_TO_DEVICE)) {
615 dev_err(dd->dev, "dma_map_sg error\n");
616 return -EINVAL;
617 }
618
619 ctx->flags |= SHA_FLAGS_SG;
620
621 count = ctx->bufcnt;
622 ctx->bufcnt = 0;
623 return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg),
624 length, ctx->dma_addr, count, final);
625 }
626 }
627
628 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
629 dev_err(dd->dev, "dma_map_sg error\n");
630 return -EINVAL;
631 }
632
633 ctx->flags |= SHA_FLAGS_SG;
634
635 /* next call does not fail... so no unmap in the case of error */
636 return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg), length, 0,
637 0, final);
638 }
639
640 static int atmel_sha_update_dma_stop(struct atmel_sha_dev *dd)
641 {
642 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
643
644 if (ctx->flags & SHA_FLAGS_SG) {
645 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
646 if (ctx->sg->length == ctx->offset) {
647 ctx->sg = sg_next(ctx->sg);
648 if (ctx->sg)
649 ctx->offset = 0;
650 }
651 if (ctx->flags & SHA_FLAGS_PAD) {
652 dma_unmap_single(dd->dev, ctx->dma_addr,
653 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
654 }
655 } else {
656 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen +
657 ctx->block_size, DMA_TO_DEVICE);
658 }
659
660 return 0;
661 }
662
663 static int atmel_sha_update_req(struct atmel_sha_dev *dd)
664 {
665 struct ahash_request *req = dd->req;
666 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
667 int err;
668
669 dev_dbg(dd->dev, "update_req: total: %u, digcnt: 0x%llx 0x%llx\n",
670 ctx->total, ctx->digcnt[1], ctx->digcnt[0]);
671
672 if (ctx->flags & SHA_FLAGS_CPU)
673 err = atmel_sha_update_cpu(dd);
674 else
675 err = atmel_sha_update_dma_start(dd);
676
677 /* wait for dma completion before can take more data */
678 dev_dbg(dd->dev, "update: err: %d, digcnt: 0x%llx 0%llx\n",
679 err, ctx->digcnt[1], ctx->digcnt[0]);
680
681 return err;
682 }
683
684 static int atmel_sha_final_req(struct atmel_sha_dev *dd)
685 {
686 struct ahash_request *req = dd->req;
687 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
688 int err = 0;
689 int count;
690
691 if (ctx->bufcnt >= ATMEL_SHA_DMA_THRESHOLD) {
692 atmel_sha_fill_padding(ctx, 0);
693 count = ctx->bufcnt;
694 ctx->bufcnt = 0;
695 err = atmel_sha_xmit_dma_map(dd, ctx, count, 1);
696 }
697 /* faster to handle last block with cpu */
698 else {
699 atmel_sha_fill_padding(ctx, 0);
700 count = ctx->bufcnt;
701 ctx->bufcnt = 0;
702 err = atmel_sha_xmit_cpu(dd, ctx->buffer, count, 1);
703 }
704
705 dev_dbg(dd->dev, "final_req: err: %d\n", err);
706
707 return err;
708 }
709
710 static void atmel_sha_copy_hash(struct ahash_request *req)
711 {
712 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
713 u32 *hash = (u32 *)ctx->digest;
714 int i;
715
716 if (ctx->flags & SHA_FLAGS_SHA1)
717 for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
718 hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
719 else if (ctx->flags & SHA_FLAGS_SHA224)
720 for (i = 0; i < SHA224_DIGEST_SIZE / sizeof(u32); i++)
721 hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
722 else if (ctx->flags & SHA_FLAGS_SHA256)
723 for (i = 0; i < SHA256_DIGEST_SIZE / sizeof(u32); i++)
724 hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
725 else if (ctx->flags & SHA_FLAGS_SHA384)
726 for (i = 0; i < SHA384_DIGEST_SIZE / sizeof(u32); i++)
727 hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
728 else
729 for (i = 0; i < SHA512_DIGEST_SIZE / sizeof(u32); i++)
730 hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
731 }
732
733 static void atmel_sha_copy_ready_hash(struct ahash_request *req)
734 {
735 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
736
737 if (!req->result)
738 return;
739
740 if (ctx->flags & SHA_FLAGS_SHA1)
741 memcpy(req->result, ctx->digest, SHA1_DIGEST_SIZE);
742 else if (ctx->flags & SHA_FLAGS_SHA224)
743 memcpy(req->result, ctx->digest, SHA224_DIGEST_SIZE);
744 else if (ctx->flags & SHA_FLAGS_SHA256)
745 memcpy(req->result, ctx->digest, SHA256_DIGEST_SIZE);
746 else if (ctx->flags & SHA_FLAGS_SHA384)
747 memcpy(req->result, ctx->digest, SHA384_DIGEST_SIZE);
748 else
749 memcpy(req->result, ctx->digest, SHA512_DIGEST_SIZE);
750 }
751
752 static int atmel_sha_finish(struct ahash_request *req)
753 {
754 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
755 struct atmel_sha_dev *dd = ctx->dd;
756 int err = 0;
757
758 if (ctx->digcnt[0] || ctx->digcnt[1])
759 atmel_sha_copy_ready_hash(req);
760
761 dev_dbg(dd->dev, "digcnt: 0x%llx 0x%llx, bufcnt: %d\n", ctx->digcnt[1],
762 ctx->digcnt[0], ctx->bufcnt);
763
764 return err;
765 }
766
767 static void atmel_sha_finish_req(struct ahash_request *req, int err)
768 {
769 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
770 struct atmel_sha_dev *dd = ctx->dd;
771
772 if (!err) {
773 atmel_sha_copy_hash(req);
774 if (SHA_FLAGS_FINAL & dd->flags)
775 err = atmel_sha_finish(req);
776 } else {
777 ctx->flags |= SHA_FLAGS_ERROR;
778 }
779
780 /* atomic operation is not needed here */
781 dd->flags &= ~(SHA_FLAGS_BUSY | SHA_FLAGS_FINAL | SHA_FLAGS_CPU |
782 SHA_FLAGS_DMA_READY | SHA_FLAGS_OUTPUT_READY);
783
784 clk_disable_unprepare(dd->iclk);
785
786 if (req->base.complete)
787 req->base.complete(&req->base, err);
788
789 /* handle new request */
790 tasklet_schedule(&dd->done_task);
791 }
792
793 static int atmel_sha_hw_init(struct atmel_sha_dev *dd)
794 {
795 clk_prepare_enable(dd->iclk);
796
797 if (!(SHA_FLAGS_INIT & dd->flags)) {
798 atmel_sha_write(dd, SHA_CR, SHA_CR_SWRST);
799 dd->flags |= SHA_FLAGS_INIT;
800 dd->err = 0;
801 }
802
803 return 0;
804 }
805
806 static inline unsigned int atmel_sha_get_version(struct atmel_sha_dev *dd)
807 {
808 return atmel_sha_read(dd, SHA_HW_VERSION) & 0x00000fff;
809 }
810
811 static void atmel_sha_hw_version_init(struct atmel_sha_dev *dd)
812 {
813 atmel_sha_hw_init(dd);
814
815 dd->hw_version = atmel_sha_get_version(dd);
816
817 dev_info(dd->dev,
818 "version: 0x%x\n", dd->hw_version);
819
820 clk_disable_unprepare(dd->iclk);
821 }
822
823 static int atmel_sha_handle_queue(struct atmel_sha_dev *dd,
824 struct ahash_request *req)
825 {
826 struct crypto_async_request *async_req, *backlog;
827 struct atmel_sha_reqctx *ctx;
828 unsigned long flags;
829 int err = 0, ret = 0;
830
831 spin_lock_irqsave(&dd->lock, flags);
832 if (req)
833 ret = ahash_enqueue_request(&dd->queue, req);
834
835 if (SHA_FLAGS_BUSY & dd->flags) {
836 spin_unlock_irqrestore(&dd->lock, flags);
837 return ret;
838 }
839
840 backlog = crypto_get_backlog(&dd->queue);
841 async_req = crypto_dequeue_request(&dd->queue);
842 if (async_req)
843 dd->flags |= SHA_FLAGS_BUSY;
844
845 spin_unlock_irqrestore(&dd->lock, flags);
846
847 if (!async_req)
848 return ret;
849
850 if (backlog)
851 backlog->complete(backlog, -EINPROGRESS);
852
853 req = ahash_request_cast(async_req);
854 dd->req = req;
855 ctx = ahash_request_ctx(req);
856
857 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
858 ctx->op, req->nbytes);
859
860 err = atmel_sha_hw_init(dd);
861
862 if (err)
863 goto err1;
864
865 if (ctx->op == SHA_OP_UPDATE) {
866 err = atmel_sha_update_req(dd);
867 if (err != -EINPROGRESS && (ctx->flags & SHA_FLAGS_FINUP))
868 /* no final() after finup() */
869 err = atmel_sha_final_req(dd);
870 } else if (ctx->op == SHA_OP_FINAL) {
871 err = atmel_sha_final_req(dd);
872 }
873
874 err1:
875 if (err != -EINPROGRESS)
876 /* done_task will not finish it, so do it here */
877 atmel_sha_finish_req(req, err);
878
879 dev_dbg(dd->dev, "exit, err: %d\n", err);
880
881 return ret;
882 }
883
884 static int atmel_sha_enqueue(struct ahash_request *req, unsigned int op)
885 {
886 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
887 struct atmel_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
888 struct atmel_sha_dev *dd = tctx->dd;
889
890 ctx->op = op;
891
892 return atmel_sha_handle_queue(dd, req);
893 }
894
895 static int atmel_sha_update(struct ahash_request *req)
896 {
897 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
898
899 if (!req->nbytes)
900 return 0;
901
902 ctx->total = req->nbytes;
903 ctx->sg = req->src;
904 ctx->offset = 0;
905
906 if (ctx->flags & SHA_FLAGS_FINUP) {
907 if (ctx->bufcnt + ctx->total < ATMEL_SHA_DMA_THRESHOLD)
908 /* faster to use CPU for short transfers */
909 ctx->flags |= SHA_FLAGS_CPU;
910 } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
911 atmel_sha_append_sg(ctx);
912 return 0;
913 }
914 return atmel_sha_enqueue(req, SHA_OP_UPDATE);
915 }
916
917 static int atmel_sha_final(struct ahash_request *req)
918 {
919 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
920 struct atmel_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
921 struct atmel_sha_dev *dd = tctx->dd;
922
923 int err = 0;
924
925 ctx->flags |= SHA_FLAGS_FINUP;
926
927 if (ctx->flags & SHA_FLAGS_ERROR)
928 return 0; /* uncompleted hash is not needed */
929
930 if (ctx->bufcnt) {
931 return atmel_sha_enqueue(req, SHA_OP_FINAL);
932 } else if (!(ctx->flags & SHA_FLAGS_PAD)) { /* add padding */
933 err = atmel_sha_hw_init(dd);
934 if (err)
935 goto err1;
936
937 dd->flags |= SHA_FLAGS_BUSY;
938 err = atmel_sha_final_req(dd);
939 } else {
940 /* copy ready hash (+ finalize hmac) */
941 return atmel_sha_finish(req);
942 }
943
944 err1:
945 if (err != -EINPROGRESS)
946 /* done_task will not finish it, so do it here */
947 atmel_sha_finish_req(req, err);
948
949 return err;
950 }
951
952 static int atmel_sha_finup(struct ahash_request *req)
953 {
954 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
955 int err1, err2;
956
957 ctx->flags |= SHA_FLAGS_FINUP;
958
959 err1 = atmel_sha_update(req);
960 if (err1 == -EINPROGRESS ||
961 (err1 == -EBUSY && (ahash_request_flags(req) &
962 CRYPTO_TFM_REQ_MAY_BACKLOG)))
963 return err1;
964
965 /*
966 * final() has to be always called to cleanup resources
967 * even if udpate() failed, except EINPROGRESS
968 */
969 err2 = atmel_sha_final(req);
970
971 return err1 ?: err2;
972 }
973
974 static int atmel_sha_digest(struct ahash_request *req)
975 {
976 return atmel_sha_init(req) ?: atmel_sha_finup(req);
977 }
978
979 static int atmel_sha_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
980 {
981 struct atmel_sha_ctx *tctx = crypto_tfm_ctx(tfm);
982 const char *alg_name = crypto_tfm_alg_name(tfm);
983
984 /* Allocate a fallback and abort if it failed. */
985 tctx->fallback = crypto_alloc_shash(alg_name, 0,
986 CRYPTO_ALG_NEED_FALLBACK);
987 if (IS_ERR(tctx->fallback)) {
988 pr_err("atmel-sha: fallback driver '%s' could not be loaded.\n",
989 alg_name);
990 return PTR_ERR(tctx->fallback);
991 }
992 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
993 sizeof(struct atmel_sha_reqctx) +
994 SHA_BUFFER_LEN + SHA512_BLOCK_SIZE);
995
996 return 0;
997 }
998
999 static int atmel_sha_cra_init(struct crypto_tfm *tfm)
1000 {
1001 return atmel_sha_cra_init_alg(tfm, NULL);
1002 }
1003
1004 static void atmel_sha_cra_exit(struct crypto_tfm *tfm)
1005 {
1006 struct atmel_sha_ctx *tctx = crypto_tfm_ctx(tfm);
1007
1008 crypto_free_shash(tctx->fallback);
1009 tctx->fallback = NULL;
1010 }
1011
1012 static struct ahash_alg sha_1_256_algs[] = {
1013 {
1014 .init = atmel_sha_init,
1015 .update = atmel_sha_update,
1016 .final = atmel_sha_final,
1017 .finup = atmel_sha_finup,
1018 .digest = atmel_sha_digest,
1019 .halg = {
1020 .digestsize = SHA1_DIGEST_SIZE,
1021 .base = {
1022 .cra_name = "sha1",
1023 .cra_driver_name = "atmel-sha1",
1024 .cra_priority = 100,
1025 .cra_flags = CRYPTO_ALG_ASYNC |
1026 CRYPTO_ALG_NEED_FALLBACK,
1027 .cra_blocksize = SHA1_BLOCK_SIZE,
1028 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1029 .cra_alignmask = 0,
1030 .cra_module = THIS_MODULE,
1031 .cra_init = atmel_sha_cra_init,
1032 .cra_exit = atmel_sha_cra_exit,
1033 }
1034 }
1035 },
1036 {
1037 .init = atmel_sha_init,
1038 .update = atmel_sha_update,
1039 .final = atmel_sha_final,
1040 .finup = atmel_sha_finup,
1041 .digest = atmel_sha_digest,
1042 .halg = {
1043 .digestsize = SHA256_DIGEST_SIZE,
1044 .base = {
1045 .cra_name = "sha256",
1046 .cra_driver_name = "atmel-sha256",
1047 .cra_priority = 100,
1048 .cra_flags = CRYPTO_ALG_ASYNC |
1049 CRYPTO_ALG_NEED_FALLBACK,
1050 .cra_blocksize = SHA256_BLOCK_SIZE,
1051 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1052 .cra_alignmask = 0,
1053 .cra_module = THIS_MODULE,
1054 .cra_init = atmel_sha_cra_init,
1055 .cra_exit = atmel_sha_cra_exit,
1056 }
1057 }
1058 },
1059 };
1060
1061 static struct ahash_alg sha_224_alg = {
1062 .init = atmel_sha_init,
1063 .update = atmel_sha_update,
1064 .final = atmel_sha_final,
1065 .finup = atmel_sha_finup,
1066 .digest = atmel_sha_digest,
1067 .halg = {
1068 .digestsize = SHA224_DIGEST_SIZE,
1069 .base = {
1070 .cra_name = "sha224",
1071 .cra_driver_name = "atmel-sha224",
1072 .cra_priority = 100,
1073 .cra_flags = CRYPTO_ALG_ASYNC |
1074 CRYPTO_ALG_NEED_FALLBACK,
1075 .cra_blocksize = SHA224_BLOCK_SIZE,
1076 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1077 .cra_alignmask = 0,
1078 .cra_module = THIS_MODULE,
1079 .cra_init = atmel_sha_cra_init,
1080 .cra_exit = atmel_sha_cra_exit,
1081 }
1082 }
1083 };
1084
1085 static struct ahash_alg sha_384_512_algs[] = {
1086 {
1087 .init = atmel_sha_init,
1088 .update = atmel_sha_update,
1089 .final = atmel_sha_final,
1090 .finup = atmel_sha_finup,
1091 .digest = atmel_sha_digest,
1092 .halg = {
1093 .digestsize = SHA384_DIGEST_SIZE,
1094 .base = {
1095 .cra_name = "sha384",
1096 .cra_driver_name = "atmel-sha384",
1097 .cra_priority = 100,
1098 .cra_flags = CRYPTO_ALG_ASYNC |
1099 CRYPTO_ALG_NEED_FALLBACK,
1100 .cra_blocksize = SHA384_BLOCK_SIZE,
1101 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1102 .cra_alignmask = 0x3,
1103 .cra_module = THIS_MODULE,
1104 .cra_init = atmel_sha_cra_init,
1105 .cra_exit = atmel_sha_cra_exit,
1106 }
1107 }
1108 },
1109 {
1110 .init = atmel_sha_init,
1111 .update = atmel_sha_update,
1112 .final = atmel_sha_final,
1113 .finup = atmel_sha_finup,
1114 .digest = atmel_sha_digest,
1115 .halg = {
1116 .digestsize = SHA512_DIGEST_SIZE,
1117 .base = {
1118 .cra_name = "sha512",
1119 .cra_driver_name = "atmel-sha512",
1120 .cra_priority = 100,
1121 .cra_flags = CRYPTO_ALG_ASYNC |
1122 CRYPTO_ALG_NEED_FALLBACK,
1123 .cra_blocksize = SHA512_BLOCK_SIZE,
1124 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1125 .cra_alignmask = 0x3,
1126 .cra_module = THIS_MODULE,
1127 .cra_init = atmel_sha_cra_init,
1128 .cra_exit = atmel_sha_cra_exit,
1129 }
1130 }
1131 },
1132 };
1133
1134 static void atmel_sha_done_task(unsigned long data)
1135 {
1136 struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data;
1137 int err = 0;
1138
1139 if (!(SHA_FLAGS_BUSY & dd->flags)) {
1140 atmel_sha_handle_queue(dd, NULL);
1141 return;
1142 }
1143
1144 if (SHA_FLAGS_CPU & dd->flags) {
1145 if (SHA_FLAGS_OUTPUT_READY & dd->flags) {
1146 dd->flags &= ~SHA_FLAGS_OUTPUT_READY;
1147 goto finish;
1148 }
1149 } else if (SHA_FLAGS_DMA_READY & dd->flags) {
1150 if (SHA_FLAGS_DMA_ACTIVE & dd->flags) {
1151 dd->flags &= ~SHA_FLAGS_DMA_ACTIVE;
1152 atmel_sha_update_dma_stop(dd);
1153 if (dd->err) {
1154 err = dd->err;
1155 goto finish;
1156 }
1157 }
1158 if (SHA_FLAGS_OUTPUT_READY & dd->flags) {
1159 /* hash or semi-hash ready */
1160 dd->flags &= ~(SHA_FLAGS_DMA_READY |
1161 SHA_FLAGS_OUTPUT_READY);
1162 err = atmel_sha_update_dma_start(dd);
1163 if (err != -EINPROGRESS)
1164 goto finish;
1165 }
1166 }
1167 return;
1168
1169 finish:
1170 /* finish curent request */
1171 atmel_sha_finish_req(dd->req, err);
1172 }
1173
1174 static irqreturn_t atmel_sha_irq(int irq, void *dev_id)
1175 {
1176 struct atmel_sha_dev *sha_dd = dev_id;
1177 u32 reg;
1178
1179 reg = atmel_sha_read(sha_dd, SHA_ISR);
1180 if (reg & atmel_sha_read(sha_dd, SHA_IMR)) {
1181 atmel_sha_write(sha_dd, SHA_IDR, reg);
1182 if (SHA_FLAGS_BUSY & sha_dd->flags) {
1183 sha_dd->flags |= SHA_FLAGS_OUTPUT_READY;
1184 if (!(SHA_FLAGS_CPU & sha_dd->flags))
1185 sha_dd->flags |= SHA_FLAGS_DMA_READY;
1186 tasklet_schedule(&sha_dd->done_task);
1187 } else {
1188 dev_warn(sha_dd->dev, "SHA interrupt when no active requests.\n");
1189 }
1190 return IRQ_HANDLED;
1191 }
1192
1193 return IRQ_NONE;
1194 }
1195
1196 static void atmel_sha_unregister_algs(struct atmel_sha_dev *dd)
1197 {
1198 int i;
1199
1200 for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++)
1201 crypto_unregister_ahash(&sha_1_256_algs[i]);
1202
1203 if (dd->caps.has_sha224)
1204 crypto_unregister_ahash(&sha_224_alg);
1205
1206 if (dd->caps.has_sha_384_512) {
1207 for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++)
1208 crypto_unregister_ahash(&sha_384_512_algs[i]);
1209 }
1210 }
1211
1212 static int atmel_sha_register_algs(struct atmel_sha_dev *dd)
1213 {
1214 int err, i, j;
1215
1216 for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) {
1217 err = crypto_register_ahash(&sha_1_256_algs[i]);
1218 if (err)
1219 goto err_sha_1_256_algs;
1220 }
1221
1222 if (dd->caps.has_sha224) {
1223 err = crypto_register_ahash(&sha_224_alg);
1224 if (err)
1225 goto err_sha_224_algs;
1226 }
1227
1228 if (dd->caps.has_sha_384_512) {
1229 for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) {
1230 err = crypto_register_ahash(&sha_384_512_algs[i]);
1231 if (err)
1232 goto err_sha_384_512_algs;
1233 }
1234 }
1235
1236 return 0;
1237
1238 err_sha_384_512_algs:
1239 for (j = 0; j < i; j++)
1240 crypto_unregister_ahash(&sha_384_512_algs[j]);
1241 crypto_unregister_ahash(&sha_224_alg);
1242 err_sha_224_algs:
1243 i = ARRAY_SIZE(sha_1_256_algs);
1244 err_sha_1_256_algs:
1245 for (j = 0; j < i; j++)
1246 crypto_unregister_ahash(&sha_1_256_algs[j]);
1247
1248 return err;
1249 }
1250
1251 static bool atmel_sha_filter(struct dma_chan *chan, void *slave)
1252 {
1253 struct at_dma_slave *sl = slave;
1254
1255 if (sl && sl->dma_dev == chan->device->dev) {
1256 chan->private = sl;
1257 return true;
1258 } else {
1259 return false;
1260 }
1261 }
1262
1263 static int atmel_sha_dma_init(struct atmel_sha_dev *dd,
1264 struct crypto_platform_data *pdata)
1265 {
1266 int err = -ENOMEM;
1267 dma_cap_mask_t mask_in;
1268
1269 /* Try to grab DMA channel */
1270 dma_cap_zero(mask_in);
1271 dma_cap_set(DMA_SLAVE, mask_in);
1272
1273 dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask_in,
1274 atmel_sha_filter, &pdata->dma_slave->rxdata, dd->dev, "tx");
1275 if (!dd->dma_lch_in.chan) {
1276 dev_warn(dd->dev, "no DMA channel available\n");
1277 return err;
1278 }
1279
1280 dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV;
1281 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
1282 SHA_REG_DIN(0);
1283 dd->dma_lch_in.dma_conf.src_maxburst = 1;
1284 dd->dma_lch_in.dma_conf.src_addr_width =
1285 DMA_SLAVE_BUSWIDTH_4_BYTES;
1286 dd->dma_lch_in.dma_conf.dst_maxburst = 1;
1287 dd->dma_lch_in.dma_conf.dst_addr_width =
1288 DMA_SLAVE_BUSWIDTH_4_BYTES;
1289 dd->dma_lch_in.dma_conf.device_fc = false;
1290
1291 return 0;
1292 }
1293
1294 static void atmel_sha_dma_cleanup(struct atmel_sha_dev *dd)
1295 {
1296 dma_release_channel(dd->dma_lch_in.chan);
1297 }
1298
1299 static void atmel_sha_get_cap(struct atmel_sha_dev *dd)
1300 {
1301
1302 dd->caps.has_dma = 0;
1303 dd->caps.has_dualbuff = 0;
1304 dd->caps.has_sha224 = 0;
1305 dd->caps.has_sha_384_512 = 0;
1306
1307 /* keep only major version number */
1308 switch (dd->hw_version & 0xff0) {
1309 case 0x410:
1310 dd->caps.has_dma = 1;
1311 dd->caps.has_dualbuff = 1;
1312 dd->caps.has_sha224 = 1;
1313 dd->caps.has_sha_384_512 = 1;
1314 break;
1315 case 0x400:
1316 dd->caps.has_dma = 1;
1317 dd->caps.has_dualbuff = 1;
1318 dd->caps.has_sha224 = 1;
1319 break;
1320 case 0x320:
1321 break;
1322 default:
1323 dev_warn(dd->dev,
1324 "Unmanaged sha version, set minimum capabilities\n");
1325 break;
1326 }
1327 }
1328
1329 #if defined(CONFIG_OF)
1330 static const struct of_device_id atmel_sha_dt_ids[] = {
1331 { .compatible = "atmel,at91sam9g46-sha" },
1332 { /* sentinel */ }
1333 };
1334
1335 MODULE_DEVICE_TABLE(of, atmel_sha_dt_ids);
1336
1337 static struct crypto_platform_data *atmel_sha_of_init(struct platform_device *pdev)
1338 {
1339 struct device_node *np = pdev->dev.of_node;
1340 struct crypto_platform_data *pdata;
1341
1342 if (!np) {
1343 dev_err(&pdev->dev, "device node not found\n");
1344 return ERR_PTR(-EINVAL);
1345 }
1346
1347 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1348 if (!pdata) {
1349 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
1350 return ERR_PTR(-ENOMEM);
1351 }
1352
1353 pdata->dma_slave = devm_kzalloc(&pdev->dev,
1354 sizeof(*(pdata->dma_slave)),
1355 GFP_KERNEL);
1356 if (!pdata->dma_slave) {
1357 dev_err(&pdev->dev, "could not allocate memory for dma_slave\n");
1358 return ERR_PTR(-ENOMEM);
1359 }
1360
1361 return pdata;
1362 }
1363 #else /* CONFIG_OF */
1364 static inline struct crypto_platform_data *atmel_sha_of_init(struct platform_device *dev)
1365 {
1366 return ERR_PTR(-EINVAL);
1367 }
1368 #endif
1369
1370 static int atmel_sha_probe(struct platform_device *pdev)
1371 {
1372 struct atmel_sha_dev *sha_dd;
1373 struct crypto_platform_data *pdata;
1374 struct device *dev = &pdev->dev;
1375 struct resource *sha_res;
1376 unsigned long sha_phys_size;
1377 int err;
1378
1379 sha_dd = devm_kzalloc(&pdev->dev, sizeof(struct atmel_sha_dev),
1380 GFP_KERNEL);
1381 if (sha_dd == NULL) {
1382 dev_err(dev, "unable to alloc data struct.\n");
1383 err = -ENOMEM;
1384 goto sha_dd_err;
1385 }
1386
1387 sha_dd->dev = dev;
1388
1389 platform_set_drvdata(pdev, sha_dd);
1390
1391 INIT_LIST_HEAD(&sha_dd->list);
1392
1393 tasklet_init(&sha_dd->done_task, atmel_sha_done_task,
1394 (unsigned long)sha_dd);
1395
1396 crypto_init_queue(&sha_dd->queue, ATMEL_SHA_QUEUE_LENGTH);
1397
1398 sha_dd->irq = -1;
1399
1400 /* Get the base address */
1401 sha_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1402 if (!sha_res) {
1403 dev_err(dev, "no MEM resource info\n");
1404 err = -ENODEV;
1405 goto res_err;
1406 }
1407 sha_dd->phys_base = sha_res->start;
1408 sha_phys_size = resource_size(sha_res);
1409
1410 /* Get the IRQ */
1411 sha_dd->irq = platform_get_irq(pdev, 0);
1412 if (sha_dd->irq < 0) {
1413 dev_err(dev, "no IRQ resource info\n");
1414 err = sha_dd->irq;
1415 goto res_err;
1416 }
1417
1418 err = request_irq(sha_dd->irq, atmel_sha_irq, IRQF_SHARED, "atmel-sha",
1419 sha_dd);
1420 if (err) {
1421 dev_err(dev, "unable to request sha irq.\n");
1422 goto res_err;
1423 }
1424
1425 /* Initializing the clock */
1426 sha_dd->iclk = clk_get(&pdev->dev, "sha_clk");
1427 if (IS_ERR(sha_dd->iclk)) {
1428 dev_err(dev, "clock intialization failed.\n");
1429 err = PTR_ERR(sha_dd->iclk);
1430 goto clk_err;
1431 }
1432
1433 sha_dd->io_base = ioremap(sha_dd->phys_base, sha_phys_size);
1434 if (!sha_dd->io_base) {
1435 dev_err(dev, "can't ioremap\n");
1436 err = -ENOMEM;
1437 goto sha_io_err;
1438 }
1439
1440 atmel_sha_hw_version_init(sha_dd);
1441
1442 atmel_sha_get_cap(sha_dd);
1443
1444 if (sha_dd->caps.has_dma) {
1445 pdata = pdev->dev.platform_data;
1446 if (!pdata) {
1447 pdata = atmel_sha_of_init(pdev);
1448 if (IS_ERR(pdata)) {
1449 dev_err(&pdev->dev, "platform data not available\n");
1450 err = PTR_ERR(pdata);
1451 goto err_pdata;
1452 }
1453 }
1454 if (!pdata->dma_slave) {
1455 err = -ENXIO;
1456 goto err_pdata;
1457 }
1458 err = atmel_sha_dma_init(sha_dd, pdata);
1459 if (err)
1460 goto err_sha_dma;
1461
1462 dev_info(dev, "using %s for DMA transfers\n",
1463 dma_chan_name(sha_dd->dma_lch_in.chan));
1464 }
1465
1466 spin_lock(&atmel_sha.lock);
1467 list_add_tail(&sha_dd->list, &atmel_sha.dev_list);
1468 spin_unlock(&atmel_sha.lock);
1469
1470 err = atmel_sha_register_algs(sha_dd);
1471 if (err)
1472 goto err_algs;
1473
1474 dev_info(dev, "Atmel SHA1/SHA256%s%s\n",
1475 sha_dd->caps.has_sha224 ? "/SHA224" : "",
1476 sha_dd->caps.has_sha_384_512 ? "/SHA384/SHA512" : "");
1477
1478 return 0;
1479
1480 err_algs:
1481 spin_lock(&atmel_sha.lock);
1482 list_del(&sha_dd->list);
1483 spin_unlock(&atmel_sha.lock);
1484 if (sha_dd->caps.has_dma)
1485 atmel_sha_dma_cleanup(sha_dd);
1486 err_sha_dma:
1487 err_pdata:
1488 iounmap(sha_dd->io_base);
1489 sha_io_err:
1490 clk_put(sha_dd->iclk);
1491 clk_err:
1492 free_irq(sha_dd->irq, sha_dd);
1493 res_err:
1494 tasklet_kill(&sha_dd->done_task);
1495 sha_dd_err:
1496 dev_err(dev, "initialization failed.\n");
1497
1498 return err;
1499 }
1500
1501 static int atmel_sha_remove(struct platform_device *pdev)
1502 {
1503 static struct atmel_sha_dev *sha_dd;
1504
1505 sha_dd = platform_get_drvdata(pdev);
1506 if (!sha_dd)
1507 return -ENODEV;
1508 spin_lock(&atmel_sha.lock);
1509 list_del(&sha_dd->list);
1510 spin_unlock(&atmel_sha.lock);
1511
1512 atmel_sha_unregister_algs(sha_dd);
1513
1514 tasklet_kill(&sha_dd->done_task);
1515
1516 if (sha_dd->caps.has_dma)
1517 atmel_sha_dma_cleanup(sha_dd);
1518
1519 iounmap(sha_dd->io_base);
1520
1521 clk_put(sha_dd->iclk);
1522
1523 if (sha_dd->irq >= 0)
1524 free_irq(sha_dd->irq, sha_dd);
1525
1526 return 0;
1527 }
1528
1529 static struct platform_driver atmel_sha_driver = {
1530 .probe = atmel_sha_probe,
1531 .remove = atmel_sha_remove,
1532 .driver = {
1533 .name = "atmel_sha",
1534 .owner = THIS_MODULE,
1535 .of_match_table = of_match_ptr(atmel_sha_dt_ids),
1536 },
1537 };
1538
1539 module_platform_driver(atmel_sha_driver);
1540
1541 MODULE_DESCRIPTION("Atmel SHA (1/256/224/384/512) hw acceleration support.");
1542 MODULE_LICENSE("GPL v2");
1543 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");
Linux with added FPC-III support