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Linux 3.18.86
[linux/fpc-iii.git] / drivers / net / ethernet / mellanox / mlx4 / cmd.c
blob2a6b149d7da39af04ba4a01b37352387b1cc3e13
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
40
41 #include <linux/mlx4/cmd.h>
42 #include <linux/mlx4/device.h>
43 #include <linux/semaphore.h>
44 #include <rdma/ib_smi.h>
45
46 #include <asm/io.h>
47
48 #include "mlx4.h"
49 #include "fw.h"
50
51 #define CMD_POLL_TOKEN 0xffff
52 #define INBOX_MASK 0xffffffffffffff00ULL
53
54 #define CMD_CHAN_VER 1
55 #define CMD_CHAN_IF_REV 1
56
57 enum {
58 /* command completed successfully: */
59 CMD_STAT_OK = 0x00,
60 /* Internal error (such as a bus error) occurred while processing command: */
61 CMD_STAT_INTERNAL_ERR = 0x01,
62 /* Operation/command not supported or opcode modifier not supported: */
63 CMD_STAT_BAD_OP = 0x02,
64 /* Parameter not supported or parameter out of range: */
65 CMD_STAT_BAD_PARAM = 0x03,
66 /* System not enabled or bad system state: */
67 CMD_STAT_BAD_SYS_STATE = 0x04,
68 /* Attempt to access reserved or unallocaterd resource: */
69 CMD_STAT_BAD_RESOURCE = 0x05,
70 /* Requested resource is currently executing a command, or is otherwise busy: */
71 CMD_STAT_RESOURCE_BUSY = 0x06,
72 /* Required capability exceeds device limits: */
73 CMD_STAT_EXCEED_LIM = 0x08,
74 /* Resource is not in the appropriate state or ownership: */
75 CMD_STAT_BAD_RES_STATE = 0x09,
76 /* Index out of range: */
77 CMD_STAT_BAD_INDEX = 0x0a,
78 /* FW image corrupted: */
79 CMD_STAT_BAD_NVMEM = 0x0b,
80 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
81 CMD_STAT_ICM_ERROR = 0x0c,
82 /* Attempt to modify a QP/EE which is not in the presumed state: */
83 CMD_STAT_BAD_QP_STATE = 0x10,
84 /* Bad segment parameters (Address/Size): */
85 CMD_STAT_BAD_SEG_PARAM = 0x20,
86 /* Memory Region has Memory Windows bound to: */
87 CMD_STAT_REG_BOUND = 0x21,
88 /* HCA local attached memory not present: */
89 CMD_STAT_LAM_NOT_PRE = 0x22,
90 /* Bad management packet (silently discarded): */
91 CMD_STAT_BAD_PKT = 0x30,
92 /* More outstanding CQEs in CQ than new CQ size: */
93 CMD_STAT_BAD_SIZE = 0x40,
94 /* Multi Function device support required: */
95 CMD_STAT_MULTI_FUNC_REQ = 0x50,
96 };
97
98 enum {
99 HCR_IN_PARAM_OFFSET = 0x00,
100 HCR_IN_MODIFIER_OFFSET = 0x08,
101 HCR_OUT_PARAM_OFFSET = 0x0c,
102 HCR_TOKEN_OFFSET = 0x14,
103 HCR_STATUS_OFFSET = 0x18,
104
105 HCR_OPMOD_SHIFT = 12,
106 HCR_T_BIT = 21,
107 HCR_E_BIT = 22,
108 HCR_GO_BIT = 23
109 };
110
111 enum {
112 GO_BIT_TIMEOUT_MSECS = 10000
113 };
114
115 enum mlx4_vlan_transition {
116 MLX4_VLAN_TRANSITION_VST_VST = 0,
117 MLX4_VLAN_TRANSITION_VST_VGT = 1,
118 MLX4_VLAN_TRANSITION_VGT_VST = 2,
119 MLX4_VLAN_TRANSITION_VGT_VGT = 3,
120 };
121
122
123 struct mlx4_cmd_context {
124 struct completion done;
125 int result;
126 int next;
127 u64 out_param;
128 u16 token;
129 u8 fw_status;
130 };
131
132 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
133 struct mlx4_vhcr_cmd *in_vhcr);
134
135 static int mlx4_status_to_errno(u8 status)
136 {
137 static const int trans_table[] = {
138 [CMD_STAT_INTERNAL_ERR] = -EIO,
139 [CMD_STAT_BAD_OP] = -EPERM,
140 [CMD_STAT_BAD_PARAM] = -EINVAL,
141 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
142 [CMD_STAT_BAD_RESOURCE] = -EBADF,
143 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
144 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
145 [CMD_STAT_BAD_RES_STATE] = -EBADF,
146 [CMD_STAT_BAD_INDEX] = -EBADF,
147 [CMD_STAT_BAD_NVMEM] = -EFAULT,
148 [CMD_STAT_ICM_ERROR] = -ENFILE,
149 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
150 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
151 [CMD_STAT_REG_BOUND] = -EBUSY,
152 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
153 [CMD_STAT_BAD_PKT] = -EINVAL,
154 [CMD_STAT_BAD_SIZE] = -ENOMEM,
155 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
156 };
157
158 if (status >= ARRAY_SIZE(trans_table) ||
159 (status != CMD_STAT_OK && trans_table[status] == 0))
160 return -EIO;
161
162 return trans_table[status];
163 }
164
165 static u8 mlx4_errno_to_status(int errno)
166 {
167 switch (errno) {
168 case -EPERM:
169 return CMD_STAT_BAD_OP;
170 case -EINVAL:
171 return CMD_STAT_BAD_PARAM;
172 case -ENXIO:
173 return CMD_STAT_BAD_SYS_STATE;
174 case -EBUSY:
175 return CMD_STAT_RESOURCE_BUSY;
176 case -ENOMEM:
177 return CMD_STAT_EXCEED_LIM;
178 case -ENFILE:
179 return CMD_STAT_ICM_ERROR;
180 default:
181 return CMD_STAT_INTERNAL_ERR;
182 }
183 }
184
185 static int comm_pending(struct mlx4_dev *dev)
186 {
187 struct mlx4_priv *priv = mlx4_priv(dev);
188 u32 status = readl(&priv->mfunc.comm->slave_read);
189
190 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
191 }
192
193 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
194 {
195 struct mlx4_priv *priv = mlx4_priv(dev);
196 u32 val;
197
198 priv->cmd.comm_toggle ^= 1;
199 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
200 __raw_writel((__force u32) cpu_to_be32(val),
201 &priv->mfunc.comm->slave_write);
202 mmiowb();
203 }
204
205 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
206 unsigned long timeout)
207 {
208 struct mlx4_priv *priv = mlx4_priv(dev);
209 unsigned long end;
210 int err = 0;
211 int ret_from_pending = 0;
212
213 /* First, verify that the master reports correct status */
214 if (comm_pending(dev)) {
215 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
216 priv->cmd.comm_toggle, cmd);
217 return -EAGAIN;
218 }
219
220 /* Write command */
221 down(&priv->cmd.poll_sem);
222 mlx4_comm_cmd_post(dev, cmd, param);
223
224 end = msecs_to_jiffies(timeout) + jiffies;
225 while (comm_pending(dev) && time_before(jiffies, end))
226 cond_resched();
227 ret_from_pending = comm_pending(dev);
228 if (ret_from_pending) {
229 /* check if the slave is trying to boot in the middle of
230 * FLR process. The only non-zero result in the RESET command
231 * is MLX4_DELAY_RESET_SLAVE*/
232 if ((MLX4_COMM_CMD_RESET == cmd)) {
233 err = MLX4_DELAY_RESET_SLAVE;
234 } else {
235 mlx4_warn(dev, "Communication channel timed out\n");
236 err = -ETIMEDOUT;
237 }
238 }
239
240 up(&priv->cmd.poll_sem);
241 return err;
242 }
243
244 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
245 u16 param, unsigned long timeout)
246 {
247 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
248 struct mlx4_cmd_context *context;
249 unsigned long end;
250 int err = 0;
251
252 down(&cmd->event_sem);
253
254 spin_lock(&cmd->context_lock);
255 BUG_ON(cmd->free_head < 0);
256 context = &cmd->context[cmd->free_head];
257 context->token += cmd->token_mask + 1;
258 cmd->free_head = context->next;
259 spin_unlock(&cmd->context_lock);
260
261 init_completion(&context->done);
262
263 mlx4_comm_cmd_post(dev, op, param);
264
265 if (!wait_for_completion_timeout(&context->done,
266 msecs_to_jiffies(timeout))) {
267 mlx4_warn(dev, "communication channel command 0x%x timed out\n",
268 op);
269 err = -EBUSY;
270 goto out;
271 }
272
273 err = context->result;
274 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
275 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
276 op, context->fw_status);
277 goto out;
278 }
279
280 out:
281 /* wait for comm channel ready
282 * this is necessary for prevention the race
283 * when switching between event to polling mode
284 */
285 end = msecs_to_jiffies(timeout) + jiffies;
286 while (comm_pending(dev) && time_before(jiffies, end))
287 cond_resched();
288
289 spin_lock(&cmd->context_lock);
290 context->next = cmd->free_head;
291 cmd->free_head = context - cmd->context;
292 spin_unlock(&cmd->context_lock);
293
294 up(&cmd->event_sem);
295 return err;
296 }
297
298 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
299 unsigned long timeout)
300 {
301 if (mlx4_priv(dev)->cmd.use_events)
302 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
303 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
304 }
305
306 static int cmd_pending(struct mlx4_dev *dev)
307 {
308 u32 status;
309
310 if (pci_channel_offline(dev->pdev))
311 return -EIO;
312
313 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
314
315 return (status & swab32(1 << HCR_GO_BIT)) ||
316 (mlx4_priv(dev)->cmd.toggle ==
317 !!(status & swab32(1 << HCR_T_BIT)));
318 }
319
320 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
321 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
322 int event)
323 {
324 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
325 u32 __iomem *hcr = cmd->hcr;
326 int ret = -EAGAIN;
327 unsigned long end;
328
329 mutex_lock(&cmd->hcr_mutex);
330
331 if (pci_channel_offline(dev->pdev)) {
332 /*
333 * Device is going through error recovery
334 * and cannot accept commands.
335 */
336 ret = -EIO;
337 goto out;
338 }
339
340 end = jiffies;
341 if (event)
342 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
343
344 while (cmd_pending(dev)) {
345 if (pci_channel_offline(dev->pdev)) {
346 /*
347 * Device is going through error recovery
348 * and cannot accept commands.
349 */
350 ret = -EIO;
351 goto out;
352 }
353
354 if (time_after_eq(jiffies, end)) {
355 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
356 goto out;
357 }
358 cond_resched();
359 }
360
361 /*
362 * We use writel (instead of something like memcpy_toio)
363 * because writes of less than 32 bits to the HCR don't work
364 * (and some architectures such as ia64 implement memcpy_toio
365 * in terms of writeb).
366 */
367 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
368 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
369 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
370 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
371 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
372 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
373
374 /* __raw_writel may not order writes. */
375 wmb();
376
377 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
378 (cmd->toggle << HCR_T_BIT) |
379 (event ? (1 << HCR_E_BIT) : 0) |
380 (op_modifier << HCR_OPMOD_SHIFT) |
381 op), hcr + 6);
382
383 /*
384 * Make sure that our HCR writes don't get mixed in with
385 * writes from another CPU starting a FW command.
386 */
387 mmiowb();
388
389 cmd->toggle = cmd->toggle ^ 1;
390
391 ret = 0;
392
393 out:
394 mutex_unlock(&cmd->hcr_mutex);
395 return ret;
396 }
397
398 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
399 int out_is_imm, u32 in_modifier, u8 op_modifier,
400 u16 op, unsigned long timeout)
401 {
402 struct mlx4_priv *priv = mlx4_priv(dev);
403 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
404 int ret;
405
406 mutex_lock(&priv->cmd.slave_cmd_mutex);
407
408 vhcr->in_param = cpu_to_be64(in_param);
409 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
410 vhcr->in_modifier = cpu_to_be32(in_modifier);
411 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
412 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
413 vhcr->status = 0;
414 vhcr->flags = !!(priv->cmd.use_events) << 6;
415
416 if (mlx4_is_master(dev)) {
417 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
418 if (!ret) {
419 if (out_is_imm) {
420 if (out_param)
421 *out_param =
422 be64_to_cpu(vhcr->out_param);
423 else {
424 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
425 op);
426 vhcr->status = CMD_STAT_BAD_PARAM;
427 }
428 }
429 ret = mlx4_status_to_errno(vhcr->status);
430 }
431 } else {
432 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
433 MLX4_COMM_TIME + timeout);
434 if (!ret) {
435 if (out_is_imm) {
436 if (out_param)
437 *out_param =
438 be64_to_cpu(vhcr->out_param);
439 else {
440 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
441 op);
442 vhcr->status = CMD_STAT_BAD_PARAM;
443 }
444 }
445 ret = mlx4_status_to_errno(vhcr->status);
446 } else
447 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n",
448 op);
449 }
450
451 mutex_unlock(&priv->cmd.slave_cmd_mutex);
452 return ret;
453 }
454
455 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
456 int out_is_imm, u32 in_modifier, u8 op_modifier,
457 u16 op, unsigned long timeout)
458 {
459 struct mlx4_priv *priv = mlx4_priv(dev);
460 void __iomem *hcr = priv->cmd.hcr;
461 int err = 0;
462 unsigned long end;
463 u32 stat;
464
465 down(&priv->cmd.poll_sem);
466
467 if (pci_channel_offline(dev->pdev)) {
468 /*
469 * Device is going through error recovery
470 * and cannot accept commands.
471 */
472 err = -EIO;
473 goto out;
474 }
475
476 if (out_is_imm && !out_param) {
477 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
478 op);
479 err = -EINVAL;
480 goto out;
481 }
482
483 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
484 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
485 if (err)
486 goto out;
487
488 end = msecs_to_jiffies(timeout) + jiffies;
489 while (cmd_pending(dev) && time_before(jiffies, end)) {
490 if (pci_channel_offline(dev->pdev)) {
491 /*
492 * Device is going through error recovery
493 * and cannot accept commands.
494 */
495 err = -EIO;
496 goto out;
497 }
498
499 cond_resched();
500 }
501
502 if (cmd_pending(dev)) {
503 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
504 op);
505 err = -ETIMEDOUT;
506 goto out;
507 }
508
509 if (out_is_imm)
510 *out_param =
511 (u64) be32_to_cpu((__force __be32)
512 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
513 (u64) be32_to_cpu((__force __be32)
514 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
515 stat = be32_to_cpu((__force __be32)
516 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
517 err = mlx4_status_to_errno(stat);
518 if (err)
519 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
520 op, stat);
521
522 out:
523 up(&priv->cmd.poll_sem);
524 return err;
525 }
526
527 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
528 {
529 struct mlx4_priv *priv = mlx4_priv(dev);
530 struct mlx4_cmd_context *context =
531 &priv->cmd.context[token & priv->cmd.token_mask];
532
533 /* previously timed out command completing at long last */
534 if (token != context->token)
535 return;
536
537 context->fw_status = status;
538 context->result = mlx4_status_to_errno(status);
539 context->out_param = out_param;
540
541 complete(&context->done);
542 }
543
544 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
545 int out_is_imm, u32 in_modifier, u8 op_modifier,
546 u16 op, unsigned long timeout)
547 {
548 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
549 struct mlx4_cmd_context *context;
550 int err = 0;
551
552 down(&cmd->event_sem);
553
554 spin_lock(&cmd->context_lock);
555 BUG_ON(cmd->free_head < 0);
556 context = &cmd->context[cmd->free_head];
557 context->token += cmd->token_mask + 1;
558 cmd->free_head = context->next;
559 spin_unlock(&cmd->context_lock);
560
561 if (out_is_imm && !out_param) {
562 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
563 op);
564 err = -EINVAL;
565 goto out;
566 }
567
568 init_completion(&context->done);
569
570 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
571 in_modifier, op_modifier, op, context->token, 1);
572
573 if (!wait_for_completion_timeout(&context->done,
574 msecs_to_jiffies(timeout))) {
575 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
576 op);
577 err = -EBUSY;
578 goto out;
579 }
580
581 err = context->result;
582 if (err) {
583 /* Since we do not want to have this error message always
584 * displayed at driver start when there are ConnectX2 HCAs
585 * on the host, we deprecate the error message for this
586 * specific command/input_mod/opcode_mod/fw-status to be debug.
587 */
588 if (op == MLX4_CMD_SET_PORT &&
589 (in_modifier == 1 || in_modifier == 2) &&
590 op_modifier == 0 && context->fw_status == CMD_STAT_BAD_SIZE)
591 mlx4_dbg(dev, "command 0x%x failed: fw status = 0x%x\n",
592 op, context->fw_status);
593 else
594 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
595 op, context->fw_status);
596 goto out;
597 }
598
599 if (out_is_imm)
600 *out_param = context->out_param;
601
602 out:
603 spin_lock(&cmd->context_lock);
604 context->next = cmd->free_head;
605 cmd->free_head = context - cmd->context;
606 spin_unlock(&cmd->context_lock);
607
608 up(&cmd->event_sem);
609 return err;
610 }
611
612 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
613 int out_is_imm, u32 in_modifier, u8 op_modifier,
614 u16 op, unsigned long timeout, int native)
615 {
616 if (pci_channel_offline(dev->pdev))
617 return -EIO;
618
619 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
620 if (mlx4_priv(dev)->cmd.use_events)
621 return mlx4_cmd_wait(dev, in_param, out_param,
622 out_is_imm, in_modifier,
623 op_modifier, op, timeout);
624 else
625 return mlx4_cmd_poll(dev, in_param, out_param,
626 out_is_imm, in_modifier,
627 op_modifier, op, timeout);
628 }
629 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
630 in_modifier, op_modifier, op, timeout);
631 }
632 EXPORT_SYMBOL_GPL(__mlx4_cmd);
633
634
635 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
636 {
637 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
638 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
639 }
640
641 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
642 int slave, u64 slave_addr,
643 int size, int is_read)
644 {
645 u64 in_param;
646 u64 out_param;
647
648 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
649 (slave & ~0x7f) | (size & 0xff)) {
650 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
651 slave_addr, master_addr, slave, size);
652 return -EINVAL;
653 }
654
655 if (is_read) {
656 in_param = (u64) slave | slave_addr;
657 out_param = (u64) dev->caps.function | master_addr;
658 } else {
659 in_param = (u64) dev->caps.function | master_addr;
660 out_param = (u64) slave | slave_addr;
661 }
662
663 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
664 MLX4_CMD_ACCESS_MEM,
665 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
666 }
667
668 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
669 struct mlx4_cmd_mailbox *inbox,
670 struct mlx4_cmd_mailbox *outbox)
671 {
672 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
673 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
674 int err;
675 int i;
676
677 if (index & 0x1f)
678 return -EINVAL;
679
680 in_mad->attr_mod = cpu_to_be32(index / 32);
681
682 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
683 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
684 MLX4_CMD_NATIVE);
685 if (err)
686 return err;
687
688 for (i = 0; i < 32; ++i)
689 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
690
691 return err;
692 }
693
694 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
695 struct mlx4_cmd_mailbox *inbox,
696 struct mlx4_cmd_mailbox *outbox)
697 {
698 int i;
699 int err;
700
701 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
702 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
703 if (err)
704 return err;
705 }
706
707 return 0;
708 }
709 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
710 #define PORT_STATE_OFFSET 32
711
712 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
713 {
714 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
715 return IB_PORT_ACTIVE;
716 else
717 return IB_PORT_DOWN;
718 }
719
720 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
721 struct mlx4_vhcr *vhcr,
722 struct mlx4_cmd_mailbox *inbox,
723 struct mlx4_cmd_mailbox *outbox,
724 struct mlx4_cmd_info *cmd)
725 {
726 struct ib_smp *smp = inbox->buf;
727 u32 index;
728 u8 port;
729 u8 opcode_modifier;
730 u16 *table;
731 int err;
732 int vidx, pidx;
733 int network_view;
734 struct mlx4_priv *priv = mlx4_priv(dev);
735 struct ib_smp *outsmp = outbox->buf;
736 __be16 *outtab = (__be16 *)(outsmp->data);
737 __be32 slave_cap_mask;
738 __be64 slave_node_guid;
739
740 port = vhcr->in_modifier;
741
742 /* network-view bit is for driver use only, and should not be passed to FW */
743 opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
744 network_view = !!(vhcr->op_modifier & 0x8);
745
746 if (smp->base_version == 1 &&
747 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
748 smp->class_version == 1) {
749 /* host view is paravirtualized */
750 if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
751 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
752 index = be32_to_cpu(smp->attr_mod);
753 if (port < 1 || port > dev->caps.num_ports)
754 return -EINVAL;
755 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
756 if (!table)
757 return -ENOMEM;
758 /* need to get the full pkey table because the paravirtualized
759 * pkeys may be scattered among several pkey blocks.
760 */
761 err = get_full_pkey_table(dev, port, table, inbox, outbox);
762 if (!err) {
763 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
764 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
765 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
766 }
767 }
768 kfree(table);
769 return err;
770 }
771 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
772 /*get the slave specific caps:*/
773 /*do the command */
774 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
775 vhcr->in_modifier, opcode_modifier,
776 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
777 /* modify the response for slaves */
778 if (!err && slave != mlx4_master_func_num(dev)) {
779 u8 *state = outsmp->data + PORT_STATE_OFFSET;
780
781 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
782 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
783 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
784 }
785 return err;
786 }
787 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
788 /* compute slave's gid block */
789 smp->attr_mod = cpu_to_be32(slave / 8);
790 /* execute cmd */
791 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
792 vhcr->in_modifier, opcode_modifier,
793 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
794 if (!err) {
795 /* if needed, move slave gid to index 0 */
796 if (slave % 8)
797 memcpy(outsmp->data,
798 outsmp->data + (slave % 8) * 8, 8);
799 /* delete all other gids */
800 memset(outsmp->data + 8, 0, 56);
801 }
802 return err;
803 }
804 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
805 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
806 vhcr->in_modifier, opcode_modifier,
807 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
808 if (!err) {
809 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
810 memcpy(outsmp->data + 12, &slave_node_guid, 8);
811 }
812 return err;
813 }
814 }
815 }
816
817 /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
818 * These are the MADs used by ib verbs (such as ib_query_gids).
819 */
820 if (slave != mlx4_master_func_num(dev) &&
821 !mlx4_vf_smi_enabled(dev, slave, port)) {
822 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
823 smp->method == IB_MGMT_METHOD_GET) || network_view) {
824 mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
825 slave, smp->method, smp->mgmt_class,
826 network_view ? "Network" : "Host",
827 be16_to_cpu(smp->attr_id));
828 return -EPERM;
829 }
830 }
831
832 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
833 vhcr->in_modifier, opcode_modifier,
834 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
835 }
836
837 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
838 struct mlx4_vhcr *vhcr,
839 struct mlx4_cmd_mailbox *inbox,
840 struct mlx4_cmd_mailbox *outbox,
841 struct mlx4_cmd_info *cmd)
842 {
843 return -EPERM;
844 }
845
846 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
847 struct mlx4_vhcr *vhcr,
848 struct mlx4_cmd_mailbox *inbox,
849 struct mlx4_cmd_mailbox *outbox,
850 struct mlx4_cmd_info *cmd)
851 {
852 u64 in_param;
853 u64 out_param;
854 int err;
855
856 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
857 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
858 if (cmd->encode_slave_id) {
859 in_param &= 0xffffffffffffff00ll;
860 in_param |= slave;
861 }
862
863 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
864 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
865 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
866
867 if (cmd->out_is_imm)
868 vhcr->out_param = out_param;
869
870 return err;
871 }
872
873 static struct mlx4_cmd_info cmd_info[] = {
874 {
875 .opcode = MLX4_CMD_QUERY_FW,
876 .has_inbox = false,
877 .has_outbox = true,
878 .out_is_imm = false,
879 .encode_slave_id = false,
880 .verify = NULL,
881 .wrapper = mlx4_QUERY_FW_wrapper
882 },
883 {
884 .opcode = MLX4_CMD_QUERY_HCA,
885 .has_inbox = false,
886 .has_outbox = true,
887 .out_is_imm = false,
888 .encode_slave_id = false,
889 .verify = NULL,
890 .wrapper = NULL
891 },
892 {
893 .opcode = MLX4_CMD_QUERY_DEV_CAP,
894 .has_inbox = false,
895 .has_outbox = true,
896 .out_is_imm = false,
897 .encode_slave_id = false,
898 .verify = NULL,
899 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
900 },
901 {
902 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
903 .has_inbox = false,
904 .has_outbox = true,
905 .out_is_imm = false,
906 .encode_slave_id = false,
907 .verify = NULL,
908 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
909 },
910 {
911 .opcode = MLX4_CMD_QUERY_ADAPTER,
912 .has_inbox = false,
913 .has_outbox = true,
914 .out_is_imm = false,
915 .encode_slave_id = false,
916 .verify = NULL,
917 .wrapper = NULL
918 },
919 {
920 .opcode = MLX4_CMD_INIT_PORT,
921 .has_inbox = false,
922 .has_outbox = false,
923 .out_is_imm = false,
924 .encode_slave_id = false,
925 .verify = NULL,
926 .wrapper = mlx4_INIT_PORT_wrapper
927 },
928 {
929 .opcode = MLX4_CMD_CLOSE_PORT,
930 .has_inbox = false,
931 .has_outbox = false,
932 .out_is_imm = false,
933 .encode_slave_id = false,
934 .verify = NULL,
935 .wrapper = mlx4_CLOSE_PORT_wrapper
936 },
937 {
938 .opcode = MLX4_CMD_QUERY_PORT,
939 .has_inbox = false,
940 .has_outbox = true,
941 .out_is_imm = false,
942 .encode_slave_id = false,
943 .verify = NULL,
944 .wrapper = mlx4_QUERY_PORT_wrapper
945 },
946 {
947 .opcode = MLX4_CMD_SET_PORT,
948 .has_inbox = true,
949 .has_outbox = false,
950 .out_is_imm = false,
951 .encode_slave_id = false,
952 .verify = NULL,
953 .wrapper = mlx4_SET_PORT_wrapper
954 },
955 {
956 .opcode = MLX4_CMD_MAP_EQ,
957 .has_inbox = false,
958 .has_outbox = false,
959 .out_is_imm = false,
960 .encode_slave_id = false,
961 .verify = NULL,
962 .wrapper = mlx4_MAP_EQ_wrapper
963 },
964 {
965 .opcode = MLX4_CMD_SW2HW_EQ,
966 .has_inbox = true,
967 .has_outbox = false,
968 .out_is_imm = false,
969 .encode_slave_id = true,
970 .verify = NULL,
971 .wrapper = mlx4_SW2HW_EQ_wrapper
972 },
973 {
974 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
975 .has_inbox = false,
976 .has_outbox = false,
977 .out_is_imm = false,
978 .encode_slave_id = false,
979 .verify = NULL,
980 .wrapper = NULL
981 },
982 {
983 .opcode = MLX4_CMD_NOP,
984 .has_inbox = false,
985 .has_outbox = false,
986 .out_is_imm = false,
987 .encode_slave_id = false,
988 .verify = NULL,
989 .wrapper = NULL
990 },
991 {
992 .opcode = MLX4_CMD_CONFIG_DEV,
993 .has_inbox = false,
994 .has_outbox = false,
995 .out_is_imm = false,
996 .encode_slave_id = false,
997 .verify = NULL,
998 .wrapper = mlx4_CMD_EPERM_wrapper
999 },
1000 {
1001 .opcode = MLX4_CMD_ALLOC_RES,
1002 .has_inbox = false,
1003 .has_outbox = false,
1004 .out_is_imm = true,
1005 .encode_slave_id = false,
1006 .verify = NULL,
1007 .wrapper = mlx4_ALLOC_RES_wrapper
1008 },
1009 {
1010 .opcode = MLX4_CMD_FREE_RES,
1011 .has_inbox = false,
1012 .has_outbox = false,
1013 .out_is_imm = false,
1014 .encode_slave_id = false,
1015 .verify = NULL,
1016 .wrapper = mlx4_FREE_RES_wrapper
1017 },
1018 {
1019 .opcode = MLX4_CMD_SW2HW_MPT,
1020 .has_inbox = true,
1021 .has_outbox = false,
1022 .out_is_imm = false,
1023 .encode_slave_id = true,
1024 .verify = NULL,
1025 .wrapper = mlx4_SW2HW_MPT_wrapper
1026 },
1027 {
1028 .opcode = MLX4_CMD_QUERY_MPT,
1029 .has_inbox = false,
1030 .has_outbox = true,
1031 .out_is_imm = false,
1032 .encode_slave_id = false,
1033 .verify = NULL,
1034 .wrapper = mlx4_QUERY_MPT_wrapper
1035 },
1036 {
1037 .opcode = MLX4_CMD_HW2SW_MPT,
1038 .has_inbox = false,
1039 .has_outbox = false,
1040 .out_is_imm = false,
1041 .encode_slave_id = false,
1042 .verify = NULL,
1043 .wrapper = mlx4_HW2SW_MPT_wrapper
1044 },
1045 {
1046 .opcode = MLX4_CMD_READ_MTT,
1047 .has_inbox = false,
1048 .has_outbox = true,
1049 .out_is_imm = false,
1050 .encode_slave_id = false,
1051 .verify = NULL,
1052 .wrapper = NULL
1053 },
1054 {
1055 .opcode = MLX4_CMD_WRITE_MTT,
1056 .has_inbox = true,
1057 .has_outbox = false,
1058 .out_is_imm = false,
1059 .encode_slave_id = false,
1060 .verify = NULL,
1061 .wrapper = mlx4_WRITE_MTT_wrapper
1062 },
1063 {
1064 .opcode = MLX4_CMD_SYNC_TPT,
1065 .has_inbox = true,
1066 .has_outbox = false,
1067 .out_is_imm = false,
1068 .encode_slave_id = false,
1069 .verify = NULL,
1070 .wrapper = NULL
1071 },
1072 {
1073 .opcode = MLX4_CMD_HW2SW_EQ,
1074 .has_inbox = false,
1075 .has_outbox = true,
1076 .out_is_imm = false,
1077 .encode_slave_id = true,
1078 .verify = NULL,
1079 .wrapper = mlx4_HW2SW_EQ_wrapper
1080 },
1081 {
1082 .opcode = MLX4_CMD_QUERY_EQ,
1083 .has_inbox = false,
1084 .has_outbox = true,
1085 .out_is_imm = false,
1086 .encode_slave_id = true,
1087 .verify = NULL,
1088 .wrapper = mlx4_QUERY_EQ_wrapper
1089 },
1090 {
1091 .opcode = MLX4_CMD_SW2HW_CQ,
1092 .has_inbox = true,
1093 .has_outbox = false,
1094 .out_is_imm = false,
1095 .encode_slave_id = true,
1096 .verify = NULL,
1097 .wrapper = mlx4_SW2HW_CQ_wrapper
1098 },
1099 {
1100 .opcode = MLX4_CMD_HW2SW_CQ,
1101 .has_inbox = false,
1102 .has_outbox = false,
1103 .out_is_imm = false,
1104 .encode_slave_id = false,
1105 .verify = NULL,
1106 .wrapper = mlx4_HW2SW_CQ_wrapper
1107 },
1108 {
1109 .opcode = MLX4_CMD_QUERY_CQ,
1110 .has_inbox = false,
1111 .has_outbox = true,
1112 .out_is_imm = false,
1113 .encode_slave_id = false,
1114 .verify = NULL,
1115 .wrapper = mlx4_QUERY_CQ_wrapper
1116 },
1117 {
1118 .opcode = MLX4_CMD_MODIFY_CQ,
1119 .has_inbox = true,
1120 .has_outbox = false,
1121 .out_is_imm = true,
1122 .encode_slave_id = false,
1123 .verify = NULL,
1124 .wrapper = mlx4_MODIFY_CQ_wrapper
1125 },
1126 {
1127 .opcode = MLX4_CMD_SW2HW_SRQ,
1128 .has_inbox = true,
1129 .has_outbox = false,
1130 .out_is_imm = false,
1131 .encode_slave_id = true,
1132 .verify = NULL,
1133 .wrapper = mlx4_SW2HW_SRQ_wrapper
1134 },
1135 {
1136 .opcode = MLX4_CMD_HW2SW_SRQ,
1137 .has_inbox = false,
1138 .has_outbox = false,
1139 .out_is_imm = false,
1140 .encode_slave_id = false,
1141 .verify = NULL,
1142 .wrapper = mlx4_HW2SW_SRQ_wrapper
1143 },
1144 {
1145 .opcode = MLX4_CMD_QUERY_SRQ,
1146 .has_inbox = false,
1147 .has_outbox = true,
1148 .out_is_imm = false,
1149 .encode_slave_id = false,
1150 .verify = NULL,
1151 .wrapper = mlx4_QUERY_SRQ_wrapper
1152 },
1153 {
1154 .opcode = MLX4_CMD_ARM_SRQ,
1155 .has_inbox = false,
1156 .has_outbox = false,
1157 .out_is_imm = false,
1158 .encode_slave_id = false,
1159 .verify = NULL,
1160 .wrapper = mlx4_ARM_SRQ_wrapper
1161 },
1162 {
1163 .opcode = MLX4_CMD_RST2INIT_QP,
1164 .has_inbox = true,
1165 .has_outbox = false,
1166 .out_is_imm = false,
1167 .encode_slave_id = true,
1168 .verify = NULL,
1169 .wrapper = mlx4_RST2INIT_QP_wrapper
1170 },
1171 {
1172 .opcode = MLX4_CMD_INIT2INIT_QP,
1173 .has_inbox = true,
1174 .has_outbox = false,
1175 .out_is_imm = false,
1176 .encode_slave_id = false,
1177 .verify = NULL,
1178 .wrapper = mlx4_INIT2INIT_QP_wrapper
1179 },
1180 {
1181 .opcode = MLX4_CMD_INIT2RTR_QP,
1182 .has_inbox = true,
1183 .has_outbox = false,
1184 .out_is_imm = false,
1185 .encode_slave_id = false,
1186 .verify = NULL,
1187 .wrapper = mlx4_INIT2RTR_QP_wrapper
1188 },
1189 {
1190 .opcode = MLX4_CMD_RTR2RTS_QP,
1191 .has_inbox = true,
1192 .has_outbox = false,
1193 .out_is_imm = false,
1194 .encode_slave_id = false,
1195 .verify = NULL,
1196 .wrapper = mlx4_RTR2RTS_QP_wrapper
1197 },
1198 {
1199 .opcode = MLX4_CMD_RTS2RTS_QP,
1200 .has_inbox = true,
1201 .has_outbox = false,
1202 .out_is_imm = false,
1203 .encode_slave_id = false,
1204 .verify = NULL,
1205 .wrapper = mlx4_RTS2RTS_QP_wrapper
1206 },
1207 {
1208 .opcode = MLX4_CMD_SQERR2RTS_QP,
1209 .has_inbox = true,
1210 .has_outbox = false,
1211 .out_is_imm = false,
1212 .encode_slave_id = false,
1213 .verify = NULL,
1214 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1215 },
1216 {
1217 .opcode = MLX4_CMD_2ERR_QP,
1218 .has_inbox = false,
1219 .has_outbox = false,
1220 .out_is_imm = false,
1221 .encode_slave_id = false,
1222 .verify = NULL,
1223 .wrapper = mlx4_GEN_QP_wrapper
1224 },
1225 {
1226 .opcode = MLX4_CMD_RTS2SQD_QP,
1227 .has_inbox = false,
1228 .has_outbox = false,
1229 .out_is_imm = false,
1230 .encode_slave_id = false,
1231 .verify = NULL,
1232 .wrapper = mlx4_GEN_QP_wrapper
1233 },
1234 {
1235 .opcode = MLX4_CMD_SQD2SQD_QP,
1236 .has_inbox = true,
1237 .has_outbox = false,
1238 .out_is_imm = false,
1239 .encode_slave_id = false,
1240 .verify = NULL,
1241 .wrapper = mlx4_SQD2SQD_QP_wrapper
1242 },
1243 {
1244 .opcode = MLX4_CMD_SQD2RTS_QP,
1245 .has_inbox = true,
1246 .has_outbox = false,
1247 .out_is_imm = false,
1248 .encode_slave_id = false,
1249 .verify = NULL,
1250 .wrapper = mlx4_SQD2RTS_QP_wrapper
1251 },
1252 {
1253 .opcode = MLX4_CMD_2RST_QP,
1254 .has_inbox = false,
1255 .has_outbox = false,
1256 .out_is_imm = false,
1257 .encode_slave_id = false,
1258 .verify = NULL,
1259 .wrapper = mlx4_2RST_QP_wrapper
1260 },
1261 {
1262 .opcode = MLX4_CMD_QUERY_QP,
1263 .has_inbox = false,
1264 .has_outbox = true,
1265 .out_is_imm = false,
1266 .encode_slave_id = false,
1267 .verify = NULL,
1268 .wrapper = mlx4_GEN_QP_wrapper
1269 },
1270 {
1271 .opcode = MLX4_CMD_SUSPEND_QP,
1272 .has_inbox = false,
1273 .has_outbox = false,
1274 .out_is_imm = false,
1275 .encode_slave_id = false,
1276 .verify = NULL,
1277 .wrapper = mlx4_GEN_QP_wrapper
1278 },
1279 {
1280 .opcode = MLX4_CMD_UNSUSPEND_QP,
1281 .has_inbox = false,
1282 .has_outbox = false,
1283 .out_is_imm = false,
1284 .encode_slave_id = false,
1285 .verify = NULL,
1286 .wrapper = mlx4_GEN_QP_wrapper
1287 },
1288 {
1289 .opcode = MLX4_CMD_UPDATE_QP,
1290 .has_inbox = true,
1291 .has_outbox = false,
1292 .out_is_imm = false,
1293 .encode_slave_id = false,
1294 .verify = NULL,
1295 .wrapper = mlx4_UPDATE_QP_wrapper
1296 },
1297 {
1298 .opcode = MLX4_CMD_GET_OP_REQ,
1299 .has_inbox = false,
1300 .has_outbox = false,
1301 .out_is_imm = false,
1302 .encode_slave_id = false,
1303 .verify = NULL,
1304 .wrapper = mlx4_CMD_EPERM_wrapper,
1305 },
1306 {
1307 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1308 .has_inbox = false,
1309 .has_outbox = false,
1310 .out_is_imm = false,
1311 .encode_slave_id = false,
1312 .verify = NULL, /* XXX verify: only demux can do this */
1313 .wrapper = NULL
1314 },
1315 {
1316 .opcode = MLX4_CMD_MAD_IFC,
1317 .has_inbox = true,
1318 .has_outbox = true,
1319 .out_is_imm = false,
1320 .encode_slave_id = false,
1321 .verify = NULL,
1322 .wrapper = mlx4_MAD_IFC_wrapper
1323 },
1324 {
1325 .opcode = MLX4_CMD_MAD_DEMUX,
1326 .has_inbox = false,
1327 .has_outbox = false,
1328 .out_is_imm = false,
1329 .encode_slave_id = false,
1330 .verify = NULL,
1331 .wrapper = mlx4_CMD_EPERM_wrapper
1332 },
1333 {
1334 .opcode = MLX4_CMD_QUERY_IF_STAT,
1335 .has_inbox = false,
1336 .has_outbox = true,
1337 .out_is_imm = false,
1338 .encode_slave_id = false,
1339 .verify = NULL,
1340 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1341 },
1342 /* Native multicast commands are not available for guests */
1343 {
1344 .opcode = MLX4_CMD_QP_ATTACH,
1345 .has_inbox = true,
1346 .has_outbox = false,
1347 .out_is_imm = false,
1348 .encode_slave_id = false,
1349 .verify = NULL,
1350 .wrapper = mlx4_QP_ATTACH_wrapper
1351 },
1352 {
1353 .opcode = MLX4_CMD_PROMISC,
1354 .has_inbox = false,
1355 .has_outbox = false,
1356 .out_is_imm = false,
1357 .encode_slave_id = false,
1358 .verify = NULL,
1359 .wrapper = mlx4_PROMISC_wrapper
1360 },
1361 /* Ethernet specific commands */
1362 {
1363 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1364 .has_inbox = true,
1365 .has_outbox = false,
1366 .out_is_imm = false,
1367 .encode_slave_id = false,
1368 .verify = NULL,
1369 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1370 },
1371 {
1372 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1373 .has_inbox = false,
1374 .has_outbox = false,
1375 .out_is_imm = false,
1376 .encode_slave_id = false,
1377 .verify = NULL,
1378 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1379 },
1380 {
1381 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1382 .has_inbox = false,
1383 .has_outbox = true,
1384 .out_is_imm = false,
1385 .encode_slave_id = false,
1386 .verify = NULL,
1387 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1388 },
1389 {
1390 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1391 .has_inbox = false,
1392 .has_outbox = false,
1393 .out_is_imm = false,
1394 .encode_slave_id = false,
1395 .verify = NULL,
1396 .wrapper = NULL
1397 },
1398 /* flow steering commands */
1399 {
1400 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1401 .has_inbox = true,
1402 .has_outbox = false,
1403 .out_is_imm = true,
1404 .encode_slave_id = false,
1405 .verify = NULL,
1406 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1407 },
1408 {
1409 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1410 .has_inbox = false,
1411 .has_outbox = false,
1412 .out_is_imm = false,
1413 .encode_slave_id = false,
1414 .verify = NULL,
1415 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1416 },
1417 {
1418 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1419 .has_inbox = false,
1420 .has_outbox = false,
1421 .out_is_imm = false,
1422 .encode_slave_id = false,
1423 .verify = NULL,
1424 .wrapper = mlx4_CMD_EPERM_wrapper
1425 },
1426 };
1427
1428 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1429 struct mlx4_vhcr_cmd *in_vhcr)
1430 {
1431 struct mlx4_priv *priv = mlx4_priv(dev);
1432 struct mlx4_cmd_info *cmd = NULL;
1433 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1434 struct mlx4_vhcr *vhcr;
1435 struct mlx4_cmd_mailbox *inbox = NULL;
1436 struct mlx4_cmd_mailbox *outbox = NULL;
1437 u64 in_param;
1438 u64 out_param;
1439 int ret = 0;
1440 int i;
1441 int err = 0;
1442
1443 /* Create sw representation of Virtual HCR */
1444 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1445 if (!vhcr)
1446 return -ENOMEM;
1447
1448 /* DMA in the vHCR */
1449 if (!in_vhcr) {
1450 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1451 priv->mfunc.master.slave_state[slave].vhcr_dma,
1452 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1453 MLX4_ACCESS_MEM_ALIGN), 1);
1454 if (ret) {
1455 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1456 __func__, ret);
1457 kfree(vhcr);
1458 return ret;
1459 }
1460 }
1461
1462 /* Fill SW VHCR fields */
1463 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1464 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1465 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1466 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1467 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1468 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1469 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1470
1471 /* Lookup command */
1472 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1473 if (vhcr->op == cmd_info[i].opcode) {
1474 cmd = &cmd_info[i];
1475 break;
1476 }
1477 }
1478 if (!cmd) {
1479 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1480 vhcr->op, slave);
1481 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1482 goto out_status;
1483 }
1484
1485 /* Read inbox */
1486 if (cmd->has_inbox) {
1487 vhcr->in_param &= INBOX_MASK;
1488 inbox = mlx4_alloc_cmd_mailbox(dev);
1489 if (IS_ERR(inbox)) {
1490 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1491 inbox = NULL;
1492 goto out_status;
1493 }
1494
1495 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1496 vhcr->in_param,
1497 MLX4_MAILBOX_SIZE, 1)) {
1498 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1499 __func__, cmd->opcode);
1500 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1501 goto out_status;
1502 }
1503 }
1504
1505 /* Apply permission and bound checks if applicable */
1506 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1507 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1508 vhcr->op, slave, vhcr->in_modifier);
1509 vhcr_cmd->status = CMD_STAT_BAD_OP;
1510 goto out_status;
1511 }
1512
1513 /* Allocate outbox */
1514 if (cmd->has_outbox) {
1515 outbox = mlx4_alloc_cmd_mailbox(dev);
1516 if (IS_ERR(outbox)) {
1517 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1518 outbox = NULL;
1519 goto out_status;
1520 }
1521 }
1522
1523 /* Execute the command! */
1524 if (cmd->wrapper) {
1525 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1526 cmd);
1527 if (cmd->out_is_imm)
1528 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1529 } else {
1530 in_param = cmd->has_inbox ? (u64) inbox->dma :
1531 vhcr->in_param;
1532 out_param = cmd->has_outbox ? (u64) outbox->dma :
1533 vhcr->out_param;
1534 err = __mlx4_cmd(dev, in_param, &out_param,
1535 cmd->out_is_imm, vhcr->in_modifier,
1536 vhcr->op_modifier, vhcr->op,
1537 MLX4_CMD_TIME_CLASS_A,
1538 MLX4_CMD_NATIVE);
1539
1540 if (cmd->out_is_imm) {
1541 vhcr->out_param = out_param;
1542 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1543 }
1544 }
1545
1546 if (err) {
1547 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
1548 vhcr->op, slave, vhcr->errno, err);
1549 vhcr_cmd->status = mlx4_errno_to_status(err);
1550 goto out_status;
1551 }
1552
1553
1554 /* Write outbox if command completed successfully */
1555 if (cmd->has_outbox && !vhcr_cmd->status) {
1556 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1557 vhcr->out_param,
1558 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1559 if (ret) {
1560 /* If we failed to write back the outbox after the
1561 *command was successfully executed, we must fail this
1562 * slave, as it is now in undefined state */
1563 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1564 goto out;
1565 }
1566 }
1567
1568 out_status:
1569 /* DMA back vhcr result */
1570 if (!in_vhcr) {
1571 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1572 priv->mfunc.master.slave_state[slave].vhcr_dma,
1573 ALIGN(sizeof(struct mlx4_vhcr),
1574 MLX4_ACCESS_MEM_ALIGN),
1575 MLX4_CMD_WRAPPED);
1576 if (ret)
1577 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1578 __func__);
1579 else if (vhcr->e_bit &&
1580 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1581 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1582 slave);
1583 }
1584
1585 out:
1586 kfree(vhcr);
1587 mlx4_free_cmd_mailbox(dev, inbox);
1588 mlx4_free_cmd_mailbox(dev, outbox);
1589 return ret;
1590 }
1591
1592 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
1593 int slave, int port)
1594 {
1595 struct mlx4_vport_oper_state *vp_oper;
1596 struct mlx4_vport_state *vp_admin;
1597 struct mlx4_vf_immed_vlan_work *work;
1598 struct mlx4_dev *dev = &(priv->dev);
1599 int err;
1600 int admin_vlan_ix = NO_INDX;
1601
1602 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1603 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1604
1605 if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
1606 vp_oper->state.default_qos == vp_admin->default_qos &&
1607 vp_oper->state.link_state == vp_admin->link_state)
1608 return 0;
1609
1610 if (!(priv->mfunc.master.slave_state[slave].active &&
1611 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
1612 /* even if the UPDATE_QP command isn't supported, we still want
1613 * to set this VF link according to the admin directive
1614 */
1615 vp_oper->state.link_state = vp_admin->link_state;
1616 return -1;
1617 }
1618
1619 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1620 slave, port);
1621 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1622 vp_admin->default_vlan, vp_admin->default_qos,
1623 vp_admin->link_state);
1624
1625 work = kzalloc(sizeof(*work), GFP_KERNEL);
1626 if (!work)
1627 return -ENOMEM;
1628
1629 if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1630 if (MLX4_VGT != vp_admin->default_vlan) {
1631 err = __mlx4_register_vlan(&priv->dev, port,
1632 vp_admin->default_vlan,
1633 &admin_vlan_ix);
1634 if (err) {
1635 kfree(work);
1636 mlx4_warn(&priv->dev,
1637 "No vlan resources slave %d, port %d\n",
1638 slave, port);
1639 return err;
1640 }
1641 } else {
1642 admin_vlan_ix = NO_INDX;
1643 }
1644 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1645 mlx4_dbg(&priv->dev,
1646 "alloc vlan %d idx %d slave %d port %d\n",
1647 (int)(vp_admin->default_vlan),
1648 admin_vlan_ix, slave, port);
1649 }
1650
1651 /* save original vlan ix and vlan id */
1652 work->orig_vlan_id = vp_oper->state.default_vlan;
1653 work->orig_vlan_ix = vp_oper->vlan_idx;
1654
1655 /* handle new qos */
1656 if (vp_oper->state.default_qos != vp_admin->default_qos)
1657 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1658
1659 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1660 vp_oper->vlan_idx = admin_vlan_ix;
1661
1662 vp_oper->state.default_vlan = vp_admin->default_vlan;
1663 vp_oper->state.default_qos = vp_admin->default_qos;
1664 vp_oper->state.link_state = vp_admin->link_state;
1665
1666 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1667 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
1668
1669 /* iterate over QPs owned by this slave, using UPDATE_QP */
1670 work->port = port;
1671 work->slave = slave;
1672 work->qos = vp_oper->state.default_qos;
1673 work->vlan_id = vp_oper->state.default_vlan;
1674 work->vlan_ix = vp_oper->vlan_idx;
1675 work->priv = priv;
1676 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1677 queue_work(priv->mfunc.master.comm_wq, &work->work);
1678
1679 return 0;
1680 }
1681
1682
1683 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1684 {
1685 int port, err;
1686 struct mlx4_vport_state *vp_admin;
1687 struct mlx4_vport_oper_state *vp_oper;
1688 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1689 &priv->dev, slave);
1690 int min_port = find_first_bit(actv_ports.ports,
1691 priv->dev.caps.num_ports) + 1;
1692 int max_port = min_port - 1 +
1693 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1694
1695 for (port = min_port; port <= max_port; port++) {
1696 if (!test_bit(port - 1, actv_ports.ports))
1697 continue;
1698 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1699 priv->mfunc.master.vf_admin[slave].enable_smi[port];
1700 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1701 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1702 vp_oper->state = *vp_admin;
1703 if (MLX4_VGT != vp_admin->default_vlan) {
1704 err = __mlx4_register_vlan(&priv->dev, port,
1705 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1706 if (err) {
1707 vp_oper->vlan_idx = NO_INDX;
1708 mlx4_warn(&priv->dev,
1709 "No vlan resources slave %d, port %d\n",
1710 slave, port);
1711 return err;
1712 }
1713 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n",
1714 (int)(vp_oper->state.default_vlan),
1715 vp_oper->vlan_idx, slave, port);
1716 }
1717 if (vp_admin->spoofchk) {
1718 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1719 port,
1720 vp_admin->mac);
1721 if (0 > vp_oper->mac_idx) {
1722 err = vp_oper->mac_idx;
1723 vp_oper->mac_idx = NO_INDX;
1724 mlx4_warn(&priv->dev,
1725 "No mac resources slave %d, port %d\n",
1726 slave, port);
1727 return err;
1728 }
1729 mlx4_dbg(&priv->dev, "alloc mac %llx idx %d slave %d port %d\n",
1730 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1731 }
1732 }
1733 return 0;
1734 }
1735
1736 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1737 {
1738 int port;
1739 struct mlx4_vport_oper_state *vp_oper;
1740 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1741 &priv->dev, slave);
1742 int min_port = find_first_bit(actv_ports.ports,
1743 priv->dev.caps.num_ports) + 1;
1744 int max_port = min_port - 1 +
1745 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1746
1747
1748 for (port = min_port; port <= max_port; port++) {
1749 if (!test_bit(port - 1, actv_ports.ports))
1750 continue;
1751 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1752 MLX4_VF_SMI_DISABLED;
1753 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1754 if (NO_INDX != vp_oper->vlan_idx) {
1755 __mlx4_unregister_vlan(&priv->dev,
1756 port, vp_oper->state.default_vlan);
1757 vp_oper->vlan_idx = NO_INDX;
1758 }
1759 if (NO_INDX != vp_oper->mac_idx) {
1760 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
1761 vp_oper->mac_idx = NO_INDX;
1762 }
1763 }
1764 return;
1765 }
1766
1767 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1768 u16 param, u8 toggle)
1769 {
1770 struct mlx4_priv *priv = mlx4_priv(dev);
1771 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1772 u32 reply;
1773 u8 is_going_down = 0;
1774 int i;
1775 unsigned long flags;
1776
1777 slave_state[slave].comm_toggle ^= 1;
1778 reply = (u32) slave_state[slave].comm_toggle << 31;
1779 if (toggle != slave_state[slave].comm_toggle) {
1780 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
1781 toggle, slave);
1782 goto reset_slave;
1783 }
1784 if (cmd == MLX4_COMM_CMD_RESET) {
1785 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1786 slave_state[slave].active = false;
1787 slave_state[slave].old_vlan_api = false;
1788 mlx4_master_deactivate_admin_state(priv, slave);
1789 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1790 slave_state[slave].event_eq[i].eqn = -1;
1791 slave_state[slave].event_eq[i].token = 0;
1792 }
1793 /*check if we are in the middle of FLR process,
1794 if so return "retry" status to the slave*/
1795 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
1796 goto inform_slave_state;
1797
1798 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1799
1800 /* write the version in the event field */
1801 reply |= mlx4_comm_get_version();
1802
1803 goto reset_slave;
1804 }
1805 /*command from slave in the middle of FLR*/
1806 if (cmd != MLX4_COMM_CMD_RESET &&
1807 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1808 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
1809 slave, cmd);
1810 return;
1811 }
1812
1813 switch (cmd) {
1814 case MLX4_COMM_CMD_VHCR0:
1815 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1816 goto reset_slave;
1817 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1818 priv->mfunc.master.slave_state[slave].cookie = 0;
1819 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1820 break;
1821 case MLX4_COMM_CMD_VHCR1:
1822 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1823 goto reset_slave;
1824 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1825 break;
1826 case MLX4_COMM_CMD_VHCR2:
1827 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1828 goto reset_slave;
1829 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1830 break;
1831 case MLX4_COMM_CMD_VHCR_EN:
1832 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1833 goto reset_slave;
1834 slave_state[slave].vhcr_dma |= param;
1835 if (mlx4_master_activate_admin_state(priv, slave))
1836 goto reset_slave;
1837 slave_state[slave].active = true;
1838 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
1839 break;
1840 case MLX4_COMM_CMD_VHCR_POST:
1841 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1842 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1843 goto reset_slave;
1844
1845 mutex_lock(&priv->cmd.slave_cmd_mutex);
1846 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1847 mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n",
1848 slave);
1849 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1850 goto reset_slave;
1851 }
1852 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1853 break;
1854 default:
1855 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1856 goto reset_slave;
1857 }
1858 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1859 if (!slave_state[slave].is_slave_going_down)
1860 slave_state[slave].last_cmd = cmd;
1861 else
1862 is_going_down = 1;
1863 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1864 if (is_going_down) {
1865 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n",
1866 cmd, slave);
1867 return;
1868 }
1869 __raw_writel((__force u32) cpu_to_be32(reply),
1870 &priv->mfunc.comm[slave].slave_read);
1871 mmiowb();
1872
1873 return;
1874
1875 reset_slave:
1876 /* cleanup any slave resources */
1877 mlx4_delete_all_resources_for_slave(dev, slave);
1878 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1879 if (!slave_state[slave].is_slave_going_down)
1880 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1881 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1882 /*with slave in the middle of flr, no need to clean resources again.*/
1883 inform_slave_state:
1884 memset(&slave_state[slave].event_eq, 0,
1885 sizeof(struct mlx4_slave_event_eq_info));
1886 __raw_writel((__force u32) cpu_to_be32(reply),
1887 &priv->mfunc.comm[slave].slave_read);
1888 wmb();
1889 }
1890
1891 /* master command processing */
1892 void mlx4_master_comm_channel(struct work_struct *work)
1893 {
1894 struct mlx4_mfunc_master_ctx *master =
1895 container_of(work,
1896 struct mlx4_mfunc_master_ctx,
1897 comm_work);
1898 struct mlx4_mfunc *mfunc =
1899 container_of(master, struct mlx4_mfunc, master);
1900 struct mlx4_priv *priv =
1901 container_of(mfunc, struct mlx4_priv, mfunc);
1902 struct mlx4_dev *dev = &priv->dev;
1903 __be32 *bit_vec;
1904 u32 comm_cmd;
1905 u32 vec;
1906 int i, j, slave;
1907 int toggle;
1908 int served = 0;
1909 int reported = 0;
1910 u32 slt;
1911
1912 bit_vec = master->comm_arm_bit_vector;
1913 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1914 vec = be32_to_cpu(bit_vec[i]);
1915 for (j = 0; j < 32; j++) {
1916 if (!(vec & (1 << j)))
1917 continue;
1918 ++reported;
1919 slave = (i * 32) + j;
1920 comm_cmd = swab32(readl(
1921 &mfunc->comm[slave].slave_write));
1922 slt = swab32(readl(&mfunc->comm[slave].slave_read))
1923 >> 31;
1924 toggle = comm_cmd >> 31;
1925 if (toggle != slt) {
1926 if (master->slave_state[slave].comm_toggle
1927 != slt) {
1928 pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
1929 slave, slt,
1930 master->slave_state[slave].comm_toggle);
1931 master->slave_state[slave].comm_toggle =
1932 slt;
1933 }
1934 mlx4_master_do_cmd(dev, slave,
1935 comm_cmd >> 16 & 0xff,
1936 comm_cmd & 0xffff, toggle);
1937 ++served;
1938 }
1939 }
1940 }
1941
1942 if (reported && reported != served)
1943 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n",
1944 reported, served);
1945
1946 if (mlx4_ARM_COMM_CHANNEL(dev))
1947 mlx4_warn(dev, "Failed to arm comm channel events\n");
1948 }
1949
1950 static int sync_toggles(struct mlx4_dev *dev)
1951 {
1952 struct mlx4_priv *priv = mlx4_priv(dev);
1953 int wr_toggle;
1954 int rd_toggle;
1955 unsigned long end;
1956
1957 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1958 end = jiffies + msecs_to_jiffies(5000);
1959
1960 while (time_before(jiffies, end)) {
1961 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1962 if (rd_toggle == wr_toggle) {
1963 priv->cmd.comm_toggle = rd_toggle;
1964 return 0;
1965 }
1966
1967 cond_resched();
1968 }
1969
1970 /*
1971 * we could reach here if for example the previous VM using this
1972 * function misbehaved and left the channel with unsynced state. We
1973 * should fix this here and give this VM a chance to use a properly
1974 * synced channel
1975 */
1976 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1977 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1978 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1979 priv->cmd.comm_toggle = 0;
1980
1981 return 0;
1982 }
1983
1984 int mlx4_multi_func_init(struct mlx4_dev *dev)
1985 {
1986 struct mlx4_priv *priv = mlx4_priv(dev);
1987 struct mlx4_slave_state *s_state;
1988 int i, j, err, port;
1989
1990 if (mlx4_is_master(dev))
1991 priv->mfunc.comm =
1992 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1993 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1994 else
1995 priv->mfunc.comm =
1996 ioremap(pci_resource_start(dev->pdev, 2) +
1997 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1998 if (!priv->mfunc.comm) {
1999 mlx4_err(dev, "Couldn't map communication vector\n");
2000 goto err_vhcr;
2001 }
2002
2003 if (mlx4_is_master(dev)) {
2004 priv->mfunc.master.slave_state =
2005 kzalloc(dev->num_slaves *
2006 sizeof(struct mlx4_slave_state), GFP_KERNEL);
2007 if (!priv->mfunc.master.slave_state)
2008 goto err_comm;
2009
2010 priv->mfunc.master.vf_admin =
2011 kzalloc(dev->num_slaves *
2012 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
2013 if (!priv->mfunc.master.vf_admin)
2014 goto err_comm_admin;
2015
2016 priv->mfunc.master.vf_oper =
2017 kzalloc(dev->num_slaves *
2018 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
2019 if (!priv->mfunc.master.vf_oper)
2020 goto err_comm_oper;
2021
2022 for (i = 0; i < dev->num_slaves; ++i) {
2023 s_state = &priv->mfunc.master.slave_state[i];
2024 s_state->last_cmd = MLX4_COMM_CMD_RESET;
2025 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
2026 s_state->event_eq[j].eqn = -1;
2027 __raw_writel((__force u32) 0,
2028 &priv->mfunc.comm[i].slave_write);
2029 __raw_writel((__force u32) 0,
2030 &priv->mfunc.comm[i].slave_read);
2031 mmiowb();
2032 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
2033 s_state->vlan_filter[port] =
2034 kzalloc(sizeof(struct mlx4_vlan_fltr),
2035 GFP_KERNEL);
2036 if (!s_state->vlan_filter[port]) {
2037 if (--port)
2038 kfree(s_state->vlan_filter[port]);
2039 goto err_slaves;
2040 }
2041 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
2042 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
2043 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
2044 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
2045 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
2046 }
2047 spin_lock_init(&s_state->lock);
2048 }
2049
2050 memset(&priv->mfunc.master.cmd_eqe, 0, sizeof(struct mlx4_eqe));
2051 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2052 INIT_WORK(&priv->mfunc.master.comm_work,
2053 mlx4_master_comm_channel);
2054 INIT_WORK(&priv->mfunc.master.slave_event_work,
2055 mlx4_gen_slave_eqe);
2056 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2057 mlx4_master_handle_slave_flr);
2058 spin_lock_init(&priv->mfunc.master.slave_state_lock);
2059 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
2060 priv->mfunc.master.comm_wq =
2061 create_singlethread_workqueue("mlx4_comm");
2062 if (!priv->mfunc.master.comm_wq)
2063 goto err_slaves;
2064
2065 if (mlx4_init_resource_tracker(dev))
2066 goto err_thread;
2067
2068 err = mlx4_ARM_COMM_CHANNEL(dev);
2069 if (err) {
2070 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
2071 err);
2072 goto err_resource;
2073 }
2074
2075 } else {
2076 err = sync_toggles(dev);
2077 if (err) {
2078 mlx4_err(dev, "Couldn't sync toggles\n");
2079 goto err_comm;
2080 }
2081 }
2082 return 0;
2083
2084 err_resource:
2085 mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
2086 err_thread:
2087 flush_workqueue(priv->mfunc.master.comm_wq);
2088 destroy_workqueue(priv->mfunc.master.comm_wq);
2089 err_slaves:
2090 while (--i) {
2091 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2092 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2093 }
2094 kfree(priv->mfunc.master.vf_oper);
2095 err_comm_oper:
2096 kfree(priv->mfunc.master.vf_admin);
2097 err_comm_admin:
2098 kfree(priv->mfunc.master.slave_state);
2099 err_comm:
2100 iounmap(priv->mfunc.comm);
2101 err_vhcr:
2102 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2103 priv->mfunc.vhcr,
2104 priv->mfunc.vhcr_dma);
2105 priv->mfunc.vhcr = NULL;
2106 return -ENOMEM;
2107 }
2108
2109 int mlx4_cmd_init(struct mlx4_dev *dev)
2110 {
2111 struct mlx4_priv *priv = mlx4_priv(dev);
2112
2113 mutex_init(&priv->cmd.hcr_mutex);
2114 mutex_init(&priv->cmd.slave_cmd_mutex);
2115 sema_init(&priv->cmd.poll_sem, 1);
2116 priv->cmd.use_events = 0;
2117 priv->cmd.toggle = 1;
2118
2119 priv->cmd.hcr = NULL;
2120 priv->mfunc.vhcr = NULL;
2121
2122 if (!mlx4_is_slave(dev)) {
2123 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
2124 MLX4_HCR_BASE, MLX4_HCR_SIZE);
2125 if (!priv->cmd.hcr) {
2126 mlx4_err(dev, "Couldn't map command register\n");
2127 return -ENOMEM;
2128 }
2129 }
2130
2131 if (mlx4_is_mfunc(dev)) {
2132 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
2133 &priv->mfunc.vhcr_dma,
2134 GFP_KERNEL);
2135 if (!priv->mfunc.vhcr)
2136 goto err_hcr;
2137 }
2138
2139 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
2140 MLX4_MAILBOX_SIZE,
2141 MLX4_MAILBOX_SIZE, 0);
2142 if (!priv->cmd.pool)
2143 goto err_vhcr;
2144
2145 return 0;
2146
2147 err_vhcr:
2148 if (mlx4_is_mfunc(dev))
2149 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2150 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2151 priv->mfunc.vhcr = NULL;
2152
2153 err_hcr:
2154 if (!mlx4_is_slave(dev))
2155 iounmap(priv->cmd.hcr);
2156 return -ENOMEM;
2157 }
2158
2159 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2160 {
2161 struct mlx4_priv *priv = mlx4_priv(dev);
2162 int i, port;
2163
2164 if (mlx4_is_master(dev)) {
2165 flush_workqueue(priv->mfunc.master.comm_wq);
2166 destroy_workqueue(priv->mfunc.master.comm_wq);
2167 for (i = 0; i < dev->num_slaves; i++) {
2168 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2169 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2170 }
2171 kfree(priv->mfunc.master.slave_state);
2172 kfree(priv->mfunc.master.vf_admin);
2173 kfree(priv->mfunc.master.vf_oper);
2174 }
2175
2176 iounmap(priv->mfunc.comm);
2177 }
2178
2179 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
2180 {
2181 struct mlx4_priv *priv = mlx4_priv(dev);
2182
2183 pci_pool_destroy(priv->cmd.pool);
2184
2185 if (!mlx4_is_slave(dev))
2186 iounmap(priv->cmd.hcr);
2187 if (mlx4_is_mfunc(dev))
2188 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2189 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2190 priv->mfunc.vhcr = NULL;
2191 }
2192
2193 /*
2194 * Switch to using events to issue FW commands (can only be called
2195 * after event queue for command events has been initialized).
2196 */
2197 int mlx4_cmd_use_events(struct mlx4_dev *dev)
2198 {
2199 struct mlx4_priv *priv = mlx4_priv(dev);
2200 int i;
2201 int err = 0;
2202
2203 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2204 sizeof (struct mlx4_cmd_context),
2205 GFP_KERNEL);
2206 if (!priv->cmd.context)
2207 return -ENOMEM;
2208
2209 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2210 priv->cmd.context[i].token = i;
2211 priv->cmd.context[i].next = i + 1;
2212 }
2213
2214 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2215 priv->cmd.free_head = 0;
2216
2217 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2218 spin_lock_init(&priv->cmd.context_lock);
2219
2220 for (priv->cmd.token_mask = 1;
2221 priv->cmd.token_mask < priv->cmd.max_cmds;
2222 priv->cmd.token_mask <<= 1)
2223 ; /* nothing */
2224 --priv->cmd.token_mask;
2225
2226 down(&priv->cmd.poll_sem);
2227 priv->cmd.use_events = 1;
2228
2229 return err;
2230 }
2231
2232 /*
2233 * Switch back to polling (used when shutting down the device)
2234 */
2235 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2236 {
2237 struct mlx4_priv *priv = mlx4_priv(dev);
2238 int i;
2239
2240 priv->cmd.use_events = 0;
2241
2242 for (i = 0; i < priv->cmd.max_cmds; ++i)
2243 down(&priv->cmd.event_sem);
2244
2245 kfree(priv->cmd.context);
2246
2247 up(&priv->cmd.poll_sem);
2248 }
2249
2250 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2251 {
2252 struct mlx4_cmd_mailbox *mailbox;
2253
2254 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2255 if (!mailbox)
2256 return ERR_PTR(-ENOMEM);
2257
2258 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2259 &mailbox->dma);
2260 if (!mailbox->buf) {
2261 kfree(mailbox);
2262 return ERR_PTR(-ENOMEM);
2263 }
2264
2265 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
2266
2267 return mailbox;
2268 }
2269 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2270
2271 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2272 struct mlx4_cmd_mailbox *mailbox)
2273 {
2274 if (!mailbox)
2275 return;
2276
2277 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2278 kfree(mailbox);
2279 }
2280 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2281
2282 u32 mlx4_comm_get_version(void)
2283 {
2284 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2285 }
2286
2287 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2288 {
2289 if ((vf < 0) || (vf >= dev->num_vfs)) {
2290 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs);
2291 return -EINVAL;
2292 }
2293
2294 return vf+1;
2295 }
2296
2297 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2298 {
2299 if (slave < 1 || slave > dev->num_vfs) {
2300 mlx4_err(dev,
2301 "Bad slave number:%d (number of activated slaves: %lu)\n",
2302 slave, dev->num_slaves);
2303 return -EINVAL;
2304 }
2305 return slave - 1;
2306 }
2307
2308 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2309 {
2310 struct mlx4_active_ports actv_ports;
2311 int vf;
2312
2313 bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2314
2315 if (slave == 0) {
2316 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2317 return actv_ports;
2318 }
2319
2320 vf = mlx4_get_vf_indx(dev, slave);
2321 if (vf < 0)
2322 return actv_ports;
2323
2324 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2325 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2326 dev->caps.num_ports));
2327
2328 return actv_ports;
2329 }
2330 EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2331
2332 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2333 {
2334 unsigned n;
2335 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2336 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2337
2338 if (port <= 0 || port > m)
2339 return -EINVAL;
2340
2341 n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2342 if (port <= n)
2343 port = n + 1;
2344
2345 return port;
2346 }
2347 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2348
2349 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2350 {
2351 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2352 if (test_bit(port - 1, actv_ports.ports))
2353 return port -
2354 find_first_bit(actv_ports.ports, dev->caps.num_ports);
2355
2356 return -1;
2357 }
2358 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2359
2360 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2361 int port)
2362 {
2363 unsigned i;
2364 struct mlx4_slaves_pport slaves_pport;
2365
2366 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2367
2368 if (port <= 0 || port > dev->caps.num_ports)
2369 return slaves_pport;
2370
2371 for (i = 0; i < dev->num_vfs + 1; i++) {
2372 struct mlx4_active_ports actv_ports =
2373 mlx4_get_active_ports(dev, i);
2374 if (test_bit(port - 1, actv_ports.ports))
2375 set_bit(i, slaves_pport.slaves);
2376 }
2377
2378 return slaves_pport;
2379 }
2380 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2381
2382 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2383 struct mlx4_dev *dev,
2384 const struct mlx4_active_ports *crit_ports)
2385 {
2386 unsigned i;
2387 struct mlx4_slaves_pport slaves_pport;
2388
2389 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2390
2391 for (i = 0; i < dev->num_vfs + 1; i++) {
2392 struct mlx4_active_ports actv_ports =
2393 mlx4_get_active_ports(dev, i);
2394 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2395 dev->caps.num_ports))
2396 set_bit(i, slaves_pport.slaves);
2397 }
2398
2399 return slaves_pport;
2400 }
2401 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2402
2403 static int mlx4_slaves_closest_port(struct mlx4_dev *dev, int slave, int port)
2404 {
2405 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2406 int min_port = find_first_bit(actv_ports.ports, dev->caps.num_ports)
2407 + 1;
2408 int max_port = min_port +
2409 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2410
2411 if (port < min_port)
2412 port = min_port;
2413 else if (port >= max_port)
2414 port = max_port - 1;
2415
2416 return port;
2417 }
2418
2419 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2420 {
2421 struct mlx4_priv *priv = mlx4_priv(dev);
2422 struct mlx4_vport_state *s_info;
2423 int slave;
2424
2425 if (!mlx4_is_master(dev))
2426 return -EPROTONOSUPPORT;
2427
2428 slave = mlx4_get_slave_indx(dev, vf);
2429 if (slave < 0)
2430 return -EINVAL;
2431
2432 port = mlx4_slaves_closest_port(dev, slave, port);
2433 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2434 s_info->mac = mac;
2435 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2436 vf, port, s_info->mac);
2437 return 0;
2438 }
2439 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2440
2441
2442 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2443 {
2444 struct mlx4_priv *priv = mlx4_priv(dev);
2445 struct mlx4_vport_state *vf_admin;
2446 int slave;
2447
2448 if ((!mlx4_is_master(dev)) ||
2449 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2450 return -EPROTONOSUPPORT;
2451
2452 if ((vlan > 4095) || (qos > 7))
2453 return -EINVAL;
2454
2455 slave = mlx4_get_slave_indx(dev, vf);
2456 if (slave < 0)
2457 return -EINVAL;
2458
2459 port = mlx4_slaves_closest_port(dev, slave, port);
2460 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2461
2462 if ((0 == vlan) && (0 == qos))
2463 vf_admin->default_vlan = MLX4_VGT;
2464 else
2465 vf_admin->default_vlan = vlan;
2466 vf_admin->default_qos = qos;
2467
2468 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2469 mlx4_info(dev,
2470 "updating vf %d port %d config will take effect on next VF restart\n",
2471 vf, port);
2472 return 0;
2473 }
2474 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2475
2476 /* mlx4_get_slave_default_vlan -
2477 * return true if VST ( default vlan)
2478 * if VST, will return vlan & qos (if not NULL)
2479 */
2480 bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
2481 u16 *vlan, u8 *qos)
2482 {
2483 struct mlx4_vport_oper_state *vp_oper;
2484 struct mlx4_priv *priv;
2485
2486 priv = mlx4_priv(dev);
2487 port = mlx4_slaves_closest_port(dev, slave, port);
2488 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2489
2490 if (MLX4_VGT != vp_oper->state.default_vlan) {
2491 if (vlan)
2492 *vlan = vp_oper->state.default_vlan;
2493 if (qos)
2494 *qos = vp_oper->state.default_qos;
2495 return true;
2496 }
2497 return false;
2498 }
2499 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
2500
2501 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2502 {
2503 struct mlx4_priv *priv = mlx4_priv(dev);
2504 struct mlx4_vport_state *s_info;
2505 int slave;
2506
2507 if ((!mlx4_is_master(dev)) ||
2508 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2509 return -EPROTONOSUPPORT;
2510
2511 slave = mlx4_get_slave_indx(dev, vf);
2512 if (slave < 0)
2513 return -EINVAL;
2514
2515 port = mlx4_slaves_closest_port(dev, slave, port);
2516 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2517 s_info->spoofchk = setting;
2518
2519 return 0;
2520 }
2521 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2522
2523 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2524 {
2525 struct mlx4_priv *priv = mlx4_priv(dev);
2526 struct mlx4_vport_state *s_info;
2527 int slave;
2528
2529 if (!mlx4_is_master(dev))
2530 return -EPROTONOSUPPORT;
2531
2532 slave = mlx4_get_slave_indx(dev, vf);
2533 if (slave < 0)
2534 return -EINVAL;
2535
2536 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2537 ivf->vf = vf;
2538
2539 /* need to convert it to a func */
2540 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2541 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2542 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2543 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2544 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2545 ivf->mac[5] = ((s_info->mac) & 0xff);
2546
2547 ivf->vlan = s_info->default_vlan;
2548 ivf->qos = s_info->default_qos;
2549 ivf->max_tx_rate = s_info->tx_rate;
2550 ivf->min_tx_rate = 0;
2551 ivf->spoofchk = s_info->spoofchk;
2552 ivf->linkstate = s_info->link_state;
2553
2554 return 0;
2555 }
2556 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
2557
2558 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
2559 {
2560 struct mlx4_priv *priv = mlx4_priv(dev);
2561 struct mlx4_vport_state *s_info;
2562 int slave;
2563 u8 link_stat_event;
2564
2565 slave = mlx4_get_slave_indx(dev, vf);
2566 if (slave < 0)
2567 return -EINVAL;
2568
2569 port = mlx4_slaves_closest_port(dev, slave, port);
2570 switch (link_state) {
2571 case IFLA_VF_LINK_STATE_AUTO:
2572 /* get current link state */
2573 if (!priv->sense.do_sense_port[port])
2574 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2575 else
2576 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2577 break;
2578
2579 case IFLA_VF_LINK_STATE_ENABLE:
2580 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2581 break;
2582
2583 case IFLA_VF_LINK_STATE_DISABLE:
2584 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2585 break;
2586
2587 default:
2588 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
2589 link_state, slave, port);
2590 return -EINVAL;
2591 };
2592 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2593 s_info->link_state = link_state;
2594
2595 /* send event */
2596 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
2597
2598 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2599 mlx4_dbg(dev,
2600 "updating vf %d port %d no link state HW enforcment\n",
2601 vf, port);
2602 return 0;
2603 }
2604 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
2605
2606 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port)
2607 {
2608 struct mlx4_priv *priv = mlx4_priv(dev);
2609
2610 if (slave < 1 || slave >= dev->num_slaves ||
2611 port < 1 || port > MLX4_MAX_PORTS)
2612 return 0;
2613
2614 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
2615 MLX4_VF_SMI_ENABLED;
2616 }
2617 EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled);
2618
2619 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port)
2620 {
2621 struct mlx4_priv *priv = mlx4_priv(dev);
2622
2623 if (slave == mlx4_master_func_num(dev))
2624 return 1;
2625
2626 if (slave < 1 || slave >= dev->num_slaves ||
2627 port < 1 || port > MLX4_MAX_PORTS)
2628 return 0;
2629
2630 return priv->mfunc.master.vf_admin[slave].enable_smi[port] ==
2631 MLX4_VF_SMI_ENABLED;
2632 }
2633 EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin);
2634
2635 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
2636 int enabled)
2637 {
2638 struct mlx4_priv *priv = mlx4_priv(dev);
2639
2640 if (slave == mlx4_master_func_num(dev))
2641 return 0;
2642
2643 if (slave < 1 || slave >= dev->num_slaves ||
2644 port < 1 || port > MLX4_MAX_PORTS ||
2645 enabled < 0 || enabled > 1)
2646 return -EINVAL;
2647
2648 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled;
2649 return 0;
2650 }
2651 EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin);
Linux with added FPC-III support