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Linux 3.18.86
[linux/fpc-iii.git] / drivers / net / ethernet / realtek / r8169.c
blobe95cb1faf43e713d8c486fbdcf7aa9a15c0027a8
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
32
33 #include <asm/io.h>
34 #include <asm/irq.h>
35
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
39
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
59
60 #ifdef RTL8169_DEBUG
61 #define assert(expr) \
62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
65 }
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
68 #else
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
72
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
75
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
82
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 32;
86
87 #define MAX_READ_REQUEST_SHIFT 12
88 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91 #define R8169_REGS_SIZE 256
92 #define R8169_NAPI_WEIGHT 64
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98 #define RTL8169_TX_TIMEOUT (6*HZ)
99 #define RTL8169_PHY_TIMEOUT (10*HZ)
100
101 /* write/read MMIO register */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) readl (ioaddr + (reg))
108
109 enum mac_version {
110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
143 RTL_GIGA_MAC_VER_34,
144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
146 RTL_GIGA_MAC_VER_37,
147 RTL_GIGA_MAC_VER_38,
148 RTL_GIGA_MAC_VER_39,
149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
151 RTL_GIGA_MAC_VER_42,
152 RTL_GIGA_MAC_VER_43,
153 RTL_GIGA_MAC_VER_44,
154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
158 RTL_GIGA_MAC_VER_49,
159 RTL_GIGA_MAC_VER_50,
160 RTL_GIGA_MAC_VER_51,
161 RTL_GIGA_MAC_NONE = 0xff,
162 };
163
164 enum rtl_tx_desc_version {
165 RTL_TD_0 = 0,
166 RTL_TD_1 = 1,
167 };
168
169 #define JUMBO_1K ETH_DATA_LEN
170 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
174
175 #define _R(NAME,TD,FW,SZ,B) { \
176 .name = NAME, \
177 .txd_version = TD, \
178 .fw_name = FW, \
179 .jumbo_max = SZ, \
180 .jumbo_tx_csum = B \
181 }
182
183 static const struct {
184 const char *name;
185 enum rtl_tx_desc_version txd_version;
186 const char *fw_name;
187 u16 jumbo_max;
188 bool jumbo_tx_csum;
189 } rtl_chip_infos[] = {
190 /* PCI devices. */
191 [RTL_GIGA_MAC_VER_01] =
192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
193 [RTL_GIGA_MAC_VER_02] =
194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
195 [RTL_GIGA_MAC_VER_03] =
196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
197 [RTL_GIGA_MAC_VER_04] =
198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
199 [RTL_GIGA_MAC_VER_05] =
200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
201 [RTL_GIGA_MAC_VER_06] =
202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
203 /* PCI-E devices. */
204 [RTL_GIGA_MAC_VER_07] =
205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
206 [RTL_GIGA_MAC_VER_08] =
207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
208 [RTL_GIGA_MAC_VER_09] =
209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
210 [RTL_GIGA_MAC_VER_10] =
211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
212 [RTL_GIGA_MAC_VER_11] =
213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
214 [RTL_GIGA_MAC_VER_12] =
215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
216 [RTL_GIGA_MAC_VER_13] =
217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
218 [RTL_GIGA_MAC_VER_14] =
219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
220 [RTL_GIGA_MAC_VER_15] =
221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
222 [RTL_GIGA_MAC_VER_16] =
223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
224 [RTL_GIGA_MAC_VER_17] =
225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
226 [RTL_GIGA_MAC_VER_18] =
227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
228 [RTL_GIGA_MAC_VER_19] =
229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
230 [RTL_GIGA_MAC_VER_20] =
231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
232 [RTL_GIGA_MAC_VER_21] =
233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
234 [RTL_GIGA_MAC_VER_22] =
235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
236 [RTL_GIGA_MAC_VER_23] =
237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
238 [RTL_GIGA_MAC_VER_24] =
239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
240 [RTL_GIGA_MAC_VER_25] =
241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
242 JUMBO_9K, false),
243 [RTL_GIGA_MAC_VER_26] =
244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
245 JUMBO_9K, false),
246 [RTL_GIGA_MAC_VER_27] =
247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
248 [RTL_GIGA_MAC_VER_28] =
249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
250 [RTL_GIGA_MAC_VER_29] =
251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
253 [RTL_GIGA_MAC_VER_30] =
254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
255 JUMBO_1K, true),
256 [RTL_GIGA_MAC_VER_31] =
257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
258 [RTL_GIGA_MAC_VER_32] =
259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
260 JUMBO_9K, false),
261 [RTL_GIGA_MAC_VER_33] =
262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
263 JUMBO_9K, false),
264 [RTL_GIGA_MAC_VER_34] =
265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
266 JUMBO_9K, false),
267 [RTL_GIGA_MAC_VER_35] =
268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
269 JUMBO_9K, false),
270 [RTL_GIGA_MAC_VER_36] =
271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
272 JUMBO_9K, false),
273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
275 JUMBO_1K, true),
276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
278 JUMBO_9K, false),
279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
281 JUMBO_1K, true),
282 [RTL_GIGA_MAC_VER_40] =
283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
284 JUMBO_9K, false),
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
289 JUMBO_9K, false),
290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
292 JUMBO_1K, true),
293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
295 JUMBO_9K, false),
296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
301 JUMBO_9K, false),
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
304 JUMBO_1K, false),
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
307 JUMBO_1K, false),
308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
310 JUMBO_9K, false),
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
313 JUMBO_9K, false),
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
316 JUMBO_9K, false),
317 };
318 #undef _R
319
320 enum cfg_version {
321 RTL_CFG_0 = 0x00,
322 RTL_CFG_1,
323 RTL_CFG_2
324 };
325
326 static const struct pci_device_id rtl8169_pci_tbl[] = {
327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
332 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
333 { PCI_VENDOR_ID_DLINK, 0x4300,
334 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
336 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
337 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
338 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
339 { PCI_VENDOR_ID_LINKSYS, 0x1032,
340 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
341 { 0x0001, 0x8168,
342 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
343 {0,},
344 };
345
346 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
347
348 static int rx_buf_sz = 16383;
349 static int use_dac;
350 static struct {
351 u32 msg_enable;
352 } debug = { -1 };
353
354 enum rtl_registers {
355 MAC0 = 0, /* Ethernet hardware address. */
356 MAC4 = 4,
357 MAR0 = 8, /* Multicast filter. */
358 CounterAddrLow = 0x10,
359 CounterAddrHigh = 0x14,
360 TxDescStartAddrLow = 0x20,
361 TxDescStartAddrHigh = 0x24,
362 TxHDescStartAddrLow = 0x28,
363 TxHDescStartAddrHigh = 0x2c,
364 FLASH = 0x30,
365 ERSR = 0x36,
366 ChipCmd = 0x37,
367 TxPoll = 0x38,
368 IntrMask = 0x3c,
369 IntrStatus = 0x3e,
370
371 TxConfig = 0x40,
372 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
373 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
374
375 RxConfig = 0x44,
376 #define RX128_INT_EN (1 << 15) /* 8111c and later */
377 #define RX_MULTI_EN (1 << 14) /* 8111c only */
378 #define RXCFG_FIFO_SHIFT 13
379 /* No threshold before first PCI xfer */
380 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
381 #define RX_EARLY_OFF (1 << 11)
382 #define RXCFG_DMA_SHIFT 8
383 /* Unlimited maximum PCI burst. */
384 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
385
386 RxMissed = 0x4c,
387 Cfg9346 = 0x50,
388 Config0 = 0x51,
389 Config1 = 0x52,
390 Config2 = 0x53,
391 #define PME_SIGNAL (1 << 5) /* 8168c and later */
392
393 Config3 = 0x54,
394 Config4 = 0x55,
395 Config5 = 0x56,
396 MultiIntr = 0x5c,
397 PHYAR = 0x60,
398 PHYstatus = 0x6c,
399 RxMaxSize = 0xda,
400 CPlusCmd = 0xe0,
401 IntrMitigate = 0xe2,
402 RxDescAddrLow = 0xe4,
403 RxDescAddrHigh = 0xe8,
404 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
405
406 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
407
408 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
409
410 #define TxPacketMax (8064 >> 7)
411 #define EarlySize 0x27
412
413 FuncEvent = 0xf0,
414 FuncEventMask = 0xf4,
415 FuncPresetState = 0xf8,
416 IBCR0 = 0xf8,
417 IBCR2 = 0xf9,
418 IBIMR0 = 0xfa,
419 IBISR0 = 0xfb,
420 FuncForceEvent = 0xfc,
421 };
422
423 enum rtl8110_registers {
424 TBICSR = 0x64,
425 TBI_ANAR = 0x68,
426 TBI_LPAR = 0x6a,
427 };
428
429 enum rtl8168_8101_registers {
430 CSIDR = 0x64,
431 CSIAR = 0x68,
432 #define CSIAR_FLAG 0x80000000
433 #define CSIAR_WRITE_CMD 0x80000000
434 #define CSIAR_BYTE_ENABLE 0x0f
435 #define CSIAR_BYTE_ENABLE_SHIFT 12
436 #define CSIAR_ADDR_MASK 0x0fff
437 #define CSIAR_FUNC_CARD 0x00000000
438 #define CSIAR_FUNC_SDIO 0x00010000
439 #define CSIAR_FUNC_NIC 0x00020000
440 #define CSIAR_FUNC_NIC2 0x00010000
441 PMCH = 0x6f,
442 EPHYAR = 0x80,
443 #define EPHYAR_FLAG 0x80000000
444 #define EPHYAR_WRITE_CMD 0x80000000
445 #define EPHYAR_REG_MASK 0x1f
446 #define EPHYAR_REG_SHIFT 16
447 #define EPHYAR_DATA_MASK 0xffff
448 DLLPR = 0xd0,
449 #define PFM_EN (1 << 6)
450 #define TX_10M_PS_EN (1 << 7)
451 DBG_REG = 0xd1,
452 #define FIX_NAK_1 (1 << 4)
453 #define FIX_NAK_2 (1 << 3)
454 TWSI = 0xd2,
455 MCU = 0xd3,
456 #define NOW_IS_OOB (1 << 7)
457 #define TX_EMPTY (1 << 5)
458 #define RX_EMPTY (1 << 4)
459 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
460 #define EN_NDP (1 << 3)
461 #define EN_OOB_RESET (1 << 2)
462 #define LINK_LIST_RDY (1 << 1)
463 EFUSEAR = 0xdc,
464 #define EFUSEAR_FLAG 0x80000000
465 #define EFUSEAR_WRITE_CMD 0x80000000
466 #define EFUSEAR_READ_CMD 0x00000000
467 #define EFUSEAR_REG_MASK 0x03ff
468 #define EFUSEAR_REG_SHIFT 8
469 #define EFUSEAR_DATA_MASK 0xff
470 MISC_1 = 0xf2,
471 #define PFM_D3COLD_EN (1 << 6)
472 };
473
474 enum rtl8168_registers {
475 LED_FREQ = 0x1a,
476 EEE_LED = 0x1b,
477 ERIDR = 0x70,
478 ERIAR = 0x74,
479 #define ERIAR_FLAG 0x80000000
480 #define ERIAR_WRITE_CMD 0x80000000
481 #define ERIAR_READ_CMD 0x00000000
482 #define ERIAR_ADDR_BYTE_ALIGN 4
483 #define ERIAR_TYPE_SHIFT 16
484 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
485 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
486 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
487 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
488 #define ERIAR_MASK_SHIFT 12
489 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
490 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
491 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
492 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
493 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
494 EPHY_RXER_NUM = 0x7c,
495 OCPDR = 0xb0, /* OCP GPHY access */
496 #define OCPDR_WRITE_CMD 0x80000000
497 #define OCPDR_READ_CMD 0x00000000
498 #define OCPDR_REG_MASK 0x7f
499 #define OCPDR_GPHY_REG_SHIFT 16
500 #define OCPDR_DATA_MASK 0xffff
501 OCPAR = 0xb4,
502 #define OCPAR_FLAG 0x80000000
503 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
504 #define OCPAR_GPHY_READ_CMD 0x0000f060
505 GPHY_OCP = 0xb8,
506 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
507 MISC = 0xf0, /* 8168e only. */
508 #define TXPLA_RST (1 << 29)
509 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
510 #define PWM_EN (1 << 22)
511 #define RXDV_GATED_EN (1 << 19)
512 #define EARLY_TALLY_EN (1 << 16)
513 };
514
515 enum rtl_register_content {
516 /* InterruptStatusBits */
517 SYSErr = 0x8000,
518 PCSTimeout = 0x4000,
519 SWInt = 0x0100,
520 TxDescUnavail = 0x0080,
521 RxFIFOOver = 0x0040,
522 LinkChg = 0x0020,
523 RxOverflow = 0x0010,
524 TxErr = 0x0008,
525 TxOK = 0x0004,
526 RxErr = 0x0002,
527 RxOK = 0x0001,
528
529 /* RxStatusDesc */
530 RxBOVF = (1 << 24),
531 RxFOVF = (1 << 23),
532 RxRWT = (1 << 22),
533 RxRES = (1 << 21),
534 RxRUNT = (1 << 20),
535 RxCRC = (1 << 19),
536
537 /* ChipCmdBits */
538 StopReq = 0x80,
539 CmdReset = 0x10,
540 CmdRxEnb = 0x08,
541 CmdTxEnb = 0x04,
542 RxBufEmpty = 0x01,
543
544 /* TXPoll register p.5 */
545 HPQ = 0x80, /* Poll cmd on the high prio queue */
546 NPQ = 0x40, /* Poll cmd on the low prio queue */
547 FSWInt = 0x01, /* Forced software interrupt */
548
549 /* Cfg9346Bits */
550 Cfg9346_Lock = 0x00,
551 Cfg9346_Unlock = 0xc0,
552
553 /* rx_mode_bits */
554 AcceptErr = 0x20,
555 AcceptRunt = 0x10,
556 AcceptBroadcast = 0x08,
557 AcceptMulticast = 0x04,
558 AcceptMyPhys = 0x02,
559 AcceptAllPhys = 0x01,
560 #define RX_CONFIG_ACCEPT_MASK 0x3f
561
562 /* TxConfigBits */
563 TxInterFrameGapShift = 24,
564 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
565
566 /* Config1 register p.24 */
567 LEDS1 = (1 << 7),
568 LEDS0 = (1 << 6),
569 Speed_down = (1 << 4),
570 MEMMAP = (1 << 3),
571 IOMAP = (1 << 2),
572 VPD = (1 << 1),
573 PMEnable = (1 << 0), /* Power Management Enable */
574
575 /* Config2 register p. 25 */
576 ClkReqEn = (1 << 7), /* Clock Request Enable */
577 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
578 PCI_Clock_66MHz = 0x01,
579 PCI_Clock_33MHz = 0x00,
580
581 /* Config3 register p.25 */
582 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
583 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
584 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
585 Rdy_to_L23 = (1 << 1), /* L23 Enable */
586 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
587
588 /* Config4 register */
589 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
590
591 /* Config5 register p.27 */
592 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
593 MWF = (1 << 5), /* Accept Multicast wakeup frame */
594 UWF = (1 << 4), /* Accept Unicast wakeup frame */
595 Spi_en = (1 << 3),
596 LanWake = (1 << 1), /* LanWake enable/disable */
597 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
598 ASPM_en = (1 << 0), /* ASPM enable */
599
600 /* TBICSR p.28 */
601 TBIReset = 0x80000000,
602 TBILoopback = 0x40000000,
603 TBINwEnable = 0x20000000,
604 TBINwRestart = 0x10000000,
605 TBILinkOk = 0x02000000,
606 TBINwComplete = 0x01000000,
607
608 /* CPlusCmd p.31 */
609 EnableBist = (1 << 15), // 8168 8101
610 Mac_dbgo_oe = (1 << 14), // 8168 8101
611 Normal_mode = (1 << 13), // unused
612 Force_half_dup = (1 << 12), // 8168 8101
613 Force_rxflow_en = (1 << 11), // 8168 8101
614 Force_txflow_en = (1 << 10), // 8168 8101
615 Cxpl_dbg_sel = (1 << 9), // 8168 8101
616 ASF = (1 << 8), // 8168 8101
617 PktCntrDisable = (1 << 7), // 8168 8101
618 Mac_dbgo_sel = 0x001c, // 8168
619 RxVlan = (1 << 6),
620 RxChkSum = (1 << 5),
621 PCIDAC = (1 << 4),
622 PCIMulRW = (1 << 3),
623 INTT_0 = 0x0000, // 8168
624 INTT_1 = 0x0001, // 8168
625 INTT_2 = 0x0002, // 8168
626 INTT_3 = 0x0003, // 8168
627
628 /* rtl8169_PHYstatus */
629 TBI_Enable = 0x80,
630 TxFlowCtrl = 0x40,
631 RxFlowCtrl = 0x20,
632 _1000bpsF = 0x10,
633 _100bps = 0x08,
634 _10bps = 0x04,
635 LinkStatus = 0x02,
636 FullDup = 0x01,
637
638 /* _TBICSRBit */
639 TBILinkOK = 0x02000000,
640
641 /* DumpCounterCommand */
642 CounterDump = 0x8,
643
644 /* magic enable v2 */
645 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
646 };
647
648 enum rtl_desc_bit {
649 /* First doubleword. */
650 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
651 RingEnd = (1 << 30), /* End of descriptor ring */
652 FirstFrag = (1 << 29), /* First segment of a packet */
653 LastFrag = (1 << 28), /* Final segment of a packet */
654 };
655
656 /* Generic case. */
657 enum rtl_tx_desc_bit {
658 /* First doubleword. */
659 TD_LSO = (1 << 27), /* Large Send Offload */
660 #define TD_MSS_MAX 0x07ffu /* MSS value */
661
662 /* Second doubleword. */
663 TxVlanTag = (1 << 17), /* Add VLAN tag */
664 };
665
666 /* 8169, 8168b and 810x except 8102e. */
667 enum rtl_tx_desc_bit_0 {
668 /* First doubleword. */
669 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
670 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
671 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
672 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
673 };
674
675 /* 8102e, 8168c and beyond. */
676 enum rtl_tx_desc_bit_1 {
677 /* First doubleword. */
678 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
679 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
680 #define GTTCPHO_SHIFT 18
681 #define GTTCPHO_MAX 0x7fU
682
683 /* Second doubleword. */
684 #define TCPHO_SHIFT 18
685 #define TCPHO_MAX 0x3ffU
686 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
687 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
688 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
689 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
690 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
691 };
692
693 enum rtl_rx_desc_bit {
694 /* Rx private */
695 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
696 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
697
698 #define RxProtoUDP (PID1)
699 #define RxProtoTCP (PID0)
700 #define RxProtoIP (PID1 | PID0)
701 #define RxProtoMask RxProtoIP
702
703 IPFail = (1 << 16), /* IP checksum failed */
704 UDPFail = (1 << 15), /* UDP/IP checksum failed */
705 TCPFail = (1 << 14), /* TCP/IP checksum failed */
706 RxVlanTag = (1 << 16), /* VLAN tag available */
707 };
708
709 #define RsvdMask 0x3fffc000
710
711 struct TxDesc {
712 __le32 opts1;
713 __le32 opts2;
714 __le64 addr;
715 };
716
717 struct RxDesc {
718 __le32 opts1;
719 __le32 opts2;
720 __le64 addr;
721 };
722
723 struct ring_info {
724 struct sk_buff *skb;
725 u32 len;
726 u8 __pad[sizeof(void *) - sizeof(u32)];
727 };
728
729 enum features {
730 RTL_FEATURE_WOL = (1 << 0),
731 RTL_FEATURE_MSI = (1 << 1),
732 RTL_FEATURE_GMII = (1 << 2),
733 };
734
735 struct rtl8169_counters {
736 __le64 tx_packets;
737 __le64 rx_packets;
738 __le64 tx_errors;
739 __le32 rx_errors;
740 __le16 rx_missed;
741 __le16 align_errors;
742 __le32 tx_one_collision;
743 __le32 tx_multi_collision;
744 __le64 rx_unicast;
745 __le64 rx_broadcast;
746 __le32 rx_multicast;
747 __le16 tx_aborted;
748 __le16 tx_underun;
749 };
750
751 enum rtl_flag {
752 RTL_FLAG_TASK_ENABLED,
753 RTL_FLAG_TASK_SLOW_PENDING,
754 RTL_FLAG_TASK_RESET_PENDING,
755 RTL_FLAG_TASK_PHY_PENDING,
756 RTL_FLAG_MAX
757 };
758
759 struct rtl8169_stats {
760 u64 packets;
761 u64 bytes;
762 struct u64_stats_sync syncp;
763 };
764
765 struct rtl8169_private {
766 void __iomem *mmio_addr; /* memory map physical address */
767 struct pci_dev *pci_dev;
768 struct net_device *dev;
769 struct napi_struct napi;
770 u32 msg_enable;
771 u16 txd_version;
772 u16 mac_version;
773 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
774 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
775 u32 dirty_tx;
776 struct rtl8169_stats rx_stats;
777 struct rtl8169_stats tx_stats;
778 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
779 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
780 dma_addr_t TxPhyAddr;
781 dma_addr_t RxPhyAddr;
782 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
783 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
784 struct timer_list timer;
785 u16 cp_cmd;
786
787 u16 event_slow;
788
789 struct mdio_ops {
790 void (*write)(struct rtl8169_private *, int, int);
791 int (*read)(struct rtl8169_private *, int);
792 } mdio_ops;
793
794 struct pll_power_ops {
795 void (*down)(struct rtl8169_private *);
796 void (*up)(struct rtl8169_private *);
797 } pll_power_ops;
798
799 struct jumbo_ops {
800 void (*enable)(struct rtl8169_private *);
801 void (*disable)(struct rtl8169_private *);
802 } jumbo_ops;
803
804 struct csi_ops {
805 void (*write)(struct rtl8169_private *, int, int);
806 u32 (*read)(struct rtl8169_private *, int);
807 } csi_ops;
808
809 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
810 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
811 void (*phy_reset_enable)(struct rtl8169_private *tp);
812 void (*hw_start)(struct net_device *);
813 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
814 unsigned int (*link_ok)(void __iomem *);
815 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
816 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
817
818 struct {
819 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
820 struct mutex mutex;
821 struct work_struct work;
822 } wk;
823
824 unsigned features;
825
826 struct mii_if_info mii;
827 struct rtl8169_counters counters;
828 u32 saved_wolopts;
829 u32 opts1_mask;
830
831 struct rtl_fw {
832 const struct firmware *fw;
833
834 #define RTL_VER_SIZE 32
835
836 char version[RTL_VER_SIZE];
837
838 struct rtl_fw_phy_action {
839 __le32 *code;
840 size_t size;
841 } phy_action;
842 } *rtl_fw;
843 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
844
845 u32 ocp_base;
846 };
847
848 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
849 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
850 module_param(use_dac, int, 0);
851 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
852 module_param_named(debug, debug.msg_enable, int, 0);
853 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
854 MODULE_LICENSE("GPL");
855 MODULE_VERSION(RTL8169_VERSION);
856 MODULE_FIRMWARE(FIRMWARE_8168D_1);
857 MODULE_FIRMWARE(FIRMWARE_8168D_2);
858 MODULE_FIRMWARE(FIRMWARE_8168E_1);
859 MODULE_FIRMWARE(FIRMWARE_8168E_2);
860 MODULE_FIRMWARE(FIRMWARE_8168E_3);
861 MODULE_FIRMWARE(FIRMWARE_8105E_1);
862 MODULE_FIRMWARE(FIRMWARE_8168F_1);
863 MODULE_FIRMWARE(FIRMWARE_8168F_2);
864 MODULE_FIRMWARE(FIRMWARE_8402_1);
865 MODULE_FIRMWARE(FIRMWARE_8411_1);
866 MODULE_FIRMWARE(FIRMWARE_8411_2);
867 MODULE_FIRMWARE(FIRMWARE_8106E_1);
868 MODULE_FIRMWARE(FIRMWARE_8106E_2);
869 MODULE_FIRMWARE(FIRMWARE_8168G_2);
870 MODULE_FIRMWARE(FIRMWARE_8168G_3);
871 MODULE_FIRMWARE(FIRMWARE_8168H_1);
872 MODULE_FIRMWARE(FIRMWARE_8168H_2);
873 MODULE_FIRMWARE(FIRMWARE_8107E_1);
874 MODULE_FIRMWARE(FIRMWARE_8107E_2);
875
876 static void rtl_lock_work(struct rtl8169_private *tp)
877 {
878 mutex_lock(&tp->wk.mutex);
879 }
880
881 static void rtl_unlock_work(struct rtl8169_private *tp)
882 {
883 mutex_unlock(&tp->wk.mutex);
884 }
885
886 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
887 {
888 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
889 PCI_EXP_DEVCTL_READRQ, force);
890 }
891
892 struct rtl_cond {
893 bool (*check)(struct rtl8169_private *);
894 const char *msg;
895 };
896
897 static void rtl_udelay(unsigned int d)
898 {
899 udelay(d);
900 }
901
902 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
903 void (*delay)(unsigned int), unsigned int d, int n,
904 bool high)
905 {
906 int i;
907
908 for (i = 0; i < n; i++) {
909 delay(d);
910 if (c->check(tp) == high)
911 return true;
912 }
913 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
914 c->msg, !high, n, d);
915 return false;
916 }
917
918 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
919 const struct rtl_cond *c,
920 unsigned int d, int n)
921 {
922 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
923 }
924
925 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
926 const struct rtl_cond *c,
927 unsigned int d, int n)
928 {
929 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
930 }
931
932 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
933 const struct rtl_cond *c,
934 unsigned int d, int n)
935 {
936 return rtl_loop_wait(tp, c, msleep, d, n, true);
937 }
938
939 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
940 const struct rtl_cond *c,
941 unsigned int d, int n)
942 {
943 return rtl_loop_wait(tp, c, msleep, d, n, false);
944 }
945
946 #define DECLARE_RTL_COND(name) \
947 static bool name ## _check(struct rtl8169_private *); \
948 \
949 static const struct rtl_cond name = { \
950 .check = name ## _check, \
951 .msg = #name \
952 }; \
953 \
954 static bool name ## _check(struct rtl8169_private *tp)
955
956 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
957 {
958 if (reg & 0xffff0001) {
959 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
960 return true;
961 }
962 return false;
963 }
964
965 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
966 {
967 void __iomem *ioaddr = tp->mmio_addr;
968
969 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
970 }
971
972 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
973 {
974 void __iomem *ioaddr = tp->mmio_addr;
975
976 if (rtl_ocp_reg_failure(tp, reg))
977 return;
978
979 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
980
981 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
982 }
983
984 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
985 {
986 void __iomem *ioaddr = tp->mmio_addr;
987
988 if (rtl_ocp_reg_failure(tp, reg))
989 return 0;
990
991 RTL_W32(GPHY_OCP, reg << 15);
992
993 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
994 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
995 }
996
997 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
998 {
999 void __iomem *ioaddr = tp->mmio_addr;
1000
1001 if (rtl_ocp_reg_failure(tp, reg))
1002 return;
1003
1004 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1005 }
1006
1007 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1008 {
1009 void __iomem *ioaddr = tp->mmio_addr;
1010
1011 if (rtl_ocp_reg_failure(tp, reg))
1012 return 0;
1013
1014 RTL_W32(OCPDR, reg << 15);
1015
1016 return RTL_R32(OCPDR);
1017 }
1018
1019 #define OCP_STD_PHY_BASE 0xa400
1020
1021 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1022 {
1023 if (reg == 0x1f) {
1024 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1025 return;
1026 }
1027
1028 if (tp->ocp_base != OCP_STD_PHY_BASE)
1029 reg -= 0x10;
1030
1031 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1032 }
1033
1034 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1035 {
1036 if (tp->ocp_base != OCP_STD_PHY_BASE)
1037 reg -= 0x10;
1038
1039 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1040 }
1041
1042 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1043 {
1044 if (reg == 0x1f) {
1045 tp->ocp_base = value << 4;
1046 return;
1047 }
1048
1049 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1050 }
1051
1052 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1053 {
1054 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1055 }
1056
1057 DECLARE_RTL_COND(rtl_phyar_cond)
1058 {
1059 void __iomem *ioaddr = tp->mmio_addr;
1060
1061 return RTL_R32(PHYAR) & 0x80000000;
1062 }
1063
1064 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1065 {
1066 void __iomem *ioaddr = tp->mmio_addr;
1067
1068 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1069
1070 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1071 /*
1072 * According to hardware specs a 20us delay is required after write
1073 * complete indication, but before sending next command.
1074 */
1075 udelay(20);
1076 }
1077
1078 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1079 {
1080 void __iomem *ioaddr = tp->mmio_addr;
1081 int value;
1082
1083 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1084
1085 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1086 RTL_R32(PHYAR) & 0xffff : ~0;
1087
1088 /*
1089 * According to hardware specs a 20us delay is required after read
1090 * complete indication, but before sending next command.
1091 */
1092 udelay(20);
1093
1094 return value;
1095 }
1096
1097 DECLARE_RTL_COND(rtl_ocpar_cond)
1098 {
1099 void __iomem *ioaddr = tp->mmio_addr;
1100
1101 return RTL_R32(OCPAR) & OCPAR_FLAG;
1102 }
1103
1104 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1105 {
1106 void __iomem *ioaddr = tp->mmio_addr;
1107
1108 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1109 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1110 RTL_W32(EPHY_RXER_NUM, 0);
1111
1112 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1113 }
1114
1115 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1116 {
1117 r8168dp_1_mdio_access(tp, reg,
1118 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1119 }
1120
1121 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1122 {
1123 void __iomem *ioaddr = tp->mmio_addr;
1124
1125 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1126
1127 mdelay(1);
1128 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1129 RTL_W32(EPHY_RXER_NUM, 0);
1130
1131 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1132 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1133 }
1134
1135 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1136
1137 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1138 {
1139 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1140 }
1141
1142 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1143 {
1144 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1145 }
1146
1147 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1148 {
1149 void __iomem *ioaddr = tp->mmio_addr;
1150
1151 r8168dp_2_mdio_start(ioaddr);
1152
1153 r8169_mdio_write(tp, reg, value);
1154
1155 r8168dp_2_mdio_stop(ioaddr);
1156 }
1157
1158 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1159 {
1160 void __iomem *ioaddr = tp->mmio_addr;
1161 int value;
1162
1163 r8168dp_2_mdio_start(ioaddr);
1164
1165 value = r8169_mdio_read(tp, reg);
1166
1167 r8168dp_2_mdio_stop(ioaddr);
1168
1169 return value;
1170 }
1171
1172 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1173 {
1174 tp->mdio_ops.write(tp, location, val);
1175 }
1176
1177 static int rtl_readphy(struct rtl8169_private *tp, int location)
1178 {
1179 return tp->mdio_ops.read(tp, location);
1180 }
1181
1182 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1183 {
1184 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1185 }
1186
1187 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1188 {
1189 int val;
1190
1191 val = rtl_readphy(tp, reg_addr);
1192 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1193 }
1194
1195 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1196 int val)
1197 {
1198 struct rtl8169_private *tp = netdev_priv(dev);
1199
1200 rtl_writephy(tp, location, val);
1201 }
1202
1203 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1204 {
1205 struct rtl8169_private *tp = netdev_priv(dev);
1206
1207 return rtl_readphy(tp, location);
1208 }
1209
1210 DECLARE_RTL_COND(rtl_ephyar_cond)
1211 {
1212 void __iomem *ioaddr = tp->mmio_addr;
1213
1214 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1215 }
1216
1217 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1218 {
1219 void __iomem *ioaddr = tp->mmio_addr;
1220
1221 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1222 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1223
1224 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1225
1226 udelay(10);
1227 }
1228
1229 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1230 {
1231 void __iomem *ioaddr = tp->mmio_addr;
1232
1233 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1234
1235 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1236 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1237 }
1238
1239 DECLARE_RTL_COND(rtl_eriar_cond)
1240 {
1241 void __iomem *ioaddr = tp->mmio_addr;
1242
1243 return RTL_R32(ERIAR) & ERIAR_FLAG;
1244 }
1245
1246 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1247 u32 val, int type)
1248 {
1249 void __iomem *ioaddr = tp->mmio_addr;
1250
1251 BUG_ON((addr & 3) || (mask == 0));
1252 RTL_W32(ERIDR, val);
1253 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1254
1255 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1256 }
1257
1258 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1259 {
1260 void __iomem *ioaddr = tp->mmio_addr;
1261
1262 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1263
1264 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1265 RTL_R32(ERIDR) : ~0;
1266 }
1267
1268 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1269 u32 m, int type)
1270 {
1271 u32 val;
1272
1273 val = rtl_eri_read(tp, addr, type);
1274 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1275 }
1276
1277 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1278 {
1279 void __iomem *ioaddr = tp->mmio_addr;
1280
1281 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1282 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1283 RTL_R32(OCPDR) : ~0;
1284 }
1285
1286 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1287 {
1288 return rtl_eri_read(tp, reg, ERIAR_OOB);
1289 }
1290
1291 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1292 {
1293 switch (tp->mac_version) {
1294 case RTL_GIGA_MAC_VER_27:
1295 case RTL_GIGA_MAC_VER_28:
1296 case RTL_GIGA_MAC_VER_31:
1297 return r8168dp_ocp_read(tp, mask, reg);
1298 case RTL_GIGA_MAC_VER_49:
1299 case RTL_GIGA_MAC_VER_50:
1300 case RTL_GIGA_MAC_VER_51:
1301 return r8168ep_ocp_read(tp, mask, reg);
1302 default:
1303 BUG();
1304 return ~0;
1305 }
1306 }
1307
1308 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1309 u32 data)
1310 {
1311 void __iomem *ioaddr = tp->mmio_addr;
1312
1313 RTL_W32(OCPDR, data);
1314 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1315 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1316 }
1317
1318 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1319 u32 data)
1320 {
1321 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1322 data, ERIAR_OOB);
1323 }
1324
1325 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1326 {
1327 switch (tp->mac_version) {
1328 case RTL_GIGA_MAC_VER_27:
1329 case RTL_GIGA_MAC_VER_28:
1330 case RTL_GIGA_MAC_VER_31:
1331 r8168dp_ocp_write(tp, mask, reg, data);
1332 break;
1333 case RTL_GIGA_MAC_VER_49:
1334 case RTL_GIGA_MAC_VER_50:
1335 case RTL_GIGA_MAC_VER_51:
1336 r8168ep_ocp_write(tp, mask, reg, data);
1337 break;
1338 default:
1339 BUG();
1340 break;
1341 }
1342 }
1343
1344 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1345 {
1346 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1347
1348 ocp_write(tp, 0x1, 0x30, 0x00000001);
1349 }
1350
1351 #define OOB_CMD_RESET 0x00
1352 #define OOB_CMD_DRIVER_START 0x05
1353 #define OOB_CMD_DRIVER_STOP 0x06
1354
1355 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1356 {
1357 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1358 }
1359
1360 DECLARE_RTL_COND(rtl_ocp_read_cond)
1361 {
1362 u16 reg;
1363
1364 reg = rtl8168_get_ocp_reg(tp);
1365
1366 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1367 }
1368
1369 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1370 {
1371 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1372 }
1373
1374 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1375 {
1376 void __iomem *ioaddr = tp->mmio_addr;
1377
1378 return RTL_R8(IBISR0) & 0x02;
1379 }
1380
1381 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1382 {
1383 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1384 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1385 }
1386
1387 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1388 {
1389 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1390 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1391 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1392 }
1393
1394 static void rtl8168_driver_start(struct rtl8169_private *tp)
1395 {
1396 switch (tp->mac_version) {
1397 case RTL_GIGA_MAC_VER_27:
1398 case RTL_GIGA_MAC_VER_28:
1399 case RTL_GIGA_MAC_VER_31:
1400 rtl8168dp_driver_start(tp);
1401 break;
1402 case RTL_GIGA_MAC_VER_49:
1403 case RTL_GIGA_MAC_VER_50:
1404 case RTL_GIGA_MAC_VER_51:
1405 rtl8168ep_driver_start(tp);
1406 break;
1407 default:
1408 BUG();
1409 break;
1410 }
1411 }
1412
1413 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1414 {
1415 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1416 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1417 }
1418
1419 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1420 {
1421 void __iomem *ioaddr = tp->mmio_addr;
1422
1423 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1424 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1425 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1426 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1427 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1428 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1429 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1430 }
1431
1432 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1433 {
1434 switch (tp->mac_version) {
1435 case RTL_GIGA_MAC_VER_27:
1436 case RTL_GIGA_MAC_VER_28:
1437 case RTL_GIGA_MAC_VER_31:
1438 rtl8168dp_driver_stop(tp);
1439 break;
1440 case RTL_GIGA_MAC_VER_49:
1441 case RTL_GIGA_MAC_VER_50:
1442 case RTL_GIGA_MAC_VER_51:
1443 rtl8168ep_driver_stop(tp);
1444 break;
1445 default:
1446 BUG();
1447 break;
1448 }
1449 }
1450
1451 static int r8168dp_check_dash(struct rtl8169_private *tp)
1452 {
1453 u16 reg = rtl8168_get_ocp_reg(tp);
1454
1455 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1456 }
1457
1458 static int r8168ep_check_dash(struct rtl8169_private *tp)
1459 {
1460 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1461 }
1462
1463 static int r8168_check_dash(struct rtl8169_private *tp)
1464 {
1465 switch (tp->mac_version) {
1466 case RTL_GIGA_MAC_VER_27:
1467 case RTL_GIGA_MAC_VER_28:
1468 case RTL_GIGA_MAC_VER_31:
1469 return r8168dp_check_dash(tp);
1470 case RTL_GIGA_MAC_VER_49:
1471 case RTL_GIGA_MAC_VER_50:
1472 case RTL_GIGA_MAC_VER_51:
1473 return r8168ep_check_dash(tp);
1474 default:
1475 return 0;
1476 }
1477 }
1478
1479 struct exgmac_reg {
1480 u16 addr;
1481 u16 mask;
1482 u32 val;
1483 };
1484
1485 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1486 const struct exgmac_reg *r, int len)
1487 {
1488 while (len-- > 0) {
1489 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1490 r++;
1491 }
1492 }
1493
1494 DECLARE_RTL_COND(rtl_efusear_cond)
1495 {
1496 void __iomem *ioaddr = tp->mmio_addr;
1497
1498 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1499 }
1500
1501 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1502 {
1503 void __iomem *ioaddr = tp->mmio_addr;
1504
1505 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1506
1507 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1508 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1509 }
1510
1511 static u16 rtl_get_events(struct rtl8169_private *tp)
1512 {
1513 void __iomem *ioaddr = tp->mmio_addr;
1514
1515 return RTL_R16(IntrStatus);
1516 }
1517
1518 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1519 {
1520 void __iomem *ioaddr = tp->mmio_addr;
1521
1522 RTL_W16(IntrStatus, bits);
1523 mmiowb();
1524 }
1525
1526 static void rtl_irq_disable(struct rtl8169_private *tp)
1527 {
1528 void __iomem *ioaddr = tp->mmio_addr;
1529
1530 RTL_W16(IntrMask, 0);
1531 mmiowb();
1532 }
1533
1534 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1535 {
1536 void __iomem *ioaddr = tp->mmio_addr;
1537
1538 RTL_W16(IntrMask, bits);
1539 }
1540
1541 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1542 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1543 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1544
1545 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1546 {
1547 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1548 }
1549
1550 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1551 {
1552 void __iomem *ioaddr = tp->mmio_addr;
1553
1554 rtl_irq_disable(tp);
1555 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1556 RTL_R8(ChipCmd);
1557 }
1558
1559 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1560 {
1561 void __iomem *ioaddr = tp->mmio_addr;
1562
1563 return RTL_R32(TBICSR) & TBIReset;
1564 }
1565
1566 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1567 {
1568 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1569 }
1570
1571 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1572 {
1573 return RTL_R32(TBICSR) & TBILinkOk;
1574 }
1575
1576 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1577 {
1578 return RTL_R8(PHYstatus) & LinkStatus;
1579 }
1580
1581 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1582 {
1583 void __iomem *ioaddr = tp->mmio_addr;
1584
1585 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1586 }
1587
1588 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1589 {
1590 unsigned int val;
1591
1592 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1593 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1594 }
1595
1596 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1597 {
1598 void __iomem *ioaddr = tp->mmio_addr;
1599 struct net_device *dev = tp->dev;
1600
1601 if (!netif_running(dev))
1602 return;
1603
1604 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1605 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1606 if (RTL_R8(PHYstatus) & _1000bpsF) {
1607 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1608 ERIAR_EXGMAC);
1609 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1610 ERIAR_EXGMAC);
1611 } else if (RTL_R8(PHYstatus) & _100bps) {
1612 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1613 ERIAR_EXGMAC);
1614 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1615 ERIAR_EXGMAC);
1616 } else {
1617 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1618 ERIAR_EXGMAC);
1619 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1620 ERIAR_EXGMAC);
1621 }
1622 /* Reset packet filter */
1623 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1624 ERIAR_EXGMAC);
1625 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1626 ERIAR_EXGMAC);
1627 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1628 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1629 if (RTL_R8(PHYstatus) & _1000bpsF) {
1630 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1631 ERIAR_EXGMAC);
1632 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1633 ERIAR_EXGMAC);
1634 } else {
1635 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1636 ERIAR_EXGMAC);
1637 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1638 ERIAR_EXGMAC);
1639 }
1640 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1641 if (RTL_R8(PHYstatus) & _10bps) {
1642 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1643 ERIAR_EXGMAC);
1644 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1645 ERIAR_EXGMAC);
1646 } else {
1647 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1648 ERIAR_EXGMAC);
1649 }
1650 }
1651 }
1652
1653 static void __rtl8169_check_link_status(struct net_device *dev,
1654 struct rtl8169_private *tp,
1655 void __iomem *ioaddr, bool pm)
1656 {
1657 if (tp->link_ok(ioaddr)) {
1658 rtl_link_chg_patch(tp);
1659 /* This is to cancel a scheduled suspend if there's one. */
1660 if (pm)
1661 pm_request_resume(&tp->pci_dev->dev);
1662 netif_carrier_on(dev);
1663 if (net_ratelimit())
1664 netif_info(tp, ifup, dev, "link up\n");
1665 } else {
1666 netif_carrier_off(dev);
1667 netif_info(tp, ifdown, dev, "link down\n");
1668 if (pm)
1669 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1670 }
1671 }
1672
1673 static void rtl8169_check_link_status(struct net_device *dev,
1674 struct rtl8169_private *tp,
1675 void __iomem *ioaddr)
1676 {
1677 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1678 }
1679
1680 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1681
1682 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1683 {
1684 void __iomem *ioaddr = tp->mmio_addr;
1685 u8 options;
1686 u32 wolopts = 0;
1687
1688 options = RTL_R8(Config1);
1689 if (!(options & PMEnable))
1690 return 0;
1691
1692 options = RTL_R8(Config3);
1693 if (options & LinkUp)
1694 wolopts |= WAKE_PHY;
1695 switch (tp->mac_version) {
1696 case RTL_GIGA_MAC_VER_34:
1697 case RTL_GIGA_MAC_VER_35:
1698 case RTL_GIGA_MAC_VER_36:
1699 case RTL_GIGA_MAC_VER_37:
1700 case RTL_GIGA_MAC_VER_38:
1701 case RTL_GIGA_MAC_VER_40:
1702 case RTL_GIGA_MAC_VER_41:
1703 case RTL_GIGA_MAC_VER_42:
1704 case RTL_GIGA_MAC_VER_43:
1705 case RTL_GIGA_MAC_VER_44:
1706 case RTL_GIGA_MAC_VER_45:
1707 case RTL_GIGA_MAC_VER_46:
1708 case RTL_GIGA_MAC_VER_47:
1709 case RTL_GIGA_MAC_VER_48:
1710 case RTL_GIGA_MAC_VER_49:
1711 case RTL_GIGA_MAC_VER_50:
1712 case RTL_GIGA_MAC_VER_51:
1713 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1714 wolopts |= WAKE_MAGIC;
1715 break;
1716 default:
1717 if (options & MagicPacket)
1718 wolopts |= WAKE_MAGIC;
1719 break;
1720 }
1721
1722 options = RTL_R8(Config5);
1723 if (options & UWF)
1724 wolopts |= WAKE_UCAST;
1725 if (options & BWF)
1726 wolopts |= WAKE_BCAST;
1727 if (options & MWF)
1728 wolopts |= WAKE_MCAST;
1729
1730 return wolopts;
1731 }
1732
1733 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1734 {
1735 struct rtl8169_private *tp = netdev_priv(dev);
1736
1737 rtl_lock_work(tp);
1738
1739 wol->supported = WAKE_ANY;
1740 wol->wolopts = __rtl8169_get_wol(tp);
1741
1742 rtl_unlock_work(tp);
1743 }
1744
1745 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1746 {
1747 void __iomem *ioaddr = tp->mmio_addr;
1748 unsigned int i, tmp;
1749 static const struct {
1750 u32 opt;
1751 u16 reg;
1752 u8 mask;
1753 } cfg[] = {
1754 { WAKE_PHY, Config3, LinkUp },
1755 { WAKE_UCAST, Config5, UWF },
1756 { WAKE_BCAST, Config5, BWF },
1757 { WAKE_MCAST, Config5, MWF },
1758 { WAKE_ANY, Config5, LanWake },
1759 { WAKE_MAGIC, Config3, MagicPacket }
1760 };
1761 u8 options;
1762
1763 RTL_W8(Cfg9346, Cfg9346_Unlock);
1764
1765 switch (tp->mac_version) {
1766 case RTL_GIGA_MAC_VER_34:
1767 case RTL_GIGA_MAC_VER_35:
1768 case RTL_GIGA_MAC_VER_36:
1769 case RTL_GIGA_MAC_VER_37:
1770 case RTL_GIGA_MAC_VER_38:
1771 case RTL_GIGA_MAC_VER_40:
1772 case RTL_GIGA_MAC_VER_41:
1773 case RTL_GIGA_MAC_VER_42:
1774 case RTL_GIGA_MAC_VER_43:
1775 case RTL_GIGA_MAC_VER_44:
1776 case RTL_GIGA_MAC_VER_45:
1777 case RTL_GIGA_MAC_VER_46:
1778 case RTL_GIGA_MAC_VER_47:
1779 case RTL_GIGA_MAC_VER_48:
1780 case RTL_GIGA_MAC_VER_49:
1781 case RTL_GIGA_MAC_VER_50:
1782 case RTL_GIGA_MAC_VER_51:
1783 tmp = ARRAY_SIZE(cfg) - 1;
1784 if (wolopts & WAKE_MAGIC)
1785 rtl_w0w1_eri(tp,
1786 0x0dc,
1787 ERIAR_MASK_0100,
1788 MagicPacket_v2,
1789 0x0000,
1790 ERIAR_EXGMAC);
1791 else
1792 rtl_w0w1_eri(tp,
1793 0x0dc,
1794 ERIAR_MASK_0100,
1795 0x0000,
1796 MagicPacket_v2,
1797 ERIAR_EXGMAC);
1798 break;
1799 default:
1800 tmp = ARRAY_SIZE(cfg);
1801 break;
1802 }
1803
1804 for (i = 0; i < tmp; i++) {
1805 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1806 if (wolopts & cfg[i].opt)
1807 options |= cfg[i].mask;
1808 RTL_W8(cfg[i].reg, options);
1809 }
1810
1811 switch (tp->mac_version) {
1812 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1813 options = RTL_R8(Config1) & ~PMEnable;
1814 if (wolopts)
1815 options |= PMEnable;
1816 RTL_W8(Config1, options);
1817 break;
1818 default:
1819 options = RTL_R8(Config2) & ~PME_SIGNAL;
1820 if (wolopts)
1821 options |= PME_SIGNAL;
1822 RTL_W8(Config2, options);
1823 break;
1824 }
1825
1826 RTL_W8(Cfg9346, Cfg9346_Lock);
1827 }
1828
1829 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1830 {
1831 struct rtl8169_private *tp = netdev_priv(dev);
1832
1833 rtl_lock_work(tp);
1834
1835 if (wol->wolopts)
1836 tp->features |= RTL_FEATURE_WOL;
1837 else
1838 tp->features &= ~RTL_FEATURE_WOL;
1839 __rtl8169_set_wol(tp, wol->wolopts);
1840
1841 rtl_unlock_work(tp);
1842
1843 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1844
1845 return 0;
1846 }
1847
1848 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1849 {
1850 return rtl_chip_infos[tp->mac_version].fw_name;
1851 }
1852
1853 static void rtl8169_get_drvinfo(struct net_device *dev,
1854 struct ethtool_drvinfo *info)
1855 {
1856 struct rtl8169_private *tp = netdev_priv(dev);
1857 struct rtl_fw *rtl_fw = tp->rtl_fw;
1858
1859 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1860 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1861 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1862 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1863 if (!IS_ERR_OR_NULL(rtl_fw))
1864 strlcpy(info->fw_version, rtl_fw->version,
1865 sizeof(info->fw_version));
1866 }
1867
1868 static int rtl8169_get_regs_len(struct net_device *dev)
1869 {
1870 return R8169_REGS_SIZE;
1871 }
1872
1873 static int rtl8169_set_speed_tbi(struct net_device *dev,
1874 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1875 {
1876 struct rtl8169_private *tp = netdev_priv(dev);
1877 void __iomem *ioaddr = tp->mmio_addr;
1878 int ret = 0;
1879 u32 reg;
1880
1881 reg = RTL_R32(TBICSR);
1882 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1883 (duplex == DUPLEX_FULL)) {
1884 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1885 } else if (autoneg == AUTONEG_ENABLE)
1886 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1887 else {
1888 netif_warn(tp, link, dev,
1889 "incorrect speed setting refused in TBI mode\n");
1890 ret = -EOPNOTSUPP;
1891 }
1892
1893 return ret;
1894 }
1895
1896 static int rtl8169_set_speed_xmii(struct net_device *dev,
1897 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1898 {
1899 struct rtl8169_private *tp = netdev_priv(dev);
1900 int giga_ctrl, bmcr;
1901 int rc = -EINVAL;
1902
1903 rtl_writephy(tp, 0x1f, 0x0000);
1904
1905 if (autoneg == AUTONEG_ENABLE) {
1906 int auto_nego;
1907
1908 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1909 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1910 ADVERTISE_100HALF | ADVERTISE_100FULL);
1911
1912 if (adv & ADVERTISED_10baseT_Half)
1913 auto_nego |= ADVERTISE_10HALF;
1914 if (adv & ADVERTISED_10baseT_Full)
1915 auto_nego |= ADVERTISE_10FULL;
1916 if (adv & ADVERTISED_100baseT_Half)
1917 auto_nego |= ADVERTISE_100HALF;
1918 if (adv & ADVERTISED_100baseT_Full)
1919 auto_nego |= ADVERTISE_100FULL;
1920
1921 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1922
1923 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1924 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1925
1926 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1927 if (tp->mii.supports_gmii) {
1928 if (adv & ADVERTISED_1000baseT_Half)
1929 giga_ctrl |= ADVERTISE_1000HALF;
1930 if (adv & ADVERTISED_1000baseT_Full)
1931 giga_ctrl |= ADVERTISE_1000FULL;
1932 } else if (adv & (ADVERTISED_1000baseT_Half |
1933 ADVERTISED_1000baseT_Full)) {
1934 netif_info(tp, link, dev,
1935 "PHY does not support 1000Mbps\n");
1936 goto out;
1937 }
1938
1939 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1940
1941 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1942 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1943 } else {
1944 giga_ctrl = 0;
1945
1946 if (speed == SPEED_10)
1947 bmcr = 0;
1948 else if (speed == SPEED_100)
1949 bmcr = BMCR_SPEED100;
1950 else
1951 goto out;
1952
1953 if (duplex == DUPLEX_FULL)
1954 bmcr |= BMCR_FULLDPLX;
1955 }
1956
1957 rtl_writephy(tp, MII_BMCR, bmcr);
1958
1959 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1960 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1961 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1962 rtl_writephy(tp, 0x17, 0x2138);
1963 rtl_writephy(tp, 0x0e, 0x0260);
1964 } else {
1965 rtl_writephy(tp, 0x17, 0x2108);
1966 rtl_writephy(tp, 0x0e, 0x0000);
1967 }
1968 }
1969
1970 rc = 0;
1971 out:
1972 return rc;
1973 }
1974
1975 static int rtl8169_set_speed(struct net_device *dev,
1976 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1977 {
1978 struct rtl8169_private *tp = netdev_priv(dev);
1979 int ret;
1980
1981 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1982 if (ret < 0)
1983 goto out;
1984
1985 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1986 (advertising & ADVERTISED_1000baseT_Full)) {
1987 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1988 }
1989 out:
1990 return ret;
1991 }
1992
1993 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1994 {
1995 struct rtl8169_private *tp = netdev_priv(dev);
1996 int ret;
1997
1998 del_timer_sync(&tp->timer);
1999
2000 rtl_lock_work(tp);
2001 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2002 cmd->duplex, cmd->advertising);
2003 rtl_unlock_work(tp);
2004
2005 return ret;
2006 }
2007
2008 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2009 netdev_features_t features)
2010 {
2011 struct rtl8169_private *tp = netdev_priv(dev);
2012
2013 if (dev->mtu > TD_MSS_MAX)
2014 features &= ~NETIF_F_ALL_TSO;
2015
2016 if (dev->mtu > JUMBO_1K &&
2017 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2018 features &= ~NETIF_F_IP_CSUM;
2019
2020 return features;
2021 }
2022
2023 static void __rtl8169_set_features(struct net_device *dev,
2024 netdev_features_t features)
2025 {
2026 struct rtl8169_private *tp = netdev_priv(dev);
2027 void __iomem *ioaddr = tp->mmio_addr;
2028 u32 rx_config;
2029
2030 rx_config = RTL_R32(RxConfig);
2031 if (features & NETIF_F_RXALL)
2032 rx_config |= (AcceptErr | AcceptRunt);
2033 else
2034 rx_config &= ~(AcceptErr | AcceptRunt);
2035
2036 RTL_W32(RxConfig, rx_config);
2037
2038 if (features & NETIF_F_RXCSUM)
2039 tp->cp_cmd |= RxChkSum;
2040 else
2041 tp->cp_cmd &= ~RxChkSum;
2042
2043 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2044 tp->cp_cmd |= RxVlan;
2045 else
2046 tp->cp_cmd &= ~RxVlan;
2047
2048 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2049
2050 RTL_W16(CPlusCmd, tp->cp_cmd);
2051 RTL_R16(CPlusCmd);
2052 }
2053
2054 static int rtl8169_set_features(struct net_device *dev,
2055 netdev_features_t features)
2056 {
2057 struct rtl8169_private *tp = netdev_priv(dev);
2058
2059 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2060
2061 rtl_lock_work(tp);
2062 if (features ^ dev->features)
2063 __rtl8169_set_features(dev, features);
2064 rtl_unlock_work(tp);
2065
2066 return 0;
2067 }
2068
2069
2070 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2071 {
2072 return (vlan_tx_tag_present(skb)) ?
2073 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
2074 }
2075
2076 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2077 {
2078 u32 opts2 = le32_to_cpu(desc->opts2);
2079
2080 if (opts2 & RxVlanTag)
2081 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2082 }
2083
2084 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
2085 {
2086 struct rtl8169_private *tp = netdev_priv(dev);
2087 void __iomem *ioaddr = tp->mmio_addr;
2088 u32 status;
2089
2090 cmd->supported =
2091 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2092 cmd->port = PORT_FIBRE;
2093 cmd->transceiver = XCVR_INTERNAL;
2094
2095 status = RTL_R32(TBICSR);
2096 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2097 cmd->autoneg = !!(status & TBINwEnable);
2098
2099 ethtool_cmd_speed_set(cmd, SPEED_1000);
2100 cmd->duplex = DUPLEX_FULL; /* Always set */
2101
2102 return 0;
2103 }
2104
2105 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
2106 {
2107 struct rtl8169_private *tp = netdev_priv(dev);
2108
2109 return mii_ethtool_gset(&tp->mii, cmd);
2110 }
2111
2112 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2113 {
2114 struct rtl8169_private *tp = netdev_priv(dev);
2115 int rc;
2116
2117 rtl_lock_work(tp);
2118 rc = tp->get_settings(dev, cmd);
2119 rtl_unlock_work(tp);
2120
2121 return rc;
2122 }
2123
2124 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2125 void *p)
2126 {
2127 struct rtl8169_private *tp = netdev_priv(dev);
2128 u32 __iomem *data = tp->mmio_addr;
2129 u32 *dw = p;
2130 int i;
2131
2132 rtl_lock_work(tp);
2133 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2134 memcpy_fromio(dw++, data++, 4);
2135 rtl_unlock_work(tp);
2136 }
2137
2138 static u32 rtl8169_get_msglevel(struct net_device *dev)
2139 {
2140 struct rtl8169_private *tp = netdev_priv(dev);
2141
2142 return tp->msg_enable;
2143 }
2144
2145 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2146 {
2147 struct rtl8169_private *tp = netdev_priv(dev);
2148
2149 tp->msg_enable = value;
2150 }
2151
2152 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2153 "tx_packets",
2154 "rx_packets",
2155 "tx_errors",
2156 "rx_errors",
2157 "rx_missed",
2158 "align_errors",
2159 "tx_single_collisions",
2160 "tx_multi_collisions",
2161 "unicast",
2162 "broadcast",
2163 "multicast",
2164 "tx_aborted",
2165 "tx_underrun",
2166 };
2167
2168 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2169 {
2170 switch (sset) {
2171 case ETH_SS_STATS:
2172 return ARRAY_SIZE(rtl8169_gstrings);
2173 default:
2174 return -EOPNOTSUPP;
2175 }
2176 }
2177
2178 DECLARE_RTL_COND(rtl_counters_cond)
2179 {
2180 void __iomem *ioaddr = tp->mmio_addr;
2181
2182 return RTL_R32(CounterAddrLow) & CounterDump;
2183 }
2184
2185 static void rtl8169_update_counters(struct net_device *dev)
2186 {
2187 struct rtl8169_private *tp = netdev_priv(dev);
2188 void __iomem *ioaddr = tp->mmio_addr;
2189 struct device *d = &tp->pci_dev->dev;
2190 struct rtl8169_counters *counters;
2191 dma_addr_t paddr;
2192 u32 cmd;
2193
2194 /*
2195 * Some chips are unable to dump tally counters when the receiver
2196 * is disabled.
2197 */
2198 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2199 return;
2200
2201 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
2202 if (!counters)
2203 return;
2204
2205 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2206 cmd = (u64)paddr & DMA_BIT_MASK(32);
2207 RTL_W32(CounterAddrLow, cmd);
2208 RTL_W32(CounterAddrLow, cmd | CounterDump);
2209
2210 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
2211 memcpy(&tp->counters, counters, sizeof(*counters));
2212
2213 RTL_W32(CounterAddrLow, 0);
2214 RTL_W32(CounterAddrHigh, 0);
2215
2216 dma_free_coherent(d, sizeof(*counters), counters, paddr);
2217 }
2218
2219 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2220 struct ethtool_stats *stats, u64 *data)
2221 {
2222 struct rtl8169_private *tp = netdev_priv(dev);
2223
2224 ASSERT_RTNL();
2225
2226 rtl8169_update_counters(dev);
2227
2228 data[0] = le64_to_cpu(tp->counters.tx_packets);
2229 data[1] = le64_to_cpu(tp->counters.rx_packets);
2230 data[2] = le64_to_cpu(tp->counters.tx_errors);
2231 data[3] = le32_to_cpu(tp->counters.rx_errors);
2232 data[4] = le16_to_cpu(tp->counters.rx_missed);
2233 data[5] = le16_to_cpu(tp->counters.align_errors);
2234 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2235 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2236 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2237 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2238 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2239 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2240 data[12] = le16_to_cpu(tp->counters.tx_underun);
2241 }
2242
2243 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2244 {
2245 switch(stringset) {
2246 case ETH_SS_STATS:
2247 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2248 break;
2249 }
2250 }
2251
2252 static const struct ethtool_ops rtl8169_ethtool_ops = {
2253 .get_drvinfo = rtl8169_get_drvinfo,
2254 .get_regs_len = rtl8169_get_regs_len,
2255 .get_link = ethtool_op_get_link,
2256 .get_settings = rtl8169_get_settings,
2257 .set_settings = rtl8169_set_settings,
2258 .get_msglevel = rtl8169_get_msglevel,
2259 .set_msglevel = rtl8169_set_msglevel,
2260 .get_regs = rtl8169_get_regs,
2261 .get_wol = rtl8169_get_wol,
2262 .set_wol = rtl8169_set_wol,
2263 .get_strings = rtl8169_get_strings,
2264 .get_sset_count = rtl8169_get_sset_count,
2265 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2266 .get_ts_info = ethtool_op_get_ts_info,
2267 };
2268
2269 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2270 struct net_device *dev, u8 default_version)
2271 {
2272 void __iomem *ioaddr = tp->mmio_addr;
2273 /*
2274 * The driver currently handles the 8168Bf and the 8168Be identically
2275 * but they can be identified more specifically through the test below
2276 * if needed:
2277 *
2278 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2279 *
2280 * Same thing for the 8101Eb and the 8101Ec:
2281 *
2282 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2283 */
2284 static const struct rtl_mac_info {
2285 u32 mask;
2286 u32 val;
2287 int mac_version;
2288 } mac_info[] = {
2289 /* 8168EP family. */
2290 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2291 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2292 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2293
2294 /* 8168H family. */
2295 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2296 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2297
2298 /* 8168G family. */
2299 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2300 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2301 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2302 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2303
2304 /* 8168F family. */
2305 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2306 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2307 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2308
2309 /* 8168E family. */
2310 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2311 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2312 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2313 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2314
2315 /* 8168D family. */
2316 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2317 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2318 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2319
2320 /* 8168DP family. */
2321 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2322 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2323 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2324
2325 /* 8168C family. */
2326 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2327 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2328 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2329 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2330 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2331 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2332 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2333 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2334 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2335
2336 /* 8168B family. */
2337 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2338 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2339 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2340 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2341
2342 /* 8101 family. */
2343 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2344 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2345 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2346 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2347 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2348 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2349 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2350 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2351 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2352 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2353 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2354 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2355 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2356 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2357 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2358 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2359 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2360 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2361 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2362 /* FIXME: where did these entries come from ? -- FR */
2363 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2364 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2365
2366 /* 8110 family. */
2367 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2368 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2369 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2370 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2371 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2372 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2373
2374 /* Catch-all */
2375 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2376 };
2377 const struct rtl_mac_info *p = mac_info;
2378 u32 reg;
2379
2380 reg = RTL_R32(TxConfig);
2381 while ((reg & p->mask) != p->val)
2382 p++;
2383 tp->mac_version = p->mac_version;
2384
2385 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2386 netif_notice(tp, probe, dev,
2387 "unknown MAC, using family default\n");
2388 tp->mac_version = default_version;
2389 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2390 tp->mac_version = tp->mii.supports_gmii ?
2391 RTL_GIGA_MAC_VER_42 :
2392 RTL_GIGA_MAC_VER_43;
2393 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2394 tp->mac_version = tp->mii.supports_gmii ?
2395 RTL_GIGA_MAC_VER_45 :
2396 RTL_GIGA_MAC_VER_47;
2397 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2398 tp->mac_version = tp->mii.supports_gmii ?
2399 RTL_GIGA_MAC_VER_46 :
2400 RTL_GIGA_MAC_VER_48;
2401 }
2402 }
2403
2404 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2405 {
2406 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2407 }
2408
2409 struct phy_reg {
2410 u16 reg;
2411 u16 val;
2412 };
2413
2414 static void rtl_writephy_batch(struct rtl8169_private *tp,
2415 const struct phy_reg *regs, int len)
2416 {
2417 while (len-- > 0) {
2418 rtl_writephy(tp, regs->reg, regs->val);
2419 regs++;
2420 }
2421 }
2422
2423 #define PHY_READ 0x00000000
2424 #define PHY_DATA_OR 0x10000000
2425 #define PHY_DATA_AND 0x20000000
2426 #define PHY_BJMPN 0x30000000
2427 #define PHY_MDIO_CHG 0x40000000
2428 #define PHY_CLEAR_READCOUNT 0x70000000
2429 #define PHY_WRITE 0x80000000
2430 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2431 #define PHY_COMP_EQ_SKIPN 0xa0000000
2432 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2433 #define PHY_WRITE_PREVIOUS 0xc0000000
2434 #define PHY_SKIPN 0xd0000000
2435 #define PHY_DELAY_MS 0xe0000000
2436
2437 struct fw_info {
2438 u32 magic;
2439 char version[RTL_VER_SIZE];
2440 __le32 fw_start;
2441 __le32 fw_len;
2442 u8 chksum;
2443 } __packed;
2444
2445 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2446
2447 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2448 {
2449 const struct firmware *fw = rtl_fw->fw;
2450 struct fw_info *fw_info = (struct fw_info *)fw->data;
2451 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2452 char *version = rtl_fw->version;
2453 bool rc = false;
2454
2455 if (fw->size < FW_OPCODE_SIZE)
2456 goto out;
2457
2458 if (!fw_info->magic) {
2459 size_t i, size, start;
2460 u8 checksum = 0;
2461
2462 if (fw->size < sizeof(*fw_info))
2463 goto out;
2464
2465 for (i = 0; i < fw->size; i++)
2466 checksum += fw->data[i];
2467 if (checksum != 0)
2468 goto out;
2469
2470 start = le32_to_cpu(fw_info->fw_start);
2471 if (start > fw->size)
2472 goto out;
2473
2474 size = le32_to_cpu(fw_info->fw_len);
2475 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2476 goto out;
2477
2478 memcpy(version, fw_info->version, RTL_VER_SIZE);
2479
2480 pa->code = (__le32 *)(fw->data + start);
2481 pa->size = size;
2482 } else {
2483 if (fw->size % FW_OPCODE_SIZE)
2484 goto out;
2485
2486 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2487
2488 pa->code = (__le32 *)fw->data;
2489 pa->size = fw->size / FW_OPCODE_SIZE;
2490 }
2491 version[RTL_VER_SIZE - 1] = 0;
2492
2493 rc = true;
2494 out:
2495 return rc;
2496 }
2497
2498 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2499 struct rtl_fw_phy_action *pa)
2500 {
2501 bool rc = false;
2502 size_t index;
2503
2504 for (index = 0; index < pa->size; index++) {
2505 u32 action = le32_to_cpu(pa->code[index]);
2506 u32 regno = (action & 0x0fff0000) >> 16;
2507
2508 switch(action & 0xf0000000) {
2509 case PHY_READ:
2510 case PHY_DATA_OR:
2511 case PHY_DATA_AND:
2512 case PHY_MDIO_CHG:
2513 case PHY_CLEAR_READCOUNT:
2514 case PHY_WRITE:
2515 case PHY_WRITE_PREVIOUS:
2516 case PHY_DELAY_MS:
2517 break;
2518
2519 case PHY_BJMPN:
2520 if (regno > index) {
2521 netif_err(tp, ifup, tp->dev,
2522 "Out of range of firmware\n");
2523 goto out;
2524 }
2525 break;
2526 case PHY_READCOUNT_EQ_SKIP:
2527 if (index + 2 >= pa->size) {
2528 netif_err(tp, ifup, tp->dev,
2529 "Out of range of firmware\n");
2530 goto out;
2531 }
2532 break;
2533 case PHY_COMP_EQ_SKIPN:
2534 case PHY_COMP_NEQ_SKIPN:
2535 case PHY_SKIPN:
2536 if (index + 1 + regno >= pa->size) {
2537 netif_err(tp, ifup, tp->dev,
2538 "Out of range of firmware\n");
2539 goto out;
2540 }
2541 break;
2542
2543 default:
2544 netif_err(tp, ifup, tp->dev,
2545 "Invalid action 0x%08x\n", action);
2546 goto out;
2547 }
2548 }
2549 rc = true;
2550 out:
2551 return rc;
2552 }
2553
2554 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2555 {
2556 struct net_device *dev = tp->dev;
2557 int rc = -EINVAL;
2558
2559 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2560 netif_err(tp, ifup, dev, "invalid firwmare\n");
2561 goto out;
2562 }
2563
2564 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2565 rc = 0;
2566 out:
2567 return rc;
2568 }
2569
2570 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2571 {
2572 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2573 struct mdio_ops org, *ops = &tp->mdio_ops;
2574 u32 predata, count;
2575 size_t index;
2576
2577 predata = count = 0;
2578 org.write = ops->write;
2579 org.read = ops->read;
2580
2581 for (index = 0; index < pa->size; ) {
2582 u32 action = le32_to_cpu(pa->code[index]);
2583 u32 data = action & 0x0000ffff;
2584 u32 regno = (action & 0x0fff0000) >> 16;
2585
2586 if (!action)
2587 break;
2588
2589 switch(action & 0xf0000000) {
2590 case PHY_READ:
2591 predata = rtl_readphy(tp, regno);
2592 count++;
2593 index++;
2594 break;
2595 case PHY_DATA_OR:
2596 predata |= data;
2597 index++;
2598 break;
2599 case PHY_DATA_AND:
2600 predata &= data;
2601 index++;
2602 break;
2603 case PHY_BJMPN:
2604 index -= regno;
2605 break;
2606 case PHY_MDIO_CHG:
2607 if (data == 0) {
2608 ops->write = org.write;
2609 ops->read = org.read;
2610 } else if (data == 1) {
2611 ops->write = mac_mcu_write;
2612 ops->read = mac_mcu_read;
2613 }
2614
2615 index++;
2616 break;
2617 case PHY_CLEAR_READCOUNT:
2618 count = 0;
2619 index++;
2620 break;
2621 case PHY_WRITE:
2622 rtl_writephy(tp, regno, data);
2623 index++;
2624 break;
2625 case PHY_READCOUNT_EQ_SKIP:
2626 index += (count == data) ? 2 : 1;
2627 break;
2628 case PHY_COMP_EQ_SKIPN:
2629 if (predata == data)
2630 index += regno;
2631 index++;
2632 break;
2633 case PHY_COMP_NEQ_SKIPN:
2634 if (predata != data)
2635 index += regno;
2636 index++;
2637 break;
2638 case PHY_WRITE_PREVIOUS:
2639 rtl_writephy(tp, regno, predata);
2640 index++;
2641 break;
2642 case PHY_SKIPN:
2643 index += regno + 1;
2644 break;
2645 case PHY_DELAY_MS:
2646 mdelay(data);
2647 index++;
2648 break;
2649
2650 default:
2651 BUG();
2652 }
2653 }
2654
2655 ops->write = org.write;
2656 ops->read = org.read;
2657 }
2658
2659 static void rtl_release_firmware(struct rtl8169_private *tp)
2660 {
2661 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2662 release_firmware(tp->rtl_fw->fw);
2663 kfree(tp->rtl_fw);
2664 }
2665 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2666 }
2667
2668 static void rtl_apply_firmware(struct rtl8169_private *tp)
2669 {
2670 struct rtl_fw *rtl_fw = tp->rtl_fw;
2671
2672 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2673 if (!IS_ERR_OR_NULL(rtl_fw))
2674 rtl_phy_write_fw(tp, rtl_fw);
2675 }
2676
2677 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2678 {
2679 if (rtl_readphy(tp, reg) != val)
2680 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2681 else
2682 rtl_apply_firmware(tp);
2683 }
2684
2685 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2686 {
2687 static const struct phy_reg phy_reg_init[] = {
2688 { 0x1f, 0x0001 },
2689 { 0x06, 0x006e },
2690 { 0x08, 0x0708 },
2691 { 0x15, 0x4000 },
2692 { 0x18, 0x65c7 },
2693
2694 { 0x1f, 0x0001 },
2695 { 0x03, 0x00a1 },
2696 { 0x02, 0x0008 },
2697 { 0x01, 0x0120 },
2698 { 0x00, 0x1000 },
2699 { 0x04, 0x0800 },
2700 { 0x04, 0x0000 },
2701
2702 { 0x03, 0xff41 },
2703 { 0x02, 0xdf60 },
2704 { 0x01, 0x0140 },
2705 { 0x00, 0x0077 },
2706 { 0x04, 0x7800 },
2707 { 0x04, 0x7000 },
2708
2709 { 0x03, 0x802f },
2710 { 0x02, 0x4f02 },
2711 { 0x01, 0x0409 },
2712 { 0x00, 0xf0f9 },
2713 { 0x04, 0x9800 },
2714 { 0x04, 0x9000 },
2715
2716 { 0x03, 0xdf01 },
2717 { 0x02, 0xdf20 },
2718 { 0x01, 0xff95 },
2719 { 0x00, 0xba00 },
2720 { 0x04, 0xa800 },
2721 { 0x04, 0xa000 },
2722
2723 { 0x03, 0xff41 },
2724 { 0x02, 0xdf20 },
2725 { 0x01, 0x0140 },
2726 { 0x00, 0x00bb },
2727 { 0x04, 0xb800 },
2728 { 0x04, 0xb000 },
2729
2730 { 0x03, 0xdf41 },
2731 { 0x02, 0xdc60 },
2732 { 0x01, 0x6340 },
2733 { 0x00, 0x007d },
2734 { 0x04, 0xd800 },
2735 { 0x04, 0xd000 },
2736
2737 { 0x03, 0xdf01 },
2738 { 0x02, 0xdf20 },
2739 { 0x01, 0x100a },
2740 { 0x00, 0xa0ff },
2741 { 0x04, 0xf800 },
2742 { 0x04, 0xf000 },
2743
2744 { 0x1f, 0x0000 },
2745 { 0x0b, 0x0000 },
2746 { 0x00, 0x9200 }
2747 };
2748
2749 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2750 }
2751
2752 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2753 {
2754 static const struct phy_reg phy_reg_init[] = {
2755 { 0x1f, 0x0002 },
2756 { 0x01, 0x90d0 },
2757 { 0x1f, 0x0000 }
2758 };
2759
2760 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2761 }
2762
2763 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2764 {
2765 struct pci_dev *pdev = tp->pci_dev;
2766
2767 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2768 (pdev->subsystem_device != 0xe000))
2769 return;
2770
2771 rtl_writephy(tp, 0x1f, 0x0001);
2772 rtl_writephy(tp, 0x10, 0xf01b);
2773 rtl_writephy(tp, 0x1f, 0x0000);
2774 }
2775
2776 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2777 {
2778 static const struct phy_reg phy_reg_init[] = {
2779 { 0x1f, 0x0001 },
2780 { 0x04, 0x0000 },
2781 { 0x03, 0x00a1 },
2782 { 0x02, 0x0008 },
2783 { 0x01, 0x0120 },
2784 { 0x00, 0x1000 },
2785 { 0x04, 0x0800 },
2786 { 0x04, 0x9000 },
2787 { 0x03, 0x802f },
2788 { 0x02, 0x4f02 },
2789 { 0x01, 0x0409 },
2790 { 0x00, 0xf099 },
2791 { 0x04, 0x9800 },
2792 { 0x04, 0xa000 },
2793 { 0x03, 0xdf01 },
2794 { 0x02, 0xdf20 },
2795 { 0x01, 0xff95 },
2796 { 0x00, 0xba00 },
2797 { 0x04, 0xa800 },
2798 { 0x04, 0xf000 },
2799 { 0x03, 0xdf01 },
2800 { 0x02, 0xdf20 },
2801 { 0x01, 0x101a },
2802 { 0x00, 0xa0ff },
2803 { 0x04, 0xf800 },
2804 { 0x04, 0x0000 },
2805 { 0x1f, 0x0000 },
2806
2807 { 0x1f, 0x0001 },
2808 { 0x10, 0xf41b },
2809 { 0x14, 0xfb54 },
2810 { 0x18, 0xf5c7 },
2811 { 0x1f, 0x0000 },
2812
2813 { 0x1f, 0x0001 },
2814 { 0x17, 0x0cc0 },
2815 { 0x1f, 0x0000 }
2816 };
2817
2818 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2819
2820 rtl8169scd_hw_phy_config_quirk(tp);
2821 }
2822
2823 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2824 {
2825 static const struct phy_reg phy_reg_init[] = {
2826 { 0x1f, 0x0001 },
2827 { 0x04, 0x0000 },
2828 { 0x03, 0x00a1 },
2829 { 0x02, 0x0008 },
2830 { 0x01, 0x0120 },
2831 { 0x00, 0x1000 },
2832 { 0x04, 0x0800 },
2833 { 0x04, 0x9000 },
2834 { 0x03, 0x802f },
2835 { 0x02, 0x4f02 },
2836 { 0x01, 0x0409 },
2837 { 0x00, 0xf099 },
2838 { 0x04, 0x9800 },
2839 { 0x04, 0xa000 },
2840 { 0x03, 0xdf01 },
2841 { 0x02, 0xdf20 },
2842 { 0x01, 0xff95 },
2843 { 0x00, 0xba00 },
2844 { 0x04, 0xa800 },
2845 { 0x04, 0xf000 },
2846 { 0x03, 0xdf01 },
2847 { 0x02, 0xdf20 },
2848 { 0x01, 0x101a },
2849 { 0x00, 0xa0ff },
2850 { 0x04, 0xf800 },
2851 { 0x04, 0x0000 },
2852 { 0x1f, 0x0000 },
2853
2854 { 0x1f, 0x0001 },
2855 { 0x0b, 0x8480 },
2856 { 0x1f, 0x0000 },
2857
2858 { 0x1f, 0x0001 },
2859 { 0x18, 0x67c7 },
2860 { 0x04, 0x2000 },
2861 { 0x03, 0x002f },
2862 { 0x02, 0x4360 },
2863 { 0x01, 0x0109 },
2864 { 0x00, 0x3022 },
2865 { 0x04, 0x2800 },
2866 { 0x1f, 0x0000 },
2867
2868 { 0x1f, 0x0001 },
2869 { 0x17, 0x0cc0 },
2870 { 0x1f, 0x0000 }
2871 };
2872
2873 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2874 }
2875
2876 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2877 {
2878 static const struct phy_reg phy_reg_init[] = {
2879 { 0x10, 0xf41b },
2880 { 0x1f, 0x0000 }
2881 };
2882
2883 rtl_writephy(tp, 0x1f, 0x0001);
2884 rtl_patchphy(tp, 0x16, 1 << 0);
2885
2886 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2887 }
2888
2889 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2890 {
2891 static const struct phy_reg phy_reg_init[] = {
2892 { 0x1f, 0x0001 },
2893 { 0x10, 0xf41b },
2894 { 0x1f, 0x0000 }
2895 };
2896
2897 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2898 }
2899
2900 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2901 {
2902 static const struct phy_reg phy_reg_init[] = {
2903 { 0x1f, 0x0000 },
2904 { 0x1d, 0x0f00 },
2905 { 0x1f, 0x0002 },
2906 { 0x0c, 0x1ec8 },
2907 { 0x1f, 0x0000 }
2908 };
2909
2910 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2911 }
2912
2913 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2914 {
2915 static const struct phy_reg phy_reg_init[] = {
2916 { 0x1f, 0x0001 },
2917 { 0x1d, 0x3d98 },
2918 { 0x1f, 0x0000 }
2919 };
2920
2921 rtl_writephy(tp, 0x1f, 0x0000);
2922 rtl_patchphy(tp, 0x14, 1 << 5);
2923 rtl_patchphy(tp, 0x0d, 1 << 5);
2924
2925 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2926 }
2927
2928 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2929 {
2930 static const struct phy_reg phy_reg_init[] = {
2931 { 0x1f, 0x0001 },
2932 { 0x12, 0x2300 },
2933 { 0x1f, 0x0002 },
2934 { 0x00, 0x88d4 },
2935 { 0x01, 0x82b1 },
2936 { 0x03, 0x7002 },
2937 { 0x08, 0x9e30 },
2938 { 0x09, 0x01f0 },
2939 { 0x0a, 0x5500 },
2940 { 0x0c, 0x00c8 },
2941 { 0x1f, 0x0003 },
2942 { 0x12, 0xc096 },
2943 { 0x16, 0x000a },
2944 { 0x1f, 0x0000 },
2945 { 0x1f, 0x0000 },
2946 { 0x09, 0x2000 },
2947 { 0x09, 0x0000 }
2948 };
2949
2950 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2951
2952 rtl_patchphy(tp, 0x14, 1 << 5);
2953 rtl_patchphy(tp, 0x0d, 1 << 5);
2954 rtl_writephy(tp, 0x1f, 0x0000);
2955 }
2956
2957 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2958 {
2959 static const struct phy_reg phy_reg_init[] = {
2960 { 0x1f, 0x0001 },
2961 { 0x12, 0x2300 },
2962 { 0x03, 0x802f },
2963 { 0x02, 0x4f02 },
2964 { 0x01, 0x0409 },
2965 { 0x00, 0xf099 },
2966 { 0x04, 0x9800 },
2967 { 0x04, 0x9000 },
2968 { 0x1d, 0x3d98 },
2969 { 0x1f, 0x0002 },
2970 { 0x0c, 0x7eb8 },
2971 { 0x06, 0x0761 },
2972 { 0x1f, 0x0003 },
2973 { 0x16, 0x0f0a },
2974 { 0x1f, 0x0000 }
2975 };
2976
2977 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2978
2979 rtl_patchphy(tp, 0x16, 1 << 0);
2980 rtl_patchphy(tp, 0x14, 1 << 5);
2981 rtl_patchphy(tp, 0x0d, 1 << 5);
2982 rtl_writephy(tp, 0x1f, 0x0000);
2983 }
2984
2985 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2986 {
2987 static const struct phy_reg phy_reg_init[] = {
2988 { 0x1f, 0x0001 },
2989 { 0x12, 0x2300 },
2990 { 0x1d, 0x3d98 },
2991 { 0x1f, 0x0002 },
2992 { 0x0c, 0x7eb8 },
2993 { 0x06, 0x5461 },
2994 { 0x1f, 0x0003 },
2995 { 0x16, 0x0f0a },
2996 { 0x1f, 0x0000 }
2997 };
2998
2999 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3000
3001 rtl_patchphy(tp, 0x16, 1 << 0);
3002 rtl_patchphy(tp, 0x14, 1 << 5);
3003 rtl_patchphy(tp, 0x0d, 1 << 5);
3004 rtl_writephy(tp, 0x1f, 0x0000);
3005 }
3006
3007 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3008 {
3009 rtl8168c_3_hw_phy_config(tp);
3010 }
3011
3012 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3013 {
3014 static const struct phy_reg phy_reg_init_0[] = {
3015 /* Channel Estimation */
3016 { 0x1f, 0x0001 },
3017 { 0x06, 0x4064 },
3018 { 0x07, 0x2863 },
3019 { 0x08, 0x059c },
3020 { 0x09, 0x26b4 },
3021 { 0x0a, 0x6a19 },
3022 { 0x0b, 0xdcc8 },
3023 { 0x10, 0xf06d },
3024 { 0x14, 0x7f68 },
3025 { 0x18, 0x7fd9 },
3026 { 0x1c, 0xf0ff },
3027 { 0x1d, 0x3d9c },
3028 { 0x1f, 0x0003 },
3029 { 0x12, 0xf49f },
3030 { 0x13, 0x070b },
3031 { 0x1a, 0x05ad },
3032 { 0x14, 0x94c0 },
3033
3034 /*
3035 * Tx Error Issue
3036 * Enhance line driver power
3037 */
3038 { 0x1f, 0x0002 },
3039 { 0x06, 0x5561 },
3040 { 0x1f, 0x0005 },
3041 { 0x05, 0x8332 },
3042 { 0x06, 0x5561 },
3043
3044 /*
3045 * Can not link to 1Gbps with bad cable
3046 * Decrease SNR threshold form 21.07dB to 19.04dB
3047 */
3048 { 0x1f, 0x0001 },
3049 { 0x17, 0x0cc0 },
3050
3051 { 0x1f, 0x0000 },
3052 { 0x0d, 0xf880 }
3053 };
3054
3055 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3056
3057 /*
3058 * Rx Error Issue
3059 * Fine Tune Switching regulator parameter
3060 */
3061 rtl_writephy(tp, 0x1f, 0x0002);
3062 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3063 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3064
3065 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3066 static const struct phy_reg phy_reg_init[] = {
3067 { 0x1f, 0x0002 },
3068 { 0x05, 0x669a },
3069 { 0x1f, 0x0005 },
3070 { 0x05, 0x8330 },
3071 { 0x06, 0x669a },
3072 { 0x1f, 0x0002 }
3073 };
3074 int val;
3075
3076 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3077
3078 val = rtl_readphy(tp, 0x0d);
3079
3080 if ((val & 0x00ff) != 0x006c) {
3081 static const u32 set[] = {
3082 0x0065, 0x0066, 0x0067, 0x0068,
3083 0x0069, 0x006a, 0x006b, 0x006c
3084 };
3085 int i;
3086
3087 rtl_writephy(tp, 0x1f, 0x0002);
3088
3089 val &= 0xff00;
3090 for (i = 0; i < ARRAY_SIZE(set); i++)
3091 rtl_writephy(tp, 0x0d, val | set[i]);
3092 }
3093 } else {
3094 static const struct phy_reg phy_reg_init[] = {
3095 { 0x1f, 0x0002 },
3096 { 0x05, 0x6662 },
3097 { 0x1f, 0x0005 },
3098 { 0x05, 0x8330 },
3099 { 0x06, 0x6662 }
3100 };
3101
3102 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3103 }
3104
3105 /* RSET couple improve */
3106 rtl_writephy(tp, 0x1f, 0x0002);
3107 rtl_patchphy(tp, 0x0d, 0x0300);
3108 rtl_patchphy(tp, 0x0f, 0x0010);
3109
3110 /* Fine tune PLL performance */
3111 rtl_writephy(tp, 0x1f, 0x0002);
3112 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3113 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3114
3115 rtl_writephy(tp, 0x1f, 0x0005);
3116 rtl_writephy(tp, 0x05, 0x001b);
3117
3118 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3119
3120 rtl_writephy(tp, 0x1f, 0x0000);
3121 }
3122
3123 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3124 {
3125 static const struct phy_reg phy_reg_init_0[] = {
3126 /* Channel Estimation */
3127 { 0x1f, 0x0001 },
3128 { 0x06, 0x4064 },
3129 { 0x07, 0x2863 },
3130 { 0x08, 0x059c },
3131 { 0x09, 0x26b4 },
3132 { 0x0a, 0x6a19 },
3133 { 0x0b, 0xdcc8 },
3134 { 0x10, 0xf06d },
3135 { 0x14, 0x7f68 },
3136 { 0x18, 0x7fd9 },
3137 { 0x1c, 0xf0ff },
3138 { 0x1d, 0x3d9c },
3139 { 0x1f, 0x0003 },
3140 { 0x12, 0xf49f },
3141 { 0x13, 0x070b },
3142 { 0x1a, 0x05ad },
3143 { 0x14, 0x94c0 },
3144
3145 /*
3146 * Tx Error Issue
3147 * Enhance line driver power
3148 */
3149 { 0x1f, 0x0002 },
3150 { 0x06, 0x5561 },
3151 { 0x1f, 0x0005 },
3152 { 0x05, 0x8332 },
3153 { 0x06, 0x5561 },
3154
3155 /*
3156 * Can not link to 1Gbps with bad cable
3157 * Decrease SNR threshold form 21.07dB to 19.04dB
3158 */
3159 { 0x1f, 0x0001 },
3160 { 0x17, 0x0cc0 },
3161
3162 { 0x1f, 0x0000 },
3163 { 0x0d, 0xf880 }
3164 };
3165
3166 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3167
3168 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3169 static const struct phy_reg phy_reg_init[] = {
3170 { 0x1f, 0x0002 },
3171 { 0x05, 0x669a },
3172 { 0x1f, 0x0005 },
3173 { 0x05, 0x8330 },
3174 { 0x06, 0x669a },
3175
3176 { 0x1f, 0x0002 }
3177 };
3178 int val;
3179
3180 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3181
3182 val = rtl_readphy(tp, 0x0d);
3183 if ((val & 0x00ff) != 0x006c) {
3184 static const u32 set[] = {
3185 0x0065, 0x0066, 0x0067, 0x0068,
3186 0x0069, 0x006a, 0x006b, 0x006c
3187 };
3188 int i;
3189
3190 rtl_writephy(tp, 0x1f, 0x0002);
3191
3192 val &= 0xff00;
3193 for (i = 0; i < ARRAY_SIZE(set); i++)
3194 rtl_writephy(tp, 0x0d, val | set[i]);
3195 }
3196 } else {
3197 static const struct phy_reg phy_reg_init[] = {
3198 { 0x1f, 0x0002 },
3199 { 0x05, 0x2642 },
3200 { 0x1f, 0x0005 },
3201 { 0x05, 0x8330 },
3202 { 0x06, 0x2642 }
3203 };
3204
3205 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3206 }
3207
3208 /* Fine tune PLL performance */
3209 rtl_writephy(tp, 0x1f, 0x0002);
3210 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3211 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3212
3213 /* Switching regulator Slew rate */
3214 rtl_writephy(tp, 0x1f, 0x0002);
3215 rtl_patchphy(tp, 0x0f, 0x0017);
3216
3217 rtl_writephy(tp, 0x1f, 0x0005);
3218 rtl_writephy(tp, 0x05, 0x001b);
3219
3220 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3221
3222 rtl_writephy(tp, 0x1f, 0x0000);
3223 }
3224
3225 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3226 {
3227 static const struct phy_reg phy_reg_init[] = {
3228 { 0x1f, 0x0002 },
3229 { 0x10, 0x0008 },
3230 { 0x0d, 0x006c },
3231
3232 { 0x1f, 0x0000 },
3233 { 0x0d, 0xf880 },
3234
3235 { 0x1f, 0x0001 },
3236 { 0x17, 0x0cc0 },
3237
3238 { 0x1f, 0x0001 },
3239 { 0x0b, 0xa4d8 },
3240 { 0x09, 0x281c },
3241 { 0x07, 0x2883 },
3242 { 0x0a, 0x6b35 },
3243 { 0x1d, 0x3da4 },
3244 { 0x1c, 0xeffd },
3245 { 0x14, 0x7f52 },
3246 { 0x18, 0x7fc6 },
3247 { 0x08, 0x0601 },
3248 { 0x06, 0x4063 },
3249 { 0x10, 0xf074 },
3250 { 0x1f, 0x0003 },
3251 { 0x13, 0x0789 },
3252 { 0x12, 0xf4bd },
3253 { 0x1a, 0x04fd },
3254 { 0x14, 0x84b0 },
3255 { 0x1f, 0x0000 },
3256 { 0x00, 0x9200 },
3257
3258 { 0x1f, 0x0005 },
3259 { 0x01, 0x0340 },
3260 { 0x1f, 0x0001 },
3261 { 0x04, 0x4000 },
3262 { 0x03, 0x1d21 },
3263 { 0x02, 0x0c32 },
3264 { 0x01, 0x0200 },
3265 { 0x00, 0x5554 },
3266 { 0x04, 0x4800 },
3267 { 0x04, 0x4000 },
3268 { 0x04, 0xf000 },
3269 { 0x03, 0xdf01 },
3270 { 0x02, 0xdf20 },
3271 { 0x01, 0x101a },
3272 { 0x00, 0xa0ff },
3273 { 0x04, 0xf800 },
3274 { 0x04, 0xf000 },
3275 { 0x1f, 0x0000 },
3276
3277 { 0x1f, 0x0007 },
3278 { 0x1e, 0x0023 },
3279 { 0x16, 0x0000 },
3280 { 0x1f, 0x0000 }
3281 };
3282
3283 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3284 }
3285
3286 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3287 {
3288 static const struct phy_reg phy_reg_init[] = {
3289 { 0x1f, 0x0001 },
3290 { 0x17, 0x0cc0 },
3291
3292 { 0x1f, 0x0007 },
3293 { 0x1e, 0x002d },
3294 { 0x18, 0x0040 },
3295 { 0x1f, 0x0000 }
3296 };
3297
3298 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3299 rtl_patchphy(tp, 0x0d, 1 << 5);
3300 }
3301
3302 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3303 {
3304 static const struct phy_reg phy_reg_init[] = {
3305 /* Enable Delay cap */
3306 { 0x1f, 0x0005 },
3307 { 0x05, 0x8b80 },
3308 { 0x06, 0xc896 },
3309 { 0x1f, 0x0000 },
3310
3311 /* Channel estimation fine tune */
3312 { 0x1f, 0x0001 },
3313 { 0x0b, 0x6c20 },
3314 { 0x07, 0x2872 },
3315 { 0x1c, 0xefff },
3316 { 0x1f, 0x0003 },
3317 { 0x14, 0x6420 },
3318 { 0x1f, 0x0000 },
3319
3320 /* Update PFM & 10M TX idle timer */
3321 { 0x1f, 0x0007 },
3322 { 0x1e, 0x002f },
3323 { 0x15, 0x1919 },
3324 { 0x1f, 0x0000 },
3325
3326 { 0x1f, 0x0007 },
3327 { 0x1e, 0x00ac },
3328 { 0x18, 0x0006 },
3329 { 0x1f, 0x0000 }
3330 };
3331
3332 rtl_apply_firmware(tp);
3333
3334 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3335
3336 /* DCO enable for 10M IDLE Power */
3337 rtl_writephy(tp, 0x1f, 0x0007);
3338 rtl_writephy(tp, 0x1e, 0x0023);
3339 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3340 rtl_writephy(tp, 0x1f, 0x0000);
3341
3342 /* For impedance matching */
3343 rtl_writephy(tp, 0x1f, 0x0002);
3344 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3345 rtl_writephy(tp, 0x1f, 0x0000);
3346
3347 /* PHY auto speed down */
3348 rtl_writephy(tp, 0x1f, 0x0007);
3349 rtl_writephy(tp, 0x1e, 0x002d);
3350 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3351 rtl_writephy(tp, 0x1f, 0x0000);
3352 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3353
3354 rtl_writephy(tp, 0x1f, 0x0005);
3355 rtl_writephy(tp, 0x05, 0x8b86);
3356 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3357 rtl_writephy(tp, 0x1f, 0x0000);
3358
3359 rtl_writephy(tp, 0x1f, 0x0005);
3360 rtl_writephy(tp, 0x05, 0x8b85);
3361 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3362 rtl_writephy(tp, 0x1f, 0x0007);
3363 rtl_writephy(tp, 0x1e, 0x0020);
3364 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3365 rtl_writephy(tp, 0x1f, 0x0006);
3366 rtl_writephy(tp, 0x00, 0x5a00);
3367 rtl_writephy(tp, 0x1f, 0x0000);
3368 rtl_writephy(tp, 0x0d, 0x0007);
3369 rtl_writephy(tp, 0x0e, 0x003c);
3370 rtl_writephy(tp, 0x0d, 0x4007);
3371 rtl_writephy(tp, 0x0e, 0x0000);
3372 rtl_writephy(tp, 0x0d, 0x0000);
3373 }
3374
3375 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3376 {
3377 const u16 w[] = {
3378 addr[0] | (addr[1] << 8),
3379 addr[2] | (addr[3] << 8),
3380 addr[4] | (addr[5] << 8)
3381 };
3382 const struct exgmac_reg e[] = {
3383 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3384 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3385 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3386 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3387 };
3388
3389 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3390 }
3391
3392 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3393 {
3394 static const struct phy_reg phy_reg_init[] = {
3395 /* Enable Delay cap */
3396 { 0x1f, 0x0004 },
3397 { 0x1f, 0x0007 },
3398 { 0x1e, 0x00ac },
3399 { 0x18, 0x0006 },
3400 { 0x1f, 0x0002 },
3401 { 0x1f, 0x0000 },
3402 { 0x1f, 0x0000 },
3403
3404 /* Channel estimation fine tune */
3405 { 0x1f, 0x0003 },
3406 { 0x09, 0xa20f },
3407 { 0x1f, 0x0000 },
3408 { 0x1f, 0x0000 },
3409
3410 /* Green Setting */
3411 { 0x1f, 0x0005 },
3412 { 0x05, 0x8b5b },
3413 { 0x06, 0x9222 },
3414 { 0x05, 0x8b6d },
3415 { 0x06, 0x8000 },
3416 { 0x05, 0x8b76 },
3417 { 0x06, 0x8000 },
3418 { 0x1f, 0x0000 }
3419 };
3420
3421 rtl_apply_firmware(tp);
3422
3423 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3424
3425 /* For 4-corner performance improve */
3426 rtl_writephy(tp, 0x1f, 0x0005);
3427 rtl_writephy(tp, 0x05, 0x8b80);
3428 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3429 rtl_writephy(tp, 0x1f, 0x0000);
3430
3431 /* PHY auto speed down */
3432 rtl_writephy(tp, 0x1f, 0x0004);
3433 rtl_writephy(tp, 0x1f, 0x0007);
3434 rtl_writephy(tp, 0x1e, 0x002d);
3435 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3436 rtl_writephy(tp, 0x1f, 0x0002);
3437 rtl_writephy(tp, 0x1f, 0x0000);
3438 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3439
3440 /* improve 10M EEE waveform */
3441 rtl_writephy(tp, 0x1f, 0x0005);
3442 rtl_writephy(tp, 0x05, 0x8b86);
3443 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3444 rtl_writephy(tp, 0x1f, 0x0000);
3445
3446 /* Improve 2-pair detection performance */
3447 rtl_writephy(tp, 0x1f, 0x0005);
3448 rtl_writephy(tp, 0x05, 0x8b85);
3449 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3450 rtl_writephy(tp, 0x1f, 0x0000);
3451
3452 /* EEE setting */
3453 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3454 rtl_writephy(tp, 0x1f, 0x0005);
3455 rtl_writephy(tp, 0x05, 0x8b85);
3456 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3457 rtl_writephy(tp, 0x1f, 0x0004);
3458 rtl_writephy(tp, 0x1f, 0x0007);
3459 rtl_writephy(tp, 0x1e, 0x0020);
3460 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3461 rtl_writephy(tp, 0x1f, 0x0002);
3462 rtl_writephy(tp, 0x1f, 0x0000);
3463 rtl_writephy(tp, 0x0d, 0x0007);
3464 rtl_writephy(tp, 0x0e, 0x003c);
3465 rtl_writephy(tp, 0x0d, 0x4007);
3466 rtl_writephy(tp, 0x0e, 0x0000);
3467 rtl_writephy(tp, 0x0d, 0x0000);
3468
3469 /* Green feature */
3470 rtl_writephy(tp, 0x1f, 0x0003);
3471 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3472 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3473 rtl_writephy(tp, 0x1f, 0x0000);
3474
3475 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3476 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3477 }
3478
3479 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3480 {
3481 /* For 4-corner performance improve */
3482 rtl_writephy(tp, 0x1f, 0x0005);
3483 rtl_writephy(tp, 0x05, 0x8b80);
3484 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3485 rtl_writephy(tp, 0x1f, 0x0000);
3486
3487 /* PHY auto speed down */
3488 rtl_writephy(tp, 0x1f, 0x0007);
3489 rtl_writephy(tp, 0x1e, 0x002d);
3490 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3491 rtl_writephy(tp, 0x1f, 0x0000);
3492 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3493
3494 /* Improve 10M EEE waveform */
3495 rtl_writephy(tp, 0x1f, 0x0005);
3496 rtl_writephy(tp, 0x05, 0x8b86);
3497 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3498 rtl_writephy(tp, 0x1f, 0x0000);
3499 }
3500
3501 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3502 {
3503 static const struct phy_reg phy_reg_init[] = {
3504 /* Channel estimation fine tune */
3505 { 0x1f, 0x0003 },
3506 { 0x09, 0xa20f },
3507 { 0x1f, 0x0000 },
3508
3509 /* Modify green table for giga & fnet */
3510 { 0x1f, 0x0005 },
3511 { 0x05, 0x8b55 },
3512 { 0x06, 0x0000 },
3513 { 0x05, 0x8b5e },
3514 { 0x06, 0x0000 },
3515 { 0x05, 0x8b67 },
3516 { 0x06, 0x0000 },
3517 { 0x05, 0x8b70 },
3518 { 0x06, 0x0000 },
3519 { 0x1f, 0x0000 },
3520 { 0x1f, 0x0007 },
3521 { 0x1e, 0x0078 },
3522 { 0x17, 0x0000 },
3523 { 0x19, 0x00fb },
3524 { 0x1f, 0x0000 },
3525
3526 /* Modify green table for 10M */
3527 { 0x1f, 0x0005 },
3528 { 0x05, 0x8b79 },
3529 { 0x06, 0xaa00 },
3530 { 0x1f, 0x0000 },
3531
3532 /* Disable hiimpedance detection (RTCT) */
3533 { 0x1f, 0x0003 },
3534 { 0x01, 0x328a },
3535 { 0x1f, 0x0000 }
3536 };
3537
3538 rtl_apply_firmware(tp);
3539
3540 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3541
3542 rtl8168f_hw_phy_config(tp);
3543
3544 /* Improve 2-pair detection performance */
3545 rtl_writephy(tp, 0x1f, 0x0005);
3546 rtl_writephy(tp, 0x05, 0x8b85);
3547 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3548 rtl_writephy(tp, 0x1f, 0x0000);
3549 }
3550
3551 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3552 {
3553 rtl_apply_firmware(tp);
3554
3555 rtl8168f_hw_phy_config(tp);
3556 }
3557
3558 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3559 {
3560 static const struct phy_reg phy_reg_init[] = {
3561 /* Channel estimation fine tune */
3562 { 0x1f, 0x0003 },
3563 { 0x09, 0xa20f },
3564 { 0x1f, 0x0000 },
3565
3566 /* Modify green table for giga & fnet */
3567 { 0x1f, 0x0005 },
3568 { 0x05, 0x8b55 },
3569 { 0x06, 0x0000 },
3570 { 0x05, 0x8b5e },
3571 { 0x06, 0x0000 },
3572 { 0x05, 0x8b67 },
3573 { 0x06, 0x0000 },
3574 { 0x05, 0x8b70 },
3575 { 0x06, 0x0000 },
3576 { 0x1f, 0x0000 },
3577 { 0x1f, 0x0007 },
3578 { 0x1e, 0x0078 },
3579 { 0x17, 0x0000 },
3580 { 0x19, 0x00aa },
3581 { 0x1f, 0x0000 },
3582
3583 /* Modify green table for 10M */
3584 { 0x1f, 0x0005 },
3585 { 0x05, 0x8b79 },
3586 { 0x06, 0xaa00 },
3587 { 0x1f, 0x0000 },
3588
3589 /* Disable hiimpedance detection (RTCT) */
3590 { 0x1f, 0x0003 },
3591 { 0x01, 0x328a },
3592 { 0x1f, 0x0000 }
3593 };
3594
3595
3596 rtl_apply_firmware(tp);
3597
3598 rtl8168f_hw_phy_config(tp);
3599
3600 /* Improve 2-pair detection performance */
3601 rtl_writephy(tp, 0x1f, 0x0005);
3602 rtl_writephy(tp, 0x05, 0x8b85);
3603 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3604 rtl_writephy(tp, 0x1f, 0x0000);
3605
3606 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3607
3608 /* Modify green table for giga */
3609 rtl_writephy(tp, 0x1f, 0x0005);
3610 rtl_writephy(tp, 0x05, 0x8b54);
3611 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3612 rtl_writephy(tp, 0x05, 0x8b5d);
3613 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3614 rtl_writephy(tp, 0x05, 0x8a7c);
3615 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3616 rtl_writephy(tp, 0x05, 0x8a7f);
3617 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3618 rtl_writephy(tp, 0x05, 0x8a82);
3619 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3620 rtl_writephy(tp, 0x05, 0x8a85);
3621 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3622 rtl_writephy(tp, 0x05, 0x8a88);
3623 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3624 rtl_writephy(tp, 0x1f, 0x0000);
3625
3626 /* uc same-seed solution */
3627 rtl_writephy(tp, 0x1f, 0x0005);
3628 rtl_writephy(tp, 0x05, 0x8b85);
3629 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3630 rtl_writephy(tp, 0x1f, 0x0000);
3631
3632 /* eee setting */
3633 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3634 rtl_writephy(tp, 0x1f, 0x0005);
3635 rtl_writephy(tp, 0x05, 0x8b85);
3636 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3637 rtl_writephy(tp, 0x1f, 0x0004);
3638 rtl_writephy(tp, 0x1f, 0x0007);
3639 rtl_writephy(tp, 0x1e, 0x0020);
3640 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3641 rtl_writephy(tp, 0x1f, 0x0000);
3642 rtl_writephy(tp, 0x0d, 0x0007);
3643 rtl_writephy(tp, 0x0e, 0x003c);
3644 rtl_writephy(tp, 0x0d, 0x4007);
3645 rtl_writephy(tp, 0x0e, 0x0000);
3646 rtl_writephy(tp, 0x0d, 0x0000);
3647
3648 /* Green feature */
3649 rtl_writephy(tp, 0x1f, 0x0003);
3650 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3651 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3652 rtl_writephy(tp, 0x1f, 0x0000);
3653 }
3654
3655 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3656 {
3657 rtl_apply_firmware(tp);
3658
3659 rtl_writephy(tp, 0x1f, 0x0a46);
3660 if (rtl_readphy(tp, 0x10) & 0x0100) {
3661 rtl_writephy(tp, 0x1f, 0x0bcc);
3662 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3663 } else {
3664 rtl_writephy(tp, 0x1f, 0x0bcc);
3665 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3666 }
3667
3668 rtl_writephy(tp, 0x1f, 0x0a46);
3669 if (rtl_readphy(tp, 0x13) & 0x0100) {
3670 rtl_writephy(tp, 0x1f, 0x0c41);
3671 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3672 } else {
3673 rtl_writephy(tp, 0x1f, 0x0c41);
3674 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3675 }
3676
3677 /* Enable PHY auto speed down */
3678 rtl_writephy(tp, 0x1f, 0x0a44);
3679 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3680
3681 rtl_writephy(tp, 0x1f, 0x0bcc);
3682 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3683 rtl_writephy(tp, 0x1f, 0x0a44);
3684 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3685 rtl_writephy(tp, 0x1f, 0x0a43);
3686 rtl_writephy(tp, 0x13, 0x8084);
3687 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3688 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3689
3690 /* EEE auto-fallback function */
3691 rtl_writephy(tp, 0x1f, 0x0a4b);
3692 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3693
3694 /* Enable UC LPF tune function */
3695 rtl_writephy(tp, 0x1f, 0x0a43);
3696 rtl_writephy(tp, 0x13, 0x8012);
3697 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3698
3699 rtl_writephy(tp, 0x1f, 0x0c42);
3700 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3701
3702 /* Improve SWR Efficiency */
3703 rtl_writephy(tp, 0x1f, 0x0bcd);
3704 rtl_writephy(tp, 0x14, 0x5065);
3705 rtl_writephy(tp, 0x14, 0xd065);
3706 rtl_writephy(tp, 0x1f, 0x0bc8);
3707 rtl_writephy(tp, 0x11, 0x5655);
3708 rtl_writephy(tp, 0x1f, 0x0bcd);
3709 rtl_writephy(tp, 0x14, 0x1065);
3710 rtl_writephy(tp, 0x14, 0x9065);
3711 rtl_writephy(tp, 0x14, 0x1065);
3712
3713 /* Check ALDPS bit, disable it if enabled */
3714 rtl_writephy(tp, 0x1f, 0x0a43);
3715 if (rtl_readphy(tp, 0x10) & 0x0004)
3716 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3717
3718 rtl_writephy(tp, 0x1f, 0x0000);
3719 }
3720
3721 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3722 {
3723 rtl_apply_firmware(tp);
3724 }
3725
3726 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3727 {
3728 u16 dout_tapbin;
3729 u32 data;
3730
3731 rtl_apply_firmware(tp);
3732
3733 /* CHN EST parameters adjust - giga master */
3734 rtl_writephy(tp, 0x1f, 0x0a43);
3735 rtl_writephy(tp, 0x13, 0x809b);
3736 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3737 rtl_writephy(tp, 0x13, 0x80a2);
3738 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3739 rtl_writephy(tp, 0x13, 0x80a4);
3740 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3741 rtl_writephy(tp, 0x13, 0x809c);
3742 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3743 rtl_writephy(tp, 0x1f, 0x0000);
3744
3745 /* CHN EST parameters adjust - giga slave */
3746 rtl_writephy(tp, 0x1f, 0x0a43);
3747 rtl_writephy(tp, 0x13, 0x80ad);
3748 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3749 rtl_writephy(tp, 0x13, 0x80b4);
3750 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3751 rtl_writephy(tp, 0x13, 0x80ac);
3752 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3753 rtl_writephy(tp, 0x1f, 0x0000);
3754
3755 /* CHN EST parameters adjust - fnet */
3756 rtl_writephy(tp, 0x1f, 0x0a43);
3757 rtl_writephy(tp, 0x13, 0x808e);
3758 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3759 rtl_writephy(tp, 0x13, 0x8090);
3760 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3761 rtl_writephy(tp, 0x13, 0x8092);
3762 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3763 rtl_writephy(tp, 0x1f, 0x0000);
3764
3765 /* enable R-tune & PGA-retune function */
3766 dout_tapbin = 0;
3767 rtl_writephy(tp, 0x1f, 0x0a46);
3768 data = rtl_readphy(tp, 0x13);
3769 data &= 3;
3770 data <<= 2;
3771 dout_tapbin |= data;
3772 data = rtl_readphy(tp, 0x12);
3773 data &= 0xc000;
3774 data >>= 14;
3775 dout_tapbin |= data;
3776 dout_tapbin = ~(dout_tapbin^0x08);
3777 dout_tapbin <<= 12;
3778 dout_tapbin &= 0xf000;
3779 rtl_writephy(tp, 0x1f, 0x0a43);
3780 rtl_writephy(tp, 0x13, 0x827a);
3781 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3782 rtl_writephy(tp, 0x13, 0x827b);
3783 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3784 rtl_writephy(tp, 0x13, 0x827c);
3785 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3786 rtl_writephy(tp, 0x13, 0x827d);
3787 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3788
3789 rtl_writephy(tp, 0x1f, 0x0a43);
3790 rtl_writephy(tp, 0x13, 0x0811);
3791 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3792 rtl_writephy(tp, 0x1f, 0x0a42);
3793 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3794 rtl_writephy(tp, 0x1f, 0x0000);
3795
3796 /* enable GPHY 10M */
3797 rtl_writephy(tp, 0x1f, 0x0a44);
3798 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3799 rtl_writephy(tp, 0x1f, 0x0000);
3800
3801 /* SAR ADC performance */
3802 rtl_writephy(tp, 0x1f, 0x0bca);
3803 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3804 rtl_writephy(tp, 0x1f, 0x0000);
3805
3806 rtl_writephy(tp, 0x1f, 0x0a43);
3807 rtl_writephy(tp, 0x13, 0x803f);
3808 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3809 rtl_writephy(tp, 0x13, 0x8047);
3810 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3811 rtl_writephy(tp, 0x13, 0x804f);
3812 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3813 rtl_writephy(tp, 0x13, 0x8057);
3814 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3815 rtl_writephy(tp, 0x13, 0x805f);
3816 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3817 rtl_writephy(tp, 0x13, 0x8067);
3818 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3819 rtl_writephy(tp, 0x13, 0x806f);
3820 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3821 rtl_writephy(tp, 0x1f, 0x0000);
3822
3823 /* disable phy pfm mode */
3824 rtl_writephy(tp, 0x1f, 0x0a44);
3825 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3826 rtl_writephy(tp, 0x1f, 0x0000);
3827
3828 /* Check ALDPS bit, disable it if enabled */
3829 rtl_writephy(tp, 0x1f, 0x0a43);
3830 if (rtl_readphy(tp, 0x10) & 0x0004)
3831 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3832
3833 rtl_writephy(tp, 0x1f, 0x0000);
3834 }
3835
3836 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3837 {
3838 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3839 u16 rlen;
3840 u32 data;
3841
3842 rtl_apply_firmware(tp);
3843
3844 /* CHIN EST parameter update */
3845 rtl_writephy(tp, 0x1f, 0x0a43);
3846 rtl_writephy(tp, 0x13, 0x808a);
3847 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3848 rtl_writephy(tp, 0x1f, 0x0000);
3849
3850 /* enable R-tune & PGA-retune function */
3851 rtl_writephy(tp, 0x1f, 0x0a43);
3852 rtl_writephy(tp, 0x13, 0x0811);
3853 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3854 rtl_writephy(tp, 0x1f, 0x0a42);
3855 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3856 rtl_writephy(tp, 0x1f, 0x0000);
3857
3858 /* enable GPHY 10M */
3859 rtl_writephy(tp, 0x1f, 0x0a44);
3860 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3861 rtl_writephy(tp, 0x1f, 0x0000);
3862
3863 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3864 data = r8168_mac_ocp_read(tp, 0xdd02);
3865 ioffset_p3 = ((data & 0x80)>>7);
3866 ioffset_p3 <<= 3;
3867
3868 data = r8168_mac_ocp_read(tp, 0xdd00);
3869 ioffset_p3 |= ((data & (0xe000))>>13);
3870 ioffset_p2 = ((data & (0x1e00))>>9);
3871 ioffset_p1 = ((data & (0x01e0))>>5);
3872 ioffset_p0 = ((data & 0x0010)>>4);
3873 ioffset_p0 <<= 3;
3874 ioffset_p0 |= (data & (0x07));
3875 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3876
3877 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3878 (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
3879 rtl_writephy(tp, 0x1f, 0x0bcf);
3880 rtl_writephy(tp, 0x16, data);
3881 rtl_writephy(tp, 0x1f, 0x0000);
3882 }
3883
3884 /* Modify rlen (TX LPF corner frequency) level */
3885 rtl_writephy(tp, 0x1f, 0x0bcd);
3886 data = rtl_readphy(tp, 0x16);
3887 data &= 0x000f;
3888 rlen = 0;
3889 if (data > 3)
3890 rlen = data - 3;
3891 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3892 rtl_writephy(tp, 0x17, data);
3893 rtl_writephy(tp, 0x1f, 0x0bcd);
3894 rtl_writephy(tp, 0x1f, 0x0000);
3895
3896 /* disable phy pfm mode */
3897 rtl_writephy(tp, 0x1f, 0x0a44);
3898 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3899 rtl_writephy(tp, 0x1f, 0x0000);
3900
3901 /* Check ALDPS bit, disable it if enabled */
3902 rtl_writephy(tp, 0x1f, 0x0a43);
3903 if (rtl_readphy(tp, 0x10) & 0x0004)
3904 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3905
3906 rtl_writephy(tp, 0x1f, 0x0000);
3907 }
3908
3909 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3910 {
3911 /* Enable PHY auto speed down */
3912 rtl_writephy(tp, 0x1f, 0x0a44);
3913 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3914 rtl_writephy(tp, 0x1f, 0x0000);
3915
3916 /* patch 10M & ALDPS */
3917 rtl_writephy(tp, 0x1f, 0x0bcc);
3918 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3919 rtl_writephy(tp, 0x1f, 0x0a44);
3920 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3921 rtl_writephy(tp, 0x1f, 0x0a43);
3922 rtl_writephy(tp, 0x13, 0x8084);
3923 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3924 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3925 rtl_writephy(tp, 0x1f, 0x0000);
3926
3927 /* Enable EEE auto-fallback function */
3928 rtl_writephy(tp, 0x1f, 0x0a4b);
3929 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3930 rtl_writephy(tp, 0x1f, 0x0000);
3931
3932 /* Enable UC LPF tune function */
3933 rtl_writephy(tp, 0x1f, 0x0a43);
3934 rtl_writephy(tp, 0x13, 0x8012);
3935 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3936 rtl_writephy(tp, 0x1f, 0x0000);
3937
3938 /* set rg_sel_sdm_rate */
3939 rtl_writephy(tp, 0x1f, 0x0c42);
3940 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3941 rtl_writephy(tp, 0x1f, 0x0000);
3942
3943 /* Check ALDPS bit, disable it if enabled */
3944 rtl_writephy(tp, 0x1f, 0x0a43);
3945 if (rtl_readphy(tp, 0x10) & 0x0004)
3946 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3947
3948 rtl_writephy(tp, 0x1f, 0x0000);
3949 }
3950
3951 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3952 {
3953 /* patch 10M & ALDPS */
3954 rtl_writephy(tp, 0x1f, 0x0bcc);
3955 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3956 rtl_writephy(tp, 0x1f, 0x0a44);
3957 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3958 rtl_writephy(tp, 0x1f, 0x0a43);
3959 rtl_writephy(tp, 0x13, 0x8084);
3960 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3961 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3962 rtl_writephy(tp, 0x1f, 0x0000);
3963
3964 /* Enable UC LPF tune function */
3965 rtl_writephy(tp, 0x1f, 0x0a43);
3966 rtl_writephy(tp, 0x13, 0x8012);
3967 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3968 rtl_writephy(tp, 0x1f, 0x0000);
3969
3970 /* Set rg_sel_sdm_rate */
3971 rtl_writephy(tp, 0x1f, 0x0c42);
3972 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3973 rtl_writephy(tp, 0x1f, 0x0000);
3974
3975 /* Channel estimation parameters */
3976 rtl_writephy(tp, 0x1f, 0x0a43);
3977 rtl_writephy(tp, 0x13, 0x80f3);
3978 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3979 rtl_writephy(tp, 0x13, 0x80f0);
3980 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3981 rtl_writephy(tp, 0x13, 0x80ef);
3982 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3983 rtl_writephy(tp, 0x13, 0x80f6);
3984 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3985 rtl_writephy(tp, 0x13, 0x80ec);
3986 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3987 rtl_writephy(tp, 0x13, 0x80ed);
3988 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3989 rtl_writephy(tp, 0x13, 0x80f2);
3990 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3991 rtl_writephy(tp, 0x13, 0x80f4);
3992 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3993 rtl_writephy(tp, 0x1f, 0x0a43);
3994 rtl_writephy(tp, 0x13, 0x8110);
3995 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3996 rtl_writephy(tp, 0x13, 0x810f);
3997 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3998 rtl_writephy(tp, 0x13, 0x8111);
3999 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4000 rtl_writephy(tp, 0x13, 0x8113);
4001 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4002 rtl_writephy(tp, 0x13, 0x8115);
4003 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4004 rtl_writephy(tp, 0x13, 0x810e);
4005 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4006 rtl_writephy(tp, 0x13, 0x810c);
4007 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4008 rtl_writephy(tp, 0x13, 0x810b);
4009 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4010 rtl_writephy(tp, 0x1f, 0x0a43);
4011 rtl_writephy(tp, 0x13, 0x80d1);
4012 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4013 rtl_writephy(tp, 0x13, 0x80cd);
4014 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4015 rtl_writephy(tp, 0x13, 0x80d3);
4016 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4017 rtl_writephy(tp, 0x13, 0x80d5);
4018 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4019 rtl_writephy(tp, 0x13, 0x80d7);
4020 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4021
4022 /* Force PWM-mode */
4023 rtl_writephy(tp, 0x1f, 0x0bcd);
4024 rtl_writephy(tp, 0x14, 0x5065);
4025 rtl_writephy(tp, 0x14, 0xd065);
4026 rtl_writephy(tp, 0x1f, 0x0bc8);
4027 rtl_writephy(tp, 0x12, 0x00ed);
4028 rtl_writephy(tp, 0x1f, 0x0bcd);
4029 rtl_writephy(tp, 0x14, 0x1065);
4030 rtl_writephy(tp, 0x14, 0x9065);
4031 rtl_writephy(tp, 0x14, 0x1065);
4032 rtl_writephy(tp, 0x1f, 0x0000);
4033
4034 /* Check ALDPS bit, disable it if enabled */
4035 rtl_writephy(tp, 0x1f, 0x0a43);
4036 if (rtl_readphy(tp, 0x10) & 0x0004)
4037 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4038
4039 rtl_writephy(tp, 0x1f, 0x0000);
4040 }
4041
4042 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4043 {
4044 static const struct phy_reg phy_reg_init[] = {
4045 { 0x1f, 0x0003 },
4046 { 0x08, 0x441d },
4047 { 0x01, 0x9100 },
4048 { 0x1f, 0x0000 }
4049 };
4050
4051 rtl_writephy(tp, 0x1f, 0x0000);
4052 rtl_patchphy(tp, 0x11, 1 << 12);
4053 rtl_patchphy(tp, 0x19, 1 << 13);
4054 rtl_patchphy(tp, 0x10, 1 << 15);
4055
4056 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4057 }
4058
4059 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4060 {
4061 static const struct phy_reg phy_reg_init[] = {
4062 { 0x1f, 0x0005 },
4063 { 0x1a, 0x0000 },
4064 { 0x1f, 0x0000 },
4065
4066 { 0x1f, 0x0004 },
4067 { 0x1c, 0x0000 },
4068 { 0x1f, 0x0000 },
4069
4070 { 0x1f, 0x0001 },
4071 { 0x15, 0x7701 },
4072 { 0x1f, 0x0000 }
4073 };
4074
4075 /* Disable ALDPS before ram code */
4076 rtl_writephy(tp, 0x1f, 0x0000);
4077 rtl_writephy(tp, 0x18, 0x0310);
4078 msleep(100);
4079
4080 rtl_apply_firmware(tp);
4081
4082 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4083 }
4084
4085 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4086 {
4087 /* Disable ALDPS before setting firmware */
4088 rtl_writephy(tp, 0x1f, 0x0000);
4089 rtl_writephy(tp, 0x18, 0x0310);
4090 msleep(20);
4091
4092 rtl_apply_firmware(tp);
4093
4094 /* EEE setting */
4095 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4096 rtl_writephy(tp, 0x1f, 0x0004);
4097 rtl_writephy(tp, 0x10, 0x401f);
4098 rtl_writephy(tp, 0x19, 0x7030);
4099 rtl_writephy(tp, 0x1f, 0x0000);
4100 }
4101
4102 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4103 {
4104 static const struct phy_reg phy_reg_init[] = {
4105 { 0x1f, 0x0004 },
4106 { 0x10, 0xc07f },
4107 { 0x19, 0x7030 },
4108 { 0x1f, 0x0000 }
4109 };
4110
4111 /* Disable ALDPS before ram code */
4112 rtl_writephy(tp, 0x1f, 0x0000);
4113 rtl_writephy(tp, 0x18, 0x0310);
4114 msleep(100);
4115
4116 rtl_apply_firmware(tp);
4117
4118 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4119 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4120
4121 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4122 }
4123
4124 static void rtl_hw_phy_config(struct net_device *dev)
4125 {
4126 struct rtl8169_private *tp = netdev_priv(dev);
4127
4128 rtl8169_print_mac_version(tp);
4129
4130 switch (tp->mac_version) {
4131 case RTL_GIGA_MAC_VER_01:
4132 break;
4133 case RTL_GIGA_MAC_VER_02:
4134 case RTL_GIGA_MAC_VER_03:
4135 rtl8169s_hw_phy_config(tp);
4136 break;
4137 case RTL_GIGA_MAC_VER_04:
4138 rtl8169sb_hw_phy_config(tp);
4139 break;
4140 case RTL_GIGA_MAC_VER_05:
4141 rtl8169scd_hw_phy_config(tp);
4142 break;
4143 case RTL_GIGA_MAC_VER_06:
4144 rtl8169sce_hw_phy_config(tp);
4145 break;
4146 case RTL_GIGA_MAC_VER_07:
4147 case RTL_GIGA_MAC_VER_08:
4148 case RTL_GIGA_MAC_VER_09:
4149 rtl8102e_hw_phy_config(tp);
4150 break;
4151 case RTL_GIGA_MAC_VER_11:
4152 rtl8168bb_hw_phy_config(tp);
4153 break;
4154 case RTL_GIGA_MAC_VER_12:
4155 rtl8168bef_hw_phy_config(tp);
4156 break;
4157 case RTL_GIGA_MAC_VER_17:
4158 rtl8168bef_hw_phy_config(tp);
4159 break;
4160 case RTL_GIGA_MAC_VER_18:
4161 rtl8168cp_1_hw_phy_config(tp);
4162 break;
4163 case RTL_GIGA_MAC_VER_19:
4164 rtl8168c_1_hw_phy_config(tp);
4165 break;
4166 case RTL_GIGA_MAC_VER_20:
4167 rtl8168c_2_hw_phy_config(tp);
4168 break;
4169 case RTL_GIGA_MAC_VER_21:
4170 rtl8168c_3_hw_phy_config(tp);
4171 break;
4172 case RTL_GIGA_MAC_VER_22:
4173 rtl8168c_4_hw_phy_config(tp);
4174 break;
4175 case RTL_GIGA_MAC_VER_23:
4176 case RTL_GIGA_MAC_VER_24:
4177 rtl8168cp_2_hw_phy_config(tp);
4178 break;
4179 case RTL_GIGA_MAC_VER_25:
4180 rtl8168d_1_hw_phy_config(tp);
4181 break;
4182 case RTL_GIGA_MAC_VER_26:
4183 rtl8168d_2_hw_phy_config(tp);
4184 break;
4185 case RTL_GIGA_MAC_VER_27:
4186 rtl8168d_3_hw_phy_config(tp);
4187 break;
4188 case RTL_GIGA_MAC_VER_28:
4189 rtl8168d_4_hw_phy_config(tp);
4190 break;
4191 case RTL_GIGA_MAC_VER_29:
4192 case RTL_GIGA_MAC_VER_30:
4193 rtl8105e_hw_phy_config(tp);
4194 break;
4195 case RTL_GIGA_MAC_VER_31:
4196 /* None. */
4197 break;
4198 case RTL_GIGA_MAC_VER_32:
4199 case RTL_GIGA_MAC_VER_33:
4200 rtl8168e_1_hw_phy_config(tp);
4201 break;
4202 case RTL_GIGA_MAC_VER_34:
4203 rtl8168e_2_hw_phy_config(tp);
4204 break;
4205 case RTL_GIGA_MAC_VER_35:
4206 rtl8168f_1_hw_phy_config(tp);
4207 break;
4208 case RTL_GIGA_MAC_VER_36:
4209 rtl8168f_2_hw_phy_config(tp);
4210 break;
4211
4212 case RTL_GIGA_MAC_VER_37:
4213 rtl8402_hw_phy_config(tp);
4214 break;
4215
4216 case RTL_GIGA_MAC_VER_38:
4217 rtl8411_hw_phy_config(tp);
4218 break;
4219
4220 case RTL_GIGA_MAC_VER_39:
4221 rtl8106e_hw_phy_config(tp);
4222 break;
4223
4224 case RTL_GIGA_MAC_VER_40:
4225 rtl8168g_1_hw_phy_config(tp);
4226 break;
4227 case RTL_GIGA_MAC_VER_42:
4228 case RTL_GIGA_MAC_VER_43:
4229 case RTL_GIGA_MAC_VER_44:
4230 rtl8168g_2_hw_phy_config(tp);
4231 break;
4232 case RTL_GIGA_MAC_VER_45:
4233 case RTL_GIGA_MAC_VER_47:
4234 rtl8168h_1_hw_phy_config(tp);
4235 break;
4236 case RTL_GIGA_MAC_VER_46:
4237 case RTL_GIGA_MAC_VER_48:
4238 rtl8168h_2_hw_phy_config(tp);
4239 break;
4240
4241 case RTL_GIGA_MAC_VER_49:
4242 rtl8168ep_1_hw_phy_config(tp);
4243 break;
4244 case RTL_GIGA_MAC_VER_50:
4245 case RTL_GIGA_MAC_VER_51:
4246 rtl8168ep_2_hw_phy_config(tp);
4247 break;
4248
4249 case RTL_GIGA_MAC_VER_41:
4250 default:
4251 break;
4252 }
4253 }
4254
4255 static void rtl_phy_work(struct rtl8169_private *tp)
4256 {
4257 struct timer_list *timer = &tp->timer;
4258 void __iomem *ioaddr = tp->mmio_addr;
4259 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4260
4261 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4262
4263 if (tp->phy_reset_pending(tp)) {
4264 /*
4265 * A busy loop could burn quite a few cycles on nowadays CPU.
4266 * Let's delay the execution of the timer for a few ticks.
4267 */
4268 timeout = HZ/10;
4269 goto out_mod_timer;
4270 }
4271
4272 if (tp->link_ok(ioaddr))
4273 return;
4274
4275 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4276
4277 tp->phy_reset_enable(tp);
4278
4279 out_mod_timer:
4280 mod_timer(timer, jiffies + timeout);
4281 }
4282
4283 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4284 {
4285 if (!test_and_set_bit(flag, tp->wk.flags))
4286 schedule_work(&tp->wk.work);
4287 }
4288
4289 static void rtl8169_phy_timer(unsigned long __opaque)
4290 {
4291 struct net_device *dev = (struct net_device *)__opaque;
4292 struct rtl8169_private *tp = netdev_priv(dev);
4293
4294 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4295 }
4296
4297 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4298 void __iomem *ioaddr)
4299 {
4300 iounmap(ioaddr);
4301 pci_release_regions(pdev);
4302 pci_clear_mwi(pdev);
4303 pci_disable_device(pdev);
4304 free_netdev(dev);
4305 }
4306
4307 DECLARE_RTL_COND(rtl_phy_reset_cond)
4308 {
4309 return tp->phy_reset_pending(tp);
4310 }
4311
4312 static void rtl8169_phy_reset(struct net_device *dev,
4313 struct rtl8169_private *tp)
4314 {
4315 tp->phy_reset_enable(tp);
4316 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4317 }
4318
4319 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4320 {
4321 void __iomem *ioaddr = tp->mmio_addr;
4322
4323 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4324 (RTL_R8(PHYstatus) & TBI_Enable);
4325 }
4326
4327 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4328 {
4329 void __iomem *ioaddr = tp->mmio_addr;
4330
4331 rtl_hw_phy_config(dev);
4332
4333 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4334 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4335 RTL_W8(0x82, 0x01);
4336 }
4337
4338 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4339
4340 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4341 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4342
4343 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4344 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4345 RTL_W8(0x82, 0x01);
4346 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4347 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4348 }
4349
4350 rtl8169_phy_reset(dev, tp);
4351
4352 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4353 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4354 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4355 (tp->mii.supports_gmii ?
4356 ADVERTISED_1000baseT_Half |
4357 ADVERTISED_1000baseT_Full : 0));
4358
4359 if (rtl_tbi_enabled(tp))
4360 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4361 }
4362
4363 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4364 {
4365 void __iomem *ioaddr = tp->mmio_addr;
4366
4367 rtl_lock_work(tp);
4368
4369 RTL_W8(Cfg9346, Cfg9346_Unlock);
4370
4371 RTL_W32(MAC4, addr[4] | addr[5] << 8);
4372 RTL_R32(MAC4);
4373
4374 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4375 RTL_R32(MAC0);
4376
4377 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4378 rtl_rar_exgmac_set(tp, addr);
4379
4380 RTL_W8(Cfg9346, Cfg9346_Lock);
4381
4382 rtl_unlock_work(tp);
4383 }
4384
4385 static int rtl_set_mac_address(struct net_device *dev, void *p)
4386 {
4387 struct rtl8169_private *tp = netdev_priv(dev);
4388 struct sockaddr *addr = p;
4389
4390 if (!is_valid_ether_addr(addr->sa_data))
4391 return -EADDRNOTAVAIL;
4392
4393 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4394
4395 rtl_rar_set(tp, dev->dev_addr);
4396
4397 return 0;
4398 }
4399
4400 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4401 {
4402 struct rtl8169_private *tp = netdev_priv(dev);
4403 struct mii_ioctl_data *data = if_mii(ifr);
4404
4405 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4406 }
4407
4408 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4409 struct mii_ioctl_data *data, int cmd)
4410 {
4411 switch (cmd) {
4412 case SIOCGMIIPHY:
4413 data->phy_id = 32; /* Internal PHY */
4414 return 0;
4415
4416 case SIOCGMIIREG:
4417 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4418 return 0;
4419
4420 case SIOCSMIIREG:
4421 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4422 return 0;
4423 }
4424 return -EOPNOTSUPP;
4425 }
4426
4427 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4428 {
4429 return -EOPNOTSUPP;
4430 }
4431
4432 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4433 {
4434 if (tp->features & RTL_FEATURE_MSI) {
4435 pci_disable_msi(pdev);
4436 tp->features &= ~RTL_FEATURE_MSI;
4437 }
4438 }
4439
4440 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4441 {
4442 struct mdio_ops *ops = &tp->mdio_ops;
4443
4444 switch (tp->mac_version) {
4445 case RTL_GIGA_MAC_VER_27:
4446 ops->write = r8168dp_1_mdio_write;
4447 ops->read = r8168dp_1_mdio_read;
4448 break;
4449 case RTL_GIGA_MAC_VER_28:
4450 case RTL_GIGA_MAC_VER_31:
4451 ops->write = r8168dp_2_mdio_write;
4452 ops->read = r8168dp_2_mdio_read;
4453 break;
4454 case RTL_GIGA_MAC_VER_40:
4455 case RTL_GIGA_MAC_VER_41:
4456 case RTL_GIGA_MAC_VER_42:
4457 case RTL_GIGA_MAC_VER_43:
4458 case RTL_GIGA_MAC_VER_44:
4459 case RTL_GIGA_MAC_VER_45:
4460 case RTL_GIGA_MAC_VER_46:
4461 case RTL_GIGA_MAC_VER_47:
4462 case RTL_GIGA_MAC_VER_48:
4463 case RTL_GIGA_MAC_VER_49:
4464 case RTL_GIGA_MAC_VER_50:
4465 case RTL_GIGA_MAC_VER_51:
4466 ops->write = r8168g_mdio_write;
4467 ops->read = r8168g_mdio_read;
4468 break;
4469 default:
4470 ops->write = r8169_mdio_write;
4471 ops->read = r8169_mdio_read;
4472 break;
4473 }
4474 }
4475
4476 static void rtl_speed_down(struct rtl8169_private *tp)
4477 {
4478 u32 adv;
4479 int lpa;
4480
4481 rtl_writephy(tp, 0x1f, 0x0000);
4482 lpa = rtl_readphy(tp, MII_LPA);
4483
4484 if (lpa & (LPA_10HALF | LPA_10FULL))
4485 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4486 else if (lpa & (LPA_100HALF | LPA_100FULL))
4487 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4488 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4489 else
4490 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4491 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4492 (tp->mii.supports_gmii ?
4493 ADVERTISED_1000baseT_Half |
4494 ADVERTISED_1000baseT_Full : 0);
4495
4496 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4497 adv);
4498 }
4499
4500 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4501 {
4502 void __iomem *ioaddr = tp->mmio_addr;
4503
4504 switch (tp->mac_version) {
4505 case RTL_GIGA_MAC_VER_25:
4506 case RTL_GIGA_MAC_VER_26:
4507 case RTL_GIGA_MAC_VER_29:
4508 case RTL_GIGA_MAC_VER_30:
4509 case RTL_GIGA_MAC_VER_32:
4510 case RTL_GIGA_MAC_VER_33:
4511 case RTL_GIGA_MAC_VER_34:
4512 case RTL_GIGA_MAC_VER_37:
4513 case RTL_GIGA_MAC_VER_38:
4514 case RTL_GIGA_MAC_VER_39:
4515 case RTL_GIGA_MAC_VER_40:
4516 case RTL_GIGA_MAC_VER_41:
4517 case RTL_GIGA_MAC_VER_42:
4518 case RTL_GIGA_MAC_VER_43:
4519 case RTL_GIGA_MAC_VER_44:
4520 case RTL_GIGA_MAC_VER_45:
4521 case RTL_GIGA_MAC_VER_46:
4522 case RTL_GIGA_MAC_VER_47:
4523 case RTL_GIGA_MAC_VER_48:
4524 case RTL_GIGA_MAC_VER_49:
4525 case RTL_GIGA_MAC_VER_50:
4526 case RTL_GIGA_MAC_VER_51:
4527 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4528 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4529 break;
4530 default:
4531 break;
4532 }
4533 }
4534
4535 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4536 {
4537 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4538 return false;
4539
4540 rtl_speed_down(tp);
4541 rtl_wol_suspend_quirk(tp);
4542
4543 return true;
4544 }
4545
4546 static void r810x_phy_power_down(struct rtl8169_private *tp)
4547 {
4548 rtl_writephy(tp, 0x1f, 0x0000);
4549 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4550 }
4551
4552 static void r810x_phy_power_up(struct rtl8169_private *tp)
4553 {
4554 rtl_writephy(tp, 0x1f, 0x0000);
4555 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4556 }
4557
4558 static void r810x_pll_power_down(struct rtl8169_private *tp)
4559 {
4560 void __iomem *ioaddr = tp->mmio_addr;
4561
4562 if (rtl_wol_pll_power_down(tp))
4563 return;
4564
4565 r810x_phy_power_down(tp);
4566
4567 switch (tp->mac_version) {
4568 case RTL_GIGA_MAC_VER_07:
4569 case RTL_GIGA_MAC_VER_08:
4570 case RTL_GIGA_MAC_VER_09:
4571 case RTL_GIGA_MAC_VER_10:
4572 case RTL_GIGA_MAC_VER_13:
4573 case RTL_GIGA_MAC_VER_16:
4574 break;
4575 default:
4576 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4577 break;
4578 }
4579 }
4580
4581 static void r810x_pll_power_up(struct rtl8169_private *tp)
4582 {
4583 void __iomem *ioaddr = tp->mmio_addr;
4584
4585 r810x_phy_power_up(tp);
4586
4587 switch (tp->mac_version) {
4588 case RTL_GIGA_MAC_VER_07:
4589 case RTL_GIGA_MAC_VER_08:
4590 case RTL_GIGA_MAC_VER_09:
4591 case RTL_GIGA_MAC_VER_10:
4592 case RTL_GIGA_MAC_VER_13:
4593 case RTL_GIGA_MAC_VER_16:
4594 break;
4595 case RTL_GIGA_MAC_VER_47:
4596 case RTL_GIGA_MAC_VER_48:
4597 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4598 break;
4599 default:
4600 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4601 break;
4602 }
4603 }
4604
4605 static void r8168_phy_power_up(struct rtl8169_private *tp)
4606 {
4607 rtl_writephy(tp, 0x1f, 0x0000);
4608 switch (tp->mac_version) {
4609 case RTL_GIGA_MAC_VER_11:
4610 case RTL_GIGA_MAC_VER_12:
4611 case RTL_GIGA_MAC_VER_17:
4612 case RTL_GIGA_MAC_VER_18:
4613 case RTL_GIGA_MAC_VER_19:
4614 case RTL_GIGA_MAC_VER_20:
4615 case RTL_GIGA_MAC_VER_21:
4616 case RTL_GIGA_MAC_VER_22:
4617 case RTL_GIGA_MAC_VER_23:
4618 case RTL_GIGA_MAC_VER_24:
4619 case RTL_GIGA_MAC_VER_25:
4620 case RTL_GIGA_MAC_VER_26:
4621 case RTL_GIGA_MAC_VER_27:
4622 case RTL_GIGA_MAC_VER_28:
4623 case RTL_GIGA_MAC_VER_31:
4624 rtl_writephy(tp, 0x0e, 0x0000);
4625 break;
4626 default:
4627 break;
4628 }
4629 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4630 }
4631
4632 static void r8168_phy_power_down(struct rtl8169_private *tp)
4633 {
4634 rtl_writephy(tp, 0x1f, 0x0000);
4635 switch (tp->mac_version) {
4636 case RTL_GIGA_MAC_VER_32:
4637 case RTL_GIGA_MAC_VER_33:
4638 case RTL_GIGA_MAC_VER_40:
4639 case RTL_GIGA_MAC_VER_41:
4640 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4641 break;
4642
4643 case RTL_GIGA_MAC_VER_11:
4644 case RTL_GIGA_MAC_VER_12:
4645 case RTL_GIGA_MAC_VER_17:
4646 case RTL_GIGA_MAC_VER_18:
4647 case RTL_GIGA_MAC_VER_19:
4648 case RTL_GIGA_MAC_VER_20:
4649 case RTL_GIGA_MAC_VER_21:
4650 case RTL_GIGA_MAC_VER_22:
4651 case RTL_GIGA_MAC_VER_23:
4652 case RTL_GIGA_MAC_VER_24:
4653 case RTL_GIGA_MAC_VER_25:
4654 case RTL_GIGA_MAC_VER_26:
4655 case RTL_GIGA_MAC_VER_27:
4656 case RTL_GIGA_MAC_VER_28:
4657 case RTL_GIGA_MAC_VER_31:
4658 rtl_writephy(tp, 0x0e, 0x0200);
4659 default:
4660 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4661 break;
4662 }
4663 }
4664
4665 static void r8168_pll_power_down(struct rtl8169_private *tp)
4666 {
4667 void __iomem *ioaddr = tp->mmio_addr;
4668
4669 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4670 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4671 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4672 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4673 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4674 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4675 r8168_check_dash(tp)) {
4676 return;
4677 }
4678
4679 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4680 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4681 (RTL_R16(CPlusCmd) & ASF)) {
4682 return;
4683 }
4684
4685 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4686 tp->mac_version == RTL_GIGA_MAC_VER_33)
4687 rtl_ephy_write(tp, 0x19, 0xff64);
4688
4689 if (rtl_wol_pll_power_down(tp))
4690 return;
4691
4692 r8168_phy_power_down(tp);
4693
4694 switch (tp->mac_version) {
4695 case RTL_GIGA_MAC_VER_25:
4696 case RTL_GIGA_MAC_VER_26:
4697 case RTL_GIGA_MAC_VER_27:
4698 case RTL_GIGA_MAC_VER_28:
4699 case RTL_GIGA_MAC_VER_31:
4700 case RTL_GIGA_MAC_VER_32:
4701 case RTL_GIGA_MAC_VER_33:
4702 case RTL_GIGA_MAC_VER_44:
4703 case RTL_GIGA_MAC_VER_45:
4704 case RTL_GIGA_MAC_VER_46:
4705 case RTL_GIGA_MAC_VER_50:
4706 case RTL_GIGA_MAC_VER_51:
4707 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4708 break;
4709 case RTL_GIGA_MAC_VER_40:
4710 case RTL_GIGA_MAC_VER_41:
4711 case RTL_GIGA_MAC_VER_49:
4712 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4713 0xfc000000, ERIAR_EXGMAC);
4714 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4715 break;
4716 }
4717 }
4718
4719 static void r8168_pll_power_up(struct rtl8169_private *tp)
4720 {
4721 void __iomem *ioaddr = tp->mmio_addr;
4722
4723 switch (tp->mac_version) {
4724 case RTL_GIGA_MAC_VER_25:
4725 case RTL_GIGA_MAC_VER_26:
4726 case RTL_GIGA_MAC_VER_27:
4727 case RTL_GIGA_MAC_VER_28:
4728 case RTL_GIGA_MAC_VER_31:
4729 case RTL_GIGA_MAC_VER_32:
4730 case RTL_GIGA_MAC_VER_33:
4731 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4732 break;
4733 case RTL_GIGA_MAC_VER_44:
4734 case RTL_GIGA_MAC_VER_45:
4735 case RTL_GIGA_MAC_VER_46:
4736 case RTL_GIGA_MAC_VER_50:
4737 case RTL_GIGA_MAC_VER_51:
4738 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4739 break;
4740 case RTL_GIGA_MAC_VER_40:
4741 case RTL_GIGA_MAC_VER_41:
4742 case RTL_GIGA_MAC_VER_49:
4743 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4744 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4745 0x00000000, ERIAR_EXGMAC);
4746 break;
4747 }
4748
4749 r8168_phy_power_up(tp);
4750 }
4751
4752 static void rtl_generic_op(struct rtl8169_private *tp,
4753 void (*op)(struct rtl8169_private *))
4754 {
4755 if (op)
4756 op(tp);
4757 }
4758
4759 static void rtl_pll_power_down(struct rtl8169_private *tp)
4760 {
4761 rtl_generic_op(tp, tp->pll_power_ops.down);
4762 }
4763
4764 static void rtl_pll_power_up(struct rtl8169_private *tp)
4765 {
4766 rtl_generic_op(tp, tp->pll_power_ops.up);
4767 }
4768
4769 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4770 {
4771 struct pll_power_ops *ops = &tp->pll_power_ops;
4772
4773 switch (tp->mac_version) {
4774 case RTL_GIGA_MAC_VER_07:
4775 case RTL_GIGA_MAC_VER_08:
4776 case RTL_GIGA_MAC_VER_09:
4777 case RTL_GIGA_MAC_VER_10:
4778 case RTL_GIGA_MAC_VER_16:
4779 case RTL_GIGA_MAC_VER_29:
4780 case RTL_GIGA_MAC_VER_30:
4781 case RTL_GIGA_MAC_VER_37:
4782 case RTL_GIGA_MAC_VER_39:
4783 case RTL_GIGA_MAC_VER_43:
4784 case RTL_GIGA_MAC_VER_47:
4785 case RTL_GIGA_MAC_VER_48:
4786 ops->down = r810x_pll_power_down;
4787 ops->up = r810x_pll_power_up;
4788 break;
4789
4790 case RTL_GIGA_MAC_VER_11:
4791 case RTL_GIGA_MAC_VER_12:
4792 case RTL_GIGA_MAC_VER_17:
4793 case RTL_GIGA_MAC_VER_18:
4794 case RTL_GIGA_MAC_VER_19:
4795 case RTL_GIGA_MAC_VER_20:
4796 case RTL_GIGA_MAC_VER_21:
4797 case RTL_GIGA_MAC_VER_22:
4798 case RTL_GIGA_MAC_VER_23:
4799 case RTL_GIGA_MAC_VER_24:
4800 case RTL_GIGA_MAC_VER_25:
4801 case RTL_GIGA_MAC_VER_26:
4802 case RTL_GIGA_MAC_VER_27:
4803 case RTL_GIGA_MAC_VER_28:
4804 case RTL_GIGA_MAC_VER_31:
4805 case RTL_GIGA_MAC_VER_32:
4806 case RTL_GIGA_MAC_VER_33:
4807 case RTL_GIGA_MAC_VER_34:
4808 case RTL_GIGA_MAC_VER_35:
4809 case RTL_GIGA_MAC_VER_36:
4810 case RTL_GIGA_MAC_VER_38:
4811 case RTL_GIGA_MAC_VER_40:
4812 case RTL_GIGA_MAC_VER_41:
4813 case RTL_GIGA_MAC_VER_42:
4814 case RTL_GIGA_MAC_VER_44:
4815 case RTL_GIGA_MAC_VER_45:
4816 case RTL_GIGA_MAC_VER_46:
4817 case RTL_GIGA_MAC_VER_49:
4818 case RTL_GIGA_MAC_VER_50:
4819 case RTL_GIGA_MAC_VER_51:
4820 ops->down = r8168_pll_power_down;
4821 ops->up = r8168_pll_power_up;
4822 break;
4823
4824 default:
4825 ops->down = NULL;
4826 ops->up = NULL;
4827 break;
4828 }
4829 }
4830
4831 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4832 {
4833 void __iomem *ioaddr = tp->mmio_addr;
4834
4835 switch (tp->mac_version) {
4836 case RTL_GIGA_MAC_VER_01:
4837 case RTL_GIGA_MAC_VER_02:
4838 case RTL_GIGA_MAC_VER_03:
4839 case RTL_GIGA_MAC_VER_04:
4840 case RTL_GIGA_MAC_VER_05:
4841 case RTL_GIGA_MAC_VER_06:
4842 case RTL_GIGA_MAC_VER_10:
4843 case RTL_GIGA_MAC_VER_11:
4844 case RTL_GIGA_MAC_VER_12:
4845 case RTL_GIGA_MAC_VER_13:
4846 case RTL_GIGA_MAC_VER_14:
4847 case RTL_GIGA_MAC_VER_15:
4848 case RTL_GIGA_MAC_VER_16:
4849 case RTL_GIGA_MAC_VER_17:
4850 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4851 break;
4852 case RTL_GIGA_MAC_VER_18:
4853 case RTL_GIGA_MAC_VER_19:
4854 case RTL_GIGA_MAC_VER_20:
4855 case RTL_GIGA_MAC_VER_21:
4856 case RTL_GIGA_MAC_VER_22:
4857 case RTL_GIGA_MAC_VER_23:
4858 case RTL_GIGA_MAC_VER_24:
4859 case RTL_GIGA_MAC_VER_34:
4860 case RTL_GIGA_MAC_VER_35:
4861 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4862 break;
4863 case RTL_GIGA_MAC_VER_40:
4864 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4865 break;
4866 case RTL_GIGA_MAC_VER_41:
4867 case RTL_GIGA_MAC_VER_42:
4868 case RTL_GIGA_MAC_VER_43:
4869 case RTL_GIGA_MAC_VER_44:
4870 case RTL_GIGA_MAC_VER_45:
4871 case RTL_GIGA_MAC_VER_46:
4872 case RTL_GIGA_MAC_VER_47:
4873 case RTL_GIGA_MAC_VER_48:
4874 case RTL_GIGA_MAC_VER_49:
4875 case RTL_GIGA_MAC_VER_50:
4876 case RTL_GIGA_MAC_VER_51:
4877 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4878 break;
4879 default:
4880 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4881 break;
4882 }
4883 }
4884
4885 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4886 {
4887 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4888 }
4889
4890 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4891 {
4892 void __iomem *ioaddr = tp->mmio_addr;
4893
4894 RTL_W8(Cfg9346, Cfg9346_Unlock);
4895 rtl_generic_op(tp, tp->jumbo_ops.enable);
4896 RTL_W8(Cfg9346, Cfg9346_Lock);
4897 }
4898
4899 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4900 {
4901 void __iomem *ioaddr = tp->mmio_addr;
4902
4903 RTL_W8(Cfg9346, Cfg9346_Unlock);
4904 rtl_generic_op(tp, tp->jumbo_ops.disable);
4905 RTL_W8(Cfg9346, Cfg9346_Lock);
4906 }
4907
4908 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4909 {
4910 void __iomem *ioaddr = tp->mmio_addr;
4911
4912 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4913 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4914 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4915 }
4916
4917 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4918 {
4919 void __iomem *ioaddr = tp->mmio_addr;
4920
4921 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4922 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4923 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4924 }
4925
4926 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4927 {
4928 void __iomem *ioaddr = tp->mmio_addr;
4929
4930 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4931 }
4932
4933 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4934 {
4935 void __iomem *ioaddr = tp->mmio_addr;
4936
4937 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4938 }
4939
4940 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4941 {
4942 void __iomem *ioaddr = tp->mmio_addr;
4943
4944 RTL_W8(MaxTxPacketSize, 0x3f);
4945 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4946 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4947 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4948 }
4949
4950 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4951 {
4952 void __iomem *ioaddr = tp->mmio_addr;
4953
4954 RTL_W8(MaxTxPacketSize, 0x0c);
4955 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4956 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4957 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4958 }
4959
4960 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4961 {
4962 rtl_tx_performance_tweak(tp->pci_dev,
4963 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4964 }
4965
4966 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4967 {
4968 rtl_tx_performance_tweak(tp->pci_dev,
4969 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4970 }
4971
4972 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4973 {
4974 void __iomem *ioaddr = tp->mmio_addr;
4975
4976 r8168b_0_hw_jumbo_enable(tp);
4977
4978 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4979 }
4980
4981 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4982 {
4983 void __iomem *ioaddr = tp->mmio_addr;
4984
4985 r8168b_0_hw_jumbo_disable(tp);
4986
4987 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4988 }
4989
4990 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4991 {
4992 struct jumbo_ops *ops = &tp->jumbo_ops;
4993
4994 switch (tp->mac_version) {
4995 case RTL_GIGA_MAC_VER_11:
4996 ops->disable = r8168b_0_hw_jumbo_disable;
4997 ops->enable = r8168b_0_hw_jumbo_enable;
4998 break;
4999 case RTL_GIGA_MAC_VER_12:
5000 case RTL_GIGA_MAC_VER_17:
5001 ops->disable = r8168b_1_hw_jumbo_disable;
5002 ops->enable = r8168b_1_hw_jumbo_enable;
5003 break;
5004 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5005 case RTL_GIGA_MAC_VER_19:
5006 case RTL_GIGA_MAC_VER_20:
5007 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5008 case RTL_GIGA_MAC_VER_22:
5009 case RTL_GIGA_MAC_VER_23:
5010 case RTL_GIGA_MAC_VER_24:
5011 case RTL_GIGA_MAC_VER_25:
5012 case RTL_GIGA_MAC_VER_26:
5013 ops->disable = r8168c_hw_jumbo_disable;
5014 ops->enable = r8168c_hw_jumbo_enable;
5015 break;
5016 case RTL_GIGA_MAC_VER_27:
5017 case RTL_GIGA_MAC_VER_28:
5018 ops->disable = r8168dp_hw_jumbo_disable;
5019 ops->enable = r8168dp_hw_jumbo_enable;
5020 break;
5021 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5022 case RTL_GIGA_MAC_VER_32:
5023 case RTL_GIGA_MAC_VER_33:
5024 case RTL_GIGA_MAC_VER_34:
5025 ops->disable = r8168e_hw_jumbo_disable;
5026 ops->enable = r8168e_hw_jumbo_enable;
5027 break;
5028
5029 /*
5030 * No action needed for jumbo frames with 8169.
5031 * No jumbo for 810x at all.
5032 */
5033 case RTL_GIGA_MAC_VER_40:
5034 case RTL_GIGA_MAC_VER_41:
5035 case RTL_GIGA_MAC_VER_42:
5036 case RTL_GIGA_MAC_VER_43:
5037 case RTL_GIGA_MAC_VER_44:
5038 case RTL_GIGA_MAC_VER_45:
5039 case RTL_GIGA_MAC_VER_46:
5040 case RTL_GIGA_MAC_VER_47:
5041 case RTL_GIGA_MAC_VER_48:
5042 case RTL_GIGA_MAC_VER_49:
5043 case RTL_GIGA_MAC_VER_50:
5044 case RTL_GIGA_MAC_VER_51:
5045 default:
5046 ops->disable = NULL;
5047 ops->enable = NULL;
5048 break;
5049 }
5050 }
5051
5052 DECLARE_RTL_COND(rtl_chipcmd_cond)
5053 {
5054 void __iomem *ioaddr = tp->mmio_addr;
5055
5056 return RTL_R8(ChipCmd) & CmdReset;
5057 }
5058
5059 static void rtl_hw_reset(struct rtl8169_private *tp)
5060 {
5061 void __iomem *ioaddr = tp->mmio_addr;
5062
5063 RTL_W8(ChipCmd, CmdReset);
5064
5065 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5066 }
5067
5068 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5069 {
5070 struct rtl_fw *rtl_fw;
5071 const char *name;
5072 int rc = -ENOMEM;
5073
5074 name = rtl_lookup_firmware_name(tp);
5075 if (!name)
5076 goto out_no_firmware;
5077
5078 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5079 if (!rtl_fw)
5080 goto err_warn;
5081
5082 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5083 if (rc < 0)
5084 goto err_free;
5085
5086 rc = rtl_check_firmware(tp, rtl_fw);
5087 if (rc < 0)
5088 goto err_release_firmware;
5089
5090 tp->rtl_fw = rtl_fw;
5091 out:
5092 return;
5093
5094 err_release_firmware:
5095 release_firmware(rtl_fw->fw);
5096 err_free:
5097 kfree(rtl_fw);
5098 err_warn:
5099 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5100 name, rc);
5101 out_no_firmware:
5102 tp->rtl_fw = NULL;
5103 goto out;
5104 }
5105
5106 static void rtl_request_firmware(struct rtl8169_private *tp)
5107 {
5108 if (IS_ERR(tp->rtl_fw))
5109 rtl_request_uncached_firmware(tp);
5110 }
5111
5112 static void rtl_rx_close(struct rtl8169_private *tp)
5113 {
5114 void __iomem *ioaddr = tp->mmio_addr;
5115
5116 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5117 }
5118
5119 DECLARE_RTL_COND(rtl_npq_cond)
5120 {
5121 void __iomem *ioaddr = tp->mmio_addr;
5122
5123 return RTL_R8(TxPoll) & NPQ;
5124 }
5125
5126 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5127 {
5128 void __iomem *ioaddr = tp->mmio_addr;
5129
5130 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5131 }
5132
5133 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5134 {
5135 void __iomem *ioaddr = tp->mmio_addr;
5136
5137 /* Disable interrupts */
5138 rtl8169_irq_mask_and_ack(tp);
5139
5140 rtl_rx_close(tp);
5141
5142 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5143 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5144 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5145 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5146 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5147 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5148 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5149 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5150 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5151 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5152 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5153 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5154 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5155 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5156 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5157 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5158 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5159 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5160 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5161 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5162 tp->mac_version == RTL_GIGA_MAC_VER_51) {
5163 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5164 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5165 } else {
5166 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5167 udelay(100);
5168 }
5169
5170 rtl_hw_reset(tp);
5171 }
5172
5173 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5174 {
5175 void __iomem *ioaddr = tp->mmio_addr;
5176
5177 /* Set DMA burst size and Interframe Gap Time */
5178 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5179 (InterFrameGap << TxInterFrameGapShift));
5180 }
5181
5182 static void rtl_hw_start(struct net_device *dev)
5183 {
5184 struct rtl8169_private *tp = netdev_priv(dev);
5185
5186 tp->hw_start(dev);
5187
5188 rtl_irq_enable_all(tp);
5189 }
5190
5191 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5192 void __iomem *ioaddr)
5193 {
5194 /*
5195 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5196 * register to be written before TxDescAddrLow to work.
5197 * Switching from MMIO to I/O access fixes the issue as well.
5198 */
5199 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5200 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5201 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5202 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5203 }
5204
5205 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5206 {
5207 u16 cmd;
5208
5209 cmd = RTL_R16(CPlusCmd);
5210 RTL_W16(CPlusCmd, cmd);
5211 return cmd;
5212 }
5213
5214 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5215 {
5216 /* Low hurts. Let's disable the filtering. */
5217 RTL_W16(RxMaxSize, rx_buf_sz + 1);
5218 }
5219
5220 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5221 {
5222 static const struct rtl_cfg2_info {
5223 u32 mac_version;
5224 u32 clk;
5225 u32 val;
5226 } cfg2_info [] = {
5227 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5228 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5229 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5230 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5231 };
5232 const struct rtl_cfg2_info *p = cfg2_info;
5233 unsigned int i;
5234 u32 clk;
5235
5236 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5237 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5238 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5239 RTL_W32(0x7c, p->val);
5240 break;
5241 }
5242 }
5243 }
5244
5245 static void rtl_set_rx_mode(struct net_device *dev)
5246 {
5247 struct rtl8169_private *tp = netdev_priv(dev);
5248 void __iomem *ioaddr = tp->mmio_addr;
5249 u32 mc_filter[2]; /* Multicast hash filter */
5250 int rx_mode;
5251 u32 tmp = 0;
5252
5253 if (dev->flags & IFF_PROMISC) {
5254 /* Unconditionally log net taps. */
5255 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5256 rx_mode =
5257 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5258 AcceptAllPhys;
5259 mc_filter[1] = mc_filter[0] = 0xffffffff;
5260 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5261 (dev->flags & IFF_ALLMULTI)) {
5262 /* Too many to filter perfectly -- accept all multicasts. */
5263 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5264 mc_filter[1] = mc_filter[0] = 0xffffffff;
5265 } else {
5266 struct netdev_hw_addr *ha;
5267
5268 rx_mode = AcceptBroadcast | AcceptMyPhys;
5269 mc_filter[1] = mc_filter[0] = 0;
5270 netdev_for_each_mc_addr(ha, dev) {
5271 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5272 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5273 rx_mode |= AcceptMulticast;
5274 }
5275 }
5276
5277 if (dev->features & NETIF_F_RXALL)
5278 rx_mode |= (AcceptErr | AcceptRunt);
5279
5280 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5281
5282 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5283 u32 data = mc_filter[0];
5284
5285 mc_filter[0] = swab32(mc_filter[1]);
5286 mc_filter[1] = swab32(data);
5287 }
5288
5289 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5290 mc_filter[1] = mc_filter[0] = 0xffffffff;
5291
5292 RTL_W32(MAR0 + 4, mc_filter[1]);
5293 RTL_W32(MAR0 + 0, mc_filter[0]);
5294
5295 RTL_W32(RxConfig, tmp);
5296 }
5297
5298 static void rtl_hw_start_8169(struct net_device *dev)
5299 {
5300 struct rtl8169_private *tp = netdev_priv(dev);
5301 void __iomem *ioaddr = tp->mmio_addr;
5302 struct pci_dev *pdev = tp->pci_dev;
5303
5304 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5305 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5306 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5307 }
5308
5309 RTL_W8(Cfg9346, Cfg9346_Unlock);
5310 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5311 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5312 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5313 tp->mac_version == RTL_GIGA_MAC_VER_04)
5314 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5315
5316 rtl_init_rxcfg(tp);
5317
5318 RTL_W8(EarlyTxThres, NoEarlyTx);
5319
5320 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5321
5322 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5323 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5324 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5325 tp->mac_version == RTL_GIGA_MAC_VER_04)
5326 rtl_set_rx_tx_config_registers(tp);
5327
5328 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5329
5330 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5331 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5332 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5333 "Bit-3 and bit-14 MUST be 1\n");
5334 tp->cp_cmd |= (1 << 14);
5335 }
5336
5337 RTL_W16(CPlusCmd, tp->cp_cmd);
5338
5339 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5340
5341 /*
5342 * Undocumented corner. Supposedly:
5343 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5344 */
5345 RTL_W16(IntrMitigate, 0x0000);
5346
5347 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5348
5349 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5350 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5351 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5352 tp->mac_version != RTL_GIGA_MAC_VER_04) {
5353 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5354 rtl_set_rx_tx_config_registers(tp);
5355 }
5356
5357 RTL_W8(Cfg9346, Cfg9346_Lock);
5358
5359 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5360 RTL_R8(IntrMask);
5361
5362 RTL_W32(RxMissed, 0);
5363
5364 rtl_set_rx_mode(dev);
5365
5366 /* no early-rx interrupts */
5367 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5368 }
5369
5370 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5371 {
5372 if (tp->csi_ops.write)
5373 tp->csi_ops.write(tp, addr, value);
5374 }
5375
5376 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5377 {
5378 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5379 }
5380
5381 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5382 {
5383 u32 csi;
5384
5385 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5386 rtl_csi_write(tp, 0x070c, csi | bits);
5387 }
5388
5389 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5390 {
5391 rtl_csi_access_enable(tp, 0x17000000);
5392 }
5393
5394 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5395 {
5396 rtl_csi_access_enable(tp, 0x27000000);
5397 }
5398
5399 DECLARE_RTL_COND(rtl_csiar_cond)
5400 {
5401 void __iomem *ioaddr = tp->mmio_addr;
5402
5403 return RTL_R32(CSIAR) & CSIAR_FLAG;
5404 }
5405
5406 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5407 {
5408 void __iomem *ioaddr = tp->mmio_addr;
5409
5410 RTL_W32(CSIDR, value);
5411 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5412 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5413
5414 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5415 }
5416
5417 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5418 {
5419 void __iomem *ioaddr = tp->mmio_addr;
5420
5421 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5422 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5423
5424 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5425 RTL_R32(CSIDR) : ~0;
5426 }
5427
5428 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5429 {
5430 void __iomem *ioaddr = tp->mmio_addr;
5431
5432 RTL_W32(CSIDR, value);
5433 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5434 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5435 CSIAR_FUNC_NIC);
5436
5437 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5438 }
5439
5440 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5441 {
5442 void __iomem *ioaddr = tp->mmio_addr;
5443
5444 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5445 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5446
5447 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5448 RTL_R32(CSIDR) : ~0;
5449 }
5450
5451 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5452 {
5453 void __iomem *ioaddr = tp->mmio_addr;
5454
5455 RTL_W32(CSIDR, value);
5456 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5457 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5458 CSIAR_FUNC_NIC2);
5459
5460 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5461 }
5462
5463 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5464 {
5465 void __iomem *ioaddr = tp->mmio_addr;
5466
5467 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5468 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5469
5470 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5471 RTL_R32(CSIDR) : ~0;
5472 }
5473
5474 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5475 {
5476 struct csi_ops *ops = &tp->csi_ops;
5477
5478 switch (tp->mac_version) {
5479 case RTL_GIGA_MAC_VER_01:
5480 case RTL_GIGA_MAC_VER_02:
5481 case RTL_GIGA_MAC_VER_03:
5482 case RTL_GIGA_MAC_VER_04:
5483 case RTL_GIGA_MAC_VER_05:
5484 case RTL_GIGA_MAC_VER_06:
5485 case RTL_GIGA_MAC_VER_10:
5486 case RTL_GIGA_MAC_VER_11:
5487 case RTL_GIGA_MAC_VER_12:
5488 case RTL_GIGA_MAC_VER_13:
5489 case RTL_GIGA_MAC_VER_14:
5490 case RTL_GIGA_MAC_VER_15:
5491 case RTL_GIGA_MAC_VER_16:
5492 case RTL_GIGA_MAC_VER_17:
5493 ops->write = NULL;
5494 ops->read = NULL;
5495 break;
5496
5497 case RTL_GIGA_MAC_VER_37:
5498 case RTL_GIGA_MAC_VER_38:
5499 ops->write = r8402_csi_write;
5500 ops->read = r8402_csi_read;
5501 break;
5502
5503 case RTL_GIGA_MAC_VER_44:
5504 ops->write = r8411_csi_write;
5505 ops->read = r8411_csi_read;
5506 break;
5507
5508 default:
5509 ops->write = r8169_csi_write;
5510 ops->read = r8169_csi_read;
5511 break;
5512 }
5513 }
5514
5515 struct ephy_info {
5516 unsigned int offset;
5517 u16 mask;
5518 u16 bits;
5519 };
5520
5521 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5522 int len)
5523 {
5524 u16 w;
5525
5526 while (len-- > 0) {
5527 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5528 rtl_ephy_write(tp, e->offset, w);
5529 e++;
5530 }
5531 }
5532
5533 static void rtl_disable_clock_request(struct pci_dev *pdev)
5534 {
5535 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5536 PCI_EXP_LNKCTL_CLKREQ_EN);
5537 }
5538
5539 static void rtl_enable_clock_request(struct pci_dev *pdev)
5540 {
5541 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5542 PCI_EXP_LNKCTL_CLKREQ_EN);
5543 }
5544
5545 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5546 {
5547 void __iomem *ioaddr = tp->mmio_addr;
5548 u8 data;
5549
5550 data = RTL_R8(Config3);
5551
5552 if (enable)
5553 data |= Rdy_to_L23;
5554 else
5555 data &= ~Rdy_to_L23;
5556
5557 RTL_W8(Config3, data);
5558 }
5559
5560 #define R8168_CPCMD_QUIRK_MASK (\
5561 EnableBist | \
5562 Mac_dbgo_oe | \
5563 Force_half_dup | \
5564 Force_rxflow_en | \
5565 Force_txflow_en | \
5566 Cxpl_dbg_sel | \
5567 ASF | \
5568 PktCntrDisable | \
5569 Mac_dbgo_sel)
5570
5571 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5572 {
5573 void __iomem *ioaddr = tp->mmio_addr;
5574 struct pci_dev *pdev = tp->pci_dev;
5575
5576 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5577
5578 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5579
5580 if (tp->dev->mtu <= ETH_DATA_LEN) {
5581 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5582 PCI_EXP_DEVCTL_NOSNOOP_EN);
5583 }
5584 }
5585
5586 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5587 {
5588 void __iomem *ioaddr = tp->mmio_addr;
5589
5590 rtl_hw_start_8168bb(tp);
5591
5592 RTL_W8(MaxTxPacketSize, TxPacketMax);
5593
5594 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5595 }
5596
5597 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5598 {
5599 void __iomem *ioaddr = tp->mmio_addr;
5600 struct pci_dev *pdev = tp->pci_dev;
5601
5602 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5603
5604 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5605
5606 if (tp->dev->mtu <= ETH_DATA_LEN)
5607 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5608
5609 rtl_disable_clock_request(pdev);
5610
5611 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5612 }
5613
5614 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5615 {
5616 static const struct ephy_info e_info_8168cp[] = {
5617 { 0x01, 0, 0x0001 },
5618 { 0x02, 0x0800, 0x1000 },
5619 { 0x03, 0, 0x0042 },
5620 { 0x06, 0x0080, 0x0000 },
5621 { 0x07, 0, 0x2000 }
5622 };
5623
5624 rtl_csi_access_enable_2(tp);
5625
5626 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5627
5628 __rtl_hw_start_8168cp(tp);
5629 }
5630
5631 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5632 {
5633 void __iomem *ioaddr = tp->mmio_addr;
5634 struct pci_dev *pdev = tp->pci_dev;
5635
5636 rtl_csi_access_enable_2(tp);
5637
5638 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5639
5640 if (tp->dev->mtu <= ETH_DATA_LEN)
5641 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5642
5643 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5644 }
5645
5646 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5647 {
5648 void __iomem *ioaddr = tp->mmio_addr;
5649 struct pci_dev *pdev = tp->pci_dev;
5650
5651 rtl_csi_access_enable_2(tp);
5652
5653 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5654
5655 /* Magic. */
5656 RTL_W8(DBG_REG, 0x20);
5657
5658 RTL_W8(MaxTxPacketSize, TxPacketMax);
5659
5660 if (tp->dev->mtu <= ETH_DATA_LEN)
5661 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5662
5663 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5664 }
5665
5666 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5667 {
5668 void __iomem *ioaddr = tp->mmio_addr;
5669 static const struct ephy_info e_info_8168c_1[] = {
5670 { 0x02, 0x0800, 0x1000 },
5671 { 0x03, 0, 0x0002 },
5672 { 0x06, 0x0080, 0x0000 }
5673 };
5674
5675 rtl_csi_access_enable_2(tp);
5676
5677 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5678
5679 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5680
5681 __rtl_hw_start_8168cp(tp);
5682 }
5683
5684 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5685 {
5686 static const struct ephy_info e_info_8168c_2[] = {
5687 { 0x01, 0, 0x0001 },
5688 { 0x03, 0x0400, 0x0220 }
5689 };
5690
5691 rtl_csi_access_enable_2(tp);
5692
5693 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5694
5695 __rtl_hw_start_8168cp(tp);
5696 }
5697
5698 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5699 {
5700 rtl_hw_start_8168c_2(tp);
5701 }
5702
5703 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5704 {
5705 rtl_csi_access_enable_2(tp);
5706
5707 __rtl_hw_start_8168cp(tp);
5708 }
5709
5710 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5711 {
5712 void __iomem *ioaddr = tp->mmio_addr;
5713 struct pci_dev *pdev = tp->pci_dev;
5714
5715 rtl_csi_access_enable_2(tp);
5716
5717 rtl_disable_clock_request(pdev);
5718
5719 RTL_W8(MaxTxPacketSize, TxPacketMax);
5720
5721 if (tp->dev->mtu <= ETH_DATA_LEN)
5722 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5723
5724 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5725 }
5726
5727 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5728 {
5729 void __iomem *ioaddr = tp->mmio_addr;
5730 struct pci_dev *pdev = tp->pci_dev;
5731
5732 rtl_csi_access_enable_1(tp);
5733
5734 if (tp->dev->mtu <= ETH_DATA_LEN)
5735 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5736
5737 RTL_W8(MaxTxPacketSize, TxPacketMax);
5738
5739 rtl_disable_clock_request(pdev);
5740 }
5741
5742 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5743 {
5744 void __iomem *ioaddr = tp->mmio_addr;
5745 struct pci_dev *pdev = tp->pci_dev;
5746 static const struct ephy_info e_info_8168d_4[] = {
5747 { 0x0b, ~0, 0x48 },
5748 { 0x19, 0x20, 0x50 },
5749 { 0x0c, ~0, 0x20 }
5750 };
5751 int i;
5752
5753 rtl_csi_access_enable_1(tp);
5754
5755 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5756
5757 RTL_W8(MaxTxPacketSize, TxPacketMax);
5758
5759 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5760 const struct ephy_info *e = e_info_8168d_4 + i;
5761 u16 w;
5762
5763 w = rtl_ephy_read(tp, e->offset);
5764 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5765 }
5766
5767 rtl_enable_clock_request(pdev);
5768 }
5769
5770 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5771 {
5772 void __iomem *ioaddr = tp->mmio_addr;
5773 struct pci_dev *pdev = tp->pci_dev;
5774 static const struct ephy_info e_info_8168e_1[] = {
5775 { 0x00, 0x0200, 0x0100 },
5776 { 0x00, 0x0000, 0x0004 },
5777 { 0x06, 0x0002, 0x0001 },
5778 { 0x06, 0x0000, 0x0030 },
5779 { 0x07, 0x0000, 0x2000 },
5780 { 0x00, 0x0000, 0x0020 },
5781 { 0x03, 0x5800, 0x2000 },
5782 { 0x03, 0x0000, 0x0001 },
5783 { 0x01, 0x0800, 0x1000 },
5784 { 0x07, 0x0000, 0x4000 },
5785 { 0x1e, 0x0000, 0x2000 },
5786 { 0x19, 0xffff, 0xfe6c },
5787 { 0x0a, 0x0000, 0x0040 }
5788 };
5789
5790 rtl_csi_access_enable_2(tp);
5791
5792 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5793
5794 if (tp->dev->mtu <= ETH_DATA_LEN)
5795 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5796
5797 RTL_W8(MaxTxPacketSize, TxPacketMax);
5798
5799 rtl_disable_clock_request(pdev);
5800
5801 /* Reset tx FIFO pointer */
5802 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5803 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5804
5805 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5806 }
5807
5808 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5809 {
5810 void __iomem *ioaddr = tp->mmio_addr;
5811 struct pci_dev *pdev = tp->pci_dev;
5812 static const struct ephy_info e_info_8168e_2[] = {
5813 { 0x09, 0x0000, 0x0080 },
5814 { 0x19, 0x0000, 0x0224 }
5815 };
5816
5817 rtl_csi_access_enable_1(tp);
5818
5819 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5820
5821 if (tp->dev->mtu <= ETH_DATA_LEN)
5822 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5823
5824 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5825 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5826 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5827 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5828 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5829 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5830 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5831 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5832
5833 RTL_W8(MaxTxPacketSize, EarlySize);
5834
5835 rtl_disable_clock_request(pdev);
5836
5837 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5838 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5839
5840 /* Adjust EEE LED frequency */
5841 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5842
5843 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5844 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5845 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5846 }
5847
5848 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5849 {
5850 void __iomem *ioaddr = tp->mmio_addr;
5851 struct pci_dev *pdev = tp->pci_dev;
5852
5853 rtl_csi_access_enable_2(tp);
5854
5855 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5856
5857 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5858 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5859 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5860 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5861 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5862 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5863 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5864 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5865 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5866 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5867
5868 RTL_W8(MaxTxPacketSize, EarlySize);
5869
5870 rtl_disable_clock_request(pdev);
5871
5872 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5873 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5874 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5875 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5876 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5877 }
5878
5879 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5880 {
5881 void __iomem *ioaddr = tp->mmio_addr;
5882 static const struct ephy_info e_info_8168f_1[] = {
5883 { 0x06, 0x00c0, 0x0020 },
5884 { 0x08, 0x0001, 0x0002 },
5885 { 0x09, 0x0000, 0x0080 },
5886 { 0x19, 0x0000, 0x0224 }
5887 };
5888
5889 rtl_hw_start_8168f(tp);
5890
5891 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5892
5893 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5894
5895 /* Adjust EEE LED frequency */
5896 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5897 }
5898
5899 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5900 {
5901 static const struct ephy_info e_info_8168f_1[] = {
5902 { 0x06, 0x00c0, 0x0020 },
5903 { 0x0f, 0xffff, 0x5200 },
5904 { 0x1e, 0x0000, 0x4000 },
5905 { 0x19, 0x0000, 0x0224 }
5906 };
5907
5908 rtl_hw_start_8168f(tp);
5909 rtl_pcie_state_l2l3_enable(tp, false);
5910
5911 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5912
5913 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5914 }
5915
5916 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5917 {
5918 void __iomem *ioaddr = tp->mmio_addr;
5919 struct pci_dev *pdev = tp->pci_dev;
5920
5921 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5922
5923 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5924 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5925 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5926 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5927
5928 rtl_csi_access_enable_1(tp);
5929
5930 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5931
5932 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5933 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5934 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5935
5936 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5937 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5938 RTL_W8(MaxTxPacketSize, EarlySize);
5939
5940 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5941 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5942
5943 /* Adjust EEE LED frequency */
5944 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5945
5946 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5947 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5948
5949 rtl_pcie_state_l2l3_enable(tp, false);
5950 }
5951
5952 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5953 {
5954 void __iomem *ioaddr = tp->mmio_addr;
5955 static const struct ephy_info e_info_8168g_2[] = {
5956 { 0x00, 0x0000, 0x0008 },
5957 { 0x0c, 0x3df0, 0x0200 },
5958 { 0x19, 0xffff, 0xfc00 },
5959 { 0x1e, 0xffff, 0x20eb }
5960 };
5961
5962 rtl_hw_start_8168g_1(tp);
5963
5964 /* disable aspm and clock request before access ephy */
5965 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5966 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5967 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5968 }
5969
5970 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5971 {
5972 void __iomem *ioaddr = tp->mmio_addr;
5973 static const struct ephy_info e_info_8411_2[] = {
5974 { 0x00, 0x0000, 0x0008 },
5975 { 0x0c, 0x3df0, 0x0200 },
5976 { 0x0f, 0xffff, 0x5200 },
5977 { 0x19, 0x0020, 0x0000 },
5978 { 0x1e, 0x0000, 0x2000 }
5979 };
5980
5981 rtl_hw_start_8168g_1(tp);
5982
5983 /* disable aspm and clock request before access ephy */
5984 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5985 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5986 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5987 }
5988
5989 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5990 {
5991 void __iomem *ioaddr = tp->mmio_addr;
5992 struct pci_dev *pdev = tp->pci_dev;
5993 u16 rg_saw_cnt;
5994 u32 data;
5995 static const struct ephy_info e_info_8168h_1[] = {
5996 { 0x1e, 0x0800, 0x0001 },
5997 { 0x1d, 0x0000, 0x0800 },
5998 { 0x05, 0xffff, 0x2089 },
5999 { 0x06, 0xffff, 0x5881 },
6000 { 0x04, 0xffff, 0x154a },
6001 { 0x01, 0xffff, 0x068b }
6002 };
6003
6004 /* disable aspm and clock request before access ephy */
6005 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6006 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6007 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6008
6009 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6010
6011 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6012 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6013 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6014 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6015
6016 rtl_csi_access_enable_1(tp);
6017
6018 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6019
6020 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6021 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6022
6023 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6024
6025 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6026
6027 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6028
6029 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6030 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6031 RTL_W8(MaxTxPacketSize, EarlySize);
6032
6033 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6034 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6035
6036 /* Adjust EEE LED frequency */
6037 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6038
6039 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6040 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6041
6042 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6043
6044 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6045
6046 rtl_pcie_state_l2l3_enable(tp, false);
6047
6048 rtl_writephy(tp, 0x1f, 0x0c42);
6049 rg_saw_cnt = rtl_readphy(tp, 0x13);
6050 rtl_writephy(tp, 0x1f, 0x0000);
6051 if (rg_saw_cnt > 0) {
6052 u16 sw_cnt_1ms_ini;
6053
6054 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6055 sw_cnt_1ms_ini &= 0x0fff;
6056 data = r8168_mac_ocp_read(tp, 0xd412);
6057 data &= 0x0fff;
6058 data |= sw_cnt_1ms_ini;
6059 r8168_mac_ocp_write(tp, 0xd412, data);
6060 }
6061
6062 data = r8168_mac_ocp_read(tp, 0xe056);
6063 data &= 0xf0;
6064 data |= 0x07;
6065 r8168_mac_ocp_write(tp, 0xe056, data);
6066
6067 data = r8168_mac_ocp_read(tp, 0xe052);
6068 data &= 0x8008;
6069 data |= 0x6000;
6070 r8168_mac_ocp_write(tp, 0xe052, data);
6071
6072 data = r8168_mac_ocp_read(tp, 0xe0d6);
6073 data &= 0x01ff;
6074 data |= 0x017f;
6075 r8168_mac_ocp_write(tp, 0xe0d6, data);
6076
6077 data = r8168_mac_ocp_read(tp, 0xd420);
6078 data &= 0x0fff;
6079 data |= 0x047f;
6080 r8168_mac_ocp_write(tp, 0xd420, data);
6081
6082 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6083 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6084 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6085 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6086 }
6087
6088 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6089 {
6090 void __iomem *ioaddr = tp->mmio_addr;
6091 struct pci_dev *pdev = tp->pci_dev;
6092
6093 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6094
6095 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6096 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6097 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6098 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6099
6100 rtl_csi_access_enable_1(tp);
6101
6102 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6103
6104 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6105 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6106
6107 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6108
6109 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6110
6111 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6112 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6113 RTL_W8(MaxTxPacketSize, EarlySize);
6114
6115 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6116 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6117
6118 /* Adjust EEE LED frequency */
6119 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6120
6121 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6122
6123 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6124
6125 rtl_pcie_state_l2l3_enable(tp, false);
6126 }
6127
6128 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6129 {
6130 void __iomem *ioaddr = tp->mmio_addr;
6131 static const struct ephy_info e_info_8168ep_1[] = {
6132 { 0x00, 0xffff, 0x10ab },
6133 { 0x06, 0xffff, 0xf030 },
6134 { 0x08, 0xffff, 0x2006 },
6135 { 0x0d, 0xffff, 0x1666 },
6136 { 0x0c, 0x3ff0, 0x0000 }
6137 };
6138
6139 /* disable aspm and clock request before access ephy */
6140 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6141 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6142 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6143
6144 rtl_hw_start_8168ep(tp);
6145 }
6146
6147 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6148 {
6149 void __iomem *ioaddr = tp->mmio_addr;
6150 static const struct ephy_info e_info_8168ep_2[] = {
6151 { 0x00, 0xffff, 0x10a3 },
6152 { 0x19, 0xffff, 0xfc00 },
6153 { 0x1e, 0xffff, 0x20ea }
6154 };
6155
6156 /* disable aspm and clock request before access ephy */
6157 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6158 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6159 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6160
6161 rtl_hw_start_8168ep(tp);
6162
6163 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6164 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6165 }
6166
6167 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6168 {
6169 void __iomem *ioaddr = tp->mmio_addr;
6170 u32 data;
6171 static const struct ephy_info e_info_8168ep_3[] = {
6172 { 0x00, 0xffff, 0x10a3 },
6173 { 0x19, 0xffff, 0x7c00 },
6174 { 0x1e, 0xffff, 0x20eb },
6175 { 0x0d, 0xffff, 0x1666 }
6176 };
6177
6178 /* disable aspm and clock request before access ephy */
6179 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6180 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6181 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6182
6183 rtl_hw_start_8168ep(tp);
6184
6185 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6186 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6187
6188 data = r8168_mac_ocp_read(tp, 0xd3e2);
6189 data &= 0xf000;
6190 data |= 0x0271;
6191 r8168_mac_ocp_write(tp, 0xd3e2, data);
6192
6193 data = r8168_mac_ocp_read(tp, 0xd3e4);
6194 data &= 0xff00;
6195 r8168_mac_ocp_write(tp, 0xd3e4, data);
6196
6197 data = r8168_mac_ocp_read(tp, 0xe860);
6198 data |= 0x0080;
6199 r8168_mac_ocp_write(tp, 0xe860, data);
6200 }
6201
6202 static void rtl_hw_start_8168(struct net_device *dev)
6203 {
6204 struct rtl8169_private *tp = netdev_priv(dev);
6205 void __iomem *ioaddr = tp->mmio_addr;
6206
6207 RTL_W8(Cfg9346, Cfg9346_Unlock);
6208
6209 RTL_W8(MaxTxPacketSize, TxPacketMax);
6210
6211 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6212
6213 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6214
6215 RTL_W16(CPlusCmd, tp->cp_cmd);
6216
6217 RTL_W16(IntrMitigate, 0x5151);
6218
6219 /* Work around for RxFIFO overflow. */
6220 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6221 tp->event_slow |= RxFIFOOver | PCSTimeout;
6222 tp->event_slow &= ~RxOverflow;
6223 }
6224
6225 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6226
6227 rtl_set_rx_tx_config_registers(tp);
6228
6229 RTL_R8(IntrMask);
6230
6231 switch (tp->mac_version) {
6232 case RTL_GIGA_MAC_VER_11:
6233 rtl_hw_start_8168bb(tp);
6234 break;
6235
6236 case RTL_GIGA_MAC_VER_12:
6237 case RTL_GIGA_MAC_VER_17:
6238 rtl_hw_start_8168bef(tp);
6239 break;
6240
6241 case RTL_GIGA_MAC_VER_18:
6242 rtl_hw_start_8168cp_1(tp);
6243 break;
6244
6245 case RTL_GIGA_MAC_VER_19:
6246 rtl_hw_start_8168c_1(tp);
6247 break;
6248
6249 case RTL_GIGA_MAC_VER_20:
6250 rtl_hw_start_8168c_2(tp);
6251 break;
6252
6253 case RTL_GIGA_MAC_VER_21:
6254 rtl_hw_start_8168c_3(tp);
6255 break;
6256
6257 case RTL_GIGA_MAC_VER_22:
6258 rtl_hw_start_8168c_4(tp);
6259 break;
6260
6261 case RTL_GIGA_MAC_VER_23:
6262 rtl_hw_start_8168cp_2(tp);
6263 break;
6264
6265 case RTL_GIGA_MAC_VER_24:
6266 rtl_hw_start_8168cp_3(tp);
6267 break;
6268
6269 case RTL_GIGA_MAC_VER_25:
6270 case RTL_GIGA_MAC_VER_26:
6271 case RTL_GIGA_MAC_VER_27:
6272 rtl_hw_start_8168d(tp);
6273 break;
6274
6275 case RTL_GIGA_MAC_VER_28:
6276 rtl_hw_start_8168d_4(tp);
6277 break;
6278
6279 case RTL_GIGA_MAC_VER_31:
6280 rtl_hw_start_8168dp(tp);
6281 break;
6282
6283 case RTL_GIGA_MAC_VER_32:
6284 case RTL_GIGA_MAC_VER_33:
6285 rtl_hw_start_8168e_1(tp);
6286 break;
6287 case RTL_GIGA_MAC_VER_34:
6288 rtl_hw_start_8168e_2(tp);
6289 break;
6290
6291 case RTL_GIGA_MAC_VER_35:
6292 case RTL_GIGA_MAC_VER_36:
6293 rtl_hw_start_8168f_1(tp);
6294 break;
6295
6296 case RTL_GIGA_MAC_VER_38:
6297 rtl_hw_start_8411(tp);
6298 break;
6299
6300 case RTL_GIGA_MAC_VER_40:
6301 case RTL_GIGA_MAC_VER_41:
6302 rtl_hw_start_8168g_1(tp);
6303 break;
6304 case RTL_GIGA_MAC_VER_42:
6305 rtl_hw_start_8168g_2(tp);
6306 break;
6307
6308 case RTL_GIGA_MAC_VER_44:
6309 rtl_hw_start_8411_2(tp);
6310 break;
6311
6312 case RTL_GIGA_MAC_VER_45:
6313 case RTL_GIGA_MAC_VER_46:
6314 rtl_hw_start_8168h_1(tp);
6315 break;
6316
6317 case RTL_GIGA_MAC_VER_49:
6318 rtl_hw_start_8168ep_1(tp);
6319 break;
6320
6321 case RTL_GIGA_MAC_VER_50:
6322 rtl_hw_start_8168ep_2(tp);
6323 break;
6324
6325 case RTL_GIGA_MAC_VER_51:
6326 rtl_hw_start_8168ep_3(tp);
6327 break;
6328
6329 default:
6330 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6331 dev->name, tp->mac_version);
6332 break;
6333 }
6334
6335 RTL_W8(Cfg9346, Cfg9346_Lock);
6336
6337 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6338
6339 rtl_set_rx_mode(dev);
6340
6341 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6342 }
6343
6344 #define R810X_CPCMD_QUIRK_MASK (\
6345 EnableBist | \
6346 Mac_dbgo_oe | \
6347 Force_half_dup | \
6348 Force_rxflow_en | \
6349 Force_txflow_en | \
6350 Cxpl_dbg_sel | \
6351 ASF | \
6352 PktCntrDisable | \
6353 Mac_dbgo_sel)
6354
6355 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6356 {
6357 void __iomem *ioaddr = tp->mmio_addr;
6358 struct pci_dev *pdev = tp->pci_dev;
6359 static const struct ephy_info e_info_8102e_1[] = {
6360 { 0x01, 0, 0x6e65 },
6361 { 0x02, 0, 0x091f },
6362 { 0x03, 0, 0xc2f9 },
6363 { 0x06, 0, 0xafb5 },
6364 { 0x07, 0, 0x0e00 },
6365 { 0x19, 0, 0xec80 },
6366 { 0x01, 0, 0x2e65 },
6367 { 0x01, 0, 0x6e65 }
6368 };
6369 u8 cfg1;
6370
6371 rtl_csi_access_enable_2(tp);
6372
6373 RTL_W8(DBG_REG, FIX_NAK_1);
6374
6375 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6376
6377 RTL_W8(Config1,
6378 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6379 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6380
6381 cfg1 = RTL_R8(Config1);
6382 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6383 RTL_W8(Config1, cfg1 & ~LEDS0);
6384
6385 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6386 }
6387
6388 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6389 {
6390 void __iomem *ioaddr = tp->mmio_addr;
6391 struct pci_dev *pdev = tp->pci_dev;
6392
6393 rtl_csi_access_enable_2(tp);
6394
6395 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6396
6397 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6398 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6399 }
6400
6401 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6402 {
6403 rtl_hw_start_8102e_2(tp);
6404
6405 rtl_ephy_write(tp, 0x03, 0xc2f9);
6406 }
6407
6408 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6409 {
6410 void __iomem *ioaddr = tp->mmio_addr;
6411 static const struct ephy_info e_info_8105e_1[] = {
6412 { 0x07, 0, 0x4000 },
6413 { 0x19, 0, 0x0200 },
6414 { 0x19, 0, 0x0020 },
6415 { 0x1e, 0, 0x2000 },
6416 { 0x03, 0, 0x0001 },
6417 { 0x19, 0, 0x0100 },
6418 { 0x19, 0, 0x0004 },
6419 { 0x0a, 0, 0x0020 }
6420 };
6421
6422 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6423 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6424
6425 /* Disable Early Tally Counter */
6426 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6427
6428 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6429 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6430
6431 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6432
6433 rtl_pcie_state_l2l3_enable(tp, false);
6434 }
6435
6436 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6437 {
6438 rtl_hw_start_8105e_1(tp);
6439 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6440 }
6441
6442 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6443 {
6444 void __iomem *ioaddr = tp->mmio_addr;
6445 static const struct ephy_info e_info_8402[] = {
6446 { 0x19, 0xffff, 0xff64 },
6447 { 0x1e, 0, 0x4000 }
6448 };
6449
6450 rtl_csi_access_enable_2(tp);
6451
6452 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6453 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6454
6455 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6456 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6457
6458 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6459
6460 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6461
6462 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6463 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6464 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6465 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6466 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6467 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6468 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6469
6470 rtl_pcie_state_l2l3_enable(tp, false);
6471 }
6472
6473 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6474 {
6475 void __iomem *ioaddr = tp->mmio_addr;
6476
6477 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6478 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6479
6480 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6481 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6482 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6483
6484 rtl_pcie_state_l2l3_enable(tp, false);
6485 }
6486
6487 static void rtl_hw_start_8101(struct net_device *dev)
6488 {
6489 struct rtl8169_private *tp = netdev_priv(dev);
6490 void __iomem *ioaddr = tp->mmio_addr;
6491 struct pci_dev *pdev = tp->pci_dev;
6492
6493 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6494 tp->event_slow &= ~RxFIFOOver;
6495
6496 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6497 tp->mac_version == RTL_GIGA_MAC_VER_16)
6498 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6499 PCI_EXP_DEVCTL_NOSNOOP_EN);
6500
6501 RTL_W8(Cfg9346, Cfg9346_Unlock);
6502
6503 RTL_W8(MaxTxPacketSize, TxPacketMax);
6504
6505 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6506
6507 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6508 RTL_W16(CPlusCmd, tp->cp_cmd);
6509
6510 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6511
6512 rtl_set_rx_tx_config_registers(tp);
6513
6514 switch (tp->mac_version) {
6515 case RTL_GIGA_MAC_VER_07:
6516 rtl_hw_start_8102e_1(tp);
6517 break;
6518
6519 case RTL_GIGA_MAC_VER_08:
6520 rtl_hw_start_8102e_3(tp);
6521 break;
6522
6523 case RTL_GIGA_MAC_VER_09:
6524 rtl_hw_start_8102e_2(tp);
6525 break;
6526
6527 case RTL_GIGA_MAC_VER_29:
6528 rtl_hw_start_8105e_1(tp);
6529 break;
6530 case RTL_GIGA_MAC_VER_30:
6531 rtl_hw_start_8105e_2(tp);
6532 break;
6533
6534 case RTL_GIGA_MAC_VER_37:
6535 rtl_hw_start_8402(tp);
6536 break;
6537
6538 case RTL_GIGA_MAC_VER_39:
6539 rtl_hw_start_8106(tp);
6540 break;
6541 case RTL_GIGA_MAC_VER_43:
6542 rtl_hw_start_8168g_2(tp);
6543 break;
6544 case RTL_GIGA_MAC_VER_47:
6545 case RTL_GIGA_MAC_VER_48:
6546 rtl_hw_start_8168h_1(tp);
6547 break;
6548 }
6549
6550 RTL_W8(Cfg9346, Cfg9346_Lock);
6551
6552 RTL_W16(IntrMitigate, 0x0000);
6553
6554 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6555
6556 rtl_set_rx_mode(dev);
6557
6558 RTL_R8(IntrMask);
6559
6560 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6561 }
6562
6563 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6564 {
6565 struct rtl8169_private *tp = netdev_priv(dev);
6566
6567 if (new_mtu < ETH_ZLEN ||
6568 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
6569 return -EINVAL;
6570
6571 if (new_mtu > ETH_DATA_LEN)
6572 rtl_hw_jumbo_enable(tp);
6573 else
6574 rtl_hw_jumbo_disable(tp);
6575
6576 dev->mtu = new_mtu;
6577 netdev_update_features(dev);
6578
6579 return 0;
6580 }
6581
6582 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6583 {
6584 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6585 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6586 }
6587
6588 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6589 void **data_buff, struct RxDesc *desc)
6590 {
6591 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6592 DMA_FROM_DEVICE);
6593
6594 kfree(*data_buff);
6595 *data_buff = NULL;
6596 rtl8169_make_unusable_by_asic(desc);
6597 }
6598
6599 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6600 {
6601 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6602
6603 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6604 }
6605
6606 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6607 u32 rx_buf_sz)
6608 {
6609 desc->addr = cpu_to_le64(mapping);
6610 wmb();
6611 rtl8169_mark_to_asic(desc, rx_buf_sz);
6612 }
6613
6614 static inline void *rtl8169_align(void *data)
6615 {
6616 return (void *)ALIGN((long)data, 16);
6617 }
6618
6619 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6620 struct RxDesc *desc)
6621 {
6622 void *data;
6623 dma_addr_t mapping;
6624 struct device *d = &tp->pci_dev->dev;
6625 struct net_device *dev = tp->dev;
6626 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6627
6628 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6629 if (!data)
6630 return NULL;
6631
6632 if (rtl8169_align(data) != data) {
6633 kfree(data);
6634 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6635 if (!data)
6636 return NULL;
6637 }
6638
6639 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6640 DMA_FROM_DEVICE);
6641 if (unlikely(dma_mapping_error(d, mapping))) {
6642 if (net_ratelimit())
6643 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6644 goto err_out;
6645 }
6646
6647 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6648 return data;
6649
6650 err_out:
6651 kfree(data);
6652 return NULL;
6653 }
6654
6655 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6656 {
6657 unsigned int i;
6658
6659 for (i = 0; i < NUM_RX_DESC; i++) {
6660 if (tp->Rx_databuff[i]) {
6661 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6662 tp->RxDescArray + i);
6663 }
6664 }
6665 }
6666
6667 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6668 {
6669 desc->opts1 |= cpu_to_le32(RingEnd);
6670 }
6671
6672 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6673 {
6674 unsigned int i;
6675
6676 for (i = 0; i < NUM_RX_DESC; i++) {
6677 void *data;
6678
6679 if (tp->Rx_databuff[i])
6680 continue;
6681
6682 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6683 if (!data) {
6684 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6685 goto err_out;
6686 }
6687 tp->Rx_databuff[i] = data;
6688 }
6689
6690 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6691 return 0;
6692
6693 err_out:
6694 rtl8169_rx_clear(tp);
6695 return -ENOMEM;
6696 }
6697
6698 static int rtl8169_init_ring(struct net_device *dev)
6699 {
6700 struct rtl8169_private *tp = netdev_priv(dev);
6701
6702 rtl8169_init_ring_indexes(tp);
6703
6704 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6705 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6706
6707 return rtl8169_rx_fill(tp);
6708 }
6709
6710 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6711 struct TxDesc *desc)
6712 {
6713 unsigned int len = tx_skb->len;
6714
6715 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6716
6717 desc->opts1 = 0x00;
6718 desc->opts2 = 0x00;
6719 desc->addr = 0x00;
6720 tx_skb->len = 0;
6721 }
6722
6723 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6724 unsigned int n)
6725 {
6726 unsigned int i;
6727
6728 for (i = 0; i < n; i++) {
6729 unsigned int entry = (start + i) % NUM_TX_DESC;
6730 struct ring_info *tx_skb = tp->tx_skb + entry;
6731 unsigned int len = tx_skb->len;
6732
6733 if (len) {
6734 struct sk_buff *skb = tx_skb->skb;
6735
6736 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6737 tp->TxDescArray + entry);
6738 if (skb) {
6739 tp->dev->stats.tx_dropped++;
6740 dev_kfree_skb_any(skb);
6741 tx_skb->skb = NULL;
6742 }
6743 }
6744 }
6745 }
6746
6747 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6748 {
6749 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6750 tp->cur_tx = tp->dirty_tx = 0;
6751 }
6752
6753 static void rtl_reset_work(struct rtl8169_private *tp)
6754 {
6755 struct net_device *dev = tp->dev;
6756 int i;
6757
6758 napi_disable(&tp->napi);
6759 netif_stop_queue(dev);
6760 synchronize_sched();
6761
6762 rtl8169_hw_reset(tp);
6763
6764 for (i = 0; i < NUM_RX_DESC; i++)
6765 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6766
6767 rtl8169_tx_clear(tp);
6768 rtl8169_init_ring_indexes(tp);
6769
6770 napi_enable(&tp->napi);
6771 rtl_hw_start(dev);
6772 netif_wake_queue(dev);
6773 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6774 }
6775
6776 static void rtl8169_tx_timeout(struct net_device *dev)
6777 {
6778 struct rtl8169_private *tp = netdev_priv(dev);
6779
6780 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6781 }
6782
6783 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6784 u32 *opts)
6785 {
6786 struct skb_shared_info *info = skb_shinfo(skb);
6787 unsigned int cur_frag, entry;
6788 struct TxDesc *uninitialized_var(txd);
6789 struct device *d = &tp->pci_dev->dev;
6790
6791 entry = tp->cur_tx;
6792 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6793 const skb_frag_t *frag = info->frags + cur_frag;
6794 dma_addr_t mapping;
6795 u32 status, len;
6796 void *addr;
6797
6798 entry = (entry + 1) % NUM_TX_DESC;
6799
6800 txd = tp->TxDescArray + entry;
6801 len = skb_frag_size(frag);
6802 addr = skb_frag_address(frag);
6803 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6804 if (unlikely(dma_mapping_error(d, mapping))) {
6805 if (net_ratelimit())
6806 netif_err(tp, drv, tp->dev,
6807 "Failed to map TX fragments DMA!\n");
6808 goto err_out;
6809 }
6810
6811 /* Anti gcc 2.95.3 bugware (sic) */
6812 status = opts[0] | len |
6813 (RingEnd * !((entry + 1) % NUM_TX_DESC));
6814
6815 txd->opts1 = cpu_to_le32(status);
6816 txd->opts2 = cpu_to_le32(opts[1]);
6817 txd->addr = cpu_to_le64(mapping);
6818
6819 tp->tx_skb[entry].len = len;
6820 }
6821
6822 if (cur_frag) {
6823 tp->tx_skb[entry].skb = skb;
6824 txd->opts1 |= cpu_to_le32(LastFrag);
6825 }
6826
6827 return cur_frag;
6828
6829 err_out:
6830 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6831 return -EIO;
6832 }
6833
6834 static bool rtl_skb_pad(struct sk_buff *skb)
6835 {
6836 if (skb_padto(skb, ETH_ZLEN))
6837 return false;
6838 skb_put(skb, ETH_ZLEN - skb->len);
6839 return true;
6840 }
6841
6842 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6843 {
6844 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6845 }
6846
6847 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6848 struct net_device *dev);
6849 /* r8169_csum_workaround()
6850 * The hw limites the value the transport offset. When the offset is out of the
6851 * range, calculate the checksum by sw.
6852 */
6853 static void r8169_csum_workaround(struct rtl8169_private *tp,
6854 struct sk_buff *skb)
6855 {
6856 if (skb_shinfo(skb)->gso_size) {
6857 netdev_features_t features = tp->dev->features;
6858 struct sk_buff *segs, *nskb;
6859
6860 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6861 segs = skb_gso_segment(skb, features);
6862 if (IS_ERR(segs) || !segs)
6863 goto drop;
6864
6865 do {
6866 nskb = segs;
6867 segs = segs->next;
6868 nskb->next = NULL;
6869 rtl8169_start_xmit(nskb, tp->dev);
6870 } while (segs);
6871
6872 dev_kfree_skb(skb);
6873 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6874 if (skb_checksum_help(skb) < 0)
6875 goto drop;
6876
6877 rtl8169_start_xmit(skb, tp->dev);
6878 } else {
6879 struct net_device_stats *stats;
6880
6881 drop:
6882 stats = &tp->dev->stats;
6883 stats->tx_dropped++;
6884 dev_kfree_skb(skb);
6885 }
6886 }
6887
6888 /* msdn_giant_send_check()
6889 * According to the document of microsoft, the TCP Pseudo Header excludes the
6890 * packet length for IPv6 TCP large packets.
6891 */
6892 static int msdn_giant_send_check(struct sk_buff *skb)
6893 {
6894 const struct ipv6hdr *ipv6h;
6895 struct tcphdr *th;
6896 int ret;
6897
6898 ret = skb_cow_head(skb, 0);
6899 if (ret)
6900 return ret;
6901
6902 ipv6h = ipv6_hdr(skb);
6903 th = tcp_hdr(skb);
6904
6905 th->check = 0;
6906 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6907
6908 return ret;
6909 }
6910
6911 static inline __be16 get_protocol(struct sk_buff *skb)
6912 {
6913 __be16 protocol;
6914
6915 if (skb->protocol == htons(ETH_P_8021Q))
6916 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6917 else
6918 protocol = skb->protocol;
6919
6920 return protocol;
6921 }
6922
6923 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6924 struct sk_buff *skb, u32 *opts)
6925 {
6926 u32 mss = skb_shinfo(skb)->gso_size;
6927
6928 if (mss) {
6929 opts[0] |= TD_LSO;
6930 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6931 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6932 const struct iphdr *ip = ip_hdr(skb);
6933
6934 if (ip->protocol == IPPROTO_TCP)
6935 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6936 else if (ip->protocol == IPPROTO_UDP)
6937 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6938 else
6939 WARN_ON_ONCE(1);
6940 }
6941
6942 return true;
6943 }
6944
6945 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6946 struct sk_buff *skb, u32 *opts)
6947 {
6948 u32 transport_offset = (u32)skb_transport_offset(skb);
6949 u32 mss = skb_shinfo(skb)->gso_size;
6950
6951 if (mss) {
6952 if (transport_offset > GTTCPHO_MAX) {
6953 netif_warn(tp, tx_err, tp->dev,
6954 "Invalid transport offset 0x%x for TSO\n",
6955 transport_offset);
6956 return false;
6957 }
6958
6959 switch (get_protocol(skb)) {
6960 case htons(ETH_P_IP):
6961 opts[0] |= TD1_GTSENV4;
6962 break;
6963
6964 case htons(ETH_P_IPV6):
6965 if (msdn_giant_send_check(skb))
6966 return false;
6967
6968 opts[0] |= TD1_GTSENV6;
6969 break;
6970
6971 default:
6972 WARN_ON_ONCE(1);
6973 break;
6974 }
6975
6976 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6977 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6978 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6979 u8 ip_protocol;
6980
6981 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6982 return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
6983
6984 if (transport_offset > TCPHO_MAX) {
6985 netif_warn(tp, tx_err, tp->dev,
6986 "Invalid transport offset 0x%x\n",
6987 transport_offset);
6988 return false;
6989 }
6990
6991 switch (get_protocol(skb)) {
6992 case htons(ETH_P_IP):
6993 opts[1] |= TD1_IPv4_CS;
6994 ip_protocol = ip_hdr(skb)->protocol;
6995 break;
6996
6997 case htons(ETH_P_IPV6):
6998 opts[1] |= TD1_IPv6_CS;
6999 ip_protocol = ipv6_hdr(skb)->nexthdr;
7000 break;
7001
7002 default:
7003 ip_protocol = IPPROTO_RAW;
7004 break;
7005 }
7006
7007 if (ip_protocol == IPPROTO_TCP)
7008 opts[1] |= TD1_TCP_CS;
7009 else if (ip_protocol == IPPROTO_UDP)
7010 opts[1] |= TD1_UDP_CS;
7011 else
7012 WARN_ON_ONCE(1);
7013
7014 opts[1] |= transport_offset << TCPHO_SHIFT;
7015 } else {
7016 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7017 return rtl_skb_pad(skb);
7018 }
7019
7020 return true;
7021 }
7022
7023 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7024 struct net_device *dev)
7025 {
7026 struct rtl8169_private *tp = netdev_priv(dev);
7027 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7028 struct TxDesc *txd = tp->TxDescArray + entry;
7029 void __iomem *ioaddr = tp->mmio_addr;
7030 struct device *d = &tp->pci_dev->dev;
7031 dma_addr_t mapping;
7032 u32 status, len;
7033 u32 opts[2];
7034 int frags;
7035
7036 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7037 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7038 goto err_stop_0;
7039 }
7040
7041 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7042 goto err_stop_0;
7043
7044 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7045 opts[0] = DescOwn;
7046
7047 if (!tp->tso_csum(tp, skb, opts)) {
7048 r8169_csum_workaround(tp, skb);
7049 return NETDEV_TX_OK;
7050 }
7051
7052 len = skb_headlen(skb);
7053 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7054 if (unlikely(dma_mapping_error(d, mapping))) {
7055 if (net_ratelimit())
7056 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7057 goto err_dma_0;
7058 }
7059
7060 tp->tx_skb[entry].len = len;
7061 txd->addr = cpu_to_le64(mapping);
7062
7063 frags = rtl8169_xmit_frags(tp, skb, opts);
7064 if (frags < 0)
7065 goto err_dma_1;
7066 else if (frags)
7067 opts[0] |= FirstFrag;
7068 else {
7069 opts[0] |= FirstFrag | LastFrag;
7070 tp->tx_skb[entry].skb = skb;
7071 }
7072
7073 txd->opts2 = cpu_to_le32(opts[1]);
7074
7075 skb_tx_timestamp(skb);
7076
7077 wmb();
7078
7079 /* Anti gcc 2.95.3 bugware (sic) */
7080 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7081 txd->opts1 = cpu_to_le32(status);
7082
7083 tp->cur_tx += frags + 1;
7084
7085 wmb();
7086
7087 RTL_W8(TxPoll, NPQ);
7088
7089 mmiowb();
7090
7091 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7092 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7093 * not miss a ring update when it notices a stopped queue.
7094 */
7095 smp_wmb();
7096 netif_stop_queue(dev);
7097 /* Sync with rtl_tx:
7098 * - publish queue status and cur_tx ring index (write barrier)
7099 * - refresh dirty_tx ring index (read barrier).
7100 * May the current thread have a pessimistic view of the ring
7101 * status and forget to wake up queue, a racing rtl_tx thread
7102 * can't.
7103 */
7104 smp_mb();
7105 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7106 netif_wake_queue(dev);
7107 }
7108
7109 return NETDEV_TX_OK;
7110
7111 err_dma_1:
7112 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7113 err_dma_0:
7114 dev_kfree_skb_any(skb);
7115 dev->stats.tx_dropped++;
7116 return NETDEV_TX_OK;
7117
7118 err_stop_0:
7119 netif_stop_queue(dev);
7120 dev->stats.tx_dropped++;
7121 return NETDEV_TX_BUSY;
7122 }
7123
7124 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7125 {
7126 struct rtl8169_private *tp = netdev_priv(dev);
7127 struct pci_dev *pdev = tp->pci_dev;
7128 u16 pci_status, pci_cmd;
7129
7130 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7131 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7132
7133 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7134 pci_cmd, pci_status);
7135
7136 /*
7137 * The recovery sequence below admits a very elaborated explanation:
7138 * - it seems to work;
7139 * - I did not see what else could be done;
7140 * - it makes iop3xx happy.
7141 *
7142 * Feel free to adjust to your needs.
7143 */
7144 if (pdev->broken_parity_status)
7145 pci_cmd &= ~PCI_COMMAND_PARITY;
7146 else
7147 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7148
7149 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7150
7151 pci_write_config_word(pdev, PCI_STATUS,
7152 pci_status & (PCI_STATUS_DETECTED_PARITY |
7153 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7154 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7155
7156 /* The infamous DAC f*ckup only happens at boot time */
7157 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7158 void __iomem *ioaddr = tp->mmio_addr;
7159
7160 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7161 tp->cp_cmd &= ~PCIDAC;
7162 RTL_W16(CPlusCmd, tp->cp_cmd);
7163 dev->features &= ~NETIF_F_HIGHDMA;
7164 }
7165
7166 rtl8169_hw_reset(tp);
7167
7168 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7169 }
7170
7171 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7172 {
7173 unsigned int dirty_tx, tx_left;
7174
7175 dirty_tx = tp->dirty_tx;
7176 smp_rmb();
7177 tx_left = tp->cur_tx - dirty_tx;
7178
7179 while (tx_left > 0) {
7180 unsigned int entry = dirty_tx % NUM_TX_DESC;
7181 struct ring_info *tx_skb = tp->tx_skb + entry;
7182 u32 status;
7183
7184 rmb();
7185 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7186 if (status & DescOwn)
7187 break;
7188
7189 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7190 tp->TxDescArray + entry);
7191 if (status & LastFrag) {
7192 u64_stats_update_begin(&tp->tx_stats.syncp);
7193 tp->tx_stats.packets++;
7194 tp->tx_stats.bytes += tx_skb->skb->len;
7195 u64_stats_update_end(&tp->tx_stats.syncp);
7196 dev_kfree_skb_any(tx_skb->skb);
7197 tx_skb->skb = NULL;
7198 }
7199 dirty_tx++;
7200 tx_left--;
7201 }
7202
7203 if (tp->dirty_tx != dirty_tx) {
7204 tp->dirty_tx = dirty_tx;
7205 /* Sync with rtl8169_start_xmit:
7206 * - publish dirty_tx ring index (write barrier)
7207 * - refresh cur_tx ring index and queue status (read barrier)
7208 * May the current thread miss the stopped queue condition,
7209 * a racing xmit thread can only have a right view of the
7210 * ring status.
7211 */
7212 smp_mb();
7213 if (netif_queue_stopped(dev) &&
7214 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7215 netif_wake_queue(dev);
7216 }
7217 /*
7218 * 8168 hack: TxPoll requests are lost when the Tx packets are
7219 * too close. Let's kick an extra TxPoll request when a burst
7220 * of start_xmit activity is detected (if it is not detected,
7221 * it is slow enough). -- FR
7222 */
7223 if (tp->cur_tx != dirty_tx) {
7224 void __iomem *ioaddr = tp->mmio_addr;
7225
7226 RTL_W8(TxPoll, NPQ);
7227 }
7228 }
7229 }
7230
7231 static inline int rtl8169_fragmented_frame(u32 status)
7232 {
7233 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7234 }
7235
7236 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7237 {
7238 u32 status = opts1 & RxProtoMask;
7239
7240 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7241 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7242 skb->ip_summed = CHECKSUM_UNNECESSARY;
7243 else
7244 skb_checksum_none_assert(skb);
7245 }
7246
7247 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7248 struct rtl8169_private *tp,
7249 int pkt_size,
7250 dma_addr_t addr)
7251 {
7252 struct sk_buff *skb;
7253 struct device *d = &tp->pci_dev->dev;
7254
7255 data = rtl8169_align(data);
7256 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7257 prefetch(data);
7258 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
7259 if (skb)
7260 memcpy(skb->data, data, pkt_size);
7261 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7262
7263 return skb;
7264 }
7265
7266 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7267 {
7268 unsigned int cur_rx, rx_left;
7269 unsigned int count;
7270
7271 cur_rx = tp->cur_rx;
7272
7273 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7274 unsigned int entry = cur_rx % NUM_RX_DESC;
7275 struct RxDesc *desc = tp->RxDescArray + entry;
7276 u32 status;
7277
7278 rmb();
7279 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7280
7281 if (status & DescOwn)
7282 break;
7283 if (unlikely(status & RxRES)) {
7284 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7285 status);
7286 dev->stats.rx_errors++;
7287 if (status & (RxRWT | RxRUNT))
7288 dev->stats.rx_length_errors++;
7289 if (status & RxCRC)
7290 dev->stats.rx_crc_errors++;
7291 if (status & RxFOVF) {
7292 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7293 dev->stats.rx_fifo_errors++;
7294 }
7295 if ((status & (RxRUNT | RxCRC)) &&
7296 !(status & (RxRWT | RxFOVF)) &&
7297 (dev->features & NETIF_F_RXALL))
7298 goto process_pkt;
7299 } else {
7300 struct sk_buff *skb;
7301 dma_addr_t addr;
7302 int pkt_size;
7303
7304 process_pkt:
7305 addr = le64_to_cpu(desc->addr);
7306 if (likely(!(dev->features & NETIF_F_RXFCS)))
7307 pkt_size = (status & 0x00003fff) - 4;
7308 else
7309 pkt_size = status & 0x00003fff;
7310
7311 /*
7312 * The driver does not support incoming fragmented
7313 * frames. They are seen as a symptom of over-mtu
7314 * sized frames.
7315 */
7316 if (unlikely(rtl8169_fragmented_frame(status))) {
7317 dev->stats.rx_dropped++;
7318 dev->stats.rx_length_errors++;
7319 goto release_descriptor;
7320 }
7321
7322 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7323 tp, pkt_size, addr);
7324 if (!skb) {
7325 dev->stats.rx_dropped++;
7326 goto release_descriptor;
7327 }
7328
7329 rtl8169_rx_csum(skb, status);
7330 skb_put(skb, pkt_size);
7331 skb->protocol = eth_type_trans(skb, dev);
7332
7333 rtl8169_rx_vlan_tag(desc, skb);
7334
7335 napi_gro_receive(&tp->napi, skb);
7336
7337 u64_stats_update_begin(&tp->rx_stats.syncp);
7338 tp->rx_stats.packets++;
7339 tp->rx_stats.bytes += pkt_size;
7340 u64_stats_update_end(&tp->rx_stats.syncp);
7341 }
7342 release_descriptor:
7343 desc->opts2 = 0;
7344 wmb();
7345 rtl8169_mark_to_asic(desc, rx_buf_sz);
7346 }
7347
7348 count = cur_rx - tp->cur_rx;
7349 tp->cur_rx = cur_rx;
7350
7351 return count;
7352 }
7353
7354 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7355 {
7356 struct net_device *dev = dev_instance;
7357 struct rtl8169_private *tp = netdev_priv(dev);
7358 int handled = 0;
7359 u16 status;
7360
7361 status = rtl_get_events(tp);
7362 if (status && status != 0xffff) {
7363 status &= RTL_EVENT_NAPI | tp->event_slow;
7364 if (status) {
7365 handled = 1;
7366
7367 rtl_irq_disable(tp);
7368 napi_schedule(&tp->napi);
7369 }
7370 }
7371 return IRQ_RETVAL(handled);
7372 }
7373
7374 /*
7375 * Workqueue context.
7376 */
7377 static void rtl_slow_event_work(struct rtl8169_private *tp)
7378 {
7379 struct net_device *dev = tp->dev;
7380 u16 status;
7381
7382 status = rtl_get_events(tp) & tp->event_slow;
7383 rtl_ack_events(tp, status);
7384
7385 if (unlikely(status & RxFIFOOver)) {
7386 switch (tp->mac_version) {
7387 /* Work around for rx fifo overflow */
7388 case RTL_GIGA_MAC_VER_11:
7389 netif_stop_queue(dev);
7390 /* XXX - Hack alert. See rtl_task(). */
7391 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7392 default:
7393 break;
7394 }
7395 }
7396
7397 if (unlikely(status & SYSErr))
7398 rtl8169_pcierr_interrupt(dev);
7399
7400 if (status & LinkChg)
7401 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7402
7403 rtl_irq_enable_all(tp);
7404 }
7405
7406 static void rtl_task(struct work_struct *work)
7407 {
7408 static const struct {
7409 int bitnr;
7410 void (*action)(struct rtl8169_private *);
7411 } rtl_work[] = {
7412 /* XXX - keep rtl_slow_event_work() as first element. */
7413 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7414 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7415 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7416 };
7417 struct rtl8169_private *tp =
7418 container_of(work, struct rtl8169_private, wk.work);
7419 struct net_device *dev = tp->dev;
7420 int i;
7421
7422 rtl_lock_work(tp);
7423
7424 if (!netif_running(dev) ||
7425 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7426 goto out_unlock;
7427
7428 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7429 bool pending;
7430
7431 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7432 if (pending)
7433 rtl_work[i].action(tp);
7434 }
7435
7436 out_unlock:
7437 rtl_unlock_work(tp);
7438 }
7439
7440 static int rtl8169_poll(struct napi_struct *napi, int budget)
7441 {
7442 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7443 struct net_device *dev = tp->dev;
7444 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7445 int work_done= 0;
7446 u16 status;
7447
7448 status = rtl_get_events(tp);
7449 rtl_ack_events(tp, status & ~tp->event_slow);
7450
7451 if (status & RTL_EVENT_NAPI_RX)
7452 work_done = rtl_rx(dev, tp, (u32) budget);
7453
7454 if (status & RTL_EVENT_NAPI_TX)
7455 rtl_tx(dev, tp);
7456
7457 if (status & tp->event_slow) {
7458 enable_mask &= ~tp->event_slow;
7459
7460 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7461 }
7462
7463 if (work_done < budget) {
7464 napi_complete(napi);
7465
7466 rtl_irq_enable(tp, enable_mask);
7467 mmiowb();
7468 }
7469
7470 return work_done;
7471 }
7472
7473 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7474 {
7475 struct rtl8169_private *tp = netdev_priv(dev);
7476
7477 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7478 return;
7479
7480 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7481 RTL_W32(RxMissed, 0);
7482 }
7483
7484 static void rtl8169_down(struct net_device *dev)
7485 {
7486 struct rtl8169_private *tp = netdev_priv(dev);
7487 void __iomem *ioaddr = tp->mmio_addr;
7488
7489 del_timer_sync(&tp->timer);
7490
7491 napi_disable(&tp->napi);
7492 netif_stop_queue(dev);
7493
7494 rtl8169_hw_reset(tp);
7495 /*
7496 * At this point device interrupts can not be enabled in any function,
7497 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7498 * and napi is disabled (rtl8169_poll).
7499 */
7500 rtl8169_rx_missed(dev, ioaddr);
7501
7502 /* Give a racing hard_start_xmit a few cycles to complete. */
7503 synchronize_sched();
7504
7505 rtl8169_tx_clear(tp);
7506
7507 rtl8169_rx_clear(tp);
7508
7509 rtl_pll_power_down(tp);
7510 }
7511
7512 static int rtl8169_close(struct net_device *dev)
7513 {
7514 struct rtl8169_private *tp = netdev_priv(dev);
7515 struct pci_dev *pdev = tp->pci_dev;
7516
7517 pm_runtime_get_sync(&pdev->dev);
7518
7519 /* Update counters before going down */
7520 rtl8169_update_counters(dev);
7521
7522 rtl_lock_work(tp);
7523 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7524
7525 rtl8169_down(dev);
7526 rtl_unlock_work(tp);
7527
7528 cancel_work_sync(&tp->wk.work);
7529
7530 free_irq(pdev->irq, dev);
7531
7532 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7533 tp->RxPhyAddr);
7534 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7535 tp->TxPhyAddr);
7536 tp->TxDescArray = NULL;
7537 tp->RxDescArray = NULL;
7538
7539 pm_runtime_put_sync(&pdev->dev);
7540
7541 return 0;
7542 }
7543
7544 #ifdef CONFIG_NET_POLL_CONTROLLER
7545 static void rtl8169_netpoll(struct net_device *dev)
7546 {
7547 struct rtl8169_private *tp = netdev_priv(dev);
7548
7549 rtl8169_interrupt(tp->pci_dev->irq, dev);
7550 }
7551 #endif
7552
7553 static int rtl_open(struct net_device *dev)
7554 {
7555 struct rtl8169_private *tp = netdev_priv(dev);
7556 void __iomem *ioaddr = tp->mmio_addr;
7557 struct pci_dev *pdev = tp->pci_dev;
7558 int retval = -ENOMEM;
7559
7560 pm_runtime_get_sync(&pdev->dev);
7561
7562 /*
7563 * Rx and Tx descriptors needs 256 bytes alignment.
7564 * dma_alloc_coherent provides more.
7565 */
7566 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7567 &tp->TxPhyAddr, GFP_KERNEL);
7568 if (!tp->TxDescArray)
7569 goto err_pm_runtime_put;
7570
7571 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7572 &tp->RxPhyAddr, GFP_KERNEL);
7573 if (!tp->RxDescArray)
7574 goto err_free_tx_0;
7575
7576 retval = rtl8169_init_ring(dev);
7577 if (retval < 0)
7578 goto err_free_rx_1;
7579
7580 INIT_WORK(&tp->wk.work, rtl_task);
7581
7582 smp_mb();
7583
7584 rtl_request_firmware(tp);
7585
7586 retval = request_irq(pdev->irq, rtl8169_interrupt,
7587 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7588 dev->name, dev);
7589 if (retval < 0)
7590 goto err_release_fw_2;
7591
7592 rtl_lock_work(tp);
7593
7594 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7595
7596 napi_enable(&tp->napi);
7597
7598 rtl8169_init_phy(dev, tp);
7599
7600 __rtl8169_set_features(dev, dev->features);
7601
7602 rtl_pll_power_up(tp);
7603
7604 rtl_hw_start(dev);
7605
7606 netif_start_queue(dev);
7607
7608 rtl_unlock_work(tp);
7609
7610 tp->saved_wolopts = 0;
7611 pm_runtime_put_noidle(&pdev->dev);
7612
7613 rtl8169_check_link_status(dev, tp, ioaddr);
7614 out:
7615 return retval;
7616
7617 err_release_fw_2:
7618 rtl_release_firmware(tp);
7619 rtl8169_rx_clear(tp);
7620 err_free_rx_1:
7621 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7622 tp->RxPhyAddr);
7623 tp->RxDescArray = NULL;
7624 err_free_tx_0:
7625 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7626 tp->TxPhyAddr);
7627 tp->TxDescArray = NULL;
7628 err_pm_runtime_put:
7629 pm_runtime_put_noidle(&pdev->dev);
7630 goto out;
7631 }
7632
7633 static struct rtnl_link_stats64 *
7634 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7635 {
7636 struct rtl8169_private *tp = netdev_priv(dev);
7637 void __iomem *ioaddr = tp->mmio_addr;
7638 unsigned int start;
7639
7640 if (netif_running(dev))
7641 rtl8169_rx_missed(dev, ioaddr);
7642
7643 do {
7644 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7645 stats->rx_packets = tp->rx_stats.packets;
7646 stats->rx_bytes = tp->rx_stats.bytes;
7647 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7648
7649
7650 do {
7651 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7652 stats->tx_packets = tp->tx_stats.packets;
7653 stats->tx_bytes = tp->tx_stats.bytes;
7654 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7655
7656 stats->rx_dropped = dev->stats.rx_dropped;
7657 stats->tx_dropped = dev->stats.tx_dropped;
7658 stats->rx_length_errors = dev->stats.rx_length_errors;
7659 stats->rx_errors = dev->stats.rx_errors;
7660 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7661 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7662 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7663
7664 return stats;
7665 }
7666
7667 static void rtl8169_net_suspend(struct net_device *dev)
7668 {
7669 struct rtl8169_private *tp = netdev_priv(dev);
7670
7671 if (!netif_running(dev))
7672 return;
7673
7674 netif_device_detach(dev);
7675 netif_stop_queue(dev);
7676
7677 rtl_lock_work(tp);
7678 napi_disable(&tp->napi);
7679 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7680 rtl_unlock_work(tp);
7681
7682 rtl_pll_power_down(tp);
7683 }
7684
7685 #ifdef CONFIG_PM
7686
7687 static int rtl8169_suspend(struct device *device)
7688 {
7689 struct pci_dev *pdev = to_pci_dev(device);
7690 struct net_device *dev = pci_get_drvdata(pdev);
7691
7692 rtl8169_net_suspend(dev);
7693
7694 return 0;
7695 }
7696
7697 static void __rtl8169_resume(struct net_device *dev)
7698 {
7699 struct rtl8169_private *tp = netdev_priv(dev);
7700
7701 netif_device_attach(dev);
7702
7703 rtl_pll_power_up(tp);
7704
7705 rtl_lock_work(tp);
7706 napi_enable(&tp->napi);
7707 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7708 rtl_unlock_work(tp);
7709
7710 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7711 }
7712
7713 static int rtl8169_resume(struct device *device)
7714 {
7715 struct pci_dev *pdev = to_pci_dev(device);
7716 struct net_device *dev = pci_get_drvdata(pdev);
7717 struct rtl8169_private *tp = netdev_priv(dev);
7718
7719 rtl8169_init_phy(dev, tp);
7720
7721 if (netif_running(dev))
7722 __rtl8169_resume(dev);
7723
7724 return 0;
7725 }
7726
7727 static int rtl8169_runtime_suspend(struct device *device)
7728 {
7729 struct pci_dev *pdev = to_pci_dev(device);
7730 struct net_device *dev = pci_get_drvdata(pdev);
7731 struct rtl8169_private *tp = netdev_priv(dev);
7732
7733 if (!tp->TxDescArray)
7734 return 0;
7735
7736 rtl_lock_work(tp);
7737 tp->saved_wolopts = __rtl8169_get_wol(tp);
7738 __rtl8169_set_wol(tp, WAKE_ANY);
7739 rtl_unlock_work(tp);
7740
7741 rtl8169_net_suspend(dev);
7742
7743 return 0;
7744 }
7745
7746 static int rtl8169_runtime_resume(struct device *device)
7747 {
7748 struct pci_dev *pdev = to_pci_dev(device);
7749 struct net_device *dev = pci_get_drvdata(pdev);
7750 struct rtl8169_private *tp = netdev_priv(dev);
7751
7752 if (!tp->TxDescArray)
7753 return 0;
7754
7755 rtl_lock_work(tp);
7756 __rtl8169_set_wol(tp, tp->saved_wolopts);
7757 tp->saved_wolopts = 0;
7758 rtl_unlock_work(tp);
7759
7760 rtl8169_init_phy(dev, tp);
7761
7762 __rtl8169_resume(dev);
7763
7764 return 0;
7765 }
7766
7767 static int rtl8169_runtime_idle(struct device *device)
7768 {
7769 struct pci_dev *pdev = to_pci_dev(device);
7770 struct net_device *dev = pci_get_drvdata(pdev);
7771 struct rtl8169_private *tp = netdev_priv(dev);
7772
7773 return tp->TxDescArray ? -EBUSY : 0;
7774 }
7775
7776 static const struct dev_pm_ops rtl8169_pm_ops = {
7777 .suspend = rtl8169_suspend,
7778 .resume = rtl8169_resume,
7779 .freeze = rtl8169_suspend,
7780 .thaw = rtl8169_resume,
7781 .poweroff = rtl8169_suspend,
7782 .restore = rtl8169_resume,
7783 .runtime_suspend = rtl8169_runtime_suspend,
7784 .runtime_resume = rtl8169_runtime_resume,
7785 .runtime_idle = rtl8169_runtime_idle,
7786 };
7787
7788 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7789
7790 #else /* !CONFIG_PM */
7791
7792 #define RTL8169_PM_OPS NULL
7793
7794 #endif /* !CONFIG_PM */
7795
7796 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7797 {
7798 void __iomem *ioaddr = tp->mmio_addr;
7799
7800 /* WoL fails with 8168b when the receiver is disabled. */
7801 switch (tp->mac_version) {
7802 case RTL_GIGA_MAC_VER_11:
7803 case RTL_GIGA_MAC_VER_12:
7804 case RTL_GIGA_MAC_VER_17:
7805 pci_clear_master(tp->pci_dev);
7806
7807 RTL_W8(ChipCmd, CmdRxEnb);
7808 /* PCI commit */
7809 RTL_R8(ChipCmd);
7810 break;
7811 default:
7812 break;
7813 }
7814 }
7815
7816 static void rtl_shutdown(struct pci_dev *pdev)
7817 {
7818 struct net_device *dev = pci_get_drvdata(pdev);
7819 struct rtl8169_private *tp = netdev_priv(dev);
7820 struct device *d = &pdev->dev;
7821
7822 pm_runtime_get_sync(d);
7823
7824 rtl8169_net_suspend(dev);
7825
7826 /* Restore original MAC address */
7827 rtl_rar_set(tp, dev->perm_addr);
7828
7829 rtl8169_hw_reset(tp);
7830
7831 if (system_state == SYSTEM_POWER_OFF) {
7832 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7833 rtl_wol_suspend_quirk(tp);
7834 rtl_wol_shutdown_quirk(tp);
7835 }
7836
7837 pci_wake_from_d3(pdev, true);
7838 pci_set_power_state(pdev, PCI_D3hot);
7839 }
7840
7841 pm_runtime_put_noidle(d);
7842 }
7843
7844 static void rtl_remove_one(struct pci_dev *pdev)
7845 {
7846 struct net_device *dev = pci_get_drvdata(pdev);
7847 struct rtl8169_private *tp = netdev_priv(dev);
7848
7849 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7850 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7851 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
7852 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
7853 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
7854 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
7855 r8168_check_dash(tp)) {
7856 rtl8168_driver_stop(tp);
7857 }
7858
7859 netif_napi_del(&tp->napi);
7860
7861 unregister_netdev(dev);
7862
7863 rtl_release_firmware(tp);
7864
7865 if (pci_dev_run_wake(pdev))
7866 pm_runtime_get_noresume(&pdev->dev);
7867
7868 /* restore original MAC address */
7869 rtl_rar_set(tp, dev->perm_addr);
7870
7871 rtl_disable_msi(pdev, tp);
7872 rtl8169_release_board(pdev, dev, tp->mmio_addr);
7873 }
7874
7875 static const struct net_device_ops rtl_netdev_ops = {
7876 .ndo_open = rtl_open,
7877 .ndo_stop = rtl8169_close,
7878 .ndo_get_stats64 = rtl8169_get_stats64,
7879 .ndo_start_xmit = rtl8169_start_xmit,
7880 .ndo_tx_timeout = rtl8169_tx_timeout,
7881 .ndo_validate_addr = eth_validate_addr,
7882 .ndo_change_mtu = rtl8169_change_mtu,
7883 .ndo_fix_features = rtl8169_fix_features,
7884 .ndo_set_features = rtl8169_set_features,
7885 .ndo_set_mac_address = rtl_set_mac_address,
7886 .ndo_do_ioctl = rtl8169_ioctl,
7887 .ndo_set_rx_mode = rtl_set_rx_mode,
7888 #ifdef CONFIG_NET_POLL_CONTROLLER
7889 .ndo_poll_controller = rtl8169_netpoll,
7890 #endif
7891
7892 };
7893
7894 static const struct rtl_cfg_info {
7895 void (*hw_start)(struct net_device *);
7896 unsigned int region;
7897 unsigned int align;
7898 u16 event_slow;
7899 unsigned features;
7900 u8 default_ver;
7901 } rtl_cfg_infos [] = {
7902 [RTL_CFG_0] = {
7903 .hw_start = rtl_hw_start_8169,
7904 .region = 1,
7905 .align = 0,
7906 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7907 .features = RTL_FEATURE_GMII,
7908 .default_ver = RTL_GIGA_MAC_VER_01,
7909 },
7910 [RTL_CFG_1] = {
7911 .hw_start = rtl_hw_start_8168,
7912 .region = 2,
7913 .align = 8,
7914 .event_slow = SYSErr | LinkChg | RxOverflow,
7915 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
7916 .default_ver = RTL_GIGA_MAC_VER_11,
7917 },
7918 [RTL_CFG_2] = {
7919 .hw_start = rtl_hw_start_8101,
7920 .region = 2,
7921 .align = 8,
7922 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7923 PCSTimeout,
7924 .features = RTL_FEATURE_MSI,
7925 .default_ver = RTL_GIGA_MAC_VER_13,
7926 }
7927 };
7928
7929 /* Cfg9346_Unlock assumed. */
7930 static unsigned rtl_try_msi(struct rtl8169_private *tp,
7931 const struct rtl_cfg_info *cfg)
7932 {
7933 void __iomem *ioaddr = tp->mmio_addr;
7934 unsigned msi = 0;
7935 u8 cfg2;
7936
7937 cfg2 = RTL_R8(Config2) & ~MSIEnable;
7938 if (cfg->features & RTL_FEATURE_MSI) {
7939 if (pci_enable_msi(tp->pci_dev)) {
7940 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
7941 } else {
7942 cfg2 |= MSIEnable;
7943 msi = RTL_FEATURE_MSI;
7944 }
7945 }
7946 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
7947 RTL_W8(Config2, cfg2);
7948 return msi;
7949 }
7950
7951 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7952 {
7953 void __iomem *ioaddr = tp->mmio_addr;
7954
7955 return RTL_R8(MCU) & LINK_LIST_RDY;
7956 }
7957
7958 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7959 {
7960 void __iomem *ioaddr = tp->mmio_addr;
7961
7962 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7963 }
7964
7965 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7966 {
7967 void __iomem *ioaddr = tp->mmio_addr;
7968 u32 data;
7969
7970 tp->ocp_base = OCP_STD_PHY_BASE;
7971
7972 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
7973
7974 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7975 return;
7976
7977 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7978 return;
7979
7980 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7981 msleep(1);
7982 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
7983
7984 data = r8168_mac_ocp_read(tp, 0xe8de);
7985 data &= ~(1 << 14);
7986 r8168_mac_ocp_write(tp, 0xe8de, data);
7987
7988 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7989 return;
7990
7991 data = r8168_mac_ocp_read(tp, 0xe8de);
7992 data |= (1 << 15);
7993 r8168_mac_ocp_write(tp, 0xe8de, data);
7994
7995 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7996 return;
7997 }
7998
7999 static void rtl_hw_initialize(struct rtl8169_private *tp)
8000 {
8001 switch (tp->mac_version) {
8002 case RTL_GIGA_MAC_VER_40:
8003 case RTL_GIGA_MAC_VER_41:
8004 case RTL_GIGA_MAC_VER_42:
8005 case RTL_GIGA_MAC_VER_43:
8006 case RTL_GIGA_MAC_VER_44:
8007 case RTL_GIGA_MAC_VER_45:
8008 case RTL_GIGA_MAC_VER_46:
8009 case RTL_GIGA_MAC_VER_47:
8010 case RTL_GIGA_MAC_VER_48:
8011 case RTL_GIGA_MAC_VER_49:
8012 case RTL_GIGA_MAC_VER_50:
8013 case RTL_GIGA_MAC_VER_51:
8014 rtl_hw_init_8168g(tp);
8015 break;
8016
8017 default:
8018 break;
8019 }
8020 }
8021
8022 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8023 {
8024 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8025 const unsigned int region = cfg->region;
8026 struct rtl8169_private *tp;
8027 struct mii_if_info *mii;
8028 struct net_device *dev;
8029 void __iomem *ioaddr;
8030 int chipset, i;
8031 int rc;
8032
8033 if (netif_msg_drv(&debug)) {
8034 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8035 MODULENAME, RTL8169_VERSION);
8036 }
8037
8038 dev = alloc_etherdev(sizeof (*tp));
8039 if (!dev) {
8040 rc = -ENOMEM;
8041 goto out;
8042 }
8043
8044 SET_NETDEV_DEV(dev, &pdev->dev);
8045 dev->netdev_ops = &rtl_netdev_ops;
8046 tp = netdev_priv(dev);
8047 tp->dev = dev;
8048 tp->pci_dev = pdev;
8049 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8050
8051 mii = &tp->mii;
8052 mii->dev = dev;
8053 mii->mdio_read = rtl_mdio_read;
8054 mii->mdio_write = rtl_mdio_write;
8055 mii->phy_id_mask = 0x1f;
8056 mii->reg_num_mask = 0x1f;
8057 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8058
8059 /* disable ASPM completely as that cause random device stop working
8060 * problems as well as full system hangs for some PCIe devices users */
8061 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8062 PCIE_LINK_STATE_CLKPM);
8063
8064 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8065 rc = pci_enable_device(pdev);
8066 if (rc < 0) {
8067 netif_err(tp, probe, dev, "enable failure\n");
8068 goto err_out_free_dev_1;
8069 }
8070
8071 if (pci_set_mwi(pdev) < 0)
8072 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8073
8074 /* make sure PCI base addr 1 is MMIO */
8075 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8076 netif_err(tp, probe, dev,
8077 "region #%d not an MMIO resource, aborting\n",
8078 region);
8079 rc = -ENODEV;
8080 goto err_out_mwi_2;
8081 }
8082
8083 /* check for weird/broken PCI region reporting */
8084 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8085 netif_err(tp, probe, dev,
8086 "Invalid PCI region size(s), aborting\n");
8087 rc = -ENODEV;
8088 goto err_out_mwi_2;
8089 }
8090
8091 rc = pci_request_regions(pdev, MODULENAME);
8092 if (rc < 0) {
8093 netif_err(tp, probe, dev, "could not request regions\n");
8094 goto err_out_mwi_2;
8095 }
8096
8097 tp->cp_cmd = 0;
8098
8099 if ((sizeof(dma_addr_t) > 4) &&
8100 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
8101 tp->cp_cmd |= PCIDAC;
8102 dev->features |= NETIF_F_HIGHDMA;
8103 } else {
8104 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8105 if (rc < 0) {
8106 netif_err(tp, probe, dev, "DMA configuration failed\n");
8107 goto err_out_free_res_3;
8108 }
8109 }
8110
8111 /* ioremap MMIO region */
8112 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8113 if (!ioaddr) {
8114 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8115 rc = -EIO;
8116 goto err_out_free_res_3;
8117 }
8118 tp->mmio_addr = ioaddr;
8119
8120 if (!pci_is_pcie(pdev))
8121 netif_info(tp, probe, dev, "not PCI Express\n");
8122
8123 /* Identify chip attached to board */
8124 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8125
8126 rtl_init_rxcfg(tp);
8127
8128 rtl_irq_disable(tp);
8129
8130 rtl_hw_initialize(tp);
8131
8132 rtl_hw_reset(tp);
8133
8134 rtl_ack_events(tp, 0xffff);
8135
8136 pci_set_master(pdev);
8137
8138 rtl_init_mdio_ops(tp);
8139 rtl_init_pll_power_ops(tp);
8140 rtl_init_jumbo_ops(tp);
8141 rtl_init_csi_ops(tp);
8142
8143 rtl8169_print_mac_version(tp);
8144
8145 chipset = tp->mac_version;
8146 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8147
8148 RTL_W8(Cfg9346, Cfg9346_Unlock);
8149 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8150 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8151 switch (tp->mac_version) {
8152 case RTL_GIGA_MAC_VER_34:
8153 case RTL_GIGA_MAC_VER_35:
8154 case RTL_GIGA_MAC_VER_36:
8155 case RTL_GIGA_MAC_VER_37:
8156 case RTL_GIGA_MAC_VER_38:
8157 case RTL_GIGA_MAC_VER_40:
8158 case RTL_GIGA_MAC_VER_41:
8159 case RTL_GIGA_MAC_VER_42:
8160 case RTL_GIGA_MAC_VER_43:
8161 case RTL_GIGA_MAC_VER_44:
8162 case RTL_GIGA_MAC_VER_45:
8163 case RTL_GIGA_MAC_VER_46:
8164 case RTL_GIGA_MAC_VER_47:
8165 case RTL_GIGA_MAC_VER_48:
8166 case RTL_GIGA_MAC_VER_49:
8167 case RTL_GIGA_MAC_VER_50:
8168 case RTL_GIGA_MAC_VER_51:
8169 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8170 tp->features |= RTL_FEATURE_WOL;
8171 if ((RTL_R8(Config3) & LinkUp) != 0)
8172 tp->features |= RTL_FEATURE_WOL;
8173 break;
8174 default:
8175 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8176 tp->features |= RTL_FEATURE_WOL;
8177 break;
8178 }
8179 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8180 tp->features |= RTL_FEATURE_WOL;
8181 tp->features |= rtl_try_msi(tp, cfg);
8182 RTL_W8(Cfg9346, Cfg9346_Lock);
8183
8184 if (rtl_tbi_enabled(tp)) {
8185 tp->set_speed = rtl8169_set_speed_tbi;
8186 tp->get_settings = rtl8169_gset_tbi;
8187 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8188 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8189 tp->link_ok = rtl8169_tbi_link_ok;
8190 tp->do_ioctl = rtl_tbi_ioctl;
8191 } else {
8192 tp->set_speed = rtl8169_set_speed_xmii;
8193 tp->get_settings = rtl8169_gset_xmii;
8194 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8195 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8196 tp->link_ok = rtl8169_xmii_link_ok;
8197 tp->do_ioctl = rtl_xmii_ioctl;
8198 }
8199
8200 mutex_init(&tp->wk.mutex);
8201 u64_stats_init(&tp->rx_stats.syncp);
8202 u64_stats_init(&tp->tx_stats.syncp);
8203
8204 /* Get MAC address */
8205 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8206 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8207 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8208 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8209 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8210 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8211 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8212 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8213 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8214 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8215 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8216 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8217 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8218 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8219 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8220 tp->mac_version == RTL_GIGA_MAC_VER_51) {
8221 u16 mac_addr[3];
8222
8223 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8224 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8225
8226 if (is_valid_ether_addr((u8 *)mac_addr))
8227 rtl_rar_set(tp, (u8 *)mac_addr);
8228 }
8229 for (i = 0; i < ETH_ALEN; i++)
8230 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8231
8232 dev->ethtool_ops = &rtl8169_ethtool_ops;
8233 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8234
8235 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8236
8237 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8238 * properly for all devices */
8239 dev->features |= NETIF_F_RXCSUM |
8240 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8241
8242 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8243 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8244 NETIF_F_HW_VLAN_CTAG_RX;
8245 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8246 NETIF_F_HIGHDMA;
8247
8248 tp->cp_cmd |= RxChkSum | RxVlan;
8249
8250 /*
8251 * Pretend we are using VLANs; This bypasses a nasty bug where
8252 * Interrupts stop flowing on high load on 8110SCd controllers.
8253 */
8254 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8255 /* Disallow toggling */
8256 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8257
8258 if (tp->txd_version == RTL_TD_0)
8259 tp->tso_csum = rtl8169_tso_csum_v1;
8260 else if (tp->txd_version == RTL_TD_1) {
8261 tp->tso_csum = rtl8169_tso_csum_v2;
8262 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8263 } else
8264 WARN_ON_ONCE(1);
8265
8266 dev->hw_features |= NETIF_F_RXALL;
8267 dev->hw_features |= NETIF_F_RXFCS;
8268
8269 tp->hw_start = cfg->hw_start;
8270 tp->event_slow = cfg->event_slow;
8271
8272 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8273 ~(RxBOVF | RxFOVF) : ~0;
8274
8275 init_timer(&tp->timer);
8276 tp->timer.data = (unsigned long) dev;
8277 tp->timer.function = rtl8169_phy_timer;
8278
8279 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8280
8281 rc = register_netdev(dev);
8282 if (rc < 0)
8283 goto err_out_msi_4;
8284
8285 pci_set_drvdata(pdev, dev);
8286
8287 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8288 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8289 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8290 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8291 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8292 "tx checksumming: %s]\n",
8293 rtl_chip_infos[chipset].jumbo_max,
8294 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8295 }
8296
8297 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8298 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8299 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8300 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8301 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8302 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8303 r8168_check_dash(tp)) {
8304 rtl8168_driver_start(tp);
8305 }
8306
8307 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8308
8309 if (pci_dev_run_wake(pdev))
8310 pm_runtime_put_noidle(&pdev->dev);
8311
8312 netif_carrier_off(dev);
8313
8314 out:
8315 return rc;
8316
8317 err_out_msi_4:
8318 netif_napi_del(&tp->napi);
8319 rtl_disable_msi(pdev, tp);
8320 iounmap(ioaddr);
8321 err_out_free_res_3:
8322 pci_release_regions(pdev);
8323 err_out_mwi_2:
8324 pci_clear_mwi(pdev);
8325 pci_disable_device(pdev);
8326 err_out_free_dev_1:
8327 free_netdev(dev);
8328 goto out;
8329 }
8330
8331 static struct pci_driver rtl8169_pci_driver = {
8332 .name = MODULENAME,
8333 .id_table = rtl8169_pci_tbl,
8334 .probe = rtl_init_one,
8335 .remove = rtl_remove_one,
8336 .shutdown = rtl_shutdown,
8337 .driver.pm = RTL8169_PM_OPS,
8338 };
8339
8340 module_pci_driver(rtl8169_pci_driver);
Linux with added FPC-III support