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Linux 3.18.86
[linux/fpc-iii.git] / drivers / net / ethernet / sfc / ef10.c
blob010009d64017461da101cf6ed055bec8e223589a
1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10 #include "net_driver.h"
11 #include "ef10_regs.h"
12 #include "io.h"
13 #include "mcdi.h"
14 #include "mcdi_pcol.h"
15 #include "nic.h"
16 #include "workarounds.h"
17 #include "selftest.h"
18 #include <linux/in.h>
19 #include <linux/jhash.h>
20 #include <linux/wait.h>
21 #include <linux/workqueue.h>
22
23 /* Hardware control for EF10 architecture including 'Huntington'. */
24
25 #define EFX_EF10_DRVGEN_EV 7
26 enum {
27 EFX_EF10_TEST = 1,
28 EFX_EF10_REFILL,
29 };
30
31 /* The reserved RSS context value */
32 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
33
34 /* The filter table(s) are managed by firmware and we have write-only
35 * access. When removing filters we must identify them to the
36 * firmware by a 64-bit handle, but this is too wide for Linux kernel
37 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
38 * be able to tell in advance whether a requested insertion will
39 * replace an existing filter. Therefore we maintain a software hash
40 * table, which should be at least as large as the hardware hash
41 * table.
42 *
43 * Huntington has a single 8K filter table shared between all filter
44 * types and both ports.
45 */
46 #define HUNT_FILTER_TBL_ROWS 8192
47
48 struct efx_ef10_filter_table {
49 /* The RX match field masks supported by this fw & hw, in order of priority */
50 enum efx_filter_match_flags rx_match_flags[
51 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
52 unsigned int rx_match_count;
53
54 struct {
55 unsigned long spec; /* pointer to spec plus flag bits */
56 /* BUSY flag indicates that an update is in progress. AUTO_OLD is
57 * used to mark and sweep MAC filters for the device address lists.
58 */
59 #define EFX_EF10_FILTER_FLAG_BUSY 1UL
60 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
61 #define EFX_EF10_FILTER_FLAGS 3UL
62 u64 handle; /* firmware handle */
63 } *entry;
64 wait_queue_head_t waitq;
65 /* Shadow of net_device address lists, guarded by mac_lock */
66 #define EFX_EF10_FILTER_DEV_UC_MAX 32
67 #define EFX_EF10_FILTER_DEV_MC_MAX 256
68 struct {
69 u8 addr[ETH_ALEN];
70 u16 id;
71 } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX],
72 dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
73 int dev_uc_count; /* negative for PROMISC */
74 int dev_mc_count; /* negative for PROMISC/ALLMULTI */
75 };
76
77 /* An arbitrary search limit for the software hash table */
78 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
79
80 static void efx_ef10_rx_push_rss_config(struct efx_nic *efx);
81 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
82 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
83
84 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
85 {
86 efx_dword_t reg;
87
88 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
89 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
90 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
91 }
92
93 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
94 {
95 return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]);
96 }
97
98 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
99 {
100 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
101 struct efx_ef10_nic_data *nic_data = efx->nic_data;
102 size_t outlen;
103 int rc;
104
105 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
106
107 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
108 outbuf, sizeof(outbuf), &outlen);
109 if (rc)
110 return rc;
111 if (outlen < sizeof(outbuf)) {
112 netif_err(efx, drv, efx->net_dev,
113 "unable to read datapath firmware capabilities\n");
114 return -EIO;
115 }
116
117 nic_data->datapath_caps =
118 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
119
120 if (!(nic_data->datapath_caps &
121 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
122 netif_err(efx, drv, efx->net_dev,
123 "current firmware does not support TSO\n");
124 return -ENODEV;
125 }
126
127 if (!(nic_data->datapath_caps &
128 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
129 netif_err(efx, probe, efx->net_dev,
130 "current firmware does not support an RX prefix\n");
131 return -ENODEV;
132 }
133
134 return 0;
135 }
136
137 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
138 {
139 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
140 int rc;
141
142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
143 outbuf, sizeof(outbuf), NULL);
144 if (rc)
145 return rc;
146 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
147 return rc > 0 ? rc : -ERANGE;
148 }
149
150 static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address)
151 {
152 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
153 size_t outlen;
154 int rc;
155
156 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
157
158 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
159 outbuf, sizeof(outbuf), &outlen);
160 if (rc)
161 return rc;
162 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
163 return -EIO;
164
165 ether_addr_copy(mac_address,
166 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
167 return 0;
168 }
169
170 static int efx_ef10_probe(struct efx_nic *efx)
171 {
172 struct efx_ef10_nic_data *nic_data;
173 int i, rc;
174
175 /* We can have one VI for each 8K region. However, until we
176 * use TX option descriptors we need two TX queues per channel.
177 */
178 efx->max_channels =
179 min_t(unsigned int,
180 EFX_MAX_CHANNELS,
181 resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) /
182 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
183 if (WARN_ON(efx->max_channels == 0))
184 return -EIO;
185
186 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
187 if (!nic_data)
188 return -ENOMEM;
189 efx->nic_data = nic_data;
190
191 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
192 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
193 if (rc)
194 goto fail1;
195
196 /* Get the MC's warm boot count. In case it's rebooting right
197 * now, be prepared to retry.
198 */
199 i = 0;
200 for (;;) {
201 rc = efx_ef10_get_warm_boot_count(efx);
202 if (rc >= 0)
203 break;
204 if (++i == 5)
205 goto fail2;
206 ssleep(1);
207 }
208 nic_data->warm_boot_count = rc;
209
210 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
211
212 /* In case we're recovering from a crash (kexec), we want to
213 * cancel any outstanding request by the previous user of this
214 * function. We send a special message using the least
215 * significant bits of the 'high' (doorbell) register.
216 */
217 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
218
219 rc = efx_mcdi_init(efx);
220 if (rc)
221 goto fail2;
222
223 /* Reset (most) configuration for this function */
224 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
225 if (rc)
226 goto fail3;
227
228 /* Enable event logging */
229 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
230 if (rc)
231 goto fail3;
232
233 rc = efx_ef10_init_datapath_caps(efx);
234 if (rc < 0)
235 goto fail3;
236
237 efx->rx_packet_len_offset =
238 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
239
240 rc = efx_mcdi_port_get_number(efx);
241 if (rc < 0)
242 goto fail3;
243 efx->port_num = rc;
244
245 rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr);
246 if (rc)
247 goto fail3;
248
249 rc = efx_ef10_get_sysclk_freq(efx);
250 if (rc < 0)
251 goto fail3;
252 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
253
254 /* Check whether firmware supports bug 35388 workaround */
255 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
256 if (rc == 0)
257 nic_data->workaround_35388 = true;
258 else if (rc != -ENOSYS && rc != -ENOENT)
259 goto fail3;
260 netif_dbg(efx, probe, efx->net_dev,
261 "workaround for bug 35388 is %sabled\n",
262 nic_data->workaround_35388 ? "en" : "dis");
263
264 rc = efx_mcdi_mon_probe(efx);
265 if (rc)
266 goto fail3;
267
268 efx_ptp_probe(efx, NULL);
269
270 return 0;
271
272 fail3:
273 efx_mcdi_fini(efx);
274 fail2:
275 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
276 fail1:
277 kfree(nic_data);
278 efx->nic_data = NULL;
279 return rc;
280 }
281
282 static int efx_ef10_free_vis(struct efx_nic *efx)
283 {
284 MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, 0);
285 size_t outlen;
286 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
287 outbuf, sizeof(outbuf), &outlen);
288
289 /* -EALREADY means nothing to free, so ignore */
290 if (rc == -EALREADY)
291 rc = 0;
292 if (rc)
293 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
294 rc);
295 return rc;
296 }
297
298 #ifdef EFX_USE_PIO
299
300 static void efx_ef10_free_piobufs(struct efx_nic *efx)
301 {
302 struct efx_ef10_nic_data *nic_data = efx->nic_data;
303 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
304 unsigned int i;
305 int rc;
306
307 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
308
309 for (i = 0; i < nic_data->n_piobufs; i++) {
310 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
311 nic_data->piobuf_handle[i]);
312 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
313 NULL, 0, NULL);
314 WARN_ON(rc);
315 }
316
317 nic_data->n_piobufs = 0;
318 }
319
320 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
321 {
322 struct efx_ef10_nic_data *nic_data = efx->nic_data;
323 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
324 unsigned int i;
325 size_t outlen;
326 int rc = 0;
327
328 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
329
330 for (i = 0; i < n; i++) {
331 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
332 outbuf, sizeof(outbuf), &outlen);
333 if (rc)
334 break;
335 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
336 rc = -EIO;
337 break;
338 }
339 nic_data->piobuf_handle[i] =
340 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
341 netif_dbg(efx, probe, efx->net_dev,
342 "allocated PIO buffer %u handle %x\n", i,
343 nic_data->piobuf_handle[i]);
344 }
345
346 nic_data->n_piobufs = i;
347 if (rc)
348 efx_ef10_free_piobufs(efx);
349 return rc;
350 }
351
352 static int efx_ef10_link_piobufs(struct efx_nic *efx)
353 {
354 struct efx_ef10_nic_data *nic_data = efx->nic_data;
355 MCDI_DECLARE_BUF(inbuf,
356 max(MC_CMD_LINK_PIOBUF_IN_LEN,
357 MC_CMD_UNLINK_PIOBUF_IN_LEN));
358 struct efx_channel *channel;
359 struct efx_tx_queue *tx_queue;
360 unsigned int offset, index;
361 int rc;
362
363 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
364 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
365
366 /* Link a buffer to each VI in the write-combining mapping */
367 for (index = 0; index < nic_data->n_piobufs; ++index) {
368 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
369 nic_data->piobuf_handle[index]);
370 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
371 nic_data->pio_write_vi_base + index);
372 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
373 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
374 NULL, 0, NULL);
375 if (rc) {
376 netif_err(efx, drv, efx->net_dev,
377 "failed to link VI %u to PIO buffer %u (%d)\n",
378 nic_data->pio_write_vi_base + index, index,
379 rc);
380 goto fail;
381 }
382 netif_dbg(efx, probe, efx->net_dev,
383 "linked VI %u to PIO buffer %u\n",
384 nic_data->pio_write_vi_base + index, index);
385 }
386
387 /* Link a buffer to each TX queue */
388 efx_for_each_channel(channel, efx) {
389 efx_for_each_channel_tx_queue(tx_queue, channel) {
390 /* We assign the PIO buffers to queues in
391 * reverse order to allow for the following
392 * special case.
393 */
394 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
395 tx_queue->channel->channel - 1) *
396 efx_piobuf_size);
397 index = offset / ER_DZ_TX_PIOBUF_SIZE;
398 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
399
400 /* When the host page size is 4K, the first
401 * host page in the WC mapping may be within
402 * the same VI page as the last TX queue. We
403 * can only link one buffer to each VI.
404 */
405 if (tx_queue->queue == nic_data->pio_write_vi_base) {
406 BUG_ON(index != 0);
407 rc = 0;
408 } else {
409 MCDI_SET_DWORD(inbuf,
410 LINK_PIOBUF_IN_PIOBUF_HANDLE,
411 nic_data->piobuf_handle[index]);
412 MCDI_SET_DWORD(inbuf,
413 LINK_PIOBUF_IN_TXQ_INSTANCE,
414 tx_queue->queue);
415 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
416 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
417 NULL, 0, NULL);
418 }
419
420 if (rc) {
421 /* This is non-fatal; the TX path just
422 * won't use PIO for this queue
423 */
424 netif_err(efx, drv, efx->net_dev,
425 "failed to link VI %u to PIO buffer %u (%d)\n",
426 tx_queue->queue, index, rc);
427 tx_queue->piobuf = NULL;
428 } else {
429 tx_queue->piobuf =
430 nic_data->pio_write_base +
431 index * EFX_VI_PAGE_SIZE + offset;
432 tx_queue->piobuf_offset = offset;
433 netif_dbg(efx, probe, efx->net_dev,
434 "linked VI %u to PIO buffer %u offset %x addr %p\n",
435 tx_queue->queue, index,
436 tx_queue->piobuf_offset,
437 tx_queue->piobuf);
438 }
439 }
440 }
441
442 return 0;
443
444 fail:
445 while (index--) {
446 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
447 nic_data->pio_write_vi_base + index);
448 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
449 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
450 NULL, 0, NULL);
451 }
452 return rc;
453 }
454
455 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
456 {
457 struct efx_channel *channel;
458 struct efx_tx_queue *tx_queue;
459
460 /* All our existing PIO buffers went away */
461 efx_for_each_channel(channel, efx)
462 efx_for_each_channel_tx_queue(tx_queue, channel)
463 tx_queue->piobuf = NULL;
464 }
465
466 #else /* !EFX_USE_PIO */
467
468 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
469 {
470 return n == 0 ? 0 : -ENOBUFS;
471 }
472
473 static int efx_ef10_link_piobufs(struct efx_nic *efx)
474 {
475 return 0;
476 }
477
478 static void efx_ef10_free_piobufs(struct efx_nic *efx)
479 {
480 }
481
482 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
483 {
484 }
485
486 #endif /* EFX_USE_PIO */
487
488 static void efx_ef10_remove(struct efx_nic *efx)
489 {
490 struct efx_ef10_nic_data *nic_data = efx->nic_data;
491 int rc;
492
493 efx_ptp_remove(efx);
494
495 efx_mcdi_mon_remove(efx);
496
497 efx_ef10_rx_free_indir_table(efx);
498
499 if (nic_data->wc_membase)
500 iounmap(nic_data->wc_membase);
501
502 rc = efx_ef10_free_vis(efx);
503 WARN_ON(rc != 0);
504
505 if (!nic_data->must_restore_piobufs)
506 efx_ef10_free_piobufs(efx);
507
508 efx_mcdi_fini(efx);
509 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
510 kfree(nic_data);
511 }
512
513 static int efx_ef10_alloc_vis(struct efx_nic *efx,
514 unsigned int min_vis, unsigned int max_vis)
515 {
516 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
517 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
518 struct efx_ef10_nic_data *nic_data = efx->nic_data;
519 size_t outlen;
520 int rc;
521
522 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
523 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
524 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
525 outbuf, sizeof(outbuf), &outlen);
526 if (rc != 0)
527 return rc;
528
529 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
530 return -EIO;
531
532 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
533 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
534
535 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
536 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
537 return 0;
538 }
539
540 /* Note that the failure path of this function does not free
541 * resources, as this will be done by efx_ef10_remove().
542 */
543 static int efx_ef10_dimension_resources(struct efx_nic *efx)
544 {
545 struct efx_ef10_nic_data *nic_data = efx->nic_data;
546 unsigned int uc_mem_map_size, wc_mem_map_size;
547 unsigned int min_vis, pio_write_vi_base, max_vis;
548 void __iomem *membase;
549 int rc;
550
551 min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
552
553 #ifdef EFX_USE_PIO
554 /* Try to allocate PIO buffers if wanted and if the full
555 * number of PIO buffers would be sufficient to allocate one
556 * copy-buffer per TX channel. Failure is non-fatal, as there
557 * are only a small number of PIO buffers shared between all
558 * functions of the controller.
559 */
560 if (efx_piobuf_size != 0 &&
561 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
562 efx->n_tx_channels) {
563 unsigned int n_piobufs =
564 DIV_ROUND_UP(efx->n_tx_channels,
565 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
566
567 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
568 if (rc)
569 netif_err(efx, probe, efx->net_dev,
570 "failed to allocate PIO buffers (%d)\n", rc);
571 else
572 netif_dbg(efx, probe, efx->net_dev,
573 "allocated %u PIO buffers\n", n_piobufs);
574 }
575 #else
576 nic_data->n_piobufs = 0;
577 #endif
578
579 /* PIO buffers should be mapped with write-combining enabled,
580 * and we want to make single UC and WC mappings rather than
581 * several of each (in fact that's the only option if host
582 * page size is >4K). So we may allocate some extra VIs just
583 * for writing PIO buffers through.
584 *
585 * The UC mapping contains (min_vis - 1) complete VIs and the
586 * first half of the next VI. Then the WC mapping begins with
587 * the second half of this last VI.
588 */
589 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
590 ER_DZ_TX_PIOBUF);
591 if (nic_data->n_piobufs) {
592 /* pio_write_vi_base rounds down to give the number of complete
593 * VIs inside the UC mapping.
594 */
595 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
596 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
597 nic_data->n_piobufs) *
598 EFX_VI_PAGE_SIZE) -
599 uc_mem_map_size);
600 max_vis = pio_write_vi_base + nic_data->n_piobufs;
601 } else {
602 pio_write_vi_base = 0;
603 wc_mem_map_size = 0;
604 max_vis = min_vis;
605 }
606
607 /* In case the last attached driver failed to free VIs, do it now */
608 rc = efx_ef10_free_vis(efx);
609 if (rc != 0)
610 return rc;
611
612 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
613 if (rc != 0)
614 return rc;
615
616 /* If we didn't get enough VIs to map all the PIO buffers, free the
617 * PIO buffers
618 */
619 if (nic_data->n_piobufs &&
620 nic_data->n_allocated_vis <
621 pio_write_vi_base + nic_data->n_piobufs) {
622 netif_dbg(efx, probe, efx->net_dev,
623 "%u VIs are not sufficient to map %u PIO buffers\n",
624 nic_data->n_allocated_vis, nic_data->n_piobufs);
625 efx_ef10_free_piobufs(efx);
626 }
627
628 /* Shrink the original UC mapping of the memory BAR */
629 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
630 if (!membase) {
631 netif_err(efx, probe, efx->net_dev,
632 "could not shrink memory BAR to %x\n",
633 uc_mem_map_size);
634 return -ENOMEM;
635 }
636 iounmap(efx->membase);
637 efx->membase = membase;
638
639 /* Set up the WC mapping if needed */
640 if (wc_mem_map_size) {
641 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
642 uc_mem_map_size,
643 wc_mem_map_size);
644 if (!nic_data->wc_membase) {
645 netif_err(efx, probe, efx->net_dev,
646 "could not allocate WC mapping of size %x\n",
647 wc_mem_map_size);
648 return -ENOMEM;
649 }
650 nic_data->pio_write_vi_base = pio_write_vi_base;
651 nic_data->pio_write_base =
652 nic_data->wc_membase +
653 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
654 uc_mem_map_size);
655
656 rc = efx_ef10_link_piobufs(efx);
657 if (rc)
658 efx_ef10_free_piobufs(efx);
659 }
660
661 netif_dbg(efx, probe, efx->net_dev,
662 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
663 &efx->membase_phys, efx->membase, uc_mem_map_size,
664 nic_data->wc_membase, wc_mem_map_size);
665
666 return 0;
667 }
668
669 static int efx_ef10_init_nic(struct efx_nic *efx)
670 {
671 struct efx_ef10_nic_data *nic_data = efx->nic_data;
672 int rc;
673
674 if (nic_data->must_check_datapath_caps) {
675 rc = efx_ef10_init_datapath_caps(efx);
676 if (rc)
677 return rc;
678 nic_data->must_check_datapath_caps = false;
679 }
680
681 if (nic_data->must_realloc_vis) {
682 /* We cannot let the number of VIs change now */
683 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
684 nic_data->n_allocated_vis);
685 if (rc)
686 return rc;
687 nic_data->must_realloc_vis = false;
688 }
689
690 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
691 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
692 if (rc == 0) {
693 rc = efx_ef10_link_piobufs(efx);
694 if (rc)
695 efx_ef10_free_piobufs(efx);
696 }
697
698 /* Log an error on failure, but this is non-fatal */
699 if (rc)
700 netif_err(efx, drv, efx->net_dev,
701 "failed to restore PIO buffers (%d)\n", rc);
702 nic_data->must_restore_piobufs = false;
703 }
704
705 efx_ef10_rx_push_rss_config(efx);
706 return 0;
707 }
708
709 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
710 {
711 struct efx_ef10_nic_data *nic_data = efx->nic_data;
712
713 /* All our allocations have been reset */
714 nic_data->must_realloc_vis = true;
715 nic_data->must_restore_filters = true;
716 nic_data->must_restore_piobufs = true;
717 efx_ef10_forget_old_piobufs(efx);
718 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
719 }
720
721 static int efx_ef10_map_reset_flags(u32 *flags)
722 {
723 enum {
724 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
725 ETH_RESET_SHARED_SHIFT),
726 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
727 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
728 ETH_RESET_PHY | ETH_RESET_MGMT) <<
729 ETH_RESET_SHARED_SHIFT)
730 };
731
732 /* We assume for now that our PCI function is permitted to
733 * reset everything.
734 */
735
736 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
737 *flags &= ~EF10_RESET_MC;
738 return RESET_TYPE_WORLD;
739 }
740
741 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
742 *flags &= ~EF10_RESET_PORT;
743 return RESET_TYPE_ALL;
744 }
745
746 /* no invisible reset implemented */
747
748 return -EINVAL;
749 }
750
751 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
752 {
753 int rc = efx_mcdi_reset(efx, reset_type);
754
755 /* If it was a port reset, trigger reallocation of MC resources.
756 * Note that on an MC reset nothing needs to be done now because we'll
757 * detect the MC reset later and handle it then.
758 * For an FLR, we never get an MC reset event, but the MC has reset all
759 * resources assigned to us, so we have to trigger reallocation now.
760 */
761 if ((reset_type == RESET_TYPE_ALL ||
762 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
763 efx_ef10_reset_mc_allocations(efx);
764 return rc;
765 }
766
767 #define EF10_DMA_STAT(ext_name, mcdi_name) \
768 [EF10_STAT_ ## ext_name] = \
769 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
770 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
771 [EF10_STAT_ ## int_name] = \
772 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
773 #define EF10_OTHER_STAT(ext_name) \
774 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
775 #define GENERIC_SW_STAT(ext_name) \
776 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
777
778 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
779 EF10_DMA_STAT(tx_bytes, TX_BYTES),
780 EF10_DMA_STAT(tx_packets, TX_PKTS),
781 EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
782 EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS),
783 EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
784 EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
785 EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
786 EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS),
787 EF10_DMA_STAT(tx_64, TX_64_PKTS),
788 EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
789 EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
790 EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
791 EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
792 EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
793 EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
794 EF10_DMA_STAT(rx_bytes, RX_BYTES),
795 EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES),
796 EF10_OTHER_STAT(rx_good_bytes),
797 EF10_OTHER_STAT(rx_bad_bytes),
798 EF10_DMA_STAT(rx_packets, RX_PKTS),
799 EF10_DMA_STAT(rx_good, RX_GOOD_PKTS),
800 EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
801 EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
802 EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS),
803 EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
804 EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
805 EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
806 EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
807 EF10_DMA_STAT(rx_64, RX_64_PKTS),
808 EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
809 EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
810 EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
811 EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
812 EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
813 EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
814 EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
815 EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
816 EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
817 EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
818 EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
819 EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS),
820 GENERIC_SW_STAT(rx_nodesc_trunc),
821 GENERIC_SW_STAT(rx_noskb_drops),
822 EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
823 EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
824 EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
825 EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
826 EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB),
827 EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB),
828 EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING),
829 EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
830 EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
831 EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
832 EF10_DMA_STAT(rx_dp_hlb_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS),
833 EF10_DMA_STAT(rx_dp_hlb_wait, RXDP_EMERGENCY_WAIT_CONDITIONS),
834 };
835
836 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \
837 (1ULL << EF10_STAT_tx_packets) | \
838 (1ULL << EF10_STAT_tx_pause) | \
839 (1ULL << EF10_STAT_tx_unicast) | \
840 (1ULL << EF10_STAT_tx_multicast) | \
841 (1ULL << EF10_STAT_tx_broadcast) | \
842 (1ULL << EF10_STAT_rx_bytes) | \
843 (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \
844 (1ULL << EF10_STAT_rx_good_bytes) | \
845 (1ULL << EF10_STAT_rx_bad_bytes) | \
846 (1ULL << EF10_STAT_rx_packets) | \
847 (1ULL << EF10_STAT_rx_good) | \
848 (1ULL << EF10_STAT_rx_bad) | \
849 (1ULL << EF10_STAT_rx_pause) | \
850 (1ULL << EF10_STAT_rx_control) | \
851 (1ULL << EF10_STAT_rx_unicast) | \
852 (1ULL << EF10_STAT_rx_multicast) | \
853 (1ULL << EF10_STAT_rx_broadcast) | \
854 (1ULL << EF10_STAT_rx_lt64) | \
855 (1ULL << EF10_STAT_rx_64) | \
856 (1ULL << EF10_STAT_rx_65_to_127) | \
857 (1ULL << EF10_STAT_rx_128_to_255) | \
858 (1ULL << EF10_STAT_rx_256_to_511) | \
859 (1ULL << EF10_STAT_rx_512_to_1023) | \
860 (1ULL << EF10_STAT_rx_1024_to_15xx) | \
861 (1ULL << EF10_STAT_rx_15xx_to_jumbo) | \
862 (1ULL << EF10_STAT_rx_gtjumbo) | \
863 (1ULL << EF10_STAT_rx_bad_gtjumbo) | \
864 (1ULL << EF10_STAT_rx_overflow) | \
865 (1ULL << EF10_STAT_rx_nodesc_drops) | \
866 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
867 (1ULL << GENERIC_STAT_rx_noskb_drops))
868
869 /* These statistics are only provided by the 10G MAC. For a 10G/40G
870 * switchable port we do not expose these because they might not
871 * include all the packets they should.
872 */
873 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) | \
874 (1ULL << EF10_STAT_tx_lt64) | \
875 (1ULL << EF10_STAT_tx_64) | \
876 (1ULL << EF10_STAT_tx_65_to_127) | \
877 (1ULL << EF10_STAT_tx_128_to_255) | \
878 (1ULL << EF10_STAT_tx_256_to_511) | \
879 (1ULL << EF10_STAT_tx_512_to_1023) | \
880 (1ULL << EF10_STAT_tx_1024_to_15xx) | \
881 (1ULL << EF10_STAT_tx_15xx_to_jumbo))
882
883 /* These statistics are only provided by the 40G MAC. For a 10G/40G
884 * switchable port we do expose these because the errors will otherwise
885 * be silent.
886 */
887 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \
888 (1ULL << EF10_STAT_rx_length_error))
889
890 /* These statistics are only provided if the firmware supports the
891 * capability PM_AND_RXDP_COUNTERS.
892 */
893 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
894 (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) | \
895 (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) | \
896 (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) | \
897 (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) | \
898 (1ULL << EF10_STAT_rx_pm_trunc_qbb) | \
899 (1ULL << EF10_STAT_rx_pm_discard_qbb) | \
900 (1ULL << EF10_STAT_rx_pm_discard_mapping) | \
901 (1ULL << EF10_STAT_rx_dp_q_disabled_packets) | \
902 (1ULL << EF10_STAT_rx_dp_di_dropped_packets) | \
903 (1ULL << EF10_STAT_rx_dp_streaming_packets) | \
904 (1ULL << EF10_STAT_rx_dp_hlb_fetch) | \
905 (1ULL << EF10_STAT_rx_dp_hlb_wait))
906
907 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
908 {
909 u64 raw_mask = HUNT_COMMON_STAT_MASK;
910 u32 port_caps = efx_mcdi_phy_get_caps(efx);
911 struct efx_ef10_nic_data *nic_data = efx->nic_data;
912
913 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
914 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
915 else
916 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
917
918 if (nic_data->datapath_caps &
919 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
920 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
921
922 return raw_mask;
923 }
924
925 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
926 {
927 u64 raw_mask = efx_ef10_raw_stat_mask(efx);
928
929 #if BITS_PER_LONG == 64
930 mask[0] = raw_mask;
931 #else
932 mask[0] = raw_mask & 0xffffffff;
933 mask[1] = raw_mask >> 32;
934 #endif
935 }
936
937 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
938 {
939 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
940
941 efx_ef10_get_stat_mask(efx, mask);
942 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
943 mask, names);
944 }
945
946 static int efx_ef10_try_update_nic_stats(struct efx_nic *efx)
947 {
948 struct efx_ef10_nic_data *nic_data = efx->nic_data;
949 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
950 __le64 generation_start, generation_end;
951 u64 *stats = nic_data->stats;
952 __le64 *dma_stats;
953
954 efx_ef10_get_stat_mask(efx, mask);
955
956 dma_stats = efx->stats_buffer.addr;
957 nic_data = efx->nic_data;
958
959 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
960 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
961 return 0;
962 rmb();
963 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
964 stats, efx->stats_buffer.addr, false);
965 rmb();
966 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
967 if (generation_end != generation_start)
968 return -EAGAIN;
969
970 /* Update derived statistics */
971 efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]);
972 stats[EF10_STAT_rx_good_bytes] =
973 stats[EF10_STAT_rx_bytes] -
974 stats[EF10_STAT_rx_bytes_minus_good_bytes];
975 efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes],
976 stats[EF10_STAT_rx_bytes_minus_good_bytes]);
977 efx_update_sw_stats(efx, stats);
978 return 0;
979 }
980
981
982 static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats,
983 struct rtnl_link_stats64 *core_stats)
984 {
985 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
986 struct efx_ef10_nic_data *nic_data = efx->nic_data;
987 u64 *stats = nic_data->stats;
988 size_t stats_count = 0, index;
989 int retry;
990
991 efx_ef10_get_stat_mask(efx, mask);
992
993 /* If we're unlucky enough to read statistics during the DMA, wait
994 * up to 10ms for it to finish (typically takes <500us)
995 */
996 for (retry = 0; retry < 100; ++retry) {
997 if (efx_ef10_try_update_nic_stats(efx) == 0)
998 break;
999 udelay(100);
1000 }
1001
1002 if (full_stats) {
1003 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1004 if (efx_ef10_stat_desc[index].name) {
1005 *full_stats++ = stats[index];
1006 ++stats_count;
1007 }
1008 }
1009 }
1010
1011 if (core_stats) {
1012 core_stats->rx_packets = stats[EF10_STAT_rx_packets];
1013 core_stats->tx_packets = stats[EF10_STAT_tx_packets];
1014 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes];
1015 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes];
1016 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops] +
1017 stats[GENERIC_STAT_rx_nodesc_trunc] +
1018 stats[GENERIC_STAT_rx_noskb_drops];
1019 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1020 core_stats->rx_length_errors =
1021 stats[EF10_STAT_rx_gtjumbo] +
1022 stats[EF10_STAT_rx_length_error];
1023 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1024 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error];
1025 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1026 core_stats->rx_errors = (core_stats->rx_length_errors +
1027 core_stats->rx_crc_errors +
1028 core_stats->rx_frame_errors);
1029 }
1030
1031 return stats_count;
1032 }
1033
1034 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1035 {
1036 struct efx_nic *efx = channel->efx;
1037 unsigned int mode, value;
1038 efx_dword_t timer_cmd;
1039
1040 if (channel->irq_moderation) {
1041 mode = 3;
1042 value = channel->irq_moderation - 1;
1043 } else {
1044 mode = 0;
1045 value = 0;
1046 }
1047
1048 if (EFX_EF10_WORKAROUND_35388(efx)) {
1049 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1050 EFE_DD_EVQ_IND_TIMER_FLAGS,
1051 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1052 ERF_DD_EVQ_IND_TIMER_VAL, value);
1053 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1054 channel->channel);
1055 } else {
1056 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1057 ERF_DZ_TC_TIMER_VAL, value);
1058 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1059 channel->channel);
1060 }
1061 }
1062
1063 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1064 {
1065 wol->supported = 0;
1066 wol->wolopts = 0;
1067 memset(&wol->sopass, 0, sizeof(wol->sopass));
1068 }
1069
1070 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1071 {
1072 if (type != 0)
1073 return -EINVAL;
1074 return 0;
1075 }
1076
1077 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1078 const efx_dword_t *hdr, size_t hdr_len,
1079 const efx_dword_t *sdu, size_t sdu_len)
1080 {
1081 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1082 u8 *pdu = nic_data->mcdi_buf.addr;
1083
1084 memcpy(pdu, hdr, hdr_len);
1085 memcpy(pdu + hdr_len, sdu, sdu_len);
1086 wmb();
1087
1088 /* The hardware provides 'low' and 'high' (doorbell) registers
1089 * for passing the 64-bit address of an MCDI request to
1090 * firmware. However the dwords are swapped by firmware. The
1091 * least significant bits of the doorbell are then 0 for all
1092 * MCDI requests due to alignment.
1093 */
1094 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1095 ER_DZ_MC_DB_LWRD);
1096 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1097 ER_DZ_MC_DB_HWRD);
1098 }
1099
1100 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1101 {
1102 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1103 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1104
1105 rmb();
1106 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1107 }
1108
1109 static void
1110 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1111 size_t offset, size_t outlen)
1112 {
1113 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1114 const u8 *pdu = nic_data->mcdi_buf.addr;
1115
1116 memcpy(outbuf, pdu + offset, outlen);
1117 }
1118
1119 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1120 {
1121 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1122 int rc;
1123
1124 rc = efx_ef10_get_warm_boot_count(efx);
1125 if (rc < 0) {
1126 /* The firmware is presumably in the process of
1127 * rebooting. However, we are supposed to report each
1128 * reboot just once, so we must only do that once we
1129 * can read and store the updated warm boot count.
1130 */
1131 return 0;
1132 }
1133
1134 if (rc == nic_data->warm_boot_count)
1135 return 0;
1136
1137 nic_data->warm_boot_count = rc;
1138
1139 /* All our allocations have been reset */
1140 efx_ef10_reset_mc_allocations(efx);
1141
1142 /* The datapath firmware might have been changed */
1143 nic_data->must_check_datapath_caps = true;
1144
1145 /* MAC statistics have been cleared on the NIC; clear the local
1146 * statistic that we update with efx_update_diff_stat().
1147 */
1148 nic_data->stats[EF10_STAT_rx_bad_bytes] = 0;
1149
1150 return -EIO;
1151 }
1152
1153 /* Handle an MSI interrupt
1154 *
1155 * Handle an MSI hardware interrupt. This routine schedules event
1156 * queue processing. No interrupt acknowledgement cycle is necessary.
1157 * Also, we never need to check that the interrupt is for us, since
1158 * MSI interrupts cannot be shared.
1159 */
1160 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1161 {
1162 struct efx_msi_context *context = dev_id;
1163 struct efx_nic *efx = context->efx;
1164
1165 netif_vdbg(efx, intr, efx->net_dev,
1166 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1167
1168 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1169 /* Note test interrupts */
1170 if (context->index == efx->irq_level)
1171 efx->last_irq_cpu = raw_smp_processor_id();
1172
1173 /* Schedule processing of the channel */
1174 efx_schedule_channel_irq(efx->channel[context->index]);
1175 }
1176
1177 return IRQ_HANDLED;
1178 }
1179
1180 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1181 {
1182 struct efx_nic *efx = dev_id;
1183 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1184 struct efx_channel *channel;
1185 efx_dword_t reg;
1186 u32 queues;
1187
1188 /* Read the ISR which also ACKs the interrupts */
1189 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1190 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1191
1192 if (queues == 0)
1193 return IRQ_NONE;
1194
1195 if (likely(soft_enabled)) {
1196 /* Note test interrupts */
1197 if (queues & (1U << efx->irq_level))
1198 efx->last_irq_cpu = raw_smp_processor_id();
1199
1200 efx_for_each_channel(channel, efx) {
1201 if (queues & 1)
1202 efx_schedule_channel_irq(channel);
1203 queues >>= 1;
1204 }
1205 }
1206
1207 netif_vdbg(efx, intr, efx->net_dev,
1208 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1209 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1210
1211 return IRQ_HANDLED;
1212 }
1213
1214 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1215 {
1216 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1217
1218 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1219
1220 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1221 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1222 inbuf, sizeof(inbuf), NULL, 0, NULL);
1223 }
1224
1225 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1226 {
1227 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1228 (tx_queue->ptr_mask + 1) *
1229 sizeof(efx_qword_t),
1230 GFP_KERNEL);
1231 }
1232
1233 /* This writes to the TX_DESC_WPTR and also pushes data */
1234 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1235 const efx_qword_t *txd)
1236 {
1237 unsigned int write_ptr;
1238 efx_oword_t reg;
1239
1240 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1241 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1242 reg.qword[0] = *txd;
1243 efx_writeo_page(tx_queue->efx, &reg,
1244 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1245 }
1246
1247 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1248 {
1249 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1250 EFX_BUF_SIZE));
1251 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN);
1252 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1253 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1254 struct efx_channel *channel = tx_queue->channel;
1255 struct efx_nic *efx = tx_queue->efx;
1256 size_t inlen, outlen;
1257 dma_addr_t dma_addr;
1258 efx_qword_t *txd;
1259 int rc;
1260 int i;
1261
1262 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1263 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1264 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1265 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1266 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1267 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1268 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1269 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1270 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1271
1272 dma_addr = tx_queue->txd.buf.dma_addr;
1273
1274 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1275 tx_queue->queue, entries, (u64)dma_addr);
1276
1277 for (i = 0; i < entries; ++i) {
1278 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1279 dma_addr += EFX_BUF_SIZE;
1280 }
1281
1282 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1283
1284 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1285 outbuf, sizeof(outbuf), &outlen);
1286 if (rc)
1287 goto fail;
1288
1289 /* A previous user of this TX queue might have set us up the
1290 * bomb by writing a descriptor to the TX push collector but
1291 * not the doorbell. (Each collector belongs to a port, not a
1292 * queue or function, so cannot easily be reset.) We must
1293 * attempt to push a no-op descriptor in its place.
1294 */
1295 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1296 tx_queue->insert_count = 1;
1297 txd = efx_tx_desc(tx_queue, 0);
1298 EFX_POPULATE_QWORD_4(*txd,
1299 ESF_DZ_TX_DESC_IS_OPT, true,
1300 ESF_DZ_TX_OPTION_TYPE,
1301 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1302 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1303 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1304 tx_queue->write_count = 1;
1305 wmb();
1306 efx_ef10_push_tx_desc(tx_queue, txd);
1307
1308 return;
1309
1310 fail:
1311 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1312 tx_queue->queue);
1313 }
1314
1315 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1316 {
1317 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1318 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN);
1319 struct efx_nic *efx = tx_queue->efx;
1320 size_t outlen;
1321 int rc;
1322
1323 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1324 tx_queue->queue);
1325
1326 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
1327 outbuf, sizeof(outbuf), &outlen);
1328
1329 if (rc && rc != -EALREADY)
1330 goto fail;
1331
1332 return;
1333
1334 fail:
1335 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1336 outbuf, outlen, rc);
1337 }
1338
1339 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1340 {
1341 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1342 }
1343
1344 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1345 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1346 {
1347 unsigned int write_ptr;
1348 efx_dword_t reg;
1349
1350 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1351 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1352 efx_writed_page(tx_queue->efx, &reg,
1353 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1354 }
1355
1356 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1357 {
1358 unsigned int old_write_count = tx_queue->write_count;
1359 struct efx_tx_buffer *buffer;
1360 unsigned int write_ptr;
1361 efx_qword_t *txd;
1362
1363 tx_queue->xmit_more_available = false;
1364 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
1365 return;
1366
1367 do {
1368 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1369 buffer = &tx_queue->buffer[write_ptr];
1370 txd = efx_tx_desc(tx_queue, write_ptr);
1371 ++tx_queue->write_count;
1372
1373 /* Create TX descriptor ring entry */
1374 if (buffer->flags & EFX_TX_BUF_OPTION) {
1375 *txd = buffer->option;
1376 } else {
1377 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1378 EFX_POPULATE_QWORD_3(
1379 *txd,
1380 ESF_DZ_TX_KER_CONT,
1381 buffer->flags & EFX_TX_BUF_CONT,
1382 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1383 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1384 }
1385 } while (tx_queue->write_count != tx_queue->insert_count);
1386
1387 wmb(); /* Ensure descriptors are written before they are fetched */
1388
1389 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1390 txd = efx_tx_desc(tx_queue,
1391 old_write_count & tx_queue->ptr_mask);
1392 efx_ef10_push_tx_desc(tx_queue, txd);
1393 ++tx_queue->pushes;
1394 } else {
1395 efx_ef10_notify_tx_desc(tx_queue);
1396 }
1397 }
1398
1399 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context)
1400 {
1401 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1402 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1403 size_t outlen;
1404 int rc;
1405
1406 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1407 EVB_PORT_ID_ASSIGNED);
1408 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE,
1409 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE);
1410 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES,
1411 EFX_MAX_CHANNELS);
1412
1413 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1414 outbuf, sizeof(outbuf), &outlen);
1415 if (rc != 0)
1416 return rc;
1417
1418 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1419 return -EIO;
1420
1421 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1422
1423 return 0;
1424 }
1425
1426 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1427 {
1428 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1429 int rc;
1430
1431 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1432 context);
1433
1434 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1435 NULL, 0, NULL);
1436 WARN_ON(rc != 0);
1437 }
1438
1439 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context)
1440 {
1441 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1442 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1443 int i, rc;
1444
1445 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1446 context);
1447 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1448 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1449
1450 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1451 MCDI_PTR(tablebuf,
1452 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1453 (u8) efx->rx_indir_table[i];
1454
1455 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1456 sizeof(tablebuf), NULL, 0, NULL);
1457 if (rc != 0)
1458 return rc;
1459
1460 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1461 context);
1462 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1463 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1464 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1465 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1466 efx->rx_hash_key[i];
1467
1468 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1469 sizeof(keybuf), NULL, 0, NULL);
1470 }
1471
1472 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1473 {
1474 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1475
1476 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1477 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1478 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1479 }
1480
1481 static void efx_ef10_rx_push_rss_config(struct efx_nic *efx)
1482 {
1483 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1484 int rc;
1485
1486 netif_dbg(efx, drv, efx->net_dev, "pushing RSS config\n");
1487
1488 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) {
1489 rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context);
1490 if (rc != 0)
1491 goto fail;
1492 }
1493
1494 rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context);
1495 if (rc != 0)
1496 goto fail;
1497
1498 return;
1499
1500 fail:
1501 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1502 }
1503
1504 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
1505 {
1506 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
1507 (rx_queue->ptr_mask + 1) *
1508 sizeof(efx_qword_t),
1509 GFP_KERNEL);
1510 }
1511
1512 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
1513 {
1514 MCDI_DECLARE_BUF(inbuf,
1515 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1516 EFX_BUF_SIZE));
1517 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN);
1518 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1519 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
1520 struct efx_nic *efx = rx_queue->efx;
1521 size_t inlen, outlen;
1522 dma_addr_t dma_addr;
1523 int rc;
1524 int i;
1525
1526 rx_queue->scatter_n = 0;
1527 rx_queue->scatter_len = 0;
1528
1529 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
1530 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
1531 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
1532 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
1533 efx_rx_queue_index(rx_queue));
1534 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
1535 INIT_RXQ_IN_FLAG_PREFIX, 1,
1536 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
1537 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
1538 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1539
1540 dma_addr = rx_queue->rxd.buf.dma_addr;
1541
1542 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
1543 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
1544
1545 for (i = 0; i < entries; ++i) {
1546 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
1547 dma_addr += EFX_BUF_SIZE;
1548 }
1549
1550 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
1551
1552 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
1553 outbuf, sizeof(outbuf), &outlen);
1554 if (rc)
1555 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
1556 efx_rx_queue_index(rx_queue));
1557 }
1558
1559 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
1560 {
1561 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
1562 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN);
1563 struct efx_nic *efx = rx_queue->efx;
1564 size_t outlen;
1565 int rc;
1566
1567 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
1568 efx_rx_queue_index(rx_queue));
1569
1570 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
1571 outbuf, sizeof(outbuf), &outlen);
1572
1573 if (rc && rc != -EALREADY)
1574 goto fail;
1575
1576 return;
1577
1578 fail:
1579 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
1580 outbuf, outlen, rc);
1581 }
1582
1583 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
1584 {
1585 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
1586 }
1587
1588 /* This creates an entry in the RX descriptor queue */
1589 static inline void
1590 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
1591 {
1592 struct efx_rx_buffer *rx_buf;
1593 efx_qword_t *rxd;
1594
1595 rxd = efx_rx_desc(rx_queue, index);
1596 rx_buf = efx_rx_buffer(rx_queue, index);
1597 EFX_POPULATE_QWORD_2(*rxd,
1598 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
1599 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
1600 }
1601
1602 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
1603 {
1604 struct efx_nic *efx = rx_queue->efx;
1605 unsigned int write_count;
1606 efx_dword_t reg;
1607
1608 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1609 write_count = rx_queue->added_count & ~7;
1610 if (rx_queue->notified_count == write_count)
1611 return;
1612
1613 do
1614 efx_ef10_build_rx_desc(
1615 rx_queue,
1616 rx_queue->notified_count & rx_queue->ptr_mask);
1617 while (++rx_queue->notified_count != write_count);
1618
1619 wmb();
1620 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
1621 write_count & rx_queue->ptr_mask);
1622 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
1623 efx_rx_queue_index(rx_queue));
1624 }
1625
1626 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
1627
1628 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
1629 {
1630 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1631 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1632 efx_qword_t event;
1633
1634 EFX_POPULATE_QWORD_2(event,
1635 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1636 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
1637
1638 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1639
1640 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1641 * already swapped the data to little-endian order.
1642 */
1643 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1644 sizeof(efx_qword_t));
1645
1646 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
1647 inbuf, sizeof(inbuf), 0,
1648 efx_ef10_rx_defer_refill_complete, 0);
1649 }
1650
1651 static void
1652 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
1653 int rc, efx_dword_t *outbuf,
1654 size_t outlen_actual)
1655 {
1656 /* nothing to do */
1657 }
1658
1659 static int efx_ef10_ev_probe(struct efx_channel *channel)
1660 {
1661 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
1662 (channel->eventq_mask + 1) *
1663 sizeof(efx_qword_t),
1664 GFP_KERNEL);
1665 }
1666
1667 static int efx_ef10_ev_init(struct efx_channel *channel)
1668 {
1669 MCDI_DECLARE_BUF(inbuf,
1670 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
1671 EFX_BUF_SIZE));
1672 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
1673 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
1674 struct efx_nic *efx = channel->efx;
1675 struct efx_ef10_nic_data *nic_data;
1676 bool supports_rx_merge;
1677 size_t inlen, outlen;
1678 dma_addr_t dma_addr;
1679 int rc;
1680 int i;
1681
1682 nic_data = efx->nic_data;
1683 supports_rx_merge =
1684 !!(nic_data->datapath_caps &
1685 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
1686
1687 /* Fill event queue with all ones (i.e. empty events) */
1688 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1689
1690 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
1691 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
1692 /* INIT_EVQ expects index in vector table, not absolute */
1693 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
1694 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
1695 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
1696 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
1697 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
1698 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
1699 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
1700 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
1701 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
1702 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
1703 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
1704 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
1705 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
1706
1707 dma_addr = channel->eventq.buf.dma_addr;
1708 for (i = 0; i < entries; ++i) {
1709 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
1710 dma_addr += EFX_BUF_SIZE;
1711 }
1712
1713 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
1714
1715 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
1716 outbuf, sizeof(outbuf), &outlen);
1717 /* IRQ return is ignored */
1718 return rc;
1719 }
1720
1721 static void efx_ef10_ev_fini(struct efx_channel *channel)
1722 {
1723 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
1724 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN);
1725 struct efx_nic *efx = channel->efx;
1726 size_t outlen;
1727 int rc;
1728
1729 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
1730
1731 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
1732 outbuf, sizeof(outbuf), &outlen);
1733
1734 if (rc && rc != -EALREADY)
1735 goto fail;
1736
1737 return;
1738
1739 fail:
1740 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
1741 outbuf, outlen, rc);
1742 }
1743
1744 static void efx_ef10_ev_remove(struct efx_channel *channel)
1745 {
1746 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
1747 }
1748
1749 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
1750 unsigned int rx_queue_label)
1751 {
1752 struct efx_nic *efx = rx_queue->efx;
1753
1754 netif_info(efx, hw, efx->net_dev,
1755 "rx event arrived on queue %d labeled as queue %u\n",
1756 efx_rx_queue_index(rx_queue), rx_queue_label);
1757
1758 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1759 }
1760
1761 static void
1762 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
1763 unsigned int actual, unsigned int expected)
1764 {
1765 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
1766 struct efx_nic *efx = rx_queue->efx;
1767
1768 netif_info(efx, hw, efx->net_dev,
1769 "dropped %d events (index=%d expected=%d)\n",
1770 dropped, actual, expected);
1771
1772 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1773 }
1774
1775 /* partially received RX was aborted. clean up. */
1776 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
1777 {
1778 unsigned int rx_desc_ptr;
1779
1780 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
1781 "scattered RX aborted (dropping %u buffers)\n",
1782 rx_queue->scatter_n);
1783
1784 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
1785
1786 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
1787 0, EFX_RX_PKT_DISCARD);
1788
1789 rx_queue->removed_count += rx_queue->scatter_n;
1790 rx_queue->scatter_n = 0;
1791 rx_queue->scatter_len = 0;
1792 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
1793 }
1794
1795 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
1796 const efx_qword_t *event)
1797 {
1798 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
1799 unsigned int n_descs, n_packets, i;
1800 struct efx_nic *efx = channel->efx;
1801 struct efx_rx_queue *rx_queue;
1802 bool rx_cont;
1803 u16 flags = 0;
1804
1805 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1806 return 0;
1807
1808 /* Basic packet information */
1809 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
1810 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
1811 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
1812 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
1813 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
1814
1815 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
1816 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
1817 EFX_QWORD_FMT "\n",
1818 EFX_QWORD_VAL(*event));
1819
1820 rx_queue = efx_channel_get_rx_queue(channel);
1821
1822 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
1823 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
1824
1825 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
1826 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1827
1828 if (n_descs != rx_queue->scatter_n + 1) {
1829 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1830
1831 /* detect rx abort */
1832 if (unlikely(n_descs == rx_queue->scatter_n)) {
1833 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
1834 netdev_WARN(efx->net_dev,
1835 "invalid RX abort: scatter_n=%u event="
1836 EFX_QWORD_FMT "\n",
1837 rx_queue->scatter_n,
1838 EFX_QWORD_VAL(*event));
1839 efx_ef10_handle_rx_abort(rx_queue);
1840 return 0;
1841 }
1842
1843 /* Check that RX completion merging is valid, i.e.
1844 * the current firmware supports it and this is a
1845 * non-scattered packet.
1846 */
1847 if (!(nic_data->datapath_caps &
1848 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
1849 rx_queue->scatter_n != 0 || rx_cont) {
1850 efx_ef10_handle_rx_bad_lbits(
1851 rx_queue, next_ptr_lbits,
1852 (rx_queue->removed_count +
1853 rx_queue->scatter_n + 1) &
1854 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1855 return 0;
1856 }
1857
1858 /* Merged completion for multiple non-scattered packets */
1859 rx_queue->scatter_n = 1;
1860 rx_queue->scatter_len = 0;
1861 n_packets = n_descs;
1862 ++channel->n_rx_merge_events;
1863 channel->n_rx_merge_packets += n_packets;
1864 flags |= EFX_RX_PKT_PREFIX_LEN;
1865 } else {
1866 ++rx_queue->scatter_n;
1867 rx_queue->scatter_len += rx_bytes;
1868 if (rx_cont)
1869 return 0;
1870 n_packets = 1;
1871 }
1872
1873 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
1874 flags |= EFX_RX_PKT_DISCARD;
1875
1876 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
1877 channel->n_rx_ip_hdr_chksum_err += n_packets;
1878 } else if (unlikely(EFX_QWORD_FIELD(*event,
1879 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
1880 channel->n_rx_tcp_udp_chksum_err += n_packets;
1881 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
1882 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
1883 flags |= EFX_RX_PKT_CSUMMED;
1884 }
1885
1886 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
1887 flags |= EFX_RX_PKT_TCP;
1888
1889 channel->irq_mod_score += 2 * n_packets;
1890
1891 /* Handle received packet(s) */
1892 for (i = 0; i < n_packets; i++) {
1893 efx_rx_packet(rx_queue,
1894 rx_queue->removed_count & rx_queue->ptr_mask,
1895 rx_queue->scatter_n, rx_queue->scatter_len,
1896 flags);
1897 rx_queue->removed_count += rx_queue->scatter_n;
1898 }
1899
1900 rx_queue->scatter_n = 0;
1901 rx_queue->scatter_len = 0;
1902
1903 return n_packets;
1904 }
1905
1906 static int
1907 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
1908 {
1909 struct efx_nic *efx = channel->efx;
1910 struct efx_tx_queue *tx_queue;
1911 unsigned int tx_ev_desc_ptr;
1912 unsigned int tx_ev_q_label;
1913 int tx_descs = 0;
1914
1915 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1916 return 0;
1917
1918 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
1919 return 0;
1920
1921 /* Transmit completion */
1922 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
1923 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
1924 tx_queue = efx_channel_get_tx_queue(channel,
1925 tx_ev_q_label % EFX_TXQ_TYPES);
1926 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
1927 tx_queue->ptr_mask);
1928 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
1929
1930 return tx_descs;
1931 }
1932
1933 static void
1934 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1935 {
1936 struct efx_nic *efx = channel->efx;
1937 int subcode;
1938
1939 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
1940
1941 switch (subcode) {
1942 case ESE_DZ_DRV_TIMER_EV:
1943 case ESE_DZ_DRV_WAKE_UP_EV:
1944 break;
1945 case ESE_DZ_DRV_START_UP_EV:
1946 /* event queue init complete. ok. */
1947 break;
1948 default:
1949 netif_err(efx, hw, efx->net_dev,
1950 "channel %d unknown driver event type %d"
1951 " (data " EFX_QWORD_FMT ")\n",
1952 channel->channel, subcode,
1953 EFX_QWORD_VAL(*event));
1954
1955 }
1956 }
1957
1958 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
1959 efx_qword_t *event)
1960 {
1961 struct efx_nic *efx = channel->efx;
1962 u32 subcode;
1963
1964 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
1965
1966 switch (subcode) {
1967 case EFX_EF10_TEST:
1968 channel->event_test_cpu = raw_smp_processor_id();
1969 break;
1970 case EFX_EF10_REFILL:
1971 /* The queue must be empty, so we won't receive any rx
1972 * events, so efx_process_channel() won't refill the
1973 * queue. Refill it here
1974 */
1975 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
1976 break;
1977 default:
1978 netif_err(efx, hw, efx->net_dev,
1979 "channel %d unknown driver event type %u"
1980 " (data " EFX_QWORD_FMT ")\n",
1981 channel->channel, (unsigned) subcode,
1982 EFX_QWORD_VAL(*event));
1983 }
1984 }
1985
1986 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
1987 {
1988 struct efx_nic *efx = channel->efx;
1989 efx_qword_t event, *p_event;
1990 unsigned int read_ptr;
1991 int ev_code;
1992 int tx_descs = 0;
1993 int spent = 0;
1994
1995 if (quota <= 0)
1996 return spent;
1997
1998 read_ptr = channel->eventq_read_ptr;
1999
2000 for (;;) {
2001 p_event = efx_event(channel, read_ptr);
2002 event = *p_event;
2003
2004 if (!efx_event_present(&event))
2005 break;
2006
2007 EFX_SET_QWORD(*p_event);
2008
2009 ++read_ptr;
2010
2011 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2012
2013 netif_vdbg(efx, drv, efx->net_dev,
2014 "processing event on %d " EFX_QWORD_FMT "\n",
2015 channel->channel, EFX_QWORD_VAL(event));
2016
2017 switch (ev_code) {
2018 case ESE_DZ_EV_CODE_MCDI_EV:
2019 efx_mcdi_process_event(channel, &event);
2020 break;
2021 case ESE_DZ_EV_CODE_RX_EV:
2022 spent += efx_ef10_handle_rx_event(channel, &event);
2023 if (spent >= quota) {
2024 /* XXX can we split a merged event to
2025 * avoid going over-quota?
2026 */
2027 spent = quota;
2028 goto out;
2029 }
2030 break;
2031 case ESE_DZ_EV_CODE_TX_EV:
2032 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2033 if (tx_descs > efx->txq_entries) {
2034 spent = quota;
2035 goto out;
2036 } else if (++spent == quota) {
2037 goto out;
2038 }
2039 break;
2040 case ESE_DZ_EV_CODE_DRIVER_EV:
2041 efx_ef10_handle_driver_event(channel, &event);
2042 if (++spent == quota)
2043 goto out;
2044 break;
2045 case EFX_EF10_DRVGEN_EV:
2046 efx_ef10_handle_driver_generated_event(channel, &event);
2047 break;
2048 default:
2049 netif_err(efx, hw, efx->net_dev,
2050 "channel %d unknown event type %d"
2051 " (data " EFX_QWORD_FMT ")\n",
2052 channel->channel, ev_code,
2053 EFX_QWORD_VAL(event));
2054 }
2055 }
2056
2057 out:
2058 channel->eventq_read_ptr = read_ptr;
2059 return spent;
2060 }
2061
2062 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2063 {
2064 struct efx_nic *efx = channel->efx;
2065 efx_dword_t rptr;
2066
2067 if (EFX_EF10_WORKAROUND_35388(efx)) {
2068 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2069 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2070 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2071 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2072
2073 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2074 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2075 ERF_DD_EVQ_IND_RPTR,
2076 (channel->eventq_read_ptr &
2077 channel->eventq_mask) >>
2078 ERF_DD_EVQ_IND_RPTR_WIDTH);
2079 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2080 channel->channel);
2081 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2082 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2083 ERF_DD_EVQ_IND_RPTR,
2084 channel->eventq_read_ptr &
2085 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2086 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2087 channel->channel);
2088 } else {
2089 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2090 channel->eventq_read_ptr &
2091 channel->eventq_mask);
2092 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2093 }
2094 }
2095
2096 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2097 {
2098 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2099 struct efx_nic *efx = channel->efx;
2100 efx_qword_t event;
2101 int rc;
2102
2103 EFX_POPULATE_QWORD_2(event,
2104 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2105 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2106
2107 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2108
2109 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2110 * already swapped the data to little-endian order.
2111 */
2112 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2113 sizeof(efx_qword_t));
2114
2115 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2116 NULL, 0, NULL);
2117 if (rc != 0)
2118 goto fail;
2119
2120 return;
2121
2122 fail:
2123 WARN_ON(true);
2124 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2125 }
2126
2127 void efx_ef10_handle_drain_event(struct efx_nic *efx)
2128 {
2129 if (atomic_dec_and_test(&efx->active_queues))
2130 wake_up(&efx->flush_wq);
2131
2132 WARN_ON(atomic_read(&efx->active_queues) < 0);
2133 }
2134
2135 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2136 {
2137 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2138 struct efx_channel *channel;
2139 struct efx_tx_queue *tx_queue;
2140 struct efx_rx_queue *rx_queue;
2141 int pending;
2142
2143 /* If the MC has just rebooted, the TX/RX queues will have already been
2144 * torn down, but efx->active_queues needs to be set to zero.
2145 */
2146 if (nic_data->must_realloc_vis) {
2147 atomic_set(&efx->active_queues, 0);
2148 return 0;
2149 }
2150
2151 /* Do not attempt to write to the NIC during EEH recovery */
2152 if (efx->state != STATE_RECOVERY) {
2153 efx_for_each_channel(channel, efx) {
2154 efx_for_each_channel_rx_queue(rx_queue, channel)
2155 efx_ef10_rx_fini(rx_queue);
2156 efx_for_each_channel_tx_queue(tx_queue, channel)
2157 efx_ef10_tx_fini(tx_queue);
2158 }
2159
2160 wait_event_timeout(efx->flush_wq,
2161 atomic_read(&efx->active_queues) == 0,
2162 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2163 pending = atomic_read(&efx->active_queues);
2164 if (pending) {
2165 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2166 pending);
2167 return -ETIMEDOUT;
2168 }
2169 }
2170
2171 return 0;
2172 }
2173
2174 static void efx_ef10_prepare_flr(struct efx_nic *efx)
2175 {
2176 atomic_set(&efx->active_queues, 0);
2177 }
2178
2179 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2180 const struct efx_filter_spec *right)
2181 {
2182 if ((left->match_flags ^ right->match_flags) |
2183 ((left->flags ^ right->flags) &
2184 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2185 return false;
2186
2187 return memcmp(&left->outer_vid, &right->outer_vid,
2188 sizeof(struct efx_filter_spec) -
2189 offsetof(struct efx_filter_spec, outer_vid)) == 0;
2190 }
2191
2192 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2193 {
2194 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2195 return jhash2((const u32 *)&spec->outer_vid,
2196 (sizeof(struct efx_filter_spec) -
2197 offsetof(struct efx_filter_spec, outer_vid)) / 4,
2198 0);
2199 /* XXX should we randomise the initval? */
2200 }
2201
2202 /* Decide whether a filter should be exclusive or else should allow
2203 * delivery to additional recipients. Currently we decide that
2204 * filters for specific local unicast MAC and IP addresses are
2205 * exclusive.
2206 */
2207 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2208 {
2209 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2210 !is_multicast_ether_addr(spec->loc_mac))
2211 return true;
2212
2213 if ((spec->match_flags &
2214 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2215 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2216 if (spec->ether_type == htons(ETH_P_IP) &&
2217 !ipv4_is_multicast(spec->loc_host[0]))
2218 return true;
2219 if (spec->ether_type == htons(ETH_P_IPV6) &&
2220 ((const u8 *)spec->loc_host)[0] != 0xff)
2221 return true;
2222 }
2223
2224 return false;
2225 }
2226
2227 static struct efx_filter_spec *
2228 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2229 unsigned int filter_idx)
2230 {
2231 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2232 ~EFX_EF10_FILTER_FLAGS);
2233 }
2234
2235 static unsigned int
2236 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2237 unsigned int filter_idx)
2238 {
2239 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2240 }
2241
2242 static void
2243 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2244 unsigned int filter_idx,
2245 const struct efx_filter_spec *spec,
2246 unsigned int flags)
2247 {
2248 table->entry[filter_idx].spec = (unsigned long)spec | flags;
2249 }
2250
2251 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2252 const struct efx_filter_spec *spec,
2253 efx_dword_t *inbuf, u64 handle,
2254 bool replacing)
2255 {
2256 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2257
2258 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2259
2260 if (replacing) {
2261 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2262 MC_CMD_FILTER_OP_IN_OP_REPLACE);
2263 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2264 } else {
2265 u32 match_fields = 0;
2266
2267 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2268 efx_ef10_filter_is_exclusive(spec) ?
2269 MC_CMD_FILTER_OP_IN_OP_INSERT :
2270 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2271
2272 /* Convert match flags and values. Unlike almost
2273 * everything else in MCDI, these fields are in
2274 * network byte order.
2275 */
2276 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2277 match_fields |=
2278 is_multicast_ether_addr(spec->loc_mac) ?
2279 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2280 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2281 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2282 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2283 match_fields |= \
2284 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2285 mcdi_field ## _LBN; \
2286 BUILD_BUG_ON( \
2287 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2288 sizeof(spec->gen_field)); \
2289 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2290 &spec->gen_field, sizeof(spec->gen_field)); \
2291 }
2292 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2293 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2294 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2295 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2296 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2297 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2298 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2299 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2300 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2301 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2302 #undef COPY_FIELD
2303 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2304 match_fields);
2305 }
2306
2307 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
2308 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2309 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2310 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2311 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
2312 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2313 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
2314 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2315 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2316 0 : spec->dmaq_id);
2317 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2318 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2319 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2320 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2321 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2322 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2323 spec->rss_context !=
2324 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2325 spec->rss_context : nic_data->rx_rss_context);
2326 }
2327
2328 static int efx_ef10_filter_push(struct efx_nic *efx,
2329 const struct efx_filter_spec *spec,
2330 u64 *handle, bool replacing)
2331 {
2332 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2333 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2334 int rc;
2335
2336 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2337 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2338 outbuf, sizeof(outbuf), NULL);
2339 if (rc == 0)
2340 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2341 if (rc == -ENOSPC)
2342 rc = -EBUSY; /* to match efx_farch_filter_insert() */
2343 return rc;
2344 }
2345
2346 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2347 enum efx_filter_match_flags match_flags)
2348 {
2349 unsigned int match_pri;
2350
2351 for (match_pri = 0;
2352 match_pri < table->rx_match_count;
2353 match_pri++)
2354 if (table->rx_match_flags[match_pri] == match_flags)
2355 return match_pri;
2356
2357 return -EPROTONOSUPPORT;
2358 }
2359
2360 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
2361 struct efx_filter_spec *spec,
2362 bool replace_equal)
2363 {
2364 struct efx_ef10_filter_table *table = efx->filter_state;
2365 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2366 struct efx_filter_spec *saved_spec;
2367 unsigned int match_pri, hash;
2368 unsigned int priv_flags;
2369 bool replacing = false;
2370 int ins_index = -1;
2371 DEFINE_WAIT(wait);
2372 bool is_mc_recip;
2373 s32 rc;
2374
2375 /* For now, only support RX filters */
2376 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
2377 EFX_FILTER_FLAG_RX)
2378 return -EINVAL;
2379
2380 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
2381 if (rc < 0)
2382 return rc;
2383 match_pri = rc;
2384
2385 hash = efx_ef10_filter_hash(spec);
2386 is_mc_recip = efx_filter_is_mc_recipient(spec);
2387 if (is_mc_recip)
2388 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2389
2390 /* Find any existing filters with the same match tuple or
2391 * else a free slot to insert at. If any of them are busy,
2392 * we have to wait and retry.
2393 */
2394 for (;;) {
2395 unsigned int depth = 1;
2396 unsigned int i;
2397
2398 spin_lock_bh(&efx->filter_lock);
2399
2400 for (;;) {
2401 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2402 saved_spec = efx_ef10_filter_entry_spec(table, i);
2403
2404 if (!saved_spec) {
2405 if (ins_index < 0)
2406 ins_index = i;
2407 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2408 if (table->entry[i].spec &
2409 EFX_EF10_FILTER_FLAG_BUSY)
2410 break;
2411 if (spec->priority < saved_spec->priority &&
2412 spec->priority != EFX_FILTER_PRI_AUTO) {
2413 rc = -EPERM;
2414 goto out_unlock;
2415 }
2416 if (!is_mc_recip) {
2417 /* This is the only one */
2418 if (spec->priority ==
2419 saved_spec->priority &&
2420 !replace_equal) {
2421 rc = -EEXIST;
2422 goto out_unlock;
2423 }
2424 ins_index = i;
2425 goto found;
2426 } else if (spec->priority >
2427 saved_spec->priority ||
2428 (spec->priority ==
2429 saved_spec->priority &&
2430 replace_equal)) {
2431 if (ins_index < 0)
2432 ins_index = i;
2433 else
2434 __set_bit(depth, mc_rem_map);
2435 }
2436 }
2437
2438 /* Once we reach the maximum search depth, use
2439 * the first suitable slot or return -EBUSY if
2440 * there was none
2441 */
2442 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2443 if (ins_index < 0) {
2444 rc = -EBUSY;
2445 goto out_unlock;
2446 }
2447 goto found;
2448 }
2449
2450 ++depth;
2451 }
2452
2453 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2454 spin_unlock_bh(&efx->filter_lock);
2455 schedule();
2456 }
2457
2458 found:
2459 /* Create a software table entry if necessary, and mark it
2460 * busy. We might yet fail to insert, but any attempt to
2461 * insert a conflicting filter while we're waiting for the
2462 * firmware must find the busy entry.
2463 */
2464 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2465 if (saved_spec) {
2466 if (spec->priority == EFX_FILTER_PRI_AUTO &&
2467 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
2468 /* Just make sure it won't be removed */
2469 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
2470 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
2471 table->entry[ins_index].spec &=
2472 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
2473 rc = ins_index;
2474 goto out_unlock;
2475 }
2476 replacing = true;
2477 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
2478 } else {
2479 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2480 if (!saved_spec) {
2481 rc = -ENOMEM;
2482 goto out_unlock;
2483 }
2484 *saved_spec = *spec;
2485 priv_flags = 0;
2486 }
2487 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2488 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
2489
2490 /* Mark lower-priority multicast recipients busy prior to removal */
2491 if (is_mc_recip) {
2492 unsigned int depth, i;
2493
2494 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2495 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2496 if (test_bit(depth, mc_rem_map))
2497 table->entry[i].spec |=
2498 EFX_EF10_FILTER_FLAG_BUSY;
2499 }
2500 }
2501
2502 spin_unlock_bh(&efx->filter_lock);
2503
2504 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
2505 replacing);
2506
2507 /* Finalise the software table entry */
2508 spin_lock_bh(&efx->filter_lock);
2509 if (rc == 0) {
2510 if (replacing) {
2511 /* Update the fields that may differ */
2512 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
2513 saved_spec->flags |=
2514 EFX_FILTER_FLAG_RX_OVER_AUTO;
2515 saved_spec->priority = spec->priority;
2516 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
2517 saved_spec->flags |= spec->flags;
2518 saved_spec->rss_context = spec->rss_context;
2519 saved_spec->dmaq_id = spec->dmaq_id;
2520 }
2521 } else if (!replacing) {
2522 kfree(saved_spec);
2523 saved_spec = NULL;
2524 }
2525 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
2526
2527 /* Remove and finalise entries for lower-priority multicast
2528 * recipients
2529 */
2530 if (is_mc_recip) {
2531 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2532 unsigned int depth, i;
2533
2534 memset(inbuf, 0, sizeof(inbuf));
2535
2536 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2537 if (!test_bit(depth, mc_rem_map))
2538 continue;
2539
2540 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2541 saved_spec = efx_ef10_filter_entry_spec(table, i);
2542 priv_flags = efx_ef10_filter_entry_flags(table, i);
2543
2544 if (rc == 0) {
2545 spin_unlock_bh(&efx->filter_lock);
2546 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2547 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2548 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2549 table->entry[i].handle);
2550 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2551 inbuf, sizeof(inbuf),
2552 NULL, 0, NULL);
2553 spin_lock_bh(&efx->filter_lock);
2554 }
2555
2556 if (rc == 0) {
2557 kfree(saved_spec);
2558 saved_spec = NULL;
2559 priv_flags = 0;
2560 } else {
2561 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
2562 }
2563 efx_ef10_filter_set_entry(table, i, saved_spec,
2564 priv_flags);
2565 }
2566 }
2567
2568 /* If successful, return the inserted filter ID */
2569 if (rc == 0)
2570 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
2571
2572 wake_up_all(&table->waitq);
2573 out_unlock:
2574 spin_unlock_bh(&efx->filter_lock);
2575 finish_wait(&table->waitq, &wait);
2576 return rc;
2577 }
2578
2579 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
2580 {
2581 /* no need to do anything here on EF10 */
2582 }
2583
2584 /* Remove a filter.
2585 * If !by_index, remove by ID
2586 * If by_index, remove by index
2587 * Filter ID may come from userland and must be range-checked.
2588 */
2589 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
2590 unsigned int priority_mask,
2591 u32 filter_id, bool by_index)
2592 {
2593 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2594 struct efx_ef10_filter_table *table = efx->filter_state;
2595 MCDI_DECLARE_BUF(inbuf,
2596 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2597 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2598 struct efx_filter_spec *spec;
2599 DEFINE_WAIT(wait);
2600 int rc;
2601
2602 /* Find the software table entry and mark it busy. Don't
2603 * remove it yet; any attempt to update while we're waiting
2604 * for the firmware must find the busy entry.
2605 */
2606 for (;;) {
2607 spin_lock_bh(&efx->filter_lock);
2608 if (!(table->entry[filter_idx].spec &
2609 EFX_EF10_FILTER_FLAG_BUSY))
2610 break;
2611 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2612 spin_unlock_bh(&efx->filter_lock);
2613 schedule();
2614 }
2615
2616 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2617 if (!spec ||
2618 (!by_index &&
2619 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
2620 filter_id / HUNT_FILTER_TBL_ROWS)) {
2621 rc = -ENOENT;
2622 goto out_unlock;
2623 }
2624
2625 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
2626 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
2627 /* Just remove flags */
2628 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
2629 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
2630 rc = 0;
2631 goto out_unlock;
2632 }
2633
2634 if (!(priority_mask & (1U << spec->priority))) {
2635 rc = -ENOENT;
2636 goto out_unlock;
2637 }
2638
2639 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2640 spin_unlock_bh(&efx->filter_lock);
2641
2642 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
2643 /* Reset to an automatic filter */
2644
2645 struct efx_filter_spec new_spec = *spec;
2646
2647 new_spec.priority = EFX_FILTER_PRI_AUTO;
2648 new_spec.flags = (EFX_FILTER_FLAG_RX |
2649 EFX_FILTER_FLAG_RX_RSS);
2650 new_spec.dmaq_id = 0;
2651 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
2652 rc = efx_ef10_filter_push(efx, &new_spec,
2653 &table->entry[filter_idx].handle,
2654 true);
2655
2656 spin_lock_bh(&efx->filter_lock);
2657 if (rc == 0)
2658 *spec = new_spec;
2659 } else {
2660 /* Really remove the filter */
2661
2662 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2663 efx_ef10_filter_is_exclusive(spec) ?
2664 MC_CMD_FILTER_OP_IN_OP_REMOVE :
2665 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2666 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2667 table->entry[filter_idx].handle);
2668 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2669 inbuf, sizeof(inbuf), NULL, 0, NULL);
2670
2671 spin_lock_bh(&efx->filter_lock);
2672 if (rc == 0) {
2673 kfree(spec);
2674 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2675 }
2676 }
2677
2678 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2679 wake_up_all(&table->waitq);
2680 out_unlock:
2681 spin_unlock_bh(&efx->filter_lock);
2682 finish_wait(&table->waitq, &wait);
2683 return rc;
2684 }
2685
2686 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
2687 enum efx_filter_priority priority,
2688 u32 filter_id)
2689 {
2690 return efx_ef10_filter_remove_internal(efx, 1U << priority,
2691 filter_id, false);
2692 }
2693
2694 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
2695 enum efx_filter_priority priority,
2696 u32 filter_id, struct efx_filter_spec *spec)
2697 {
2698 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2699 struct efx_ef10_filter_table *table = efx->filter_state;
2700 const struct efx_filter_spec *saved_spec;
2701 int rc;
2702
2703 spin_lock_bh(&efx->filter_lock);
2704 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
2705 if (saved_spec && saved_spec->priority == priority &&
2706 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
2707 filter_id / HUNT_FILTER_TBL_ROWS) {
2708 *spec = *saved_spec;
2709 rc = 0;
2710 } else {
2711 rc = -ENOENT;
2712 }
2713 spin_unlock_bh(&efx->filter_lock);
2714 return rc;
2715 }
2716
2717 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
2718 enum efx_filter_priority priority)
2719 {
2720 unsigned int priority_mask;
2721 unsigned int i;
2722 int rc;
2723
2724 priority_mask = (((1U << (priority + 1)) - 1) &
2725 ~(1U << EFX_FILTER_PRI_AUTO));
2726
2727 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
2728 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
2729 i, true);
2730 if (rc && rc != -ENOENT)
2731 return rc;
2732 }
2733
2734 return 0;
2735 }
2736
2737 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
2738 enum efx_filter_priority priority)
2739 {
2740 struct efx_ef10_filter_table *table = efx->filter_state;
2741 unsigned int filter_idx;
2742 s32 count = 0;
2743
2744 spin_lock_bh(&efx->filter_lock);
2745 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2746 if (table->entry[filter_idx].spec &&
2747 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
2748 priority)
2749 ++count;
2750 }
2751 spin_unlock_bh(&efx->filter_lock);
2752 return count;
2753 }
2754
2755 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
2756 {
2757 struct efx_ef10_filter_table *table = efx->filter_state;
2758
2759 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
2760 }
2761
2762 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
2763 enum efx_filter_priority priority,
2764 u32 *buf, u32 size)
2765 {
2766 struct efx_ef10_filter_table *table = efx->filter_state;
2767 struct efx_filter_spec *spec;
2768 unsigned int filter_idx;
2769 s32 count = 0;
2770
2771 spin_lock_bh(&efx->filter_lock);
2772 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2773 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2774 if (spec && spec->priority == priority) {
2775 if (count == size) {
2776 count = -EMSGSIZE;
2777 break;
2778 }
2779 buf[count++] = (efx_ef10_filter_rx_match_pri(
2780 table, spec->match_flags) *
2781 HUNT_FILTER_TBL_ROWS +
2782 filter_idx);
2783 }
2784 }
2785 spin_unlock_bh(&efx->filter_lock);
2786 return count;
2787 }
2788
2789 #ifdef CONFIG_RFS_ACCEL
2790
2791 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
2792
2793 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
2794 struct efx_filter_spec *spec)
2795 {
2796 struct efx_ef10_filter_table *table = efx->filter_state;
2797 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2798 struct efx_filter_spec *saved_spec;
2799 unsigned int hash, i, depth = 1;
2800 bool replacing = false;
2801 int ins_index = -1;
2802 u64 cookie;
2803 s32 rc;
2804
2805 /* Must be an RX filter without RSS and not for a multicast
2806 * destination address (RFS only works for connected sockets).
2807 * These restrictions allow us to pass only a tiny amount of
2808 * data through to the completion function.
2809 */
2810 EFX_WARN_ON_PARANOID(spec->flags !=
2811 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
2812 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
2813 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
2814
2815 hash = efx_ef10_filter_hash(spec);
2816
2817 spin_lock_bh(&efx->filter_lock);
2818
2819 /* Find any existing filter with the same match tuple or else
2820 * a free slot to insert at. If an existing filter is busy,
2821 * we have to give up.
2822 */
2823 for (;;) {
2824 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2825 saved_spec = efx_ef10_filter_entry_spec(table, i);
2826
2827 if (!saved_spec) {
2828 if (ins_index < 0)
2829 ins_index = i;
2830 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2831 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
2832 rc = -EBUSY;
2833 goto fail_unlock;
2834 }
2835 if (spec->priority < saved_spec->priority) {
2836 rc = -EPERM;
2837 goto fail_unlock;
2838 }
2839 ins_index = i;
2840 break;
2841 }
2842
2843 /* Once we reach the maximum search depth, use the
2844 * first suitable slot or return -EBUSY if there was
2845 * none
2846 */
2847 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2848 if (ins_index < 0) {
2849 rc = -EBUSY;
2850 goto fail_unlock;
2851 }
2852 break;
2853 }
2854
2855 ++depth;
2856 }
2857
2858 /* Create a software table entry if necessary, and mark it
2859 * busy. We might yet fail to insert, but any attempt to
2860 * insert a conflicting filter while we're waiting for the
2861 * firmware must find the busy entry.
2862 */
2863 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2864 if (saved_spec) {
2865 replacing = true;
2866 } else {
2867 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2868 if (!saved_spec) {
2869 rc = -ENOMEM;
2870 goto fail_unlock;
2871 }
2872 *saved_spec = *spec;
2873 }
2874 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2875 EFX_EF10_FILTER_FLAG_BUSY);
2876
2877 spin_unlock_bh(&efx->filter_lock);
2878
2879 /* Pack up the variables needed on completion */
2880 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
2881
2882 efx_ef10_filter_push_prep(efx, spec, inbuf,
2883 table->entry[ins_index].handle, replacing);
2884 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2885 MC_CMD_FILTER_OP_OUT_LEN,
2886 efx_ef10_filter_rfs_insert_complete, cookie);
2887
2888 return ins_index;
2889
2890 fail_unlock:
2891 spin_unlock_bh(&efx->filter_lock);
2892 return rc;
2893 }
2894
2895 static void
2896 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
2897 int rc, efx_dword_t *outbuf,
2898 size_t outlen_actual)
2899 {
2900 struct efx_ef10_filter_table *table = efx->filter_state;
2901 unsigned int ins_index, dmaq_id;
2902 struct efx_filter_spec *spec;
2903 bool replacing;
2904
2905 /* Unpack the cookie */
2906 replacing = cookie >> 31;
2907 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
2908 dmaq_id = cookie & 0xffff;
2909
2910 spin_lock_bh(&efx->filter_lock);
2911 spec = efx_ef10_filter_entry_spec(table, ins_index);
2912 if (rc == 0) {
2913 table->entry[ins_index].handle =
2914 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2915 if (replacing)
2916 spec->dmaq_id = dmaq_id;
2917 } else if (!replacing) {
2918 kfree(spec);
2919 spec = NULL;
2920 }
2921 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
2922 spin_unlock_bh(&efx->filter_lock);
2923
2924 wake_up_all(&table->waitq);
2925 }
2926
2927 static void
2928 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2929 unsigned long filter_idx,
2930 int rc, efx_dword_t *outbuf,
2931 size_t outlen_actual);
2932
2933 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2934 unsigned int filter_idx)
2935 {
2936 struct efx_ef10_filter_table *table = efx->filter_state;
2937 struct efx_filter_spec *spec =
2938 efx_ef10_filter_entry_spec(table, filter_idx);
2939 MCDI_DECLARE_BUF(inbuf,
2940 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2941 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2942
2943 if (!spec ||
2944 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
2945 spec->priority != EFX_FILTER_PRI_HINT ||
2946 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
2947 flow_id, filter_idx))
2948 return false;
2949
2950 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2951 MC_CMD_FILTER_OP_IN_OP_REMOVE);
2952 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2953 table->entry[filter_idx].handle);
2954 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
2955 efx_ef10_filter_rfs_expire_complete, filter_idx))
2956 return false;
2957
2958 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2959 return true;
2960 }
2961
2962 static void
2963 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2964 unsigned long filter_idx,
2965 int rc, efx_dword_t *outbuf,
2966 size_t outlen_actual)
2967 {
2968 struct efx_ef10_filter_table *table = efx->filter_state;
2969 struct efx_filter_spec *spec =
2970 efx_ef10_filter_entry_spec(table, filter_idx);
2971
2972 spin_lock_bh(&efx->filter_lock);
2973 if (rc == 0) {
2974 kfree(spec);
2975 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2976 }
2977 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2978 wake_up_all(&table->waitq);
2979 spin_unlock_bh(&efx->filter_lock);
2980 }
2981
2982 #endif /* CONFIG_RFS_ACCEL */
2983
2984 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
2985 {
2986 int match_flags = 0;
2987
2988 #define MAP_FLAG(gen_flag, mcdi_field) { \
2989 u32 old_mcdi_flags = mcdi_flags; \
2990 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2991 mcdi_field ## _LBN); \
2992 if (mcdi_flags != old_mcdi_flags) \
2993 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
2994 }
2995 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
2996 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
2997 MAP_FLAG(REM_HOST, SRC_IP);
2998 MAP_FLAG(LOC_HOST, DST_IP);
2999 MAP_FLAG(REM_MAC, SRC_MAC);
3000 MAP_FLAG(REM_PORT, SRC_PORT);
3001 MAP_FLAG(LOC_MAC, DST_MAC);
3002 MAP_FLAG(LOC_PORT, DST_PORT);
3003 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3004 MAP_FLAG(INNER_VID, INNER_VLAN);
3005 MAP_FLAG(OUTER_VID, OUTER_VLAN);
3006 MAP_FLAG(IP_PROTO, IP_PROTO);
3007 #undef MAP_FLAG
3008
3009 /* Did we map them all? */
3010 if (mcdi_flags)
3011 return -EINVAL;
3012
3013 return match_flags;
3014 }
3015
3016 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3017 {
3018 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3019 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3020 unsigned int pd_match_pri, pd_match_count;
3021 struct efx_ef10_filter_table *table;
3022 size_t outlen;
3023 int rc;
3024
3025 table = kzalloc(sizeof(*table), GFP_KERNEL);
3026 if (!table)
3027 return -ENOMEM;
3028
3029 /* Find out which RX filter types are supported, and their priorities */
3030 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3031 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3032 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3033 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3034 &outlen);
3035 if (rc)
3036 goto fail;
3037 pd_match_count = MCDI_VAR_ARRAY_LEN(
3038 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3039 table->rx_match_count = 0;
3040
3041 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3042 u32 mcdi_flags =
3043 MCDI_ARRAY_DWORD(
3044 outbuf,
3045 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3046 pd_match_pri);
3047 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3048 if (rc < 0) {
3049 netif_dbg(efx, probe, efx->net_dev,
3050 "%s: fw flags %#x pri %u not supported in driver\n",
3051 __func__, mcdi_flags, pd_match_pri);
3052 } else {
3053 netif_dbg(efx, probe, efx->net_dev,
3054 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3055 __func__, mcdi_flags, pd_match_pri,
3056 rc, table->rx_match_count);
3057 table->rx_match_flags[table->rx_match_count++] = rc;
3058 }
3059 }
3060
3061 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3062 if (!table->entry) {
3063 rc = -ENOMEM;
3064 goto fail;
3065 }
3066
3067 efx->filter_state = table;
3068 init_waitqueue_head(&table->waitq);
3069 return 0;
3070
3071 fail:
3072 kfree(table);
3073 return rc;
3074 }
3075
3076 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3077 {
3078 struct efx_ef10_filter_table *table = efx->filter_state;
3079 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3080 struct efx_filter_spec *spec;
3081 unsigned int filter_idx;
3082 bool failed = false;
3083 int rc;
3084
3085 if (!nic_data->must_restore_filters)
3086 return;
3087
3088 spin_lock_bh(&efx->filter_lock);
3089
3090 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3091 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3092 if (!spec)
3093 continue;
3094
3095 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3096 spin_unlock_bh(&efx->filter_lock);
3097
3098 rc = efx_ef10_filter_push(efx, spec,
3099 &table->entry[filter_idx].handle,
3100 false);
3101 if (rc)
3102 failed = true;
3103
3104 spin_lock_bh(&efx->filter_lock);
3105 if (rc) {
3106 kfree(spec);
3107 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3108 } else {
3109 table->entry[filter_idx].spec &=
3110 ~EFX_EF10_FILTER_FLAG_BUSY;
3111 }
3112 }
3113
3114 spin_unlock_bh(&efx->filter_lock);
3115
3116 if (failed)
3117 netif_err(efx, hw, efx->net_dev,
3118 "unable to restore all filters\n");
3119 else
3120 nic_data->must_restore_filters = false;
3121 }
3122
3123 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3124 {
3125 struct efx_ef10_filter_table *table = efx->filter_state;
3126 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3127 struct efx_filter_spec *spec;
3128 unsigned int filter_idx;
3129 int rc;
3130
3131 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3132 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3133 if (!spec)
3134 continue;
3135
3136 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3137 efx_ef10_filter_is_exclusive(spec) ?
3138 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3139 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3140 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3141 table->entry[filter_idx].handle);
3142 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3143 NULL, 0, NULL);
3144 if (rc)
3145 netdev_WARN(efx->net_dev,
3146 "filter_idx=%#x handle=%#llx\n",
3147 filter_idx,
3148 table->entry[filter_idx].handle);
3149 kfree(spec);
3150 }
3151
3152 vfree(table->entry);
3153 kfree(table);
3154 }
3155
3156 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
3157 {
3158 struct efx_ef10_filter_table *table = efx->filter_state;
3159 struct net_device *net_dev = efx->net_dev;
3160 struct efx_filter_spec spec;
3161 bool remove_failed = false;
3162 struct netdev_hw_addr *uc;
3163 struct netdev_hw_addr *mc;
3164 unsigned int filter_idx;
3165 int i, n, rc;
3166
3167 if (!efx_dev_registered(efx))
3168 return;
3169
3170 /* Mark old filters that may need to be removed */
3171 spin_lock_bh(&efx->filter_lock);
3172 n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count;
3173 for (i = 0; i < n; i++) {
3174 filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
3175 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3176 }
3177 n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count;
3178 for (i = 0; i < n; i++) {
3179 filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
3180 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3181 }
3182 spin_unlock_bh(&efx->filter_lock);
3183
3184 /* Copy/convert the address lists; add the primary station
3185 * address and broadcast address
3186 */
3187 netif_addr_lock_bh(net_dev);
3188 if (net_dev->flags & IFF_PROMISC ||
3189 netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) {
3190 table->dev_uc_count = -1;
3191 } else {
3192 table->dev_uc_count = 1 + netdev_uc_count(net_dev);
3193 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3194 i = 1;
3195 netdev_for_each_uc_addr(uc, net_dev) {
3196 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
3197 i++;
3198 }
3199 }
3200 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
3201 netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) {
3202 table->dev_mc_count = -1;
3203 } else {
3204 table->dev_mc_count = 1 + netdev_mc_count(net_dev);
3205 eth_broadcast_addr(table->dev_mc_list[0].addr);
3206 i = 1;
3207 netdev_for_each_mc_addr(mc, net_dev) {
3208 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
3209 i++;
3210 }
3211 }
3212 netif_addr_unlock_bh(net_dev);
3213
3214 /* Insert/renew unicast filters */
3215 if (table->dev_uc_count >= 0) {
3216 for (i = 0; i < table->dev_uc_count; i++) {
3217 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3218 EFX_FILTER_FLAG_RX_RSS,
3219 0);
3220 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3221 table->dev_uc_list[i].addr);
3222 rc = efx_ef10_filter_insert(efx, &spec, true);
3223 if (rc < 0) {
3224 /* Fall back to unicast-promisc */
3225 while (i--)
3226 efx_ef10_filter_remove_safe(
3227 efx, EFX_FILTER_PRI_AUTO,
3228 table->dev_uc_list[i].id);
3229 table->dev_uc_count = -1;
3230 break;
3231 }
3232 table->dev_uc_list[i].id = rc;
3233 }
3234 }
3235 if (table->dev_uc_count < 0) {
3236 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3237 EFX_FILTER_FLAG_RX_RSS,
3238 0);
3239 efx_filter_set_uc_def(&spec);
3240 rc = efx_ef10_filter_insert(efx, &spec, true);
3241 if (rc < 0) {
3242 WARN_ON(1);
3243 table->dev_uc_count = 0;
3244 } else {
3245 table->dev_uc_list[0].id = rc;
3246 }
3247 }
3248
3249 /* Insert/renew multicast filters */
3250 if (table->dev_mc_count >= 0) {
3251 for (i = 0; i < table->dev_mc_count; i++) {
3252 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3253 EFX_FILTER_FLAG_RX_RSS,
3254 0);
3255 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3256 table->dev_mc_list[i].addr);
3257 rc = efx_ef10_filter_insert(efx, &spec, true);
3258 if (rc < 0) {
3259 /* Fall back to multicast-promisc */
3260 while (i--)
3261 efx_ef10_filter_remove_safe(
3262 efx, EFX_FILTER_PRI_AUTO,
3263 table->dev_mc_list[i].id);
3264 table->dev_mc_count = -1;
3265 break;
3266 }
3267 table->dev_mc_list[i].id = rc;
3268 }
3269 }
3270 if (table->dev_mc_count < 0) {
3271 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3272 EFX_FILTER_FLAG_RX_RSS,
3273 0);
3274 efx_filter_set_mc_def(&spec);
3275 rc = efx_ef10_filter_insert(efx, &spec, true);
3276 if (rc < 0) {
3277 WARN_ON(1);
3278 table->dev_mc_count = 0;
3279 } else {
3280 table->dev_mc_list[0].id = rc;
3281 }
3282 }
3283
3284 /* Remove filters that weren't renewed. Since nothing else
3285 * changes the AUTO_OLD flag or removes these filters, we
3286 * don't need to hold the filter_lock while scanning for
3287 * these filters.
3288 */
3289 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3290 if (ACCESS_ONCE(table->entry[i].spec) &
3291 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
3292 if (efx_ef10_filter_remove_internal(
3293 efx, 1U << EFX_FILTER_PRI_AUTO,
3294 i, true) < 0)
3295 remove_failed = true;
3296 }
3297 }
3298 WARN_ON(remove_failed);
3299 }
3300
3301 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
3302 {
3303 efx_ef10_filter_sync_rx_mode(efx);
3304
3305 return efx_mcdi_set_mac(efx);
3306 }
3307
3308 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
3309 {
3310 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
3311
3312 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
3313 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
3314 NULL, 0, NULL);
3315 }
3316
3317 /* MC BISTs follow a different poll mechanism to phy BISTs.
3318 * The BIST is done in the poll handler on the MC, and the MCDI command
3319 * will block until the BIST is done.
3320 */
3321 static int efx_ef10_poll_bist(struct efx_nic *efx)
3322 {
3323 int rc;
3324 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
3325 size_t outlen;
3326 u32 result;
3327
3328 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
3329 outbuf, sizeof(outbuf), &outlen);
3330 if (rc != 0)
3331 return rc;
3332
3333 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
3334 return -EIO;
3335
3336 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
3337 switch (result) {
3338 case MC_CMD_POLL_BIST_PASSED:
3339 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
3340 return 0;
3341 case MC_CMD_POLL_BIST_TIMEOUT:
3342 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
3343 return -EIO;
3344 case MC_CMD_POLL_BIST_FAILED:
3345 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
3346 return -EIO;
3347 default:
3348 netif_err(efx, hw, efx->net_dev,
3349 "BIST returned unknown result %u", result);
3350 return -EIO;
3351 }
3352 }
3353
3354 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
3355 {
3356 int rc;
3357
3358 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
3359
3360 rc = efx_ef10_start_bist(efx, bist_type);
3361 if (rc != 0)
3362 return rc;
3363
3364 return efx_ef10_poll_bist(efx);
3365 }
3366
3367 static int
3368 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
3369 {
3370 int rc, rc2;
3371
3372 efx_reset_down(efx, RESET_TYPE_WORLD);
3373
3374 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
3375 NULL, 0, NULL, 0, NULL);
3376 if (rc != 0)
3377 goto out;
3378
3379 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
3380 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
3381
3382 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
3383
3384 out:
3385 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
3386 return rc ? rc : rc2;
3387 }
3388
3389 #ifdef CONFIG_SFC_MTD
3390
3391 struct efx_ef10_nvram_type_info {
3392 u16 type, type_mask;
3393 u8 port;
3394 const char *name;
3395 };
3396
3397 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
3398 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
3399 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
3400 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
3401 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
3402 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
3403 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
3404 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
3405 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
3406 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
3407 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
3408 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
3409 };
3410
3411 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
3412 struct efx_mcdi_mtd_partition *part,
3413 unsigned int type)
3414 {
3415 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
3416 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
3417 const struct efx_ef10_nvram_type_info *info;
3418 size_t size, erase_size, outlen;
3419 bool protected;
3420 int rc;
3421
3422 for (info = efx_ef10_nvram_types; ; info++) {
3423 if (info ==
3424 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
3425 return -ENODEV;
3426 if ((type & ~info->type_mask) == info->type)
3427 break;
3428 }
3429 if (info->port != efx_port_num(efx))
3430 return -ENODEV;
3431
3432 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
3433 if (rc)
3434 return rc;
3435 if (protected)
3436 return -ENODEV; /* hide it */
3437
3438 part->nvram_type = type;
3439
3440 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
3441 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
3442 outbuf, sizeof(outbuf), &outlen);
3443 if (rc)
3444 return rc;
3445 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
3446 return -EIO;
3447 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
3448 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
3449 part->fw_subtype = MCDI_DWORD(outbuf,
3450 NVRAM_METADATA_OUT_SUBTYPE);
3451
3452 part->common.dev_type_name = "EF10 NVRAM manager";
3453 part->common.type_name = info->name;
3454
3455 part->common.mtd.type = MTD_NORFLASH;
3456 part->common.mtd.flags = MTD_CAP_NORFLASH;
3457 part->common.mtd.size = size;
3458 part->common.mtd.erasesize = erase_size;
3459
3460 return 0;
3461 }
3462
3463 static int efx_ef10_mtd_probe(struct efx_nic *efx)
3464 {
3465 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
3466 struct efx_mcdi_mtd_partition *parts;
3467 size_t outlen, n_parts_total, i, n_parts;
3468 unsigned int type;
3469 int rc;
3470
3471 ASSERT_RTNL();
3472
3473 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
3474 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
3475 outbuf, sizeof(outbuf), &outlen);
3476 if (rc)
3477 return rc;
3478 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
3479 return -EIO;
3480
3481 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
3482 if (n_parts_total >
3483 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
3484 return -EIO;
3485
3486 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
3487 if (!parts)
3488 return -ENOMEM;
3489
3490 n_parts = 0;
3491 for (i = 0; i < n_parts_total; i++) {
3492 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
3493 i);
3494 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
3495 if (rc == 0)
3496 n_parts++;
3497 else if (rc != -ENODEV)
3498 goto fail;
3499 }
3500
3501 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3502 fail:
3503 if (rc)
3504 kfree(parts);
3505 return rc;
3506 }
3507
3508 #endif /* CONFIG_SFC_MTD */
3509
3510 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3511 {
3512 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3513 }
3514
3515 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
3516 bool temp)
3517 {
3518 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
3519 int rc;
3520
3521 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
3522 channel->sync_events_state == SYNC_EVENTS_VALID ||
3523 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
3524 return 0;
3525 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
3526
3527 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
3528 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3529 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
3530 channel->channel);
3531
3532 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3533 inbuf, sizeof(inbuf), NULL, 0, NULL);
3534
3535 if (rc != 0)
3536 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3537 SYNC_EVENTS_DISABLED;
3538
3539 return rc;
3540 }
3541
3542 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
3543 bool temp)
3544 {
3545 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
3546 int rc;
3547
3548 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
3549 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
3550 return 0;
3551 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
3552 channel->sync_events_state = SYNC_EVENTS_DISABLED;
3553 return 0;
3554 }
3555 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3556 SYNC_EVENTS_DISABLED;
3557
3558 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
3559 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3560 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
3561 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
3562 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
3563 channel->channel);
3564
3565 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3566 inbuf, sizeof(inbuf), NULL, 0, NULL);
3567
3568 return rc;
3569 }
3570
3571 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
3572 bool temp)
3573 {
3574 int (*set)(struct efx_channel *channel, bool temp);
3575 struct efx_channel *channel;
3576
3577 set = en ?
3578 efx_ef10_rx_enable_timestamping :
3579 efx_ef10_rx_disable_timestamping;
3580
3581 efx_for_each_channel(channel, efx) {
3582 int rc = set(channel, temp);
3583 if (en && rc != 0) {
3584 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
3585 return rc;
3586 }
3587 }
3588
3589 return 0;
3590 }
3591
3592 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
3593 struct hwtstamp_config *init)
3594 {
3595 int rc;
3596
3597 switch (init->rx_filter) {
3598 case HWTSTAMP_FILTER_NONE:
3599 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
3600 /* if TX timestamping is still requested then leave PTP on */
3601 return efx_ptp_change_mode(efx,
3602 init->tx_type != HWTSTAMP_TX_OFF, 0);
3603 case HWTSTAMP_FILTER_ALL:
3604 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3605 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3606 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3607 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3608 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3609 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3610 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3611 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3612 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3613 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3614 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3615 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3616 init->rx_filter = HWTSTAMP_FILTER_ALL;
3617 rc = efx_ptp_change_mode(efx, true, 0);
3618 if (!rc)
3619 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
3620 if (rc)
3621 efx_ptp_change_mode(efx, false, 0);
3622 return rc;
3623 default:
3624 return -ERANGE;
3625 }
3626 }
3627
3628 const struct efx_nic_type efx_hunt_a0_nic_type = {
3629 .mem_map_size = efx_ef10_mem_map_size,
3630 .probe = efx_ef10_probe,
3631 .remove = efx_ef10_remove,
3632 .dimension_resources = efx_ef10_dimension_resources,
3633 .init = efx_ef10_init_nic,
3634 .fini = efx_port_dummy_op_void,
3635 .map_reset_reason = efx_mcdi_map_reset_reason,
3636 .map_reset_flags = efx_ef10_map_reset_flags,
3637 .reset = efx_ef10_reset,
3638 .probe_port = efx_mcdi_port_probe,
3639 .remove_port = efx_mcdi_port_remove,
3640 .fini_dmaq = efx_ef10_fini_dmaq,
3641 .prepare_flr = efx_ef10_prepare_flr,
3642 .finish_flr = efx_port_dummy_op_void,
3643 .describe_stats = efx_ef10_describe_stats,
3644 .update_stats = efx_ef10_update_stats,
3645 .start_stats = efx_mcdi_mac_start_stats,
3646 .pull_stats = efx_mcdi_mac_pull_stats,
3647 .stop_stats = efx_mcdi_mac_stop_stats,
3648 .set_id_led = efx_mcdi_set_id_led,
3649 .push_irq_moderation = efx_ef10_push_irq_moderation,
3650 .reconfigure_mac = efx_ef10_mac_reconfigure,
3651 .check_mac_fault = efx_mcdi_mac_check_fault,
3652 .reconfigure_port = efx_mcdi_port_reconfigure,
3653 .get_wol = efx_ef10_get_wol,
3654 .set_wol = efx_ef10_set_wol,
3655 .resume_wol = efx_port_dummy_op_void,
3656 .test_chip = efx_ef10_test_chip,
3657 .test_nvram = efx_mcdi_nvram_test_all,
3658 .mcdi_request = efx_ef10_mcdi_request,
3659 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
3660 .mcdi_read_response = efx_ef10_mcdi_read_response,
3661 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
3662 .irq_enable_master = efx_port_dummy_op_void,
3663 .irq_test_generate = efx_ef10_irq_test_generate,
3664 .irq_disable_non_ev = efx_port_dummy_op_void,
3665 .irq_handle_msi = efx_ef10_msi_interrupt,
3666 .irq_handle_legacy = efx_ef10_legacy_interrupt,
3667 .tx_probe = efx_ef10_tx_probe,
3668 .tx_init = efx_ef10_tx_init,
3669 .tx_remove = efx_ef10_tx_remove,
3670 .tx_write = efx_ef10_tx_write,
3671 .rx_push_rss_config = efx_ef10_rx_push_rss_config,
3672 .rx_probe = efx_ef10_rx_probe,
3673 .rx_init = efx_ef10_rx_init,
3674 .rx_remove = efx_ef10_rx_remove,
3675 .rx_write = efx_ef10_rx_write,
3676 .rx_defer_refill = efx_ef10_rx_defer_refill,
3677 .ev_probe = efx_ef10_ev_probe,
3678 .ev_init = efx_ef10_ev_init,
3679 .ev_fini = efx_ef10_ev_fini,
3680 .ev_remove = efx_ef10_ev_remove,
3681 .ev_process = efx_ef10_ev_process,
3682 .ev_read_ack = efx_ef10_ev_read_ack,
3683 .ev_test_generate = efx_ef10_ev_test_generate,
3684 .filter_table_probe = efx_ef10_filter_table_probe,
3685 .filter_table_restore = efx_ef10_filter_table_restore,
3686 .filter_table_remove = efx_ef10_filter_table_remove,
3687 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
3688 .filter_insert = efx_ef10_filter_insert,
3689 .filter_remove_safe = efx_ef10_filter_remove_safe,
3690 .filter_get_safe = efx_ef10_filter_get_safe,
3691 .filter_clear_rx = efx_ef10_filter_clear_rx,
3692 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
3693 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
3694 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
3695 #ifdef CONFIG_RFS_ACCEL
3696 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
3697 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
3698 #endif
3699 #ifdef CONFIG_SFC_MTD
3700 .mtd_probe = efx_ef10_mtd_probe,
3701 .mtd_rename = efx_mcdi_mtd_rename,
3702 .mtd_read = efx_mcdi_mtd_read,
3703 .mtd_erase = efx_mcdi_mtd_erase,
3704 .mtd_write = efx_mcdi_mtd_write,
3705 .mtd_sync = efx_mcdi_mtd_sync,
3706 #endif
3707 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
3708 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
3709 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
3710
3711 .revision = EFX_REV_HUNT_A0,
3712 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
3713 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
3714 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
3715 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
3716 .can_rx_scatter = true,
3717 .always_rx_scatter = true,
3718 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3719 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
3720 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3721 NETIF_F_RXHASH | NETIF_F_NTUPLE),
3722 .mcdi_max_ver = 2,
3723 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
3724 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
3725 1 << HWTSTAMP_FILTER_ALL,
3726 };
Linux with added FPC-III support