?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 3.18.86
[linux/fpc-iii.git] / drivers / net / ethernet / sfc / farch.c
blobb70b865fd19bf694858f511eef2d83d398c4a89a
1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/seq_file.h>
17 #include <linux/crc32.h>
18 #include "net_driver.h"
19 #include "bitfield.h"
20 #include "efx.h"
21 #include "nic.h"
22 #include "farch_regs.h"
23 #include "io.h"
24 #include "workarounds.h"
25
26 /* Falcon-architecture (SFC4000 and SFC9000-family) support */
27
28 /**************************************************************************
29 *
30 * Configurable values
31 *
32 **************************************************************************
33 */
34
35 /* This is set to 16 for a good reason. In summary, if larger than
36 * 16, the descriptor cache holds more than a default socket
37 * buffer's worth of packets (for UDP we can only have at most one
38 * socket buffer's worth outstanding). This combined with the fact
39 * that we only get 1 TX event per descriptor cache means the NIC
40 * goes idle.
41 */
42 #define TX_DC_ENTRIES 16
43 #define TX_DC_ENTRIES_ORDER 1
44
45 #define RX_DC_ENTRIES 64
46 #define RX_DC_ENTRIES_ORDER 3
47
48 /* If EFX_MAX_INT_ERRORS internal errors occur within
49 * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
50 * disable it.
51 */
52 #define EFX_INT_ERROR_EXPIRE 3600
53 #define EFX_MAX_INT_ERRORS 5
54
55 /* Depth of RX flush request fifo */
56 #define EFX_RX_FLUSH_COUNT 4
57
58 /* Driver generated events */
59 #define _EFX_CHANNEL_MAGIC_TEST 0x000101
60 #define _EFX_CHANNEL_MAGIC_FILL 0x000102
61 #define _EFX_CHANNEL_MAGIC_RX_DRAIN 0x000103
62 #define _EFX_CHANNEL_MAGIC_TX_DRAIN 0x000104
63
64 #define _EFX_CHANNEL_MAGIC(_code, _data) ((_code) << 8 | (_data))
65 #define _EFX_CHANNEL_MAGIC_CODE(_magic) ((_magic) >> 8)
66
67 #define EFX_CHANNEL_MAGIC_TEST(_channel) \
68 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TEST, (_channel)->channel)
69 #define EFX_CHANNEL_MAGIC_FILL(_rx_queue) \
70 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_FILL, \
71 efx_rx_queue_index(_rx_queue))
72 #define EFX_CHANNEL_MAGIC_RX_DRAIN(_rx_queue) \
73 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_RX_DRAIN, \
74 efx_rx_queue_index(_rx_queue))
75 #define EFX_CHANNEL_MAGIC_TX_DRAIN(_tx_queue) \
76 _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TX_DRAIN, \
77 (_tx_queue)->queue)
78
79 static void efx_farch_magic_event(struct efx_channel *channel, u32 magic);
80
81 /**************************************************************************
82 *
83 * Hardware access
84 *
85 **************************************************************************/
86
87 static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
88 unsigned int index)
89 {
90 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
91 value, index);
92 }
93
94 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
95 const efx_oword_t *mask)
96 {
97 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
98 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
99 }
100
101 int efx_farch_test_registers(struct efx_nic *efx,
102 const struct efx_farch_register_test *regs,
103 size_t n_regs)
104 {
105 unsigned address = 0, i, j;
106 efx_oword_t mask, imask, original, reg, buf;
107
108 for (i = 0; i < n_regs; ++i) {
109 address = regs[i].address;
110 mask = imask = regs[i].mask;
111 EFX_INVERT_OWORD(imask);
112
113 efx_reado(efx, &original, address);
114
115 /* bit sweep on and off */
116 for (j = 0; j < 128; j++) {
117 if (!EFX_EXTRACT_OWORD32(mask, j, j))
118 continue;
119
120 /* Test this testable bit can be set in isolation */
121 EFX_AND_OWORD(reg, original, mask);
122 EFX_SET_OWORD32(reg, j, j, 1);
123
124 efx_writeo(efx, &reg, address);
125 efx_reado(efx, &buf, address);
126
127 if (efx_masked_compare_oword(&reg, &buf, &mask))
128 goto fail;
129
130 /* Test this testable bit can be cleared in isolation */
131 EFX_OR_OWORD(reg, original, mask);
132 EFX_SET_OWORD32(reg, j, j, 0);
133
134 efx_writeo(efx, &reg, address);
135 efx_reado(efx, &buf, address);
136
137 if (efx_masked_compare_oword(&reg, &buf, &mask))
138 goto fail;
139 }
140
141 efx_writeo(efx, &original, address);
142 }
143
144 return 0;
145
146 fail:
147 netif_err(efx, hw, efx->net_dev,
148 "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
149 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
150 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
151 return -EIO;
152 }
153
154 /**************************************************************************
155 *
156 * Special buffer handling
157 * Special buffers are used for event queues and the TX and RX
158 * descriptor rings.
159 *
160 *************************************************************************/
161
162 /*
163 * Initialise a special buffer
164 *
165 * This will define a buffer (previously allocated via
166 * efx_alloc_special_buffer()) in the buffer table, allowing
167 * it to be used for event queues, descriptor rings etc.
168 */
169 static void
170 efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
171 {
172 efx_qword_t buf_desc;
173 unsigned int index;
174 dma_addr_t dma_addr;
175 int i;
176
177 EFX_BUG_ON_PARANOID(!buffer->buf.addr);
178
179 /* Write buffer descriptors to NIC */
180 for (i = 0; i < buffer->entries; i++) {
181 index = buffer->index + i;
182 dma_addr = buffer->buf.dma_addr + (i * EFX_BUF_SIZE);
183 netif_dbg(efx, probe, efx->net_dev,
184 "mapping special buffer %d at %llx\n",
185 index, (unsigned long long)dma_addr);
186 EFX_POPULATE_QWORD_3(buf_desc,
187 FRF_AZ_BUF_ADR_REGION, 0,
188 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
189 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
190 efx_write_buf_tbl(efx, &buf_desc, index);
191 }
192 }
193
194 /* Unmaps a buffer and clears the buffer table entries */
195 static void
196 efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
197 {
198 efx_oword_t buf_tbl_upd;
199 unsigned int start = buffer->index;
200 unsigned int end = (buffer->index + buffer->entries - 1);
201
202 if (!buffer->entries)
203 return;
204
205 netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n",
206 buffer->index, buffer->index + buffer->entries - 1);
207
208 EFX_POPULATE_OWORD_4(buf_tbl_upd,
209 FRF_AZ_BUF_UPD_CMD, 0,
210 FRF_AZ_BUF_CLR_CMD, 1,
211 FRF_AZ_BUF_CLR_END_ID, end,
212 FRF_AZ_BUF_CLR_START_ID, start);
213 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
214 }
215
216 /*
217 * Allocate a new special buffer
218 *
219 * This allocates memory for a new buffer, clears it and allocates a
220 * new buffer ID range. It does not write into the buffer table.
221 *
222 * This call will allocate 4KB buffers, since 8KB buffers can't be
223 * used for event queues and descriptor rings.
224 */
225 static int efx_alloc_special_buffer(struct efx_nic *efx,
226 struct efx_special_buffer *buffer,
227 unsigned int len)
228 {
229 len = ALIGN(len, EFX_BUF_SIZE);
230
231 if (efx_nic_alloc_buffer(efx, &buffer->buf, len, GFP_KERNEL))
232 return -ENOMEM;
233 buffer->entries = len / EFX_BUF_SIZE;
234 BUG_ON(buffer->buf.dma_addr & (EFX_BUF_SIZE - 1));
235
236 /* Select new buffer ID */
237 buffer->index = efx->next_buffer_table;
238 efx->next_buffer_table += buffer->entries;
239 #ifdef CONFIG_SFC_SRIOV
240 BUG_ON(efx_sriov_enabled(efx) &&
241 efx->vf_buftbl_base < efx->next_buffer_table);
242 #endif
243
244 netif_dbg(efx, probe, efx->net_dev,
245 "allocating special buffers %d-%d at %llx+%x "
246 "(virt %p phys %llx)\n", buffer->index,
247 buffer->index + buffer->entries - 1,
248 (u64)buffer->buf.dma_addr, len,
249 buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr));
250
251 return 0;
252 }
253
254 static void
255 efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
256 {
257 if (!buffer->buf.addr)
258 return;
259
260 netif_dbg(efx, hw, efx->net_dev,
261 "deallocating special buffers %d-%d at %llx+%x "
262 "(virt %p phys %llx)\n", buffer->index,
263 buffer->index + buffer->entries - 1,
264 (u64)buffer->buf.dma_addr, buffer->buf.len,
265 buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr));
266
267 efx_nic_free_buffer(efx, &buffer->buf);
268 buffer->entries = 0;
269 }
270
271 /**************************************************************************
272 *
273 * TX path
274 *
275 **************************************************************************/
276
277 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
278 static inline void efx_farch_notify_tx_desc(struct efx_tx_queue *tx_queue)
279 {
280 unsigned write_ptr;
281 efx_dword_t reg;
282
283 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
284 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
285 efx_writed_page(tx_queue->efx, &reg,
286 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
287 }
288
289 /* Write pointer and first descriptor for TX descriptor ring */
290 static inline void efx_farch_push_tx_desc(struct efx_tx_queue *tx_queue,
291 const efx_qword_t *txd)
292 {
293 unsigned write_ptr;
294 efx_oword_t reg;
295
296 BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0);
297 BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0);
298
299 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
300 EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true,
301 FRF_AZ_TX_DESC_WPTR, write_ptr);
302 reg.qword[0] = *txd;
303 efx_writeo_page(tx_queue->efx, &reg,
304 FR_BZ_TX_DESC_UPD_P0, tx_queue->queue);
305 }
306
307
308 /* For each entry inserted into the software descriptor ring, create a
309 * descriptor in the hardware TX descriptor ring (in host memory), and
310 * write a doorbell.
311 */
312 void efx_farch_tx_write(struct efx_tx_queue *tx_queue)
313 {
314 struct efx_tx_buffer *buffer;
315 efx_qword_t *txd;
316 unsigned write_ptr;
317 unsigned old_write_count = tx_queue->write_count;
318
319 tx_queue->xmit_more_available = false;
320 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
321 return;
322
323 do {
324 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
325 buffer = &tx_queue->buffer[write_ptr];
326 txd = efx_tx_desc(tx_queue, write_ptr);
327 ++tx_queue->write_count;
328
329 EFX_BUG_ON_PARANOID(buffer->flags & EFX_TX_BUF_OPTION);
330
331 /* Create TX descriptor ring entry */
332 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
333 EFX_POPULATE_QWORD_4(*txd,
334 FSF_AZ_TX_KER_CONT,
335 buffer->flags & EFX_TX_BUF_CONT,
336 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
337 FSF_AZ_TX_KER_BUF_REGION, 0,
338 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
339 } while (tx_queue->write_count != tx_queue->insert_count);
340
341 wmb(); /* Ensure descriptors are written before they are fetched */
342
343 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
344 txd = efx_tx_desc(tx_queue,
345 old_write_count & tx_queue->ptr_mask);
346 efx_farch_push_tx_desc(tx_queue, txd);
347 ++tx_queue->pushes;
348 } else {
349 efx_farch_notify_tx_desc(tx_queue);
350 }
351 }
352
353 /* Allocate hardware resources for a TX queue */
354 int efx_farch_tx_probe(struct efx_tx_queue *tx_queue)
355 {
356 struct efx_nic *efx = tx_queue->efx;
357 unsigned entries;
358
359 entries = tx_queue->ptr_mask + 1;
360 return efx_alloc_special_buffer(efx, &tx_queue->txd,
361 entries * sizeof(efx_qword_t));
362 }
363
364 void efx_farch_tx_init(struct efx_tx_queue *tx_queue)
365 {
366 struct efx_nic *efx = tx_queue->efx;
367 efx_oword_t reg;
368
369 /* Pin TX descriptor ring */
370 efx_init_special_buffer(efx, &tx_queue->txd);
371
372 /* Push TX descriptor ring to card */
373 EFX_POPULATE_OWORD_10(reg,
374 FRF_AZ_TX_DESCQ_EN, 1,
375 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
376 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
377 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
378 FRF_AZ_TX_DESCQ_EVQ_ID,
379 tx_queue->channel->channel,
380 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
381 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
382 FRF_AZ_TX_DESCQ_SIZE,
383 __ffs(tx_queue->txd.entries),
384 FRF_AZ_TX_DESCQ_TYPE, 0,
385 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
386
387 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
388 int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
389 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
390 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS,
391 !csum);
392 }
393
394 efx_writeo_table(efx, &reg, efx->type->txd_ptr_tbl_base,
395 tx_queue->queue);
396
397 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
398 /* Only 128 bits in this register */
399 BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128);
400
401 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
402 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
403 __clear_bit_le(tx_queue->queue, &reg);
404 else
405 __set_bit_le(tx_queue->queue, &reg);
406 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
407 }
408
409 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
410 EFX_POPULATE_OWORD_1(reg,
411 FRF_BZ_TX_PACE,
412 (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
413 FFE_BZ_TX_PACE_OFF :
414 FFE_BZ_TX_PACE_RESERVED);
415 efx_writeo_table(efx, &reg, FR_BZ_TX_PACE_TBL,
416 tx_queue->queue);
417 }
418 }
419
420 static void efx_farch_flush_tx_queue(struct efx_tx_queue *tx_queue)
421 {
422 struct efx_nic *efx = tx_queue->efx;
423 efx_oword_t tx_flush_descq;
424
425 WARN_ON(atomic_read(&tx_queue->flush_outstanding));
426 atomic_set(&tx_queue->flush_outstanding, 1);
427
428 EFX_POPULATE_OWORD_2(tx_flush_descq,
429 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
430 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
431 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
432 }
433
434 void efx_farch_tx_fini(struct efx_tx_queue *tx_queue)
435 {
436 struct efx_nic *efx = tx_queue->efx;
437 efx_oword_t tx_desc_ptr;
438
439 /* Remove TX descriptor ring from card */
440 EFX_ZERO_OWORD(tx_desc_ptr);
441 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
442 tx_queue->queue);
443
444 /* Unpin TX descriptor ring */
445 efx_fini_special_buffer(efx, &tx_queue->txd);
446 }
447
448 /* Free buffers backing TX queue */
449 void efx_farch_tx_remove(struct efx_tx_queue *tx_queue)
450 {
451 efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
452 }
453
454 /**************************************************************************
455 *
456 * RX path
457 *
458 **************************************************************************/
459
460 /* This creates an entry in the RX descriptor queue */
461 static inline void
462 efx_farch_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
463 {
464 struct efx_rx_buffer *rx_buf;
465 efx_qword_t *rxd;
466
467 rxd = efx_rx_desc(rx_queue, index);
468 rx_buf = efx_rx_buffer(rx_queue, index);
469 EFX_POPULATE_QWORD_3(*rxd,
470 FSF_AZ_RX_KER_BUF_SIZE,
471 rx_buf->len -
472 rx_queue->efx->type->rx_buffer_padding,
473 FSF_AZ_RX_KER_BUF_REGION, 0,
474 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
475 }
476
477 /* This writes to the RX_DESC_WPTR register for the specified receive
478 * descriptor ring.
479 */
480 void efx_farch_rx_write(struct efx_rx_queue *rx_queue)
481 {
482 struct efx_nic *efx = rx_queue->efx;
483 efx_dword_t reg;
484 unsigned write_ptr;
485
486 while (rx_queue->notified_count != rx_queue->added_count) {
487 efx_farch_build_rx_desc(
488 rx_queue,
489 rx_queue->notified_count & rx_queue->ptr_mask);
490 ++rx_queue->notified_count;
491 }
492
493 wmb();
494 write_ptr = rx_queue->added_count & rx_queue->ptr_mask;
495 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
496 efx_writed_page(efx, &reg, FR_AZ_RX_DESC_UPD_DWORD_P0,
497 efx_rx_queue_index(rx_queue));
498 }
499
500 int efx_farch_rx_probe(struct efx_rx_queue *rx_queue)
501 {
502 struct efx_nic *efx = rx_queue->efx;
503 unsigned entries;
504
505 entries = rx_queue->ptr_mask + 1;
506 return efx_alloc_special_buffer(efx, &rx_queue->rxd,
507 entries * sizeof(efx_qword_t));
508 }
509
510 void efx_farch_rx_init(struct efx_rx_queue *rx_queue)
511 {
512 efx_oword_t rx_desc_ptr;
513 struct efx_nic *efx = rx_queue->efx;
514 bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
515 bool iscsi_digest_en = is_b0;
516 bool jumbo_en;
517
518 /* For kernel-mode queues in Falcon A1, the JUMBO flag enables
519 * DMA to continue after a PCIe page boundary (and scattering
520 * is not possible). In Falcon B0 and Siena, it enables
521 * scatter.
522 */
523 jumbo_en = !is_b0 || efx->rx_scatter;
524
525 netif_dbg(efx, hw, efx->net_dev,
526 "RX queue %d ring in special buffers %d-%d\n",
527 efx_rx_queue_index(rx_queue), rx_queue->rxd.index,
528 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
529
530 rx_queue->scatter_n = 0;
531
532 /* Pin RX descriptor ring */
533 efx_init_special_buffer(efx, &rx_queue->rxd);
534
535 /* Push RX descriptor ring to card */
536 EFX_POPULATE_OWORD_10(rx_desc_ptr,
537 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
538 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
539 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
540 FRF_AZ_RX_DESCQ_EVQ_ID,
541 efx_rx_queue_channel(rx_queue)->channel,
542 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
543 FRF_AZ_RX_DESCQ_LABEL,
544 efx_rx_queue_index(rx_queue),
545 FRF_AZ_RX_DESCQ_SIZE,
546 __ffs(rx_queue->rxd.entries),
547 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
548 FRF_AZ_RX_DESCQ_JUMBO, jumbo_en,
549 FRF_AZ_RX_DESCQ_EN, 1);
550 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
551 efx_rx_queue_index(rx_queue));
552 }
553
554 static void efx_farch_flush_rx_queue(struct efx_rx_queue *rx_queue)
555 {
556 struct efx_nic *efx = rx_queue->efx;
557 efx_oword_t rx_flush_descq;
558
559 EFX_POPULATE_OWORD_2(rx_flush_descq,
560 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
561 FRF_AZ_RX_FLUSH_DESCQ,
562 efx_rx_queue_index(rx_queue));
563 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
564 }
565
566 void efx_farch_rx_fini(struct efx_rx_queue *rx_queue)
567 {
568 efx_oword_t rx_desc_ptr;
569 struct efx_nic *efx = rx_queue->efx;
570
571 /* Remove RX descriptor ring from card */
572 EFX_ZERO_OWORD(rx_desc_ptr);
573 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
574 efx_rx_queue_index(rx_queue));
575
576 /* Unpin RX descriptor ring */
577 efx_fini_special_buffer(efx, &rx_queue->rxd);
578 }
579
580 /* Free buffers backing RX queue */
581 void efx_farch_rx_remove(struct efx_rx_queue *rx_queue)
582 {
583 efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
584 }
585
586 /**************************************************************************
587 *
588 * Flush handling
589 *
590 **************************************************************************/
591
592 /* efx_farch_flush_queues() must be woken up when all flushes are completed,
593 * or more RX flushes can be kicked off.
594 */
595 static bool efx_farch_flush_wake(struct efx_nic *efx)
596 {
597 /* Ensure that all updates are visible to efx_farch_flush_queues() */
598 smp_mb();
599
600 return (atomic_read(&efx->active_queues) == 0 ||
601 (atomic_read(&efx->rxq_flush_outstanding) < EFX_RX_FLUSH_COUNT
602 && atomic_read(&efx->rxq_flush_pending) > 0));
603 }
604
605 static bool efx_check_tx_flush_complete(struct efx_nic *efx)
606 {
607 bool i = true;
608 efx_oword_t txd_ptr_tbl;
609 struct efx_channel *channel;
610 struct efx_tx_queue *tx_queue;
611
612 efx_for_each_channel(channel, efx) {
613 efx_for_each_channel_tx_queue(tx_queue, channel) {
614 efx_reado_table(efx, &txd_ptr_tbl,
615 FR_BZ_TX_DESC_PTR_TBL, tx_queue->queue);
616 if (EFX_OWORD_FIELD(txd_ptr_tbl,
617 FRF_AZ_TX_DESCQ_FLUSH) ||
618 EFX_OWORD_FIELD(txd_ptr_tbl,
619 FRF_AZ_TX_DESCQ_EN)) {
620 netif_dbg(efx, hw, efx->net_dev,
621 "flush did not complete on TXQ %d\n",
622 tx_queue->queue);
623 i = false;
624 } else if (atomic_cmpxchg(&tx_queue->flush_outstanding,
625 1, 0)) {
626 /* The flush is complete, but we didn't
627 * receive a flush completion event
628 */
629 netif_dbg(efx, hw, efx->net_dev,
630 "flush complete on TXQ %d, so drain "
631 "the queue\n", tx_queue->queue);
632 /* Don't need to increment active_queues as it
633 * has already been incremented for the queues
634 * which did not drain
635 */
636 efx_farch_magic_event(channel,
637 EFX_CHANNEL_MAGIC_TX_DRAIN(
638 tx_queue));
639 }
640 }
641 }
642
643 return i;
644 }
645
646 /* Flush all the transmit queues, and continue flushing receive queues until
647 * they're all flushed. Wait for the DRAIN events to be recieved so that there
648 * are no more RX and TX events left on any channel. */
649 static int efx_farch_do_flush(struct efx_nic *efx)
650 {
651 unsigned timeout = msecs_to_jiffies(5000); /* 5s for all flushes and drains */
652 struct efx_channel *channel;
653 struct efx_rx_queue *rx_queue;
654 struct efx_tx_queue *tx_queue;
655 int rc = 0;
656
657 efx_for_each_channel(channel, efx) {
658 efx_for_each_channel_tx_queue(tx_queue, channel) {
659 efx_farch_flush_tx_queue(tx_queue);
660 }
661 efx_for_each_channel_rx_queue(rx_queue, channel) {
662 rx_queue->flush_pending = true;
663 atomic_inc(&efx->rxq_flush_pending);
664 }
665 }
666
667 while (timeout && atomic_read(&efx->active_queues) > 0) {
668 /* If SRIOV is enabled, then offload receive queue flushing to
669 * the firmware (though we will still have to poll for
670 * completion). If that fails, fall back to the old scheme.
671 */
672 if (efx_sriov_enabled(efx)) {
673 rc = efx_mcdi_flush_rxqs(efx);
674 if (!rc)
675 goto wait;
676 }
677
678 /* The hardware supports four concurrent rx flushes, each of
679 * which may need to be retried if there is an outstanding
680 * descriptor fetch
681 */
682 efx_for_each_channel(channel, efx) {
683 efx_for_each_channel_rx_queue(rx_queue, channel) {
684 if (atomic_read(&efx->rxq_flush_outstanding) >=
685 EFX_RX_FLUSH_COUNT)
686 break;
687
688 if (rx_queue->flush_pending) {
689 rx_queue->flush_pending = false;
690 atomic_dec(&efx->rxq_flush_pending);
691 atomic_inc(&efx->rxq_flush_outstanding);
692 efx_farch_flush_rx_queue(rx_queue);
693 }
694 }
695 }
696
697 wait:
698 timeout = wait_event_timeout(efx->flush_wq,
699 efx_farch_flush_wake(efx),
700 timeout);
701 }
702
703 if (atomic_read(&efx->active_queues) &&
704 !efx_check_tx_flush_complete(efx)) {
705 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues "
706 "(rx %d+%d)\n", atomic_read(&efx->active_queues),
707 atomic_read(&efx->rxq_flush_outstanding),
708 atomic_read(&efx->rxq_flush_pending));
709 rc = -ETIMEDOUT;
710
711 atomic_set(&efx->active_queues, 0);
712 atomic_set(&efx->rxq_flush_pending, 0);
713 atomic_set(&efx->rxq_flush_outstanding, 0);
714 }
715
716 return rc;
717 }
718
719 int efx_farch_fini_dmaq(struct efx_nic *efx)
720 {
721 struct efx_channel *channel;
722 struct efx_tx_queue *tx_queue;
723 struct efx_rx_queue *rx_queue;
724 int rc = 0;
725
726 /* Do not attempt to write to the NIC during EEH recovery */
727 if (efx->state != STATE_RECOVERY) {
728 /* Only perform flush if DMA is enabled */
729 if (efx->pci_dev->is_busmaster) {
730 efx->type->prepare_flush(efx);
731 rc = efx_farch_do_flush(efx);
732 efx->type->finish_flush(efx);
733 }
734
735 efx_for_each_channel(channel, efx) {
736 efx_for_each_channel_rx_queue(rx_queue, channel)
737 efx_farch_rx_fini(rx_queue);
738 efx_for_each_channel_tx_queue(tx_queue, channel)
739 efx_farch_tx_fini(tx_queue);
740 }
741 }
742
743 return rc;
744 }
745
746 /* Reset queue and flush accounting after FLR
747 *
748 * One possible cause of FLR recovery is that DMA may be failing (eg. if bus
749 * mastering was disabled), in which case we don't receive (RXQ) flush
750 * completion events. This means that efx->rxq_flush_outstanding remained at 4
751 * after the FLR; also, efx->active_queues was non-zero (as no flush completion
752 * events were received, and we didn't go through efx_check_tx_flush_complete())
753 * If we don't fix this up, on the next call to efx_realloc_channels() we won't
754 * flush any RX queues because efx->rxq_flush_outstanding is at the limit of 4
755 * for batched flush requests; and the efx->active_queues gets messed up because
756 * we keep incrementing for the newly initialised queues, but it never went to
757 * zero previously. Then we get a timeout every time we try to restart the
758 * queues, as it doesn't go back to zero when we should be flushing the queues.
759 */
760 void efx_farch_finish_flr(struct efx_nic *efx)
761 {
762 atomic_set(&efx->rxq_flush_pending, 0);
763 atomic_set(&efx->rxq_flush_outstanding, 0);
764 atomic_set(&efx->active_queues, 0);
765 }
766
767
768 /**************************************************************************
769 *
770 * Event queue processing
771 * Event queues are processed by per-channel tasklets.
772 *
773 **************************************************************************/
774
775 /* Update a channel's event queue's read pointer (RPTR) register
776 *
777 * This writes the EVQ_RPTR_REG register for the specified channel's
778 * event queue.
779 */
780 void efx_farch_ev_read_ack(struct efx_channel *channel)
781 {
782 efx_dword_t reg;
783 struct efx_nic *efx = channel->efx;
784
785 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR,
786 channel->eventq_read_ptr & channel->eventq_mask);
787
788 /* For Falcon A1, EVQ_RPTR_KER is documented as having a step size
789 * of 4 bytes, but it is really 16 bytes just like later revisions.
790 */
791 efx_writed(efx, &reg,
792 efx->type->evq_rptr_tbl_base +
793 FR_BZ_EVQ_RPTR_STEP * channel->channel);
794 }
795
796 /* Use HW to insert a SW defined event */
797 void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
798 efx_qword_t *event)
799 {
800 efx_oword_t drv_ev_reg;
801
802 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
803 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
804 drv_ev_reg.u32[0] = event->u32[0];
805 drv_ev_reg.u32[1] = event->u32[1];
806 drv_ev_reg.u32[2] = 0;
807 drv_ev_reg.u32[3] = 0;
808 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, evq);
809 efx_writeo(efx, &drv_ev_reg, FR_AZ_DRV_EV);
810 }
811
812 static void efx_farch_magic_event(struct efx_channel *channel, u32 magic)
813 {
814 efx_qword_t event;
815
816 EFX_POPULATE_QWORD_2(event, FSF_AZ_EV_CODE,
817 FSE_AZ_EV_CODE_DRV_GEN_EV,
818 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
819 efx_farch_generate_event(channel->efx, channel->channel, &event);
820 }
821
822 /* Handle a transmit completion event
823 *
824 * The NIC batches TX completion events; the message we receive is of
825 * the form "complete all TX events up to this index".
826 */
827 static int
828 efx_farch_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
829 {
830 unsigned int tx_ev_desc_ptr;
831 unsigned int tx_ev_q_label;
832 struct efx_tx_queue *tx_queue;
833 struct efx_nic *efx = channel->efx;
834 int tx_packets = 0;
835
836 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
837 return 0;
838
839 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
840 /* Transmit completion */
841 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
842 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
843 tx_queue = efx_channel_get_tx_queue(
844 channel, tx_ev_q_label % EFX_TXQ_TYPES);
845 tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) &
846 tx_queue->ptr_mask);
847 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
848 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
849 /* Rewrite the FIFO write pointer */
850 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
851 tx_queue = efx_channel_get_tx_queue(
852 channel, tx_ev_q_label % EFX_TXQ_TYPES);
853
854 netif_tx_lock(efx->net_dev);
855 efx_farch_notify_tx_desc(tx_queue);
856 netif_tx_unlock(efx->net_dev);
857 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR)) {
858 efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
859 } else {
860 netif_err(efx, tx_err, efx->net_dev,
861 "channel %d unexpected TX event "
862 EFX_QWORD_FMT"\n", channel->channel,
863 EFX_QWORD_VAL(*event));
864 }
865
866 return tx_packets;
867 }
868
869 /* Detect errors included in the rx_evt_pkt_ok bit. */
870 static u16 efx_farch_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
871 const efx_qword_t *event)
872 {
873 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
874 struct efx_nic *efx = rx_queue->efx;
875 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
876 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
877 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
878 bool rx_ev_other_err, rx_ev_pause_frm;
879 bool rx_ev_hdr_type, rx_ev_mcast_pkt;
880 unsigned rx_ev_pkt_type;
881
882 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
883 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
884 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
885 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
886 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
887 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
888 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
889 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
890 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
891 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
892 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
893 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
894 rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
895 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
896 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
897
898 /* Every error apart from tobe_disc and pause_frm */
899 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
900 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
901 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
902
903 /* Count errors that are not in MAC stats. Ignore expected
904 * checksum errors during self-test. */
905 if (rx_ev_frm_trunc)
906 ++channel->n_rx_frm_trunc;
907 else if (rx_ev_tobe_disc)
908 ++channel->n_rx_tobe_disc;
909 else if (!efx->loopback_selftest) {
910 if (rx_ev_ip_hdr_chksum_err)
911 ++channel->n_rx_ip_hdr_chksum_err;
912 else if (rx_ev_tcp_udp_chksum_err)
913 ++channel->n_rx_tcp_udp_chksum_err;
914 }
915
916 /* TOBE_DISC is expected on unicast mismatches; don't print out an
917 * error message. FRM_TRUNC indicates RXDP dropped the packet due
918 * to a FIFO overflow.
919 */
920 #ifdef DEBUG
921 if (rx_ev_other_err && net_ratelimit()) {
922 netif_dbg(efx, rx_err, efx->net_dev,
923 " RX queue %d unexpected RX event "
924 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
925 efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event),
926 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
927 rx_ev_ip_hdr_chksum_err ?
928 " [IP_HDR_CHKSUM_ERR]" : "",
929 rx_ev_tcp_udp_chksum_err ?
930 " [TCP_UDP_CHKSUM_ERR]" : "",
931 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
932 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
933 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
934 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
935 rx_ev_pause_frm ? " [PAUSE]" : "");
936 }
937 #endif
938
939 /* The frame must be discarded if any of these are true. */
940 return (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
941 rx_ev_tobe_disc | rx_ev_pause_frm) ?
942 EFX_RX_PKT_DISCARD : 0;
943 }
944
945 /* Handle receive events that are not in-order. Return true if this
946 * can be handled as a partial packet discard, false if it's more
947 * serious.
948 */
949 static bool
950 efx_farch_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
951 {
952 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
953 struct efx_nic *efx = rx_queue->efx;
954 unsigned expected, dropped;
955
956 if (rx_queue->scatter_n &&
957 index == ((rx_queue->removed_count + rx_queue->scatter_n - 1) &
958 rx_queue->ptr_mask)) {
959 ++channel->n_rx_nodesc_trunc;
960 return true;
961 }
962
963 expected = rx_queue->removed_count & rx_queue->ptr_mask;
964 dropped = (index - expected) & rx_queue->ptr_mask;
965 netif_info(efx, rx_err, efx->net_dev,
966 "dropped %d events (index=%d expected=%d)\n",
967 dropped, index, expected);
968
969 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
970 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
971 return false;
972 }
973
974 /* Handle a packet received event
975 *
976 * The NIC gives a "discard" flag if it's a unicast packet with the
977 * wrong destination address
978 * Also "is multicast" and "matches multicast filter" flags can be used to
979 * discard non-matching multicast packets.
980 */
981 static void
982 efx_farch_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
983 {
984 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
985 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
986 unsigned expected_ptr;
987 bool rx_ev_pkt_ok, rx_ev_sop, rx_ev_cont;
988 u16 flags;
989 struct efx_rx_queue *rx_queue;
990 struct efx_nic *efx = channel->efx;
991
992 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
993 return;
994
995 rx_ev_cont = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT);
996 rx_ev_sop = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP);
997 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
998 channel->channel);
999
1000 rx_queue = efx_channel_get_rx_queue(channel);
1001
1002 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
1003 expected_ptr = ((rx_queue->removed_count + rx_queue->scatter_n) &
1004 rx_queue->ptr_mask);
1005
1006 /* Check for partial drops and other errors */
1007 if (unlikely(rx_ev_desc_ptr != expected_ptr) ||
1008 unlikely(rx_ev_sop != (rx_queue->scatter_n == 0))) {
1009 if (rx_ev_desc_ptr != expected_ptr &&
1010 !efx_farch_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr))
1011 return;
1012
1013 /* Discard all pending fragments */
1014 if (rx_queue->scatter_n) {
1015 efx_rx_packet(
1016 rx_queue,
1017 rx_queue->removed_count & rx_queue->ptr_mask,
1018 rx_queue->scatter_n, 0, EFX_RX_PKT_DISCARD);
1019 rx_queue->removed_count += rx_queue->scatter_n;
1020 rx_queue->scatter_n = 0;
1021 }
1022
1023 /* Return if there is no new fragment */
1024 if (rx_ev_desc_ptr != expected_ptr)
1025 return;
1026
1027 /* Discard new fragment if not SOP */
1028 if (!rx_ev_sop) {
1029 efx_rx_packet(
1030 rx_queue,
1031 rx_queue->removed_count & rx_queue->ptr_mask,
1032 1, 0, EFX_RX_PKT_DISCARD);
1033 ++rx_queue->removed_count;
1034 return;
1035 }
1036 }
1037
1038 ++rx_queue->scatter_n;
1039 if (rx_ev_cont)
1040 return;
1041
1042 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
1043 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
1044 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
1045
1046 if (likely(rx_ev_pkt_ok)) {
1047 /* If packet is marked as OK then we can rely on the
1048 * hardware checksum and classification.
1049 */
1050 flags = 0;
1051 switch (rx_ev_hdr_type) {
1052 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
1053 flags |= EFX_RX_PKT_TCP;
1054 /* fall through */
1055 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
1056 flags |= EFX_RX_PKT_CSUMMED;
1057 /* fall through */
1058 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
1059 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
1060 break;
1061 }
1062 } else {
1063 flags = efx_farch_handle_rx_not_ok(rx_queue, event);
1064 }
1065
1066 /* Detect multicast packets that didn't match the filter */
1067 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
1068 if (rx_ev_mcast_pkt) {
1069 unsigned int rx_ev_mcast_hash_match =
1070 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
1071
1072 if (unlikely(!rx_ev_mcast_hash_match)) {
1073 ++channel->n_rx_mcast_mismatch;
1074 flags |= EFX_RX_PKT_DISCARD;
1075 }
1076 }
1077
1078 channel->irq_mod_score += 2;
1079
1080 /* Handle received packet */
1081 efx_rx_packet(rx_queue,
1082 rx_queue->removed_count & rx_queue->ptr_mask,
1083 rx_queue->scatter_n, rx_ev_byte_cnt, flags);
1084 rx_queue->removed_count += rx_queue->scatter_n;
1085 rx_queue->scatter_n = 0;
1086 }
1087
1088 /* If this flush done event corresponds to a &struct efx_tx_queue, then
1089 * send an %EFX_CHANNEL_MAGIC_TX_DRAIN event to drain the event queue
1090 * of all transmit completions.
1091 */
1092 static void
1093 efx_farch_handle_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1094 {
1095 struct efx_tx_queue *tx_queue;
1096 int qid;
1097
1098 qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1099 if (qid < EFX_TXQ_TYPES * efx->n_tx_channels) {
1100 tx_queue = efx_get_tx_queue(efx, qid / EFX_TXQ_TYPES,
1101 qid % EFX_TXQ_TYPES);
1102 if (atomic_cmpxchg(&tx_queue->flush_outstanding, 1, 0)) {
1103 efx_farch_magic_event(tx_queue->channel,
1104 EFX_CHANNEL_MAGIC_TX_DRAIN(tx_queue));
1105 }
1106 }
1107 }
1108
1109 /* If this flush done event corresponds to a &struct efx_rx_queue: If the flush
1110 * was succesful then send an %EFX_CHANNEL_MAGIC_RX_DRAIN, otherwise add
1111 * the RX queue back to the mask of RX queues in need of flushing.
1112 */
1113 static void
1114 efx_farch_handle_rx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1115 {
1116 struct efx_channel *channel;
1117 struct efx_rx_queue *rx_queue;
1118 int qid;
1119 bool failed;
1120
1121 qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1122 failed = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1123 if (qid >= efx->n_channels)
1124 return;
1125 channel = efx_get_channel(efx, qid);
1126 if (!efx_channel_has_rx_queue(channel))
1127 return;
1128 rx_queue = efx_channel_get_rx_queue(channel);
1129
1130 if (failed) {
1131 netif_info(efx, hw, efx->net_dev,
1132 "RXQ %d flush retry\n", qid);
1133 rx_queue->flush_pending = true;
1134 atomic_inc(&efx->rxq_flush_pending);
1135 } else {
1136 efx_farch_magic_event(efx_rx_queue_channel(rx_queue),
1137 EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue));
1138 }
1139 atomic_dec(&efx->rxq_flush_outstanding);
1140 if (efx_farch_flush_wake(efx))
1141 wake_up(&efx->flush_wq);
1142 }
1143
1144 static void
1145 efx_farch_handle_drain_event(struct efx_channel *channel)
1146 {
1147 struct efx_nic *efx = channel->efx;
1148
1149 WARN_ON(atomic_read(&efx->active_queues) == 0);
1150 atomic_dec(&efx->active_queues);
1151 if (efx_farch_flush_wake(efx))
1152 wake_up(&efx->flush_wq);
1153 }
1154
1155 static void efx_farch_handle_generated_event(struct efx_channel *channel,
1156 efx_qword_t *event)
1157 {
1158 struct efx_nic *efx = channel->efx;
1159 struct efx_rx_queue *rx_queue =
1160 efx_channel_has_rx_queue(channel) ?
1161 efx_channel_get_rx_queue(channel) : NULL;
1162 unsigned magic, code;
1163
1164 magic = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC);
1165 code = _EFX_CHANNEL_MAGIC_CODE(magic);
1166
1167 if (magic == EFX_CHANNEL_MAGIC_TEST(channel)) {
1168 channel->event_test_cpu = raw_smp_processor_id();
1169 } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_FILL(rx_queue)) {
1170 /* The queue must be empty, so we won't receive any rx
1171 * events, so efx_process_channel() won't refill the
1172 * queue. Refill it here */
1173 efx_fast_push_rx_descriptors(rx_queue, true);
1174 } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)) {
1175 efx_farch_handle_drain_event(channel);
1176 } else if (code == _EFX_CHANNEL_MAGIC_TX_DRAIN) {
1177 efx_farch_handle_drain_event(channel);
1178 } else {
1179 netif_dbg(efx, hw, efx->net_dev, "channel %d received "
1180 "generated event "EFX_QWORD_FMT"\n",
1181 channel->channel, EFX_QWORD_VAL(*event));
1182 }
1183 }
1184
1185 static void
1186 efx_farch_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1187 {
1188 struct efx_nic *efx = channel->efx;
1189 unsigned int ev_sub_code;
1190 unsigned int ev_sub_data;
1191
1192 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
1193 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1194
1195 switch (ev_sub_code) {
1196 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
1197 netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n",
1198 channel->channel, ev_sub_data);
1199 efx_farch_handle_tx_flush_done(efx, event);
1200 efx_sriov_tx_flush_done(efx, event);
1201 break;
1202 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
1203 netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n",
1204 channel->channel, ev_sub_data);
1205 efx_farch_handle_rx_flush_done(efx, event);
1206 efx_sriov_rx_flush_done(efx, event);
1207 break;
1208 case FSE_AZ_EVQ_INIT_DONE_EV:
1209 netif_dbg(efx, hw, efx->net_dev,
1210 "channel %d EVQ %d initialised\n",
1211 channel->channel, ev_sub_data);
1212 break;
1213 case FSE_AZ_SRM_UPD_DONE_EV:
1214 netif_vdbg(efx, hw, efx->net_dev,
1215 "channel %d SRAM update done\n", channel->channel);
1216 break;
1217 case FSE_AZ_WAKE_UP_EV:
1218 netif_vdbg(efx, hw, efx->net_dev,
1219 "channel %d RXQ %d wakeup event\n",
1220 channel->channel, ev_sub_data);
1221 break;
1222 case FSE_AZ_TIMER_EV:
1223 netif_vdbg(efx, hw, efx->net_dev,
1224 "channel %d RX queue %d timer expired\n",
1225 channel->channel, ev_sub_data);
1226 break;
1227 case FSE_AA_RX_RECOVER_EV:
1228 netif_err(efx, rx_err, efx->net_dev,
1229 "channel %d seen DRIVER RX_RESET event. "
1230 "Resetting.\n", channel->channel);
1231 atomic_inc(&efx->rx_reset);
1232 efx_schedule_reset(efx,
1233 EFX_WORKAROUND_6555(efx) ?
1234 RESET_TYPE_RX_RECOVERY :
1235 RESET_TYPE_DISABLE);
1236 break;
1237 case FSE_BZ_RX_DSC_ERROR_EV:
1238 if (ev_sub_data < EFX_VI_BASE) {
1239 netif_err(efx, rx_err, efx->net_dev,
1240 "RX DMA Q %d reports descriptor fetch error."
1241 " RX Q %d is disabled.\n", ev_sub_data,
1242 ev_sub_data);
1243 efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
1244 } else
1245 efx_sriov_desc_fetch_err(efx, ev_sub_data);
1246 break;
1247 case FSE_BZ_TX_DSC_ERROR_EV:
1248 if (ev_sub_data < EFX_VI_BASE) {
1249 netif_err(efx, tx_err, efx->net_dev,
1250 "TX DMA Q %d reports descriptor fetch error."
1251 " TX Q %d is disabled.\n", ev_sub_data,
1252 ev_sub_data);
1253 efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
1254 } else
1255 efx_sriov_desc_fetch_err(efx, ev_sub_data);
1256 break;
1257 default:
1258 netif_vdbg(efx, hw, efx->net_dev,
1259 "channel %d unknown driver event code %d "
1260 "data %04x\n", channel->channel, ev_sub_code,
1261 ev_sub_data);
1262 break;
1263 }
1264 }
1265
1266 int efx_farch_ev_process(struct efx_channel *channel, int budget)
1267 {
1268 struct efx_nic *efx = channel->efx;
1269 unsigned int read_ptr;
1270 efx_qword_t event, *p_event;
1271 int ev_code;
1272 int tx_packets = 0;
1273 int spent = 0;
1274
1275 if (budget <= 0)
1276 return spent;
1277
1278 read_ptr = channel->eventq_read_ptr;
1279
1280 for (;;) {
1281 p_event = efx_event(channel, read_ptr);
1282 event = *p_event;
1283
1284 if (!efx_event_present(&event))
1285 /* End of events */
1286 break;
1287
1288 netif_vdbg(channel->efx, intr, channel->efx->net_dev,
1289 "channel %d event is "EFX_QWORD_FMT"\n",
1290 channel->channel, EFX_QWORD_VAL(event));
1291
1292 /* Clear this event by marking it all ones */
1293 EFX_SET_QWORD(*p_event);
1294
1295 ++read_ptr;
1296
1297 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1298
1299 switch (ev_code) {
1300 case FSE_AZ_EV_CODE_RX_EV:
1301 efx_farch_handle_rx_event(channel, &event);
1302 if (++spent == budget)
1303 goto out;
1304 break;
1305 case FSE_AZ_EV_CODE_TX_EV:
1306 tx_packets += efx_farch_handle_tx_event(channel,
1307 &event);
1308 if (tx_packets > efx->txq_entries) {
1309 spent = budget;
1310 goto out;
1311 }
1312 break;
1313 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1314 efx_farch_handle_generated_event(channel, &event);
1315 break;
1316 case FSE_AZ_EV_CODE_DRIVER_EV:
1317 efx_farch_handle_driver_event(channel, &event);
1318 break;
1319 case FSE_CZ_EV_CODE_USER_EV:
1320 efx_sriov_event(channel, &event);
1321 break;
1322 case FSE_CZ_EV_CODE_MCDI_EV:
1323 efx_mcdi_process_event(channel, &event);
1324 break;
1325 case FSE_AZ_EV_CODE_GLOBAL_EV:
1326 if (efx->type->handle_global_event &&
1327 efx->type->handle_global_event(channel, &event))
1328 break;
1329 /* else fall through */
1330 default:
1331 netif_err(channel->efx, hw, channel->efx->net_dev,
1332 "channel %d unknown event type %d (data "
1333 EFX_QWORD_FMT ")\n", channel->channel,
1334 ev_code, EFX_QWORD_VAL(event));
1335 }
1336 }
1337
1338 out:
1339 channel->eventq_read_ptr = read_ptr;
1340 return spent;
1341 }
1342
1343 /* Allocate buffer table entries for event queue */
1344 int efx_farch_ev_probe(struct efx_channel *channel)
1345 {
1346 struct efx_nic *efx = channel->efx;
1347 unsigned entries;
1348
1349 entries = channel->eventq_mask + 1;
1350 return efx_alloc_special_buffer(efx, &channel->eventq,
1351 entries * sizeof(efx_qword_t));
1352 }
1353
1354 int efx_farch_ev_init(struct efx_channel *channel)
1355 {
1356 efx_oword_t reg;
1357 struct efx_nic *efx = channel->efx;
1358
1359 netif_dbg(efx, hw, efx->net_dev,
1360 "channel %d event queue in special buffers %d-%d\n",
1361 channel->channel, channel->eventq.index,
1362 channel->eventq.index + channel->eventq.entries - 1);
1363
1364 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
1365 EFX_POPULATE_OWORD_3(reg,
1366 FRF_CZ_TIMER_Q_EN, 1,
1367 FRF_CZ_HOST_NOTIFY_MODE, 0,
1368 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1369 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1370 }
1371
1372 /* Pin event queue buffer */
1373 efx_init_special_buffer(efx, &channel->eventq);
1374
1375 /* Fill event queue with all ones (i.e. empty events) */
1376 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1377
1378 /* Push event queue to card */
1379 EFX_POPULATE_OWORD_3(reg,
1380 FRF_AZ_EVQ_EN, 1,
1381 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1382 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1383 efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1384 channel->channel);
1385
1386 return 0;
1387 }
1388
1389 void efx_farch_ev_fini(struct efx_channel *channel)
1390 {
1391 efx_oword_t reg;
1392 struct efx_nic *efx = channel->efx;
1393
1394 /* Remove event queue from card */
1395 EFX_ZERO_OWORD(reg);
1396 efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1397 channel->channel);
1398 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1399 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1400
1401 /* Unpin event queue */
1402 efx_fini_special_buffer(efx, &channel->eventq);
1403 }
1404
1405 /* Free buffers backing event queue */
1406 void efx_farch_ev_remove(struct efx_channel *channel)
1407 {
1408 efx_free_special_buffer(channel->efx, &channel->eventq);
1409 }
1410
1411
1412 void efx_farch_ev_test_generate(struct efx_channel *channel)
1413 {
1414 efx_farch_magic_event(channel, EFX_CHANNEL_MAGIC_TEST(channel));
1415 }
1416
1417 void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue)
1418 {
1419 efx_farch_magic_event(efx_rx_queue_channel(rx_queue),
1420 EFX_CHANNEL_MAGIC_FILL(rx_queue));
1421 }
1422
1423 /**************************************************************************
1424 *
1425 * Hardware interrupts
1426 * The hardware interrupt handler does very little work; all the event
1427 * queue processing is carried out by per-channel tasklets.
1428 *
1429 **************************************************************************/
1430
1431 /* Enable/disable/generate interrupts */
1432 static inline void efx_farch_interrupts(struct efx_nic *efx,
1433 bool enabled, bool force)
1434 {
1435 efx_oword_t int_en_reg_ker;
1436
1437 EFX_POPULATE_OWORD_3(int_en_reg_ker,
1438 FRF_AZ_KER_INT_LEVE_SEL, efx->irq_level,
1439 FRF_AZ_KER_INT_KER, force,
1440 FRF_AZ_DRV_INT_EN_KER, enabled);
1441 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1442 }
1443
1444 void efx_farch_irq_enable_master(struct efx_nic *efx)
1445 {
1446 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1447 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1448
1449 efx_farch_interrupts(efx, true, false);
1450 }
1451
1452 void efx_farch_irq_disable_master(struct efx_nic *efx)
1453 {
1454 /* Disable interrupts */
1455 efx_farch_interrupts(efx, false, false);
1456 }
1457
1458 /* Generate a test interrupt
1459 * Interrupt must already have been enabled, otherwise nasty things
1460 * may happen.
1461 */
1462 void efx_farch_irq_test_generate(struct efx_nic *efx)
1463 {
1464 efx_farch_interrupts(efx, true, true);
1465 }
1466
1467 /* Process a fatal interrupt
1468 * Disable bus mastering ASAP and schedule a reset
1469 */
1470 irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx)
1471 {
1472 struct falcon_nic_data *nic_data = efx->nic_data;
1473 efx_oword_t *int_ker = efx->irq_status.addr;
1474 efx_oword_t fatal_intr;
1475 int error, mem_perr;
1476
1477 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1478 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1479
1480 netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status "
1481 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1482 EFX_OWORD_VAL(fatal_intr),
1483 error ? "disabling bus mastering" : "no recognised error");
1484
1485 /* If this is a memory parity error dump which blocks are offending */
1486 mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) ||
1487 EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER));
1488 if (mem_perr) {
1489 efx_oword_t reg;
1490 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1491 netif_err(efx, hw, efx->net_dev,
1492 "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n",
1493 EFX_OWORD_VAL(reg));
1494 }
1495
1496 /* Disable both devices */
1497 pci_clear_master(efx->pci_dev);
1498 if (efx_nic_is_dual_func(efx))
1499 pci_clear_master(nic_data->pci_dev2);
1500 efx_farch_irq_disable_master(efx);
1501
1502 /* Count errors and reset or disable the NIC accordingly */
1503 if (efx->int_error_count == 0 ||
1504 time_after(jiffies, efx->int_error_expire)) {
1505 efx->int_error_count = 0;
1506 efx->int_error_expire =
1507 jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1508 }
1509 if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
1510 netif_err(efx, hw, efx->net_dev,
1511 "SYSTEM ERROR - reset scheduled\n");
1512 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1513 } else {
1514 netif_err(efx, hw, efx->net_dev,
1515 "SYSTEM ERROR - max number of errors seen."
1516 "NIC will be disabled\n");
1517 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1518 }
1519
1520 return IRQ_HANDLED;
1521 }
1522
1523 /* Handle a legacy interrupt
1524 * Acknowledges the interrupt and schedule event queue processing.
1525 */
1526 irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id)
1527 {
1528 struct efx_nic *efx = dev_id;
1529 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1530 efx_oword_t *int_ker = efx->irq_status.addr;
1531 irqreturn_t result = IRQ_NONE;
1532 struct efx_channel *channel;
1533 efx_dword_t reg;
1534 u32 queues;
1535 int syserr;
1536
1537 /* Read the ISR which also ACKs the interrupts */
1538 efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1539 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1540
1541 /* Legacy interrupts are disabled too late by the EEH kernel
1542 * code. Disable them earlier.
1543 * If an EEH error occurred, the read will have returned all ones.
1544 */
1545 if (EFX_DWORD_IS_ALL_ONES(reg) && efx_try_recovery(efx) &&
1546 !efx->eeh_disabled_legacy_irq) {
1547 disable_irq_nosync(efx->legacy_irq);
1548 efx->eeh_disabled_legacy_irq = true;
1549 }
1550
1551 /* Handle non-event-queue sources */
1552 if (queues & (1U << efx->irq_level) && soft_enabled) {
1553 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1554 if (unlikely(syserr))
1555 return efx_farch_fatal_interrupt(efx);
1556 efx->last_irq_cpu = raw_smp_processor_id();
1557 }
1558
1559 if (queues != 0) {
1560 efx->irq_zero_count = 0;
1561
1562 /* Schedule processing of any interrupting queues */
1563 if (likely(soft_enabled)) {
1564 efx_for_each_channel(channel, efx) {
1565 if (queues & 1)
1566 efx_schedule_channel_irq(channel);
1567 queues >>= 1;
1568 }
1569 }
1570 result = IRQ_HANDLED;
1571
1572 } else {
1573 efx_qword_t *event;
1574
1575 /* Legacy ISR read can return zero once (SF bug 15783) */
1576
1577 /* We can't return IRQ_HANDLED more than once on seeing ISR=0
1578 * because this might be a shared interrupt. */
1579 if (efx->irq_zero_count++ == 0)
1580 result = IRQ_HANDLED;
1581
1582 /* Ensure we schedule or rearm all event queues */
1583 if (likely(soft_enabled)) {
1584 efx_for_each_channel(channel, efx) {
1585 event = efx_event(channel,
1586 channel->eventq_read_ptr);
1587 if (efx_event_present(event))
1588 efx_schedule_channel_irq(channel);
1589 else
1590 efx_farch_ev_read_ack(channel);
1591 }
1592 }
1593 }
1594
1595 if (result == IRQ_HANDLED)
1596 netif_vdbg(efx, intr, efx->net_dev,
1597 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1598 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1599
1600 return result;
1601 }
1602
1603 /* Handle an MSI interrupt
1604 *
1605 * Handle an MSI hardware interrupt. This routine schedules event
1606 * queue processing. No interrupt acknowledgement cycle is necessary.
1607 * Also, we never need to check that the interrupt is for us, since
1608 * MSI interrupts cannot be shared.
1609 */
1610 irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id)
1611 {
1612 struct efx_msi_context *context = dev_id;
1613 struct efx_nic *efx = context->efx;
1614 efx_oword_t *int_ker = efx->irq_status.addr;
1615 int syserr;
1616
1617 netif_vdbg(efx, intr, efx->net_dev,
1618 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1619 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1620
1621 if (!likely(ACCESS_ONCE(efx->irq_soft_enabled)))
1622 return IRQ_HANDLED;
1623
1624 /* Handle non-event-queue sources */
1625 if (context->index == efx->irq_level) {
1626 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1627 if (unlikely(syserr))
1628 return efx_farch_fatal_interrupt(efx);
1629 efx->last_irq_cpu = raw_smp_processor_id();
1630 }
1631
1632 /* Schedule processing of the channel */
1633 efx_schedule_channel_irq(efx->channel[context->index]);
1634
1635 return IRQ_HANDLED;
1636 }
1637
1638 /* Setup RSS indirection table.
1639 * This maps from the hash value of the packet to RXQ
1640 */
1641 void efx_farch_rx_push_indir_table(struct efx_nic *efx)
1642 {
1643 size_t i = 0;
1644 efx_dword_t dword;
1645
1646 BUG_ON(efx_nic_rev(efx) < EFX_REV_FALCON_B0);
1647
1648 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1649 FR_BZ_RX_INDIRECTION_TBL_ROWS);
1650
1651 for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
1652 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1653 efx->rx_indir_table[i]);
1654 efx_writed(efx, &dword,
1655 FR_BZ_RX_INDIRECTION_TBL +
1656 FR_BZ_RX_INDIRECTION_TBL_STEP * i);
1657 }
1658 }
1659
1660 /* Looks at available SRAM resources and works out how many queues we
1661 * can support, and where things like descriptor caches should live.
1662 *
1663 * SRAM is split up as follows:
1664 * 0 buftbl entries for channels
1665 * efx->vf_buftbl_base buftbl entries for SR-IOV
1666 * efx->rx_dc_base RX descriptor caches
1667 * efx->tx_dc_base TX descriptor caches
1668 */
1669 void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw)
1670 {
1671 unsigned vi_count, buftbl_min;
1672
1673 /* Account for the buffer table entries backing the datapath channels
1674 * and the descriptor caches for those channels.
1675 */
1676 buftbl_min = ((efx->n_rx_channels * EFX_MAX_DMAQ_SIZE +
1677 efx->n_tx_channels * EFX_TXQ_TYPES * EFX_MAX_DMAQ_SIZE +
1678 efx->n_channels * EFX_MAX_EVQ_SIZE)
1679 * sizeof(efx_qword_t) / EFX_BUF_SIZE);
1680 vi_count = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1681
1682 #ifdef CONFIG_SFC_SRIOV
1683 if (efx_sriov_wanted(efx)) {
1684 unsigned vi_dc_entries, buftbl_free, entries_per_vf, vf_limit;
1685
1686 efx->vf_buftbl_base = buftbl_min;
1687
1688 vi_dc_entries = RX_DC_ENTRIES + TX_DC_ENTRIES;
1689 vi_count = max(vi_count, EFX_VI_BASE);
1690 buftbl_free = (sram_lim_qw - buftbl_min -
1691 vi_count * vi_dc_entries);
1692
1693 entries_per_vf = ((vi_dc_entries + EFX_VF_BUFTBL_PER_VI) *
1694 efx_vf_size(efx));
1695 vf_limit = min(buftbl_free / entries_per_vf,
1696 (1024U - EFX_VI_BASE) >> efx->vi_scale);
1697
1698 if (efx->vf_count > vf_limit) {
1699 netif_err(efx, probe, efx->net_dev,
1700 "Reducing VF count from from %d to %d\n",
1701 efx->vf_count, vf_limit);
1702 efx->vf_count = vf_limit;
1703 }
1704 vi_count += efx->vf_count * efx_vf_size(efx);
1705 }
1706 #endif
1707
1708 efx->tx_dc_base = sram_lim_qw - vi_count * TX_DC_ENTRIES;
1709 efx->rx_dc_base = efx->tx_dc_base - vi_count * RX_DC_ENTRIES;
1710 }
1711
1712 u32 efx_farch_fpga_ver(struct efx_nic *efx)
1713 {
1714 efx_oword_t altera_build;
1715 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
1716 return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
1717 }
1718
1719 void efx_farch_init_common(struct efx_nic *efx)
1720 {
1721 efx_oword_t temp;
1722
1723 /* Set positions of descriptor caches in SRAM. */
1724 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, efx->tx_dc_base);
1725 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
1726 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, efx->rx_dc_base);
1727 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
1728
1729 /* Set TX descriptor cache size. */
1730 BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
1731 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
1732 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
1733
1734 /* Set RX descriptor cache size. Set low watermark to size-8, as
1735 * this allows most efficient prefetching.
1736 */
1737 BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
1738 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
1739 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
1740 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
1741 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
1742
1743 /* Program INT_KER address */
1744 EFX_POPULATE_OWORD_2(temp,
1745 FRF_AZ_NORM_INT_VEC_DIS_KER,
1746 EFX_INT_MODE_USE_MSI(efx),
1747 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1748 efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
1749
1750 if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx))
1751 /* Use an interrupt level unused by event queues */
1752 efx->irq_level = 0x1f;
1753 else
1754 /* Use a valid MSI-X vector */
1755 efx->irq_level = 0;
1756
1757 /* Enable all the genuinely fatal interrupts. (They are still
1758 * masked by the overall interrupt mask, controlled by
1759 * falcon_interrupts()).
1760 *
1761 * Note: All other fatal interrupts are enabled
1762 */
1763 EFX_POPULATE_OWORD_3(temp,
1764 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
1765 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
1766 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
1767 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1768 EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1);
1769 EFX_INVERT_OWORD(temp);
1770 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
1771
1772 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1773 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1774 */
1775 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
1776 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1777 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1778 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
1779 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1);
1780 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1781 /* Enable SW_EV to inherit in char driver - assume harmless here */
1782 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
1783 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1784 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
1785 /* Disable hardware watchdog which can misfire */
1786 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
1787 /* Squash TX of packets of 16 bytes or less */
1788 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1789 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
1790 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
1791
1792 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1793 EFX_POPULATE_OWORD_4(temp,
1794 /* Default values */
1795 FRF_BZ_TX_PACE_SB_NOT_AF, 0x15,
1796 FRF_BZ_TX_PACE_SB_AF, 0xb,
1797 FRF_BZ_TX_PACE_FB_BASE, 0,
1798 /* Allow large pace values in the
1799 * fast bin. */
1800 FRF_BZ_TX_PACE_BIN_TH,
1801 FFE_BZ_TX_PACE_RESERVED);
1802 efx_writeo(efx, &temp, FR_BZ_TX_PACE);
1803 }
1804 }
1805
1806 /**************************************************************************
1807 *
1808 * Filter tables
1809 *
1810 **************************************************************************
1811 */
1812
1813 /* "Fudge factors" - difference between programmed value and actual depth.
1814 * Due to pipelined implementation we need to program H/W with a value that
1815 * is larger than the hop limit we want.
1816 */
1817 #define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD 3
1818 #define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL 1
1819
1820 /* Hard maximum search limit. Hardware will time-out beyond 200-something.
1821 * We also need to avoid infinite loops in efx_farch_filter_search() when the
1822 * table is full.
1823 */
1824 #define EFX_FARCH_FILTER_CTL_SRCH_MAX 200
1825
1826 /* Don't try very hard to find space for performance hints, as this is
1827 * counter-productive. */
1828 #define EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX 5
1829
1830 enum efx_farch_filter_type {
1831 EFX_FARCH_FILTER_TCP_FULL = 0,
1832 EFX_FARCH_FILTER_TCP_WILD,
1833 EFX_FARCH_FILTER_UDP_FULL,
1834 EFX_FARCH_FILTER_UDP_WILD,
1835 EFX_FARCH_FILTER_MAC_FULL = 4,
1836 EFX_FARCH_FILTER_MAC_WILD,
1837 EFX_FARCH_FILTER_UC_DEF = 8,
1838 EFX_FARCH_FILTER_MC_DEF,
1839 EFX_FARCH_FILTER_TYPE_COUNT, /* number of specific types */
1840 };
1841
1842 enum efx_farch_filter_table_id {
1843 EFX_FARCH_FILTER_TABLE_RX_IP = 0,
1844 EFX_FARCH_FILTER_TABLE_RX_MAC,
1845 EFX_FARCH_FILTER_TABLE_RX_DEF,
1846 EFX_FARCH_FILTER_TABLE_TX_MAC,
1847 EFX_FARCH_FILTER_TABLE_COUNT,
1848 };
1849
1850 enum efx_farch_filter_index {
1851 EFX_FARCH_FILTER_INDEX_UC_DEF,
1852 EFX_FARCH_FILTER_INDEX_MC_DEF,
1853 EFX_FARCH_FILTER_SIZE_RX_DEF,
1854 };
1855
1856 struct efx_farch_filter_spec {
1857 u8 type:4;
1858 u8 priority:4;
1859 u8 flags;
1860 u16 dmaq_id;
1861 u32 data[3];
1862 };
1863
1864 struct efx_farch_filter_table {
1865 enum efx_farch_filter_table_id id;
1866 u32 offset; /* address of table relative to BAR */
1867 unsigned size; /* number of entries */
1868 unsigned step; /* step between entries */
1869 unsigned used; /* number currently used */
1870 unsigned long *used_bitmap;
1871 struct efx_farch_filter_spec *spec;
1872 unsigned search_limit[EFX_FARCH_FILTER_TYPE_COUNT];
1873 };
1874
1875 struct efx_farch_filter_state {
1876 struct efx_farch_filter_table table[EFX_FARCH_FILTER_TABLE_COUNT];
1877 };
1878
1879 static void
1880 efx_farch_filter_table_clear_entry(struct efx_nic *efx,
1881 struct efx_farch_filter_table *table,
1882 unsigned int filter_idx);
1883
1884 /* The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit
1885 * key derived from the n-tuple. The initial LFSR state is 0xffff. */
1886 static u16 efx_farch_filter_hash(u32 key)
1887 {
1888 u16 tmp;
1889
1890 /* First 16 rounds */
1891 tmp = 0x1fff ^ key >> 16;
1892 tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
1893 tmp = tmp ^ tmp >> 9;
1894 /* Last 16 rounds */
1895 tmp = tmp ^ tmp << 13 ^ key;
1896 tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
1897 return tmp ^ tmp >> 9;
1898 }
1899
1900 /* To allow for hash collisions, filter search continues at these
1901 * increments from the first possible entry selected by the hash. */
1902 static u16 efx_farch_filter_increment(u32 key)
1903 {
1904 return key * 2 - 1;
1905 }
1906
1907 static enum efx_farch_filter_table_id
1908 efx_farch_filter_spec_table_id(const struct efx_farch_filter_spec *spec)
1909 {
1910 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1911 (EFX_FARCH_FILTER_TCP_FULL >> 2));
1912 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1913 (EFX_FARCH_FILTER_TCP_WILD >> 2));
1914 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1915 (EFX_FARCH_FILTER_UDP_FULL >> 2));
1916 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1917 (EFX_FARCH_FILTER_UDP_WILD >> 2));
1918 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC !=
1919 (EFX_FARCH_FILTER_MAC_FULL >> 2));
1920 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC !=
1921 (EFX_FARCH_FILTER_MAC_WILD >> 2));
1922 BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_TX_MAC !=
1923 EFX_FARCH_FILTER_TABLE_RX_MAC + 2);
1924 return (spec->type >> 2) + ((spec->flags & EFX_FILTER_FLAG_TX) ? 2 : 0);
1925 }
1926
1927 static void efx_farch_filter_push_rx_config(struct efx_nic *efx)
1928 {
1929 struct efx_farch_filter_state *state = efx->filter_state;
1930 struct efx_farch_filter_table *table;
1931 efx_oword_t filter_ctl;
1932
1933 efx_reado(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
1934
1935 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
1936 EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_FULL_SRCH_LIMIT,
1937 table->search_limit[EFX_FARCH_FILTER_TCP_FULL] +
1938 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1939 EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_WILD_SRCH_LIMIT,
1940 table->search_limit[EFX_FARCH_FILTER_TCP_WILD] +
1941 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1942 EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_FULL_SRCH_LIMIT,
1943 table->search_limit[EFX_FARCH_FILTER_UDP_FULL] +
1944 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1945 EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_WILD_SRCH_LIMIT,
1946 table->search_limit[EFX_FARCH_FILTER_UDP_WILD] +
1947 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1948
1949 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC];
1950 if (table->size) {
1951 EFX_SET_OWORD_FIELD(
1952 filter_ctl, FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT,
1953 table->search_limit[EFX_FARCH_FILTER_MAC_FULL] +
1954 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1955 EFX_SET_OWORD_FIELD(
1956 filter_ctl, FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT,
1957 table->search_limit[EFX_FARCH_FILTER_MAC_WILD] +
1958 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1959 }
1960
1961 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
1962 if (table->size) {
1963 EFX_SET_OWORD_FIELD(
1964 filter_ctl, FRF_CZ_UNICAST_NOMATCH_Q_ID,
1965 table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].dmaq_id);
1966 EFX_SET_OWORD_FIELD(
1967 filter_ctl, FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED,
1968 !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags &
1969 EFX_FILTER_FLAG_RX_RSS));
1970 EFX_SET_OWORD_FIELD(
1971 filter_ctl, FRF_CZ_MULTICAST_NOMATCH_Q_ID,
1972 table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].dmaq_id);
1973 EFX_SET_OWORD_FIELD(
1974 filter_ctl, FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED,
1975 !!(table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags &
1976 EFX_FILTER_FLAG_RX_RSS));
1977
1978 /* There is a single bit to enable RX scatter for all
1979 * unmatched packets. Only set it if scatter is
1980 * enabled in both filter specs.
1981 */
1982 EFX_SET_OWORD_FIELD(
1983 filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q,
1984 !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags &
1985 table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags &
1986 EFX_FILTER_FLAG_RX_SCATTER));
1987 } else if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1988 /* We don't expose 'default' filters because unmatched
1989 * packets always go to the queue number found in the
1990 * RSS table. But we still need to set the RX scatter
1991 * bit here.
1992 */
1993 EFX_SET_OWORD_FIELD(
1994 filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q,
1995 efx->rx_scatter);
1996 }
1997
1998 efx_writeo(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
1999 }
2000
2001 static void efx_farch_filter_push_tx_limits(struct efx_nic *efx)
2002 {
2003 struct efx_farch_filter_state *state = efx->filter_state;
2004 struct efx_farch_filter_table *table;
2005 efx_oword_t tx_cfg;
2006
2007 efx_reado(efx, &tx_cfg, FR_AZ_TX_CFG);
2008
2009 table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC];
2010 if (table->size) {
2011 EFX_SET_OWORD_FIELD(
2012 tx_cfg, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE,
2013 table->search_limit[EFX_FARCH_FILTER_MAC_FULL] +
2014 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
2015 EFX_SET_OWORD_FIELD(
2016 tx_cfg, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE,
2017 table->search_limit[EFX_FARCH_FILTER_MAC_WILD] +
2018 EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
2019 }
2020
2021 efx_writeo(efx, &tx_cfg, FR_AZ_TX_CFG);
2022 }
2023
2024 static int
2025 efx_farch_filter_from_gen_spec(struct efx_farch_filter_spec *spec,
2026 const struct efx_filter_spec *gen_spec)
2027 {
2028 bool is_full = false;
2029
2030 if ((gen_spec->flags & EFX_FILTER_FLAG_RX_RSS) &&
2031 gen_spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT)
2032 return -EINVAL;
2033
2034 spec->priority = gen_spec->priority;
2035 spec->flags = gen_spec->flags;
2036 spec->dmaq_id = gen_spec->dmaq_id;
2037
2038 switch (gen_spec->match_flags) {
2039 case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
2040 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
2041 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT):
2042 is_full = true;
2043 /* fall through */
2044 case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
2045 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT): {
2046 __be32 rhost, host1, host2;
2047 __be16 rport, port1, port2;
2048
2049 EFX_BUG_ON_PARANOID(!(gen_spec->flags & EFX_FILTER_FLAG_RX));
2050
2051 if (gen_spec->ether_type != htons(ETH_P_IP))
2052 return -EPROTONOSUPPORT;
2053 if (gen_spec->loc_port == 0 ||
2054 (is_full && gen_spec->rem_port == 0))
2055 return -EADDRNOTAVAIL;
2056 switch (gen_spec->ip_proto) {
2057 case IPPROTO_TCP:
2058 spec->type = (is_full ? EFX_FARCH_FILTER_TCP_FULL :
2059 EFX_FARCH_FILTER_TCP_WILD);
2060 break;
2061 case IPPROTO_UDP:
2062 spec->type = (is_full ? EFX_FARCH_FILTER_UDP_FULL :
2063 EFX_FARCH_FILTER_UDP_WILD);
2064 break;
2065 default:
2066 return -EPROTONOSUPPORT;
2067 }
2068
2069 /* Filter is constructed in terms of source and destination,
2070 * with the odd wrinkle that the ports are swapped in a UDP
2071 * wildcard filter. We need to convert from local and remote
2072 * (= zero for wildcard) addresses.
2073 */
2074 rhost = is_full ? gen_spec->rem_host[0] : 0;
2075 rport = is_full ? gen_spec->rem_port : 0;
2076 host1 = rhost;
2077 host2 = gen_spec->loc_host[0];
2078 if (!is_full && gen_spec->ip_proto == IPPROTO_UDP) {
2079 port1 = gen_spec->loc_port;
2080 port2 = rport;
2081 } else {
2082 port1 = rport;
2083 port2 = gen_spec->loc_port;
2084 }
2085 spec->data[0] = ntohl(host1) << 16 | ntohs(port1);
2086 spec->data[1] = ntohs(port2) << 16 | ntohl(host1) >> 16;
2087 spec->data[2] = ntohl(host2);
2088
2089 break;
2090 }
2091
2092 case EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_OUTER_VID:
2093 is_full = true;
2094 /* fall through */
2095 case EFX_FILTER_MATCH_LOC_MAC:
2096 spec->type = (is_full ? EFX_FARCH_FILTER_MAC_FULL :
2097 EFX_FARCH_FILTER_MAC_WILD);
2098 spec->data[0] = is_full ? ntohs(gen_spec->outer_vid) : 0;
2099 spec->data[1] = (gen_spec->loc_mac[2] << 24 |
2100 gen_spec->loc_mac[3] << 16 |
2101 gen_spec->loc_mac[4] << 8 |
2102 gen_spec->loc_mac[5]);
2103 spec->data[2] = (gen_spec->loc_mac[0] << 8 |
2104 gen_spec->loc_mac[1]);
2105 break;
2106
2107 case EFX_FILTER_MATCH_LOC_MAC_IG:
2108 spec->type = (is_multicast_ether_addr(gen_spec->loc_mac) ?
2109 EFX_FARCH_FILTER_MC_DEF :
2110 EFX_FARCH_FILTER_UC_DEF);
2111 memset(spec->data, 0, sizeof(spec->data)); /* ensure equality */
2112 break;
2113
2114 default:
2115 return -EPROTONOSUPPORT;
2116 }
2117
2118 return 0;
2119 }
2120
2121 static void
2122 efx_farch_filter_to_gen_spec(struct efx_filter_spec *gen_spec,
2123 const struct efx_farch_filter_spec *spec)
2124 {
2125 bool is_full = false;
2126
2127 /* *gen_spec should be completely initialised, to be consistent
2128 * with efx_filter_init_{rx,tx}() and in case we want to copy
2129 * it back to userland.
2130 */
2131 memset(gen_spec, 0, sizeof(*gen_spec));
2132
2133 gen_spec->priority = spec->priority;
2134 gen_spec->flags = spec->flags;
2135 gen_spec->dmaq_id = spec->dmaq_id;
2136
2137 switch (spec->type) {
2138 case EFX_FARCH_FILTER_TCP_FULL:
2139 case EFX_FARCH_FILTER_UDP_FULL:
2140 is_full = true;
2141 /* fall through */
2142 case EFX_FARCH_FILTER_TCP_WILD:
2143 case EFX_FARCH_FILTER_UDP_WILD: {
2144 __be32 host1, host2;
2145 __be16 port1, port2;
2146
2147 gen_spec->match_flags =
2148 EFX_FILTER_MATCH_ETHER_TYPE |
2149 EFX_FILTER_MATCH_IP_PROTO |
2150 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
2151 if (is_full)
2152 gen_spec->match_flags |= (EFX_FILTER_MATCH_REM_HOST |
2153 EFX_FILTER_MATCH_REM_PORT);
2154 gen_spec->ether_type = htons(ETH_P_IP);
2155 gen_spec->ip_proto =
2156 (spec->type == EFX_FARCH_FILTER_TCP_FULL ||
2157 spec->type == EFX_FARCH_FILTER_TCP_WILD) ?
2158 IPPROTO_TCP : IPPROTO_UDP;
2159
2160 host1 = htonl(spec->data[0] >> 16 | spec->data[1] << 16);
2161 port1 = htons(spec->data[0]);
2162 host2 = htonl(spec->data[2]);
2163 port2 = htons(spec->data[1] >> 16);
2164 if (spec->flags & EFX_FILTER_FLAG_TX) {
2165 gen_spec->loc_host[0] = host1;
2166 gen_spec->rem_host[0] = host2;
2167 } else {
2168 gen_spec->loc_host[0] = host2;
2169 gen_spec->rem_host[0] = host1;
2170 }
2171 if (!!(gen_spec->flags & EFX_FILTER_FLAG_TX) ^
2172 (!is_full && gen_spec->ip_proto == IPPROTO_UDP)) {
2173 gen_spec->loc_port = port1;
2174 gen_spec->rem_port = port2;
2175 } else {
2176 gen_spec->loc_port = port2;
2177 gen_spec->rem_port = port1;
2178 }
2179
2180 break;
2181 }
2182
2183 case EFX_FARCH_FILTER_MAC_FULL:
2184 is_full = true;
2185 /* fall through */
2186 case EFX_FARCH_FILTER_MAC_WILD:
2187 gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC;
2188 if (is_full)
2189 gen_spec->match_flags |= EFX_FILTER_MATCH_OUTER_VID;
2190 gen_spec->loc_mac[0] = spec->data[2] >> 8;
2191 gen_spec->loc_mac[1] = spec->data[2];
2192 gen_spec->loc_mac[2] = spec->data[1] >> 24;
2193 gen_spec->loc_mac[3] = spec->data[1] >> 16;
2194 gen_spec->loc_mac[4] = spec->data[1] >> 8;
2195 gen_spec->loc_mac[5] = spec->data[1];
2196 gen_spec->outer_vid = htons(spec->data[0]);
2197 break;
2198
2199 case EFX_FARCH_FILTER_UC_DEF:
2200 case EFX_FARCH_FILTER_MC_DEF:
2201 gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC_IG;
2202 gen_spec->loc_mac[0] = spec->type == EFX_FARCH_FILTER_MC_DEF;
2203 break;
2204
2205 default:
2206 WARN_ON(1);
2207 break;
2208 }
2209 }
2210
2211 static void
2212 efx_farch_filter_init_rx_auto(struct efx_nic *efx,
2213 struct efx_farch_filter_spec *spec)
2214 {
2215 /* If there's only one channel then disable RSS for non VF
2216 * traffic, thereby allowing VFs to use RSS when the PF can't.
2217 */
2218 spec->priority = EFX_FILTER_PRI_AUTO;
2219 spec->flags = (EFX_FILTER_FLAG_RX |
2220 (efx->n_rx_channels > 1 ? EFX_FILTER_FLAG_RX_RSS : 0) |
2221 (efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0));
2222 spec->dmaq_id = 0;
2223 }
2224
2225 /* Build a filter entry and return its n-tuple key. */
2226 static u32 efx_farch_filter_build(efx_oword_t *filter,
2227 struct efx_farch_filter_spec *spec)
2228 {
2229 u32 data3;
2230
2231 switch (efx_farch_filter_spec_table_id(spec)) {
2232 case EFX_FARCH_FILTER_TABLE_RX_IP: {
2233 bool is_udp = (spec->type == EFX_FARCH_FILTER_UDP_FULL ||
2234 spec->type == EFX_FARCH_FILTER_UDP_WILD);
2235 EFX_POPULATE_OWORD_7(
2236 *filter,
2237 FRF_BZ_RSS_EN,
2238 !!(spec->flags & EFX_FILTER_FLAG_RX_RSS),
2239 FRF_BZ_SCATTER_EN,
2240 !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER),
2241 FRF_BZ_TCP_UDP, is_udp,
2242 FRF_BZ_RXQ_ID, spec->dmaq_id,
2243 EFX_DWORD_2, spec->data[2],
2244 EFX_DWORD_1, spec->data[1],
2245 EFX_DWORD_0, spec->data[0]);
2246 data3 = is_udp;
2247 break;
2248 }
2249
2250 case EFX_FARCH_FILTER_TABLE_RX_MAC: {
2251 bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD;
2252 EFX_POPULATE_OWORD_7(
2253 *filter,
2254 FRF_CZ_RMFT_RSS_EN,
2255 !!(spec->flags & EFX_FILTER_FLAG_RX_RSS),
2256 FRF_CZ_RMFT_SCATTER_EN,
2257 !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER),
2258 FRF_CZ_RMFT_RXQ_ID, spec->dmaq_id,
2259 FRF_CZ_RMFT_WILDCARD_MATCH, is_wild,
2260 FRF_CZ_RMFT_DEST_MAC_HI, spec->data[2],
2261 FRF_CZ_RMFT_DEST_MAC_LO, spec->data[1],
2262 FRF_CZ_RMFT_VLAN_ID, spec->data[0]);
2263 data3 = is_wild;
2264 break;
2265 }
2266
2267 case EFX_FARCH_FILTER_TABLE_TX_MAC: {
2268 bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD;
2269 EFX_POPULATE_OWORD_5(*filter,
2270 FRF_CZ_TMFT_TXQ_ID, spec->dmaq_id,
2271 FRF_CZ_TMFT_WILDCARD_MATCH, is_wild,
2272 FRF_CZ_TMFT_SRC_MAC_HI, spec->data[2],
2273 FRF_CZ_TMFT_SRC_MAC_LO, spec->data[1],
2274 FRF_CZ_TMFT_VLAN_ID, spec->data[0]);
2275 data3 = is_wild | spec->dmaq_id << 1;
2276 break;
2277 }
2278
2279 default:
2280 BUG();
2281 }
2282
2283 return spec->data[0] ^ spec->data[1] ^ spec->data[2] ^ data3;
2284 }
2285
2286 static bool efx_farch_filter_equal(const struct efx_farch_filter_spec *left,
2287 const struct efx_farch_filter_spec *right)
2288 {
2289 if (left->type != right->type ||
2290 memcmp(left->data, right->data, sizeof(left->data)))
2291 return false;
2292
2293 if (left->flags & EFX_FILTER_FLAG_TX &&
2294 left->dmaq_id != right->dmaq_id)
2295 return false;
2296
2297 return true;
2298 }
2299
2300 /*
2301 * Construct/deconstruct external filter IDs. At least the RX filter
2302 * IDs must be ordered by matching priority, for RX NFC semantics.
2303 *
2304 * Deconstruction needs to be robust against invalid IDs so that
2305 * efx_filter_remove_id_safe() and efx_filter_get_filter_safe() can
2306 * accept user-provided IDs.
2307 */
2308
2309 #define EFX_FARCH_FILTER_MATCH_PRI_COUNT 5
2310
2311 static const u8 efx_farch_filter_type_match_pri[EFX_FARCH_FILTER_TYPE_COUNT] = {
2312 [EFX_FARCH_FILTER_TCP_FULL] = 0,
2313 [EFX_FARCH_FILTER_UDP_FULL] = 0,
2314 [EFX_FARCH_FILTER_TCP_WILD] = 1,
2315 [EFX_FARCH_FILTER_UDP_WILD] = 1,
2316 [EFX_FARCH_FILTER_MAC_FULL] = 2,
2317 [EFX_FARCH_FILTER_MAC_WILD] = 3,
2318 [EFX_FARCH_FILTER_UC_DEF] = 4,
2319 [EFX_FARCH_FILTER_MC_DEF] = 4,
2320 };
2321
2322 static const enum efx_farch_filter_table_id efx_farch_filter_range_table[] = {
2323 EFX_FARCH_FILTER_TABLE_RX_IP, /* RX match pri 0 */
2324 EFX_FARCH_FILTER_TABLE_RX_IP,
2325 EFX_FARCH_FILTER_TABLE_RX_MAC,
2326 EFX_FARCH_FILTER_TABLE_RX_MAC,
2327 EFX_FARCH_FILTER_TABLE_RX_DEF, /* RX match pri 4 */
2328 EFX_FARCH_FILTER_TABLE_TX_MAC, /* TX match pri 0 */
2329 EFX_FARCH_FILTER_TABLE_TX_MAC, /* TX match pri 1 */
2330 };
2331
2332 #define EFX_FARCH_FILTER_INDEX_WIDTH 13
2333 #define EFX_FARCH_FILTER_INDEX_MASK ((1 << EFX_FARCH_FILTER_INDEX_WIDTH) - 1)
2334
2335 static inline u32
2336 efx_farch_filter_make_id(const struct efx_farch_filter_spec *spec,
2337 unsigned int index)
2338 {
2339 unsigned int range;
2340
2341 range = efx_farch_filter_type_match_pri[spec->type];
2342 if (!(spec->flags & EFX_FILTER_FLAG_RX))
2343 range += EFX_FARCH_FILTER_MATCH_PRI_COUNT;
2344
2345 return range << EFX_FARCH_FILTER_INDEX_WIDTH | index;
2346 }
2347
2348 static inline enum efx_farch_filter_table_id
2349 efx_farch_filter_id_table_id(u32 id)
2350 {
2351 unsigned int range = id >> EFX_FARCH_FILTER_INDEX_WIDTH;
2352
2353 if (range < ARRAY_SIZE(efx_farch_filter_range_table))
2354 return efx_farch_filter_range_table[range];
2355 else
2356 return EFX_FARCH_FILTER_TABLE_COUNT; /* invalid */
2357 }
2358
2359 static inline unsigned int efx_farch_filter_id_index(u32 id)
2360 {
2361 return id & EFX_FARCH_FILTER_INDEX_MASK;
2362 }
2363
2364 u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx)
2365 {
2366 struct efx_farch_filter_state *state = efx->filter_state;
2367 unsigned int range = EFX_FARCH_FILTER_MATCH_PRI_COUNT - 1;
2368 enum efx_farch_filter_table_id table_id;
2369
2370 do {
2371 table_id = efx_farch_filter_range_table[range];
2372 if (state->table[table_id].size != 0)
2373 return range << EFX_FARCH_FILTER_INDEX_WIDTH |
2374 state->table[table_id].size;
2375 } while (range--);
2376
2377 return 0;
2378 }
2379
2380 s32 efx_farch_filter_insert(struct efx_nic *efx,
2381 struct efx_filter_spec *gen_spec,
2382 bool replace_equal)
2383 {
2384 struct efx_farch_filter_state *state = efx->filter_state;
2385 struct efx_farch_filter_table *table;
2386 struct efx_farch_filter_spec spec;
2387 efx_oword_t filter;
2388 int rep_index, ins_index;
2389 unsigned int depth = 0;
2390 int rc;
2391
2392 rc = efx_farch_filter_from_gen_spec(&spec, gen_spec);
2393 if (rc)
2394 return rc;
2395
2396 table = &state->table[efx_farch_filter_spec_table_id(&spec)];
2397 if (table->size == 0)
2398 return -EINVAL;
2399
2400 netif_vdbg(efx, hw, efx->net_dev,
2401 "%s: type %d search_limit=%d", __func__, spec.type,
2402 table->search_limit[spec.type]);
2403
2404 if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) {
2405 /* One filter spec per type */
2406 BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_UC_DEF != 0);
2407 BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_MC_DEF !=
2408 EFX_FARCH_FILTER_MC_DEF - EFX_FARCH_FILTER_UC_DEF);
2409 rep_index = spec.type - EFX_FARCH_FILTER_UC_DEF;
2410 ins_index = rep_index;
2411
2412 spin_lock_bh(&efx->filter_lock);
2413 } else {
2414 /* Search concurrently for
2415 * (1) a filter to be replaced (rep_index): any filter
2416 * with the same match values, up to the current
2417 * search depth for this type, and
2418 * (2) the insertion point (ins_index): (1) or any
2419 * free slot before it or up to the maximum search
2420 * depth for this priority
2421 * We fail if we cannot find (2).
2422 *
2423 * We can stop once either
2424 * (a) we find (1), in which case we have definitely
2425 * found (2) as well; or
2426 * (b) we have searched exhaustively for (1), and have
2427 * either found (2) or searched exhaustively for it
2428 */
2429 u32 key = efx_farch_filter_build(&filter, &spec);
2430 unsigned int hash = efx_farch_filter_hash(key);
2431 unsigned int incr = efx_farch_filter_increment(key);
2432 unsigned int max_rep_depth = table->search_limit[spec.type];
2433 unsigned int max_ins_depth =
2434 spec.priority <= EFX_FILTER_PRI_HINT ?
2435 EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX :
2436 EFX_FARCH_FILTER_CTL_SRCH_MAX;
2437 unsigned int i = hash & (table->size - 1);
2438
2439 ins_index = -1;
2440 depth = 1;
2441
2442 spin_lock_bh(&efx->filter_lock);
2443
2444 for (;;) {
2445 if (!test_bit(i, table->used_bitmap)) {
2446 if (ins_index < 0)
2447 ins_index = i;
2448 } else if (efx_farch_filter_equal(&spec,
2449 &table->spec[i])) {
2450 /* Case (a) */
2451 if (ins_index < 0)
2452 ins_index = i;
2453 rep_index = i;
2454 break;
2455 }
2456
2457 if (depth >= max_rep_depth &&
2458 (ins_index >= 0 || depth >= max_ins_depth)) {
2459 /* Case (b) */
2460 if (ins_index < 0) {
2461 rc = -EBUSY;
2462 goto out;
2463 }
2464 rep_index = -1;
2465 break;
2466 }
2467
2468 i = (i + incr) & (table->size - 1);
2469 ++depth;
2470 }
2471 }
2472
2473 /* If we found a filter to be replaced, check whether we
2474 * should do so
2475 */
2476 if (rep_index >= 0) {
2477 struct efx_farch_filter_spec *saved_spec =
2478 &table->spec[rep_index];
2479
2480 if (spec.priority == saved_spec->priority && !replace_equal) {
2481 rc = -EEXIST;
2482 goto out;
2483 }
2484 if (spec.priority < saved_spec->priority) {
2485 rc = -EPERM;
2486 goto out;
2487 }
2488 if (saved_spec->priority == EFX_FILTER_PRI_AUTO ||
2489 saved_spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO)
2490 spec.flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
2491 }
2492
2493 /* Insert the filter */
2494 if (ins_index != rep_index) {
2495 __set_bit(ins_index, table->used_bitmap);
2496 ++table->used;
2497 }
2498 table->spec[ins_index] = spec;
2499
2500 if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) {
2501 efx_farch_filter_push_rx_config(efx);
2502 } else {
2503 if (table->search_limit[spec.type] < depth) {
2504 table->search_limit[spec.type] = depth;
2505 if (spec.flags & EFX_FILTER_FLAG_TX)
2506 efx_farch_filter_push_tx_limits(efx);
2507 else
2508 efx_farch_filter_push_rx_config(efx);
2509 }
2510
2511 efx_writeo(efx, &filter,
2512 table->offset + table->step * ins_index);
2513
2514 /* If we were able to replace a filter by inserting
2515 * at a lower depth, clear the replaced filter
2516 */
2517 if (ins_index != rep_index && rep_index >= 0)
2518 efx_farch_filter_table_clear_entry(efx, table,
2519 rep_index);
2520 }
2521
2522 netif_vdbg(efx, hw, efx->net_dev,
2523 "%s: filter type %d index %d rxq %u set",
2524 __func__, spec.type, ins_index, spec.dmaq_id);
2525 rc = efx_farch_filter_make_id(&spec, ins_index);
2526
2527 out:
2528 spin_unlock_bh(&efx->filter_lock);
2529 return rc;
2530 }
2531
2532 static void
2533 efx_farch_filter_table_clear_entry(struct efx_nic *efx,
2534 struct efx_farch_filter_table *table,
2535 unsigned int filter_idx)
2536 {
2537 static efx_oword_t filter;
2538
2539 EFX_WARN_ON_PARANOID(!test_bit(filter_idx, table->used_bitmap));
2540 BUG_ON(table->offset == 0); /* can't clear MAC default filters */
2541
2542 __clear_bit(filter_idx, table->used_bitmap);
2543 --table->used;
2544 memset(&table->spec[filter_idx], 0, sizeof(table->spec[0]));
2545
2546 efx_writeo(efx, &filter, table->offset + table->step * filter_idx);
2547
2548 /* If this filter required a greater search depth than
2549 * any other, the search limit for its type can now be
2550 * decreased. However, it is hard to determine that
2551 * unless the table has become completely empty - in
2552 * which case, all its search limits can be set to 0.
2553 */
2554 if (unlikely(table->used == 0)) {
2555 memset(table->search_limit, 0, sizeof(table->search_limit));
2556 if (table->id == EFX_FARCH_FILTER_TABLE_TX_MAC)
2557 efx_farch_filter_push_tx_limits(efx);
2558 else
2559 efx_farch_filter_push_rx_config(efx);
2560 }
2561 }
2562
2563 static int efx_farch_filter_remove(struct efx_nic *efx,
2564 struct efx_farch_filter_table *table,
2565 unsigned int filter_idx,
2566 enum efx_filter_priority priority)
2567 {
2568 struct efx_farch_filter_spec *spec = &table->spec[filter_idx];
2569
2570 if (!test_bit(filter_idx, table->used_bitmap) ||
2571 spec->priority != priority)
2572 return -ENOENT;
2573
2574 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
2575 efx_farch_filter_init_rx_auto(efx, spec);
2576 efx_farch_filter_push_rx_config(efx);
2577 } else {
2578 efx_farch_filter_table_clear_entry(efx, table, filter_idx);
2579 }
2580
2581 return 0;
2582 }
2583
2584 int efx_farch_filter_remove_safe(struct efx_nic *efx,
2585 enum efx_filter_priority priority,
2586 u32 filter_id)
2587 {
2588 struct efx_farch_filter_state *state = efx->filter_state;
2589 enum efx_farch_filter_table_id table_id;
2590 struct efx_farch_filter_table *table;
2591 unsigned int filter_idx;
2592 struct efx_farch_filter_spec *spec;
2593 int rc;
2594
2595 table_id = efx_farch_filter_id_table_id(filter_id);
2596 if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT)
2597 return -ENOENT;
2598 table = &state->table[table_id];
2599
2600 filter_idx = efx_farch_filter_id_index(filter_id);
2601 if (filter_idx >= table->size)
2602 return -ENOENT;
2603 spec = &table->spec[filter_idx];
2604
2605 spin_lock_bh(&efx->filter_lock);
2606 rc = efx_farch_filter_remove(efx, table, filter_idx, priority);
2607 spin_unlock_bh(&efx->filter_lock);
2608
2609 return rc;
2610 }
2611
2612 int efx_farch_filter_get_safe(struct efx_nic *efx,
2613 enum efx_filter_priority priority,
2614 u32 filter_id, struct efx_filter_spec *spec_buf)
2615 {
2616 struct efx_farch_filter_state *state = efx->filter_state;
2617 enum efx_farch_filter_table_id table_id;
2618 struct efx_farch_filter_table *table;
2619 struct efx_farch_filter_spec *spec;
2620 unsigned int filter_idx;
2621 int rc;
2622
2623 table_id = efx_farch_filter_id_table_id(filter_id);
2624 if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT)
2625 return -ENOENT;
2626 table = &state->table[table_id];
2627
2628 filter_idx = efx_farch_filter_id_index(filter_id);
2629 if (filter_idx >= table->size)
2630 return -ENOENT;
2631 spec = &table->spec[filter_idx];
2632
2633 spin_lock_bh(&efx->filter_lock);
2634
2635 if (test_bit(filter_idx, table->used_bitmap) &&
2636 spec->priority == priority) {
2637 efx_farch_filter_to_gen_spec(spec_buf, spec);
2638 rc = 0;
2639 } else {
2640 rc = -ENOENT;
2641 }
2642
2643 spin_unlock_bh(&efx->filter_lock);
2644
2645 return rc;
2646 }
2647
2648 static void
2649 efx_farch_filter_table_clear(struct efx_nic *efx,
2650 enum efx_farch_filter_table_id table_id,
2651 enum efx_filter_priority priority)
2652 {
2653 struct efx_farch_filter_state *state = efx->filter_state;
2654 struct efx_farch_filter_table *table = &state->table[table_id];
2655 unsigned int filter_idx;
2656
2657 spin_lock_bh(&efx->filter_lock);
2658 for (filter_idx = 0; filter_idx < table->size; ++filter_idx) {
2659 if (table->spec[filter_idx].priority != EFX_FILTER_PRI_AUTO)
2660 efx_farch_filter_remove(efx, table,
2661 filter_idx, priority);
2662 }
2663 spin_unlock_bh(&efx->filter_lock);
2664 }
2665
2666 int efx_farch_filter_clear_rx(struct efx_nic *efx,
2667 enum efx_filter_priority priority)
2668 {
2669 efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_IP,
2670 priority);
2671 efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_MAC,
2672 priority);
2673 efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_DEF,
2674 priority);
2675 return 0;
2676 }
2677
2678 u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
2679 enum efx_filter_priority priority)
2680 {
2681 struct efx_farch_filter_state *state = efx->filter_state;
2682 enum efx_farch_filter_table_id table_id;
2683 struct efx_farch_filter_table *table;
2684 unsigned int filter_idx;
2685 u32 count = 0;
2686
2687 spin_lock_bh(&efx->filter_lock);
2688
2689 for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2690 table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2691 table_id++) {
2692 table = &state->table[table_id];
2693 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2694 if (test_bit(filter_idx, table->used_bitmap) &&
2695 table->spec[filter_idx].priority == priority)
2696 ++count;
2697 }
2698 }
2699
2700 spin_unlock_bh(&efx->filter_lock);
2701
2702 return count;
2703 }
2704
2705 s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
2706 enum efx_filter_priority priority,
2707 u32 *buf, u32 size)
2708 {
2709 struct efx_farch_filter_state *state = efx->filter_state;
2710 enum efx_farch_filter_table_id table_id;
2711 struct efx_farch_filter_table *table;
2712 unsigned int filter_idx;
2713 s32 count = 0;
2714
2715 spin_lock_bh(&efx->filter_lock);
2716
2717 for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2718 table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2719 table_id++) {
2720 table = &state->table[table_id];
2721 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2722 if (test_bit(filter_idx, table->used_bitmap) &&
2723 table->spec[filter_idx].priority == priority) {
2724 if (count == size) {
2725 count = -EMSGSIZE;
2726 goto out;
2727 }
2728 buf[count++] = efx_farch_filter_make_id(
2729 &table->spec[filter_idx], filter_idx);
2730 }
2731 }
2732 }
2733 out:
2734 spin_unlock_bh(&efx->filter_lock);
2735
2736 return count;
2737 }
2738
2739 /* Restore filter stater after reset */
2740 void efx_farch_filter_table_restore(struct efx_nic *efx)
2741 {
2742 struct efx_farch_filter_state *state = efx->filter_state;
2743 enum efx_farch_filter_table_id table_id;
2744 struct efx_farch_filter_table *table;
2745 efx_oword_t filter;
2746 unsigned int filter_idx;
2747
2748 spin_lock_bh(&efx->filter_lock);
2749
2750 for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2751 table = &state->table[table_id];
2752
2753 /* Check whether this is a regular register table */
2754 if (table->step == 0)
2755 continue;
2756
2757 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2758 if (!test_bit(filter_idx, table->used_bitmap))
2759 continue;
2760 efx_farch_filter_build(&filter, &table->spec[filter_idx]);
2761 efx_writeo(efx, &filter,
2762 table->offset + table->step * filter_idx);
2763 }
2764 }
2765
2766 efx_farch_filter_push_rx_config(efx);
2767 efx_farch_filter_push_tx_limits(efx);
2768
2769 spin_unlock_bh(&efx->filter_lock);
2770 }
2771
2772 void efx_farch_filter_table_remove(struct efx_nic *efx)
2773 {
2774 struct efx_farch_filter_state *state = efx->filter_state;
2775 enum efx_farch_filter_table_id table_id;
2776
2777 for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2778 kfree(state->table[table_id].used_bitmap);
2779 vfree(state->table[table_id].spec);
2780 }
2781 kfree(state);
2782 }
2783
2784 int efx_farch_filter_table_probe(struct efx_nic *efx)
2785 {
2786 struct efx_farch_filter_state *state;
2787 struct efx_farch_filter_table *table;
2788 unsigned table_id;
2789
2790 state = kzalloc(sizeof(struct efx_farch_filter_state), GFP_KERNEL);
2791 if (!state)
2792 return -ENOMEM;
2793 efx->filter_state = state;
2794
2795 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
2796 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
2797 table->id = EFX_FARCH_FILTER_TABLE_RX_IP;
2798 table->offset = FR_BZ_RX_FILTER_TBL0;
2799 table->size = FR_BZ_RX_FILTER_TBL0_ROWS;
2800 table->step = FR_BZ_RX_FILTER_TBL0_STEP;
2801 }
2802
2803 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
2804 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC];
2805 table->id = EFX_FARCH_FILTER_TABLE_RX_MAC;
2806 table->offset = FR_CZ_RX_MAC_FILTER_TBL0;
2807 table->size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS;
2808 table->step = FR_CZ_RX_MAC_FILTER_TBL0_STEP;
2809
2810 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
2811 table->id = EFX_FARCH_FILTER_TABLE_RX_DEF;
2812 table->size = EFX_FARCH_FILTER_SIZE_RX_DEF;
2813
2814 table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC];
2815 table->id = EFX_FARCH_FILTER_TABLE_TX_MAC;
2816 table->offset = FR_CZ_TX_MAC_FILTER_TBL0;
2817 table->size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS;
2818 table->step = FR_CZ_TX_MAC_FILTER_TBL0_STEP;
2819 }
2820
2821 for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2822 table = &state->table[table_id];
2823 if (table->size == 0)
2824 continue;
2825 table->used_bitmap = kcalloc(BITS_TO_LONGS(table->size),
2826 sizeof(unsigned long),
2827 GFP_KERNEL);
2828 if (!table->used_bitmap)
2829 goto fail;
2830 table->spec = vzalloc(table->size * sizeof(*table->spec));
2831 if (!table->spec)
2832 goto fail;
2833 }
2834
2835 table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
2836 if (table->size) {
2837 /* RX default filters must always exist */
2838 struct efx_farch_filter_spec *spec;
2839 unsigned i;
2840
2841 for (i = 0; i < EFX_FARCH_FILTER_SIZE_RX_DEF; i++) {
2842 spec = &table->spec[i];
2843 spec->type = EFX_FARCH_FILTER_UC_DEF + i;
2844 efx_farch_filter_init_rx_auto(efx, spec);
2845 __set_bit(i, table->used_bitmap);
2846 }
2847 }
2848
2849 efx_farch_filter_push_rx_config(efx);
2850
2851 return 0;
2852
2853 fail:
2854 efx_farch_filter_table_remove(efx);
2855 return -ENOMEM;
2856 }
2857
2858 /* Update scatter enable flags for filters pointing to our own RX queues */
2859 void efx_farch_filter_update_rx_scatter(struct efx_nic *efx)
2860 {
2861 struct efx_farch_filter_state *state = efx->filter_state;
2862 enum efx_farch_filter_table_id table_id;
2863 struct efx_farch_filter_table *table;
2864 efx_oword_t filter;
2865 unsigned int filter_idx;
2866
2867 spin_lock_bh(&efx->filter_lock);
2868
2869 for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2870 table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2871 table_id++) {
2872 table = &state->table[table_id];
2873
2874 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2875 if (!test_bit(filter_idx, table->used_bitmap) ||
2876 table->spec[filter_idx].dmaq_id >=
2877 efx->n_rx_channels)
2878 continue;
2879
2880 if (efx->rx_scatter)
2881 table->spec[filter_idx].flags |=
2882 EFX_FILTER_FLAG_RX_SCATTER;
2883 else
2884 table->spec[filter_idx].flags &=
2885 ~EFX_FILTER_FLAG_RX_SCATTER;
2886
2887 if (table_id == EFX_FARCH_FILTER_TABLE_RX_DEF)
2888 /* Pushed by efx_farch_filter_push_rx_config() */
2889 continue;
2890
2891 efx_farch_filter_build(&filter, &table->spec[filter_idx]);
2892 efx_writeo(efx, &filter,
2893 table->offset + table->step * filter_idx);
2894 }
2895 }
2896
2897 efx_farch_filter_push_rx_config(efx);
2898
2899 spin_unlock_bh(&efx->filter_lock);
2900 }
2901
2902 #ifdef CONFIG_RFS_ACCEL
2903
2904 s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
2905 struct efx_filter_spec *gen_spec)
2906 {
2907 return efx_farch_filter_insert(efx, gen_spec, true);
2908 }
2909
2910 bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2911 unsigned int index)
2912 {
2913 struct efx_farch_filter_state *state = efx->filter_state;
2914 struct efx_farch_filter_table *table =
2915 &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
2916
2917 if (test_bit(index, table->used_bitmap) &&
2918 table->spec[index].priority == EFX_FILTER_PRI_HINT &&
2919 rps_may_expire_flow(efx->net_dev, table->spec[index].dmaq_id,
2920 flow_id, index)) {
2921 efx_farch_filter_table_clear_entry(efx, table, index);
2922 return true;
2923 }
2924
2925 return false;
2926 }
2927
2928 #endif /* CONFIG_RFS_ACCEL */
2929
2930 void efx_farch_filter_sync_rx_mode(struct efx_nic *efx)
2931 {
2932 struct net_device *net_dev = efx->net_dev;
2933 struct netdev_hw_addr *ha;
2934 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2935 u32 crc;
2936 int bit;
2937
2938 if (!efx_dev_registered(efx))
2939 return;
2940
2941 netif_addr_lock_bh(net_dev);
2942
2943 efx->unicast_filter = !(net_dev->flags & IFF_PROMISC);
2944
2945 /* Build multicast hash table */
2946 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2947 memset(mc_hash, 0xff, sizeof(*mc_hash));
2948 } else {
2949 memset(mc_hash, 0x00, sizeof(*mc_hash));
2950 netdev_for_each_mc_addr(ha, net_dev) {
2951 crc = ether_crc_le(ETH_ALEN, ha->addr);
2952 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
2953 __set_bit_le(bit, mc_hash);
2954 }
2955
2956 /* Broadcast packets go through the multicast hash filter.
2957 * ether_crc_le() of the broadcast address is 0xbe2612ff
2958 * so we always add bit 0xff to the mask.
2959 */
2960 __set_bit_le(0xff, mc_hash);
2961 }
2962
2963 netif_addr_unlock_bh(net_dev);
2964 }
Linux with added FPC-III support