drivers/net/wireless/mwifiex/sdio.h

   1 /*
   2  * Marvell Wireless LAN device driver: SDIO specific definitions
   3  *
   4  * Copyright (C) 2011-2014, Marvell International Ltd.
   5  *
   6  * This software file (the "File") is distributed by Marvell International
   7  * Ltd. under the terms of the GNU General Public License Version 2, June 1991
   8  * (the "License").  You may use, redistribute and/or modify this File in
   9  * accordance with the terms and conditions of the License, a copy of which
  10  * is available by writing to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
  12  * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
  13  *
  14  * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
  17  * this warranty disclaimer.
  18  */
  19
  20 #ifndef _MWIFIEX_SDIO_H
  21 #define _MWIFIEX_SDIO_H
  22
  23
  24 #include <linux/mmc/sdio.h>
  25 #include <linux/mmc/sdio_ids.h>
  26 #include <linux/mmc/sdio_func.h>
  27 #include <linux/mmc/card.h>
  28 #include <linux/mmc/host.h>
  29
  30 #include "main.h"
  31
  32 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
  33 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
  34 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
  35 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
  36 #define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
  37
  38 #define BLOCK_MODE      1
  39 #define BYTE_MODE       0
  40
  41 #define REG_PORT                        0
  42
  43 #define MWIFIEX_SDIO_IO_PORT_MASK               0xfffff
  44
  45 #define MWIFIEX_SDIO_BYTE_MODE_MASK     0x80000000
  46
  47 #define SDIO_MPA_ADDR_BASE              0x1000
  48 #define CTRL_PORT                       0
  49 #define CTRL_PORT_MASK                  0x0001
  50
  51 #define CMD_PORT_UPLD_INT_MASK          (0x1U<<6)
  52 #define CMD_PORT_DNLD_INT_MASK          (0x1U<<7)
  53 #define HOST_TERM_CMD53                 (0x1U << 2)
  54 #define REG_PORT                        0
  55 #define MEM_PORT                        0x10000
  56
  57 #define CMD53_NEW_MODE                  (0x1U << 0)
  58 #define CMD_PORT_RD_LEN_EN              (0x1U << 2)
  59 #define CMD_PORT_AUTO_EN                (0x1U << 0)
  60 #define CMD_PORT_SLCT                   0x8000
  61 #define UP_LD_CMD_PORT_HOST_INT_STATUS  (0x40U)
  62 #define DN_LD_CMD_PORT_HOST_INT_STATUS  (0x80U)
  63
  64 #define MWIFIEX_MP_AGGR_BUF_SIZE_16K    (16384)
  65 #define MWIFIEX_MP_AGGR_BUF_SIZE_32K    (32768)
  66
  67 /* Misc. Config Register : Auto Re-enable interrupts */
  68 #define AUTO_RE_ENABLE_INT              BIT(4)
  69
  70 /* Host Control Registers : Configuration */
  71 #define CONFIGURATION_REG               0x00
  72 /* Host Control Registers : Host power up */
  73 #define HOST_POWER_UP                   (0x1U << 1)
  74
  75 /* Host Control Registers : Upload host interrupt mask */
  76 #define UP_LD_HOST_INT_MASK             (0x1U)
  77 /* Host Control Registers : Download host interrupt mask */
  78 #define DN_LD_HOST_INT_MASK             (0x2U)
  79
  80 /* Host Control Registers : Upload host interrupt status */
  81 #define UP_LD_HOST_INT_STATUS           (0x1U)
  82 /* Host Control Registers : Download host interrupt status */
  83 #define DN_LD_HOST_INT_STATUS           (0x2U)
  84
  85 /* Host Control Registers : Host interrupt status */
  86 #define CARD_INT_STATUS_REG             0x28
  87
  88 /* Card Control Registers : Card I/O ready */
  89 #define CARD_IO_READY                   (0x1U << 3)
  90 /* Card Control Registers : Download card ready */
  91 #define DN_LD_CARD_RDY                  (0x1U << 0)
  92
  93 /* Max retry number of CMD53 write */
  94 #define MAX_WRITE_IOMEM_RETRY           2
  95
  96 /* SDIO Tx aggregation in progress ? */
  97 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
  98
  99 /* SDIO Tx aggregation buffer room for next packet ? */
 100 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len)        \
 101                                                 <= a->mpa_tx.buf_size)
 102
 103 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
 104 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do {              \
 105         memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len],                      \
 106                         payload, pkt_len);                              \
 107         a->mpa_tx.buf_len += pkt_len;                                   \
 108         if (!a->mpa_tx.pkt_cnt)                                         \
 109                 a->mpa_tx.start_port = port;                            \
 110         if (a->mpa_tx.start_port <= port)                               \
 111                 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt));            \
 112         else                                                            \
 113                 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+            \
 114                                                 (a->max_ports - \
 115                                                 a->mp_end_port)));      \
 116         a->mpa_tx.pkt_cnt++;                                            \
 117 } while (0)
 118
 119 /* SDIO Tx aggregation limit ? */
 120 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a)                                 \
 121                         (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
 122
 123 /* Reset SDIO Tx aggregation buffer parameters */
 124 #define MP_TX_AGGR_BUF_RESET(a) do {                                    \
 125         a->mpa_tx.pkt_cnt = 0;                                          \
 126         a->mpa_tx.buf_len = 0;                                          \
 127         a->mpa_tx.ports = 0;                                            \
 128         a->mpa_tx.start_port = 0;                                       \
 129 } while (0)
 130
 131 /* SDIO Rx aggregation limit ? */
 132 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a)                                 \
 133                         (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
 134
 135 /* SDIO Rx aggregation in progress ? */
 136 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
 137
 138 /* SDIO Rx aggregation buffer room for next packet ? */
 139 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len)                              \
 140                         ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
 141
 142 /* Reset SDIO Rx aggregation buffer parameters */
 143 #define MP_RX_AGGR_BUF_RESET(a) do {                                    \
 144         a->mpa_rx.pkt_cnt = 0;                                          \
 145         a->mpa_rx.buf_len = 0;                                          \
 146         a->mpa_rx.ports = 0;                                            \
 147         a->mpa_rx.start_port = 0;                                       \
 148 } while (0)
 149
 150 /* data structure for SDIO MPA TX */
 151 struct mwifiex_sdio_mpa_tx {
 152         /* multiport tx aggregation buffer pointer */
 153         u8 *buf;
 154         u32 buf_len;
 155         u32 pkt_cnt;
 156         u32 ports;
 157         u16 start_port;
 158         u8 enabled;
 159         u32 buf_size;
 160         u32 pkt_aggr_limit;
 161 };
 162
 163 struct mwifiex_sdio_mpa_rx {
 164         u8 *buf;
 165         u32 buf_len;
 166         u32 pkt_cnt;
 167         u32 ports;
 168         u16 start_port;
 169
 170         struct sk_buff **skb_arr;
 171         u32 *len_arr;
 172
 173         u8 enabled;
 174         u32 buf_size;
 175         u32 pkt_aggr_limit;
 176 };
 177
 178 int mwifiex_bus_register(void);
 179 void mwifiex_bus_unregister(void);
 180
 181 struct mwifiex_sdio_card_reg {
 182         u8 start_rd_port;
 183         u8 start_wr_port;
 184         u8 base_0_reg;
 185         u8 base_1_reg;
 186         u8 poll_reg;
 187         u8 host_int_enable;
 188         u8 host_int_rsr_reg;
 189         u8 host_int_status_reg;
 190         u8 host_int_mask_reg;
 191         u8 status_reg_0;
 192         u8 status_reg_1;
 193         u8 sdio_int_mask;
 194         u32 data_port_mask;
 195         u8 io_port_0_reg;
 196         u8 io_port_1_reg;
 197         u8 io_port_2_reg;
 198         u8 max_mp_regs;
 199         u8 rd_bitmap_l;
 200         u8 rd_bitmap_u;
 201         u8 rd_bitmap_1l;
 202         u8 rd_bitmap_1u;
 203         u8 wr_bitmap_l;
 204         u8 wr_bitmap_u;
 205         u8 wr_bitmap_1l;
 206         u8 wr_bitmap_1u;
 207         u8 rd_len_p0_l;
 208         u8 rd_len_p0_u;
 209         u8 card_misc_cfg_reg;
 210         u8 card_cfg_2_1_reg;
 211         u8 cmd_rd_len_0;
 212         u8 cmd_rd_len_1;
 213         u8 cmd_rd_len_2;
 214         u8 cmd_rd_len_3;
 215         u8 cmd_cfg_0;
 216         u8 cmd_cfg_1;
 217         u8 cmd_cfg_2;
 218         u8 cmd_cfg_3;
 219         u8 fw_dump_ctrl;
 220         u8 fw_dump_start;
 221         u8 fw_dump_end;
 222 };
 223
 224 struct sdio_mmc_card {
 225         struct sdio_func *func;
 226         struct mwifiex_adapter *adapter;
 227
 228         const char *firmware;
 229         const struct mwifiex_sdio_card_reg *reg;
 230         u8 max_ports;
 231         u8 mp_agg_pkt_limit;
 232         bool supports_sdio_new_mode;
 233         bool has_control_mask;
 234         bool supports_fw_dump;
 235         u16 tx_buf_size;
 236         u32 mp_tx_agg_buf_size;
 237         u32 mp_rx_agg_buf_size;
 238
 239         u32 mp_rd_bitmap;
 240         u32 mp_wr_bitmap;
 241
 242         u16 mp_end_port;
 243         u32 mp_data_port_mask;
 244
 245         u8 curr_rd_port;
 246         u8 curr_wr_port;
 247
 248         u8 *mp_regs;
 249
 250         struct mwifiex_sdio_mpa_tx mpa_tx;
 251         struct mwifiex_sdio_mpa_rx mpa_rx;
 252 };
 253
 254 struct mwifiex_sdio_device {
 255         const char *firmware;
 256         const struct mwifiex_sdio_card_reg *reg;
 257         u8 max_ports;
 258         u8 mp_agg_pkt_limit;
 259         bool supports_sdio_new_mode;
 260         bool has_control_mask;
 261         bool supports_fw_dump;
 262         u16 tx_buf_size;
 263         u32 mp_tx_agg_buf_size;
 264         u32 mp_rx_agg_buf_size;
 265 };
 266
 267 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
 268         .start_rd_port = 1,
 269         .start_wr_port = 1,
 270         .base_0_reg = 0x0040,
 271         .base_1_reg = 0x0041,
 272         .poll_reg = 0x30,
 273         .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
 274         .host_int_rsr_reg = 0x1,
 275         .host_int_mask_reg = 0x02,
 276         .host_int_status_reg = 0x03,
 277         .status_reg_0 = 0x60,
 278         .status_reg_1 = 0x61,
 279         .sdio_int_mask = 0x3f,
 280         .data_port_mask = 0x0000fffe,
 281         .io_port_0_reg = 0x78,
 282         .io_port_1_reg = 0x79,
 283         .io_port_2_reg = 0x7A,
 284         .max_mp_regs = 64,
 285         .rd_bitmap_l = 0x04,
 286         .rd_bitmap_u = 0x05,
 287         .wr_bitmap_l = 0x06,
 288         .wr_bitmap_u = 0x07,
 289         .rd_len_p0_l = 0x08,
 290         .rd_len_p0_u = 0x09,
 291         .card_misc_cfg_reg = 0x6c,
 292 };
 293
 294 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
 295         .start_rd_port = 0,
 296         .start_wr_port = 0,
 297         .base_0_reg = 0x60,
 298         .base_1_reg = 0x61,
 299         .poll_reg = 0x50,
 300         .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
 301                         CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
 302         .host_int_rsr_reg = 0x1,
 303         .host_int_status_reg = 0x03,
 304         .host_int_mask_reg = 0x02,
 305         .status_reg_0 = 0xc0,
 306         .status_reg_1 = 0xc1,
 307         .sdio_int_mask = 0xff,
 308         .data_port_mask = 0xffffffff,
 309         .io_port_0_reg = 0xD8,
 310         .io_port_1_reg = 0xD9,
 311         .io_port_2_reg = 0xDA,
 312         .max_mp_regs = 184,
 313         .rd_bitmap_l = 0x04,
 314         .rd_bitmap_u = 0x05,
 315         .rd_bitmap_1l = 0x06,
 316         .rd_bitmap_1u = 0x07,
 317         .wr_bitmap_l = 0x08,
 318         .wr_bitmap_u = 0x09,
 319         .wr_bitmap_1l = 0x0a,
 320         .wr_bitmap_1u = 0x0b,
 321         .rd_len_p0_l = 0x0c,
 322         .rd_len_p0_u = 0x0d,
 323         .card_misc_cfg_reg = 0xcc,
 324         .card_cfg_2_1_reg = 0xcd,
 325         .cmd_rd_len_0 = 0xb4,
 326         .cmd_rd_len_1 = 0xb5,
 327         .cmd_rd_len_2 = 0xb6,
 328         .cmd_rd_len_3 = 0xb7,
 329         .cmd_cfg_0 = 0xb8,
 330         .cmd_cfg_1 = 0xb9,
 331         .cmd_cfg_2 = 0xba,
 332         .cmd_cfg_3 = 0xbb,
 333         .fw_dump_ctrl = 0xe2,
 334         .fw_dump_start = 0xe3,
 335         .fw_dump_end = 0xea,
 336 };
 337
 338 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887 = {
 339         .start_rd_port = 0,
 340         .start_wr_port = 0,
 341         .base_0_reg = 0x6C,
 342         .base_1_reg = 0x6D,
 343         .poll_reg = 0x5C,
 344         .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
 345                         CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
 346         .host_int_rsr_reg = 0x4,
 347         .host_int_status_reg = 0x0C,
 348         .host_int_mask_reg = 0x08,
 349         .status_reg_0 = 0x90,
 350         .status_reg_1 = 0x91,
 351         .sdio_int_mask = 0xff,
 352         .data_port_mask = 0xffffffff,
 353         .io_port_0_reg = 0xE4,
 354         .io_port_1_reg = 0xE5,
 355         .io_port_2_reg = 0xE6,
 356         .max_mp_regs = 196,
 357         .rd_bitmap_l = 0x10,
 358         .rd_bitmap_u = 0x11,
 359         .rd_bitmap_1l = 0x12,
 360         .rd_bitmap_1u = 0x13,
 361         .wr_bitmap_l = 0x14,
 362         .wr_bitmap_u = 0x15,
 363         .wr_bitmap_1l = 0x16,
 364         .wr_bitmap_1u = 0x17,
 365         .rd_len_p0_l = 0x18,
 366         .rd_len_p0_u = 0x19,
 367         .card_misc_cfg_reg = 0xd8,
 368         .card_cfg_2_1_reg = 0xd9,
 369         .cmd_rd_len_0 = 0xc0,
 370         .cmd_rd_len_1 = 0xc1,
 371         .cmd_rd_len_2 = 0xc2,
 372         .cmd_rd_len_3 = 0xc3,
 373         .cmd_cfg_0 = 0xc4,
 374         .cmd_cfg_1 = 0xc5,
 375         .cmd_cfg_2 = 0xc6,
 376         .cmd_cfg_3 = 0xc7,
 377 };
 378
 379 static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
 380         .firmware = SD8786_DEFAULT_FW_NAME,
 381         .reg = &mwifiex_reg_sd87xx,
 382         .max_ports = 16,
 383         .mp_agg_pkt_limit = 8,
 384         .supports_sdio_new_mode = false,
 385         .has_control_mask = true,
 386         .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
 387         .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
 388         .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
 389         .supports_fw_dump = false,
 390 };
 391
 392 static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
 393         .firmware = SD8787_DEFAULT_FW_NAME,
 394         .reg = &mwifiex_reg_sd87xx,
 395         .max_ports = 16,
 396         .mp_agg_pkt_limit = 8,
 397         .supports_sdio_new_mode = false,
 398         .has_control_mask = true,
 399         .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
 400         .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
 401         .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
 402         .supports_fw_dump = false,
 403 };
 404
 405 static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
 406         .firmware = SD8797_DEFAULT_FW_NAME,
 407         .reg = &mwifiex_reg_sd87xx,
 408         .max_ports = 16,
 409         .mp_agg_pkt_limit = 8,
 410         .supports_sdio_new_mode = false,
 411         .has_control_mask = true,
 412         .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
 413         .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
 414         .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
 415         .supports_fw_dump = false,
 416 };
 417
 418 static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
 419         .firmware = SD8897_DEFAULT_FW_NAME,
 420         .reg = &mwifiex_reg_sd8897,
 421         .max_ports = 32,
 422         .mp_agg_pkt_limit = 16,
 423         .supports_sdio_new_mode = true,
 424         .has_control_mask = false,
 425         .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
 426         .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
 427         .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
 428         .supports_fw_dump = true,
 429 };
 430
 431 static const struct mwifiex_sdio_device mwifiex_sdio_sd8887 = {
 432         .firmware = SD8887_DEFAULT_FW_NAME,
 433         .reg = &mwifiex_reg_sd8887,
 434         .max_ports = 32,
 435         .mp_agg_pkt_limit = 16,
 436         .supports_sdio_new_mode = true,
 437         .has_control_mask = false,
 438         .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
 439         .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
 440         .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
 441         .supports_fw_dump = false,
 442 };
 443
 444 /*
 445  * .cmdrsp_complete handler
 446  */
 447 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
 448                                                struct sk_buff *skb)
 449 {
 450         dev_kfree_skb_any(skb);
 451         return 0;
 452 }
 453
 454 /*
 455  * .event_complete handler
 456  */
 457 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
 458                                               struct sk_buff *skb)
 459 {
 460         dev_kfree_skb_any(skb);
 461         return 0;
 462 }
 463
 464 static inline bool
 465 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
 466 {
 467         u8 tmp;
 468
 469         if (card->curr_rd_port < card->mpa_rx.start_port) {
 470                 if (card->supports_sdio_new_mode)
 471                         tmp = card->mp_end_port >> 1;
 472                 else
 473                         tmp = card->mp_agg_pkt_limit;
 474
 475                 if (((card->max_ports - card->mpa_rx.start_port) +
 476                     card->curr_rd_port) >= tmp)
 477                         return true;
 478         }
 479
 480         if (!card->supports_sdio_new_mode)
 481                 return false;
 482
 483         if ((card->curr_rd_port - card->mpa_rx.start_port) >=
 484             (card->mp_end_port >> 1))
 485                 return true;
 486
 487         return false;
 488 }
 489
 490 static inline bool
 491 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
 492 {
 493         u16 tmp;
 494
 495         if (card->curr_wr_port < card->mpa_tx.start_port) {
 496                 if (card->supports_sdio_new_mode)
 497                         tmp = card->mp_end_port >> 1;
 498                 else
 499                         tmp = card->mp_agg_pkt_limit;
 500
 501                 if (((card->max_ports - card->mpa_tx.start_port) +
 502                     card->curr_wr_port) >= tmp)
 503                         return true;
 504         }
 505
 506         if (!card->supports_sdio_new_mode)
 507                 return false;
 508
 509         if ((card->curr_wr_port - card->mpa_tx.start_port) >=
 510             (card->mp_end_port >> 1))
 511                 return true;
 512
 513         return false;
 514 }
 515
 516 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
 517 static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
 518                                     struct sk_buff *skb, u8 port)
 519 {
 520         card->mpa_rx.buf_len += skb->len;
 521
 522         if (!card->mpa_rx.pkt_cnt)
 523                 card->mpa_rx.start_port = port;
 524
 525         if (card->supports_sdio_new_mode) {
 526                 card->mpa_rx.ports |= (1 << port);
 527         } else {
 528                 if (card->mpa_rx.start_port <= port)
 529                         card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
 530                 else
 531                         card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
 532         }
 533         card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = skb;
 534         card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = skb->len;
 535         card->mpa_rx.pkt_cnt++;
 536 }
 537 #endif /* _MWIFIEX_SDIO_H */