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hwmon: (adt7475) fan stall prevention
[linux/fpc-iii.git] / drivers / staging / rts5208 / ms.c
blob482a29dd06f84493c3d526594b5ec26e21053de0
1 /* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
21 */
22
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/vmalloc.h>
27
28 #include "rtsx.h"
29 #include "ms.h"
30
31 static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code)
32 {
33 struct ms_info *ms_card = &chip->ms_card;
34
35 ms_card->err_code = err_code;
36 }
37
38 static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code)
39 {
40 struct ms_info *ms_card = &chip->ms_card;
41
42 return (ms_card->err_code == err_code);
43 }
44
45 static int ms_parse_err_code(struct rtsx_chip *chip)
46 {
47 rtsx_trace(chip);
48 return STATUS_FAIL;
49 }
50
51 static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode,
52 u8 tpc, u8 cnt, u8 cfg)
53 {
54 struct ms_info *ms_card = &chip->ms_card;
55 int retval;
56 u8 *ptr;
57
58 dev_dbg(rtsx_dev(chip), "%s: tpc = 0x%x\n", __func__, tpc);
59
60 rtsx_init_cmd(chip);
61
62 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
63 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
64 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
65 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
66 0x01, PINGPONG_BUFFER);
67
68 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER,
69 0xFF, MS_TRANSFER_START | trans_mode);
70 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
71 MS_TRANSFER_END, MS_TRANSFER_END);
72
73 rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
74
75 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
76 if (retval < 0) {
77 rtsx_clear_ms_error(chip);
78 ms_set_err_code(chip, MS_TO_ERROR);
79 rtsx_trace(chip);
80 return ms_parse_err_code(chip);
81 }
82
83 ptr = rtsx_get_cmd_data(chip) + 1;
84
85 if (!(tpc & 0x08)) { /* Read Packet */
86 if (*ptr & MS_CRC16_ERR) {
87 ms_set_err_code(chip, MS_CRC16_ERROR);
88 rtsx_trace(chip);
89 return ms_parse_err_code(chip);
90 }
91 } else { /* Write Packet */
92 if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) {
93 if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) {
94 ms_set_err_code(chip, MS_CMD_NK);
95 rtsx_trace(chip);
96 return ms_parse_err_code(chip);
97 }
98 }
99 }
100
101 if (*ptr & MS_RDY_TIMEOUT) {
102 rtsx_clear_ms_error(chip);
103 ms_set_err_code(chip, MS_TO_ERROR);
104 rtsx_trace(chip);
105 return ms_parse_err_code(chip);
106 }
107
108 return STATUS_SUCCESS;
109 }
110
111 static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode,
112 u8 tpc, u16 sec_cnt, u8 cfg, bool mode_2k,
113 int use_sg, void *buf, int buf_len)
114 {
115 int retval;
116 u8 val, err_code = 0;
117 enum dma_data_direction dir;
118
119 if (!buf || !buf_len) {
120 rtsx_trace(chip);
121 return STATUS_FAIL;
122 }
123
124 if (trans_mode == MS_TM_AUTO_READ) {
125 dir = DMA_FROM_DEVICE;
126 err_code = MS_FLASH_READ_ERROR;
127 } else if (trans_mode == MS_TM_AUTO_WRITE) {
128 dir = DMA_TO_DEVICE;
129 err_code = MS_FLASH_WRITE_ERROR;
130 } else {
131 rtsx_trace(chip);
132 return STATUS_FAIL;
133 }
134
135 rtsx_init_cmd(chip);
136
137 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
138 rtsx_add_cmd(chip, WRITE_REG_CMD,
139 MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8));
140 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt);
141 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
142
143 if (mode_2k) {
144 rtsx_add_cmd(chip, WRITE_REG_CMD,
145 MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE);
146 } else {
147 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0);
148 }
149
150 trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512);
151
152 rtsx_add_cmd(chip, WRITE_REG_CMD,
153 MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode);
154 rtsx_add_cmd(chip, CHECK_REG_CMD,
155 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
156
157 rtsx_send_cmd_no_wait(chip);
158
159 retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len,
160 use_sg, dir, chip->mspro_timeout);
161 if (retval < 0) {
162 ms_set_err_code(chip, err_code);
163 if (retval == -ETIMEDOUT)
164 retval = STATUS_TIMEDOUT;
165 else
166 retval = STATUS_FAIL;
167
168 rtsx_trace(chip);
169 return retval;
170 }
171
172 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
173 if (retval) {
174 rtsx_trace(chip);
175 return retval;
176 }
177 if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
178 rtsx_trace(chip);
179 return STATUS_FAIL;
180 }
181
182 return STATUS_SUCCESS;
183 }
184
185 static int ms_write_bytes(struct rtsx_chip *chip,
186 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
187 {
188 struct ms_info *ms_card = &chip->ms_card;
189 int retval, i;
190
191 if (!data || (data_len < cnt)) {
192 rtsx_trace(chip);
193 return STATUS_ERROR;
194 }
195
196 rtsx_init_cmd(chip);
197
198 for (i = 0; i < cnt; i++) {
199 rtsx_add_cmd(chip, WRITE_REG_CMD,
200 PPBUF_BASE2 + i, 0xFF, data[i]);
201 }
202 if (cnt % 2)
203 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF);
204
205 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
206 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
207 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
208 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
209 0x01, PINGPONG_BUFFER);
210
211 rtsx_add_cmd(chip, WRITE_REG_CMD,
212 MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES);
213 rtsx_add_cmd(chip, CHECK_REG_CMD,
214 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
215
216 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
217 if (retval < 0) {
218 u8 val = 0;
219
220 rtsx_read_register(chip, MS_TRANS_CFG, &val);
221 dev_dbg(rtsx_dev(chip), "MS_TRANS_CFG: 0x%02x\n", val);
222
223 rtsx_clear_ms_error(chip);
224
225 if (!(tpc & 0x08)) {
226 if (val & MS_CRC16_ERR) {
227 ms_set_err_code(chip, MS_CRC16_ERROR);
228 rtsx_trace(chip);
229 return ms_parse_err_code(chip);
230 }
231 } else {
232 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
233 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
234 ms_set_err_code(chip, MS_CMD_NK);
235 rtsx_trace(chip);
236 return ms_parse_err_code(chip);
237 }
238 }
239 }
240
241 if (val & MS_RDY_TIMEOUT) {
242 ms_set_err_code(chip, MS_TO_ERROR);
243 rtsx_trace(chip);
244 return ms_parse_err_code(chip);
245 }
246
247 ms_set_err_code(chip, MS_TO_ERROR);
248 rtsx_trace(chip);
249 return ms_parse_err_code(chip);
250 }
251
252 return STATUS_SUCCESS;
253 }
254
255 static int ms_read_bytes(struct rtsx_chip *chip,
256 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
257 {
258 struct ms_info *ms_card = &chip->ms_card;
259 int retval, i;
260 u8 *ptr;
261
262 if (!data) {
263 rtsx_trace(chip);
264 return STATUS_ERROR;
265 }
266
267 rtsx_init_cmd(chip);
268
269 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
270 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
271 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
272 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
273 0x01, PINGPONG_BUFFER);
274
275 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
276 MS_TRANSFER_START | MS_TM_READ_BYTES);
277 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
278 MS_TRANSFER_END, MS_TRANSFER_END);
279
280 for (i = 0; i < data_len - 1; i++)
281 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
282
283 if (data_len % 2)
284 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0);
285 else
286 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1,
287 0, 0);
288
289 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
290 if (retval < 0) {
291 u8 val = 0;
292
293 rtsx_read_register(chip, MS_TRANS_CFG, &val);
294 rtsx_clear_ms_error(chip);
295
296 if (!(tpc & 0x08)) {
297 if (val & MS_CRC16_ERR) {
298 ms_set_err_code(chip, MS_CRC16_ERROR);
299 rtsx_trace(chip);
300 return ms_parse_err_code(chip);
301 }
302 } else {
303 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
304 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
305 ms_set_err_code(chip, MS_CMD_NK);
306 rtsx_trace(chip);
307 return ms_parse_err_code(chip);
308 }
309 }
310 }
311
312 if (val & MS_RDY_TIMEOUT) {
313 ms_set_err_code(chip, MS_TO_ERROR);
314 rtsx_trace(chip);
315 return ms_parse_err_code(chip);
316 }
317
318 ms_set_err_code(chip, MS_TO_ERROR);
319 rtsx_trace(chip);
320 return ms_parse_err_code(chip);
321 }
322
323 ptr = rtsx_get_cmd_data(chip) + 1;
324
325 for (i = 0; i < data_len; i++)
326 data[i] = ptr[i];
327
328 if ((tpc == PRO_READ_SHORT_DATA) && (data_len == 8)) {
329 dev_dbg(rtsx_dev(chip), "Read format progress:\n");
330 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, ptr,
331 cnt);
332 }
333
334 return STATUS_SUCCESS;
335 }
336
337 static int ms_set_rw_reg_addr(struct rtsx_chip *chip, u8 read_start,
338 u8 read_cnt, u8 write_start, u8 write_cnt)
339 {
340 int retval, i;
341 u8 data[4];
342
343 data[0] = read_start;
344 data[1] = read_cnt;
345 data[2] = write_start;
346 data[3] = write_cnt;
347
348 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
349 retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4,
350 NO_WAIT_INT, data, 4);
351 if (retval == STATUS_SUCCESS)
352 return STATUS_SUCCESS;
353 rtsx_clear_ms_error(chip);
354 }
355
356 rtsx_trace(chip);
357 return STATUS_FAIL;
358 }
359
360 static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg)
361 {
362 u8 data[2];
363
364 data[0] = cmd;
365 data[1] = 0;
366
367 return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1);
368 }
369
370 static int ms_set_init_para(struct rtsx_chip *chip)
371 {
372 struct ms_info *ms_card = &chip->ms_card;
373 int retval;
374
375 if (CHK_HG8BIT(ms_card)) {
376 if (chip->asic_code)
377 ms_card->ms_clock = chip->asic_ms_hg_clk;
378 else
379 ms_card->ms_clock = chip->fpga_ms_hg_clk;
380
381 } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) {
382 if (chip->asic_code)
383 ms_card->ms_clock = chip->asic_ms_4bit_clk;
384 else
385 ms_card->ms_clock = chip->fpga_ms_4bit_clk;
386
387 } else {
388 if (chip->asic_code)
389 ms_card->ms_clock = chip->asic_ms_1bit_clk;
390 else
391 ms_card->ms_clock = chip->fpga_ms_1bit_clk;
392 }
393
394 retval = switch_clock(chip, ms_card->ms_clock);
395 if (retval != STATUS_SUCCESS) {
396 rtsx_trace(chip);
397 return STATUS_FAIL;
398 }
399
400 retval = select_card(chip, MS_CARD);
401 if (retval != STATUS_SUCCESS) {
402 rtsx_trace(chip);
403 return STATUS_FAIL;
404 }
405
406 return STATUS_SUCCESS;
407 }
408
409 static int ms_switch_clock(struct rtsx_chip *chip)
410 {
411 struct ms_info *ms_card = &chip->ms_card;
412 int retval;
413
414 retval = select_card(chip, MS_CARD);
415 if (retval != STATUS_SUCCESS) {
416 rtsx_trace(chip);
417 return STATUS_FAIL;
418 }
419
420 retval = switch_clock(chip, ms_card->ms_clock);
421 if (retval != STATUS_SUCCESS) {
422 rtsx_trace(chip);
423 return STATUS_FAIL;
424 }
425
426 return STATUS_SUCCESS;
427 }
428
429 static int ms_pull_ctl_disable(struct rtsx_chip *chip)
430 {
431 int retval;
432
433 if (CHECK_PID(chip, 0x5208)) {
434 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF,
435 MS_D1_PD | MS_D2_PD | MS_CLK_PD |
436 MS_D6_PD);
437 if (retval) {
438 rtsx_trace(chip);
439 return retval;
440 }
441 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF,
442 MS_D3_PD | MS_D0_PD | MS_BS_PD |
443 XD_D4_PD);
444 if (retval) {
445 rtsx_trace(chip);
446 return retval;
447 }
448 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF,
449 MS_D7_PD | XD_CE_PD | XD_CLE_PD |
450 XD_CD_PU);
451 if (retval) {
452 rtsx_trace(chip);
453 return retval;
454 }
455 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF,
456 XD_RDY_PD | SD_D3_PD | SD_D2_PD |
457 XD_ALE_PD);
458 if (retval) {
459 rtsx_trace(chip);
460 return retval;
461 }
462 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF,
463 MS_INS_PU | SD_WP_PD | SD_CD_PU |
464 SD_CMD_PD);
465 if (retval) {
466 rtsx_trace(chip);
467 return retval;
468 }
469 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF,
470 MS_D5_PD | MS_D4_PD);
471 if (retval) {
472 rtsx_trace(chip);
473 return retval;
474 }
475 } else if (CHECK_PID(chip, 0x5288)) {
476 if (CHECK_BARO_PKG(chip, QFN)) {
477 retval = rtsx_write_register(chip, CARD_PULL_CTL1,
478 0xFF, 0x55);
479 if (retval) {
480 rtsx_trace(chip);
481 return retval;
482 }
483 retval = rtsx_write_register(chip, CARD_PULL_CTL2,
484 0xFF, 0x55);
485 if (retval) {
486 rtsx_trace(chip);
487 return retval;
488 }
489 retval = rtsx_write_register(chip, CARD_PULL_CTL3,
490 0xFF, 0x4B);
491 if (retval) {
492 rtsx_trace(chip);
493 return retval;
494 }
495 retval = rtsx_write_register(chip, CARD_PULL_CTL4,
496 0xFF, 0x69);
497 if (retval) {
498 rtsx_trace(chip);
499 return retval;
500 }
501 }
502 }
503
504 return STATUS_SUCCESS;
505 }
506
507 static int ms_pull_ctl_enable(struct rtsx_chip *chip)
508 {
509 int retval;
510
511 rtsx_init_cmd(chip);
512
513 if (CHECK_PID(chip, 0x5208)) {
514 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
515 MS_D1_PD | MS_D2_PD | MS_CLK_NP | MS_D6_PD);
516 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
517 MS_D3_PD | MS_D0_PD | MS_BS_NP | XD_D4_PD);
518 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
519 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
520 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
521 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
522 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
523 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
524 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
525 MS_D5_PD | MS_D4_PD);
526 } else if (CHECK_PID(chip, 0x5288)) {
527 if (CHECK_BARO_PKG(chip, QFN)) {
528 rtsx_add_cmd(chip, WRITE_REG_CMD,
529 CARD_PULL_CTL1, 0xFF, 0x55);
530 rtsx_add_cmd(chip, WRITE_REG_CMD,
531 CARD_PULL_CTL2, 0xFF, 0x45);
532 rtsx_add_cmd(chip, WRITE_REG_CMD,
533 CARD_PULL_CTL3, 0xFF, 0x4B);
534 rtsx_add_cmd(chip, WRITE_REG_CMD,
535 CARD_PULL_CTL4, 0xFF, 0x29);
536 }
537 }
538
539 retval = rtsx_send_cmd(chip, MS_CARD, 100);
540 if (retval < 0) {
541 rtsx_trace(chip);
542 return STATUS_FAIL;
543 }
544
545 return STATUS_SUCCESS;
546 }
547
548 static int ms_prepare_reset(struct rtsx_chip *chip)
549 {
550 struct ms_info *ms_card = &chip->ms_card;
551 int retval;
552 u8 oc_mask = 0;
553
554 ms_card->ms_type = 0;
555 ms_card->check_ms_flow = 0;
556 ms_card->switch_8bit_fail = 0;
557 ms_card->delay_write.delay_write_flag = 0;
558
559 ms_card->pro_under_formatting = 0;
560
561 retval = ms_power_off_card3v3(chip);
562 if (retval != STATUS_SUCCESS) {
563 rtsx_trace(chip);
564 return STATUS_FAIL;
565 }
566
567 if (!chip->ft2_fast_mode)
568 wait_timeout(250);
569
570 retval = enable_card_clock(chip, MS_CARD);
571 if (retval != STATUS_SUCCESS) {
572 rtsx_trace(chip);
573 return STATUS_FAIL;
574 }
575
576 if (chip->asic_code) {
577 retval = ms_pull_ctl_enable(chip);
578 if (retval != STATUS_SUCCESS) {
579 rtsx_trace(chip);
580 return STATUS_FAIL;
581 }
582 } else {
583 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
584 FPGA_MS_PULL_CTL_BIT | 0x20, 0);
585 if (retval) {
586 rtsx_trace(chip);
587 return retval;
588 }
589 }
590
591 if (!chip->ft2_fast_mode) {
592 retval = card_power_on(chip, MS_CARD);
593 if (retval != STATUS_SUCCESS) {
594 rtsx_trace(chip);
595 return STATUS_FAIL;
596 }
597
598 wait_timeout(150);
599
600 #ifdef SUPPORT_OCP
601 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
602 oc_mask = MS_OC_NOW | MS_OC_EVER;
603 else
604 oc_mask = SD_OC_NOW | SD_OC_EVER;
605
606 if (chip->ocp_stat & oc_mask) {
607 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
608 chip->ocp_stat);
609 rtsx_trace(chip);
610 return STATUS_FAIL;
611 }
612 #endif
613 }
614
615 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN,
616 MS_OUTPUT_EN);
617 if (retval) {
618 rtsx_trace(chip);
619 return retval;
620 }
621
622 if (chip->asic_code) {
623 retval = rtsx_write_register(chip, MS_CFG, 0xFF,
624 SAMPLE_TIME_RISING |
625 PUSH_TIME_DEFAULT |
626 NO_EXTEND_TOGGLE |
627 MS_BUS_WIDTH_1);
628 if (retval) {
629 rtsx_trace(chip);
630 return retval;
631 }
632 } else {
633 retval = rtsx_write_register(chip, MS_CFG, 0xFF,
634 SAMPLE_TIME_FALLING |
635 PUSH_TIME_DEFAULT |
636 NO_EXTEND_TOGGLE |
637 MS_BUS_WIDTH_1);
638 if (retval) {
639 rtsx_trace(chip);
640 return retval;
641 }
642 }
643 retval = rtsx_write_register(chip, MS_TRANS_CFG, 0xFF,
644 NO_WAIT_INT | NO_AUTO_READ_INT_REG);
645 if (retval) {
646 rtsx_trace(chip);
647 return retval;
648 }
649 retval = rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR,
650 MS_STOP | MS_CLR_ERR);
651 if (retval) {
652 rtsx_trace(chip);
653 return retval;
654 }
655
656 retval = ms_set_init_para(chip);
657 if (retval != STATUS_SUCCESS) {
658 rtsx_trace(chip);
659 return STATUS_FAIL;
660 }
661
662 return STATUS_SUCCESS;
663 }
664
665 static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus)
666 {
667 struct ms_info *ms_card = &chip->ms_card;
668 int retval, i;
669 u8 val;
670
671 retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1);
672 if (retval != STATUS_SUCCESS) {
673 rtsx_trace(chip);
674 return STATUS_FAIL;
675 }
676
677 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
678 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG,
679 6, NO_WAIT_INT);
680 if (retval == STATUS_SUCCESS)
681 break;
682 }
683 if (i == MS_MAX_RETRY_COUNT) {
684 rtsx_trace(chip);
685 return STATUS_FAIL;
686 }
687
688 retval = rtsx_read_register(chip, PPBUF_BASE2 + 2, &val);
689 if (retval) {
690 rtsx_trace(chip);
691 return retval;
692 }
693 dev_dbg(rtsx_dev(chip), "Type register: 0x%x\n", val);
694 if (val != 0x01) {
695 if (val != 0x02)
696 ms_card->check_ms_flow = 1;
697
698 rtsx_trace(chip);
699 return STATUS_FAIL;
700 }
701
702 retval = rtsx_read_register(chip, PPBUF_BASE2 + 4, &val);
703 if (retval) {
704 rtsx_trace(chip);
705 return retval;
706 }
707 dev_dbg(rtsx_dev(chip), "Category register: 0x%x\n", val);
708 if (val != 0) {
709 ms_card->check_ms_flow = 1;
710 rtsx_trace(chip);
711 return STATUS_FAIL;
712 }
713
714 retval = rtsx_read_register(chip, PPBUF_BASE2 + 5, &val);
715 if (retval) {
716 rtsx_trace(chip);
717 return retval;
718 }
719 dev_dbg(rtsx_dev(chip), "Class register: 0x%x\n", val);
720 if (val == 0) {
721 retval = rtsx_read_register(chip, PPBUF_BASE2, &val);
722 if (retval) {
723 rtsx_trace(chip);
724 return retval;
725 }
726 if (val & WRT_PRTCT)
727 chip->card_wp |= MS_CARD;
728 else
729 chip->card_wp &= ~MS_CARD;
730
731 } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) {
732 chip->card_wp |= MS_CARD;
733 } else {
734 ms_card->check_ms_flow = 1;
735 rtsx_trace(chip);
736 return STATUS_FAIL;
737 }
738
739 ms_card->ms_type |= TYPE_MSPRO;
740
741 retval = rtsx_read_register(chip, PPBUF_BASE2 + 3, &val);
742 if (retval) {
743 rtsx_trace(chip);
744 return retval;
745 }
746 dev_dbg(rtsx_dev(chip), "IF Mode register: 0x%x\n", val);
747 if (val == 0) {
748 ms_card->ms_type &= 0x0F;
749 } else if (val == 7) {
750 if (switch_8bit_bus)
751 ms_card->ms_type |= MS_HG;
752 else
753 ms_card->ms_type &= 0x0F;
754
755 } else {
756 rtsx_trace(chip);
757 return STATUS_FAIL;
758 }
759
760 return STATUS_SUCCESS;
761 }
762
763 static int ms_confirm_cpu_startup(struct rtsx_chip *chip)
764 {
765 int retval, i, k;
766 u8 val;
767
768 /* Confirm CPU StartUp */
769 k = 0;
770 do {
771 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
772 ms_set_err_code(chip, MS_NO_CARD);
773 rtsx_trace(chip);
774 return STATUS_FAIL;
775 }
776
777 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
778 retval = ms_read_bytes(chip, GET_INT, 1,
779 NO_WAIT_INT, &val, 1);
780 if (retval == STATUS_SUCCESS)
781 break;
782 }
783 if (i == MS_MAX_RETRY_COUNT) {
784 rtsx_trace(chip);
785 return STATUS_FAIL;
786 }
787
788 if (k > 100) {
789 rtsx_trace(chip);
790 return STATUS_FAIL;
791 }
792
793 k++;
794 wait_timeout(100);
795 } while (!(val & INT_REG_CED));
796
797 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
798 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
799 if (retval == STATUS_SUCCESS)
800 break;
801 }
802 if (i == MS_MAX_RETRY_COUNT) {
803 rtsx_trace(chip);
804 return STATUS_FAIL;
805 }
806
807 if (val & INT_REG_ERR) {
808 if (val & INT_REG_CMDNK) {
809 chip->card_wp |= (MS_CARD);
810 } else {
811 rtsx_trace(chip);
812 return STATUS_FAIL;
813 }
814 }
815 /* -- end confirm CPU startup */
816
817 return STATUS_SUCCESS;
818 }
819
820 static int ms_switch_parallel_bus(struct rtsx_chip *chip)
821 {
822 int retval, i;
823 u8 data[2];
824
825 data[0] = PARALLEL_4BIT_IF;
826 data[1] = 0;
827 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
828 retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT,
829 data, 2);
830 if (retval == STATUS_SUCCESS)
831 break;
832 }
833 if (retval != STATUS_SUCCESS) {
834 rtsx_trace(chip);
835 return STATUS_FAIL;
836 }
837
838 return STATUS_SUCCESS;
839 }
840
841 static int ms_switch_8bit_bus(struct rtsx_chip *chip)
842 {
843 struct ms_info *ms_card = &chip->ms_card;
844 int retval, i;
845 u8 data[2];
846
847 data[0] = PARALLEL_8BIT_IF;
848 data[1] = 0;
849 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
850 retval = ms_write_bytes(chip, WRITE_REG, 1,
851 NO_WAIT_INT, data, 2);
852 if (retval == STATUS_SUCCESS)
853 break;
854 }
855 if (retval != STATUS_SUCCESS) {
856 rtsx_trace(chip);
857 return STATUS_FAIL;
858 }
859
860 retval = rtsx_write_register(chip, MS_CFG, 0x98,
861 MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING);
862 if (retval) {
863 rtsx_trace(chip);
864 return retval;
865 }
866 ms_card->ms_type |= MS_8BIT;
867 retval = ms_set_init_para(chip);
868 if (retval != STATUS_SUCCESS) {
869 rtsx_trace(chip);
870 return STATUS_FAIL;
871 }
872
873 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
874 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT,
875 1, NO_WAIT_INT);
876 if (retval != STATUS_SUCCESS) {
877 rtsx_trace(chip);
878 return STATUS_FAIL;
879 }
880 }
881
882 return STATUS_SUCCESS;
883 }
884
885 static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus)
886 {
887 struct ms_info *ms_card = &chip->ms_card;
888 int retval, i;
889
890 for (i = 0; i < 3; i++) {
891 retval = ms_prepare_reset(chip);
892 if (retval != STATUS_SUCCESS) {
893 rtsx_trace(chip);
894 return STATUS_FAIL;
895 }
896
897 retval = ms_identify_media_type(chip, switch_8bit_bus);
898 if (retval != STATUS_SUCCESS) {
899 rtsx_trace(chip);
900 return STATUS_FAIL;
901 }
902
903 retval = ms_confirm_cpu_startup(chip);
904 if (retval != STATUS_SUCCESS) {
905 rtsx_trace(chip);
906 return STATUS_FAIL;
907 }
908
909 retval = ms_switch_parallel_bus(chip);
910 if (retval != STATUS_SUCCESS) {
911 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
912 ms_set_err_code(chip, MS_NO_CARD);
913 rtsx_trace(chip);
914 return STATUS_FAIL;
915 }
916 continue;
917 } else {
918 break;
919 }
920 }
921
922 if (retval != STATUS_SUCCESS) {
923 rtsx_trace(chip);
924 return STATUS_FAIL;
925 }
926
927 /* Switch MS-PRO into Parallel mode */
928 retval = rtsx_write_register(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);
929 if (retval) {
930 rtsx_trace(chip);
931 return retval;
932 }
933 retval = rtsx_write_register(chip, MS_CFG, PUSH_TIME_ODD,
934 PUSH_TIME_ODD);
935 if (retval) {
936 rtsx_trace(chip);
937 return retval;
938 }
939
940 retval = ms_set_init_para(chip);
941 if (retval != STATUS_SUCCESS) {
942 rtsx_trace(chip);
943 return STATUS_FAIL;
944 }
945
946 /* If MSPro HG Card, We shall try to switch to 8-bit bus */
947 if (CHK_MSHG(ms_card) && chip->support_ms_8bit && switch_8bit_bus) {
948 retval = ms_switch_8bit_bus(chip);
949 if (retval != STATUS_SUCCESS) {
950 ms_card->switch_8bit_fail = 1;
951 rtsx_trace(chip);
952 return STATUS_FAIL;
953 }
954 }
955
956 return STATUS_SUCCESS;
957 }
958
959 #ifdef XC_POWERCLASS
960 static int msxc_change_power(struct rtsx_chip *chip, u8 mode)
961 {
962 int retval;
963 u8 buf[6];
964
965 ms_cleanup_work(chip);
966
967 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
968 if (retval != STATUS_SUCCESS) {
969 rtsx_trace(chip);
970 return STATUS_FAIL;
971 }
972
973 buf[0] = 0;
974 buf[1] = mode;
975 buf[2] = 0;
976 buf[3] = 0;
977 buf[4] = 0;
978 buf[5] = 0;
979
980 retval = ms_write_bytes(chip, PRO_WRITE_REG, 6, NO_WAIT_INT, buf, 6);
981 if (retval != STATUS_SUCCESS) {
982 rtsx_trace(chip);
983 return STATUS_FAIL;
984 }
985
986 retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT);
987 if (retval != STATUS_SUCCESS) {
988 rtsx_trace(chip);
989 return STATUS_FAIL;
990 }
991
992 retval = rtsx_read_register(chip, MS_TRANS_CFG, buf);
993 if (retval) {
994 rtsx_trace(chip);
995 return retval;
996 }
997 if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR)) {
998 rtsx_trace(chip);
999 return STATUS_FAIL;
1000 }
1001
1002 return STATUS_SUCCESS;
1003 }
1004 #endif
1005
1006 static int ms_read_attribute_info(struct rtsx_chip *chip)
1007 {
1008 struct ms_info *ms_card = &chip->ms_card;
1009 int retval, i;
1010 u8 val, *buf, class_code, device_type, sub_class, data[16];
1011 u16 total_blk = 0, blk_size = 0;
1012 #ifdef SUPPORT_MSXC
1013 u32 xc_total_blk = 0, xc_blk_size = 0;
1014 #endif
1015 u32 sys_info_addr = 0, sys_info_size;
1016 #ifdef SUPPORT_PCGL_1P18
1017 u32 model_name_addr = 0, model_name_size;
1018 int found_sys_info = 0, found_model_name = 0;
1019 #endif
1020
1021 retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7);
1022 if (retval != STATUS_SUCCESS) {
1023 rtsx_trace(chip);
1024 return STATUS_FAIL;
1025 }
1026
1027 if (CHK_MS8BIT(ms_card))
1028 data[0] = PARALLEL_8BIT_IF;
1029 else
1030 data[0] = PARALLEL_4BIT_IF;
1031
1032 data[1] = 0;
1033
1034 data[2] = 0x40;
1035 data[3] = 0;
1036 data[4] = 0;
1037 data[5] = 0;
1038 data[6] = 0;
1039 data[7] = 0;
1040
1041 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1042 retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT,
1043 data, 8);
1044 if (retval == STATUS_SUCCESS)
1045 break;
1046 }
1047 if (retval != STATUS_SUCCESS) {
1048 rtsx_trace(chip);
1049 return STATUS_FAIL;
1050 }
1051
1052 buf = kmalloc(64 * 512, GFP_KERNEL);
1053 if (!buf) {
1054 rtsx_trace(chip);
1055 return STATUS_ERROR;
1056 }
1057
1058 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1059 retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT);
1060 if (retval != STATUS_SUCCESS)
1061 continue;
1062
1063 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
1064 if (retval != STATUS_SUCCESS) {
1065 kfree(buf);
1066 rtsx_trace(chip);
1067 return STATUS_FAIL;
1068 }
1069 if (!(val & MS_INT_BREQ)) {
1070 kfree(buf);
1071 rtsx_trace(chip);
1072 return STATUS_FAIL;
1073 }
1074 retval = ms_transfer_data(chip, MS_TM_AUTO_READ,
1075 PRO_READ_LONG_DATA, 0x40, WAIT_INT,
1076 0, 0, buf, 64 * 512);
1077 if (retval == STATUS_SUCCESS)
1078 break;
1079
1080 rtsx_clear_ms_error(chip);
1081 }
1082 if (retval != STATUS_SUCCESS) {
1083 kfree(buf);
1084 rtsx_trace(chip);
1085 return STATUS_FAIL;
1086 }
1087
1088 i = 0;
1089 do {
1090 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
1091 if (retval != STATUS_SUCCESS) {
1092 kfree(buf);
1093 rtsx_trace(chip);
1094 return STATUS_FAIL;
1095 }
1096
1097 if ((val & MS_INT_CED) || !(val & MS_INT_BREQ))
1098 break;
1099
1100 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ,
1101 PRO_READ_LONG_DATA, 0, WAIT_INT);
1102 if (retval != STATUS_SUCCESS) {
1103 kfree(buf);
1104 rtsx_trace(chip);
1105 return STATUS_FAIL;
1106 }
1107
1108 i++;
1109 } while (i < 1024);
1110
1111 if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) {
1112 /* Signature code is wrong */
1113 kfree(buf);
1114 rtsx_trace(chip);
1115 return STATUS_FAIL;
1116 }
1117
1118 if ((buf[4] < 1) || (buf[4] > 12)) {
1119 kfree(buf);
1120 rtsx_trace(chip);
1121 return STATUS_FAIL;
1122 }
1123
1124 for (i = 0; i < buf[4]; i++) {
1125 int cur_addr_off = 16 + i * 12;
1126
1127 #ifdef SUPPORT_MSXC
1128 if ((buf[cur_addr_off + 8] == 0x10) ||
1129 (buf[cur_addr_off + 8] == 0x13)) {
1130 #else
1131 if (buf[cur_addr_off + 8] == 0x10) {
1132 #endif
1133 sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) |
1134 ((u32)buf[cur_addr_off + 1] << 16) |
1135 ((u32)buf[cur_addr_off + 2] << 8) |
1136 buf[cur_addr_off + 3];
1137 sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) |
1138 ((u32)buf[cur_addr_off + 5] << 16) |
1139 ((u32)buf[cur_addr_off + 6] << 8) |
1140 buf[cur_addr_off + 7];
1141 dev_dbg(rtsx_dev(chip), "sys_info_addr = 0x%x, sys_info_size = 0x%x\n",
1142 sys_info_addr, sys_info_size);
1143 if (sys_info_size != 96) {
1144 kfree(buf);
1145 rtsx_trace(chip);
1146 return STATUS_FAIL;
1147 }
1148 if (sys_info_addr < 0x1A0) {
1149 kfree(buf);
1150 rtsx_trace(chip);
1151 return STATUS_FAIL;
1152 }
1153 if ((sys_info_size + sys_info_addr) > 0x8000) {
1154 kfree(buf);
1155 rtsx_trace(chip);
1156 return STATUS_FAIL;
1157 }
1158
1159 #ifdef SUPPORT_MSXC
1160 if (buf[cur_addr_off + 8] == 0x13)
1161 ms_card->ms_type |= MS_XC;
1162 #endif
1163 #ifdef SUPPORT_PCGL_1P18
1164 found_sys_info = 1;
1165 #else
1166 break;
1167 #endif
1168 }
1169 #ifdef SUPPORT_PCGL_1P18
1170 if (buf[cur_addr_off + 8] == 0x15) {
1171 model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) |
1172 ((u32)buf[cur_addr_off + 1] << 16) |
1173 ((u32)buf[cur_addr_off + 2] << 8) |
1174 buf[cur_addr_off + 3];
1175 model_name_size = ((u32)buf[cur_addr_off + 4] << 24) |
1176 ((u32)buf[cur_addr_off + 5] << 16) |
1177 ((u32)buf[cur_addr_off + 6] << 8) |
1178 buf[cur_addr_off + 7];
1179 dev_dbg(rtsx_dev(chip), "model_name_addr = 0x%x, model_name_size = 0x%x\n",
1180 model_name_addr, model_name_size);
1181 if (model_name_size != 48) {
1182 kfree(buf);
1183 rtsx_trace(chip);
1184 return STATUS_FAIL;
1185 }
1186 if (model_name_addr < 0x1A0) {
1187 kfree(buf);
1188 rtsx_trace(chip);
1189 return STATUS_FAIL;
1190 }
1191 if ((model_name_size + model_name_addr) > 0x8000) {
1192 kfree(buf);
1193 rtsx_trace(chip);
1194 return STATUS_FAIL;
1195 }
1196
1197 found_model_name = 1;
1198 }
1199
1200 if (found_sys_info && found_model_name)
1201 break;
1202 #endif
1203 }
1204
1205 if (i == buf[4]) {
1206 kfree(buf);
1207 rtsx_trace(chip);
1208 return STATUS_FAIL;
1209 }
1210
1211 class_code = buf[sys_info_addr + 0];
1212 device_type = buf[sys_info_addr + 56];
1213 sub_class = buf[sys_info_addr + 46];
1214 #ifdef SUPPORT_MSXC
1215 if (CHK_MSXC(ms_card)) {
1216 xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) |
1217 ((u32)buf[sys_info_addr + 7] << 16) |
1218 ((u32)buf[sys_info_addr + 8] << 8) |
1219 buf[sys_info_addr + 9];
1220 xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) |
1221 ((u32)buf[sys_info_addr + 33] << 16) |
1222 ((u32)buf[sys_info_addr + 34] << 8) |
1223 buf[sys_info_addr + 35];
1224 dev_dbg(rtsx_dev(chip), "xc_total_blk = 0x%x, xc_blk_size = 0x%x\n",
1225 xc_total_blk, xc_blk_size);
1226 } else {
1227 total_blk = ((u16)buf[sys_info_addr + 6] << 8) |
1228 buf[sys_info_addr + 7];
1229 blk_size = ((u16)buf[sys_info_addr + 2] << 8) |
1230 buf[sys_info_addr + 3];
1231 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n",
1232 total_blk, blk_size);
1233 }
1234 #else
1235 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];
1236 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];
1237 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n",
1238 total_blk, blk_size);
1239 #endif
1240
1241 dev_dbg(rtsx_dev(chip), "class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n",
1242 class_code, device_type, sub_class);
1243
1244 memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96);
1245 #ifdef SUPPORT_PCGL_1P18
1246 memcpy(ms_card->raw_model_name, buf + model_name_addr, 48);
1247 #endif
1248
1249 kfree(buf);
1250
1251 #ifdef SUPPORT_MSXC
1252 if (CHK_MSXC(ms_card)) {
1253 if (class_code != 0x03) {
1254 rtsx_trace(chip);
1255 return STATUS_FAIL;
1256 }
1257 } else {
1258 if (class_code != 0x02) {
1259 rtsx_trace(chip);
1260 return STATUS_FAIL;
1261 }
1262 }
1263 #else
1264 if (class_code != 0x02) {
1265 rtsx_trace(chip);
1266 return STATUS_FAIL;
1267 }
1268 #endif
1269
1270 if (device_type != 0x00) {
1271 if ((device_type == 0x01) || (device_type == 0x02) ||
1272 (device_type == 0x03)) {
1273 chip->card_wp |= MS_CARD;
1274 } else {
1275 rtsx_trace(chip);
1276 return STATUS_FAIL;
1277 }
1278 }
1279
1280 if (sub_class & 0xC0) {
1281 rtsx_trace(chip);
1282 return STATUS_FAIL;
1283 }
1284
1285 dev_dbg(rtsx_dev(chip), "class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n",
1286 class_code, device_type, sub_class);
1287
1288 #ifdef SUPPORT_MSXC
1289 if (CHK_MSXC(ms_card)) {
1290 chip->capacity[chip->card2lun[MS_CARD]] =
1291 ms_card->capacity = xc_total_blk * xc_blk_size;
1292 } else {
1293 chip->capacity[chip->card2lun[MS_CARD]] =
1294 ms_card->capacity = total_blk * blk_size;
1295 }
1296 #else
1297 ms_card->capacity = total_blk * blk_size;
1298 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
1299 #endif
1300
1301 return STATUS_SUCCESS;
1302 }
1303
1304 #ifdef SUPPORT_MAGIC_GATE
1305 static int mg_set_tpc_para_sub(struct rtsx_chip *chip,
1306 int type, u8 mg_entry_num);
1307 #endif
1308
1309 static int reset_ms_pro(struct rtsx_chip *chip)
1310 {
1311 struct ms_info *ms_card = &chip->ms_card;
1312 int retval;
1313 #ifdef XC_POWERCLASS
1314 u8 change_power_class;
1315
1316 if (chip->ms_power_class_en & 0x02)
1317 change_power_class = 2;
1318 else if (chip->ms_power_class_en & 0x01)
1319 change_power_class = 1;
1320 else
1321 change_power_class = 0;
1322 #endif
1323
1324 #ifdef XC_POWERCLASS
1325 retry:
1326 #endif
1327 retval = ms_pro_reset_flow(chip, 1);
1328 if (retval != STATUS_SUCCESS) {
1329 if (ms_card->switch_8bit_fail) {
1330 retval = ms_pro_reset_flow(chip, 0);
1331 if (retval != STATUS_SUCCESS) {
1332 rtsx_trace(chip);
1333 return STATUS_FAIL;
1334 }
1335 } else {
1336 rtsx_trace(chip);
1337 return STATUS_FAIL;
1338 }
1339 }
1340
1341 retval = ms_read_attribute_info(chip);
1342 if (retval != STATUS_SUCCESS) {
1343 rtsx_trace(chip);
1344 return STATUS_FAIL;
1345 }
1346
1347 #ifdef XC_POWERCLASS
1348 if (CHK_HG8BIT(ms_card))
1349 change_power_class = 0;
1350
1351 if (change_power_class && CHK_MSXC(ms_card)) {
1352 u8 power_class_en = chip->ms_power_class_en;
1353
1354 dev_dbg(rtsx_dev(chip), "power_class_en = 0x%x\n",
1355 power_class_en);
1356 dev_dbg(rtsx_dev(chip), "change_power_class = %d\n",
1357 change_power_class);
1358
1359 if (change_power_class)
1360 power_class_en &= (1 << (change_power_class - 1));
1361 else
1362 power_class_en = 0;
1363
1364 if (power_class_en) {
1365 u8 power_class_mode =
1366 (ms_card->raw_sys_info[46] & 0x18) >> 3;
1367 dev_dbg(rtsx_dev(chip), "power_class_mode = 0x%x",
1368 power_class_mode);
1369 if (change_power_class > power_class_mode)
1370 change_power_class = power_class_mode;
1371 if (change_power_class) {
1372 retval = msxc_change_power(chip,
1373 change_power_class);
1374 if (retval != STATUS_SUCCESS) {
1375 change_power_class--;
1376 goto retry;
1377 }
1378 }
1379 }
1380 }
1381 #endif
1382
1383 #ifdef SUPPORT_MAGIC_GATE
1384 retval = mg_set_tpc_para_sub(chip, 0, 0);
1385 if (retval != STATUS_SUCCESS) {
1386 rtsx_trace(chip);
1387 return STATUS_FAIL;
1388 }
1389 #endif
1390
1391 if (CHK_HG8BIT(ms_card))
1392 chip->card_bus_width[chip->card2lun[MS_CARD]] = 8;
1393 else
1394 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
1395
1396 return STATUS_SUCCESS;
1397 }
1398
1399 static int ms_read_status_reg(struct rtsx_chip *chip)
1400 {
1401 int retval;
1402 u8 val[2];
1403
1404 retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0);
1405 if (retval != STATUS_SUCCESS) {
1406 rtsx_trace(chip);
1407 return STATUS_FAIL;
1408 }
1409
1410 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2);
1411 if (retval != STATUS_SUCCESS) {
1412 rtsx_trace(chip);
1413 return STATUS_FAIL;
1414 }
1415
1416 if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) {
1417 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1418 rtsx_trace(chip);
1419 return STATUS_FAIL;
1420 }
1421
1422 return STATUS_SUCCESS;
1423 }
1424
1425 static int ms_read_extra_data(struct rtsx_chip *chip,
1426 u16 block_addr, u8 page_num, u8 *buf, int buf_len)
1427 {
1428 struct ms_info *ms_card = &chip->ms_card;
1429 int retval, i;
1430 u8 val, data[10];
1431
1432 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1433 SystemParm, 6);
1434 if (retval != STATUS_SUCCESS) {
1435 rtsx_trace(chip);
1436 return STATUS_FAIL;
1437 }
1438
1439 if (CHK_MS4BIT(ms_card)) {
1440 /* Parallel interface */
1441 data[0] = 0x88;
1442 } else {
1443 /* Serial interface */
1444 data[0] = 0x80;
1445 }
1446 data[1] = 0;
1447 data[2] = (u8)(block_addr >> 8);
1448 data[3] = (u8)block_addr;
1449 data[4] = 0x40;
1450 data[5] = page_num;
1451
1452 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1453 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
1454 data, 6);
1455 if (retval == STATUS_SUCCESS)
1456 break;
1457 }
1458 if (i == MS_MAX_RETRY_COUNT) {
1459 rtsx_trace(chip);
1460 return STATUS_FAIL;
1461 }
1462
1463 ms_set_err_code(chip, MS_NO_ERROR);
1464
1465 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1466 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1467 if (retval == STATUS_SUCCESS)
1468 break;
1469 }
1470 if (i == MS_MAX_RETRY_COUNT) {
1471 rtsx_trace(chip);
1472 return STATUS_FAIL;
1473 }
1474
1475 ms_set_err_code(chip, MS_NO_ERROR);
1476 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1477 if (retval != STATUS_SUCCESS) {
1478 rtsx_trace(chip);
1479 return STATUS_FAIL;
1480 }
1481
1482 if (val & INT_REG_CMDNK) {
1483 ms_set_err_code(chip, MS_CMD_NK);
1484 rtsx_trace(chip);
1485 return STATUS_FAIL;
1486 }
1487 if (val & INT_REG_CED) {
1488 if (val & INT_REG_ERR) {
1489 retval = ms_read_status_reg(chip);
1490 if (retval != STATUS_SUCCESS) {
1491 rtsx_trace(chip);
1492 return STATUS_FAIL;
1493 }
1494
1495 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1496 MS_EXTRA_SIZE, SystemParm,
1497 6);
1498 if (retval != STATUS_SUCCESS) {
1499 rtsx_trace(chip);
1500 return STATUS_FAIL;
1501 }
1502 }
1503 }
1504
1505 retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT,
1506 data, MS_EXTRA_SIZE);
1507 if (retval != STATUS_SUCCESS) {
1508 rtsx_trace(chip);
1509 return STATUS_FAIL;
1510 }
1511
1512 if (buf && buf_len) {
1513 if (buf_len > MS_EXTRA_SIZE)
1514 buf_len = MS_EXTRA_SIZE;
1515 memcpy(buf, data, buf_len);
1516 }
1517
1518 return STATUS_SUCCESS;
1519 }
1520
1521 static int ms_write_extra_data(struct rtsx_chip *chip, u16 block_addr,
1522 u8 page_num, u8 *buf, int buf_len)
1523 {
1524 struct ms_info *ms_card = &chip->ms_card;
1525 int retval, i;
1526 u8 val, data[16];
1527
1528 if (!buf || (buf_len < MS_EXTRA_SIZE)) {
1529 rtsx_trace(chip);
1530 return STATUS_FAIL;
1531 }
1532
1533 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1534 SystemParm, 6 + MS_EXTRA_SIZE);
1535 if (retval != STATUS_SUCCESS) {
1536 rtsx_trace(chip);
1537 return STATUS_FAIL;
1538 }
1539
1540 if (CHK_MS4BIT(ms_card))
1541 data[0] = 0x88;
1542 else
1543 data[0] = 0x80;
1544
1545 data[1] = 0;
1546 data[2] = (u8)(block_addr >> 8);
1547 data[3] = (u8)block_addr;
1548 data[4] = 0x40;
1549 data[5] = page_num;
1550
1551 for (i = 6; i < MS_EXTRA_SIZE + 6; i++)
1552 data[i] = buf[i - 6];
1553
1554 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),
1555 NO_WAIT_INT, data, 16);
1556 if (retval != STATUS_SUCCESS) {
1557 rtsx_trace(chip);
1558 return STATUS_FAIL;
1559 }
1560
1561 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1562 if (retval != STATUS_SUCCESS) {
1563 rtsx_trace(chip);
1564 return STATUS_FAIL;
1565 }
1566
1567 ms_set_err_code(chip, MS_NO_ERROR);
1568 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1569 if (retval != STATUS_SUCCESS) {
1570 rtsx_trace(chip);
1571 return STATUS_FAIL;
1572 }
1573
1574 if (val & INT_REG_CMDNK) {
1575 ms_set_err_code(chip, MS_CMD_NK);
1576 rtsx_trace(chip);
1577 return STATUS_FAIL;
1578 }
1579 if (val & INT_REG_CED) {
1580 if (val & INT_REG_ERR) {
1581 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1582 rtsx_trace(chip);
1583 return STATUS_FAIL;
1584 }
1585 }
1586
1587 return STATUS_SUCCESS;
1588 }
1589
1590 static int ms_read_page(struct rtsx_chip *chip, u16 block_addr, u8 page_num)
1591 {
1592 struct ms_info *ms_card = &chip->ms_card;
1593 int retval;
1594 u8 val, data[6];
1595
1596 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1597 SystemParm, 6);
1598 if (retval != STATUS_SUCCESS) {
1599 rtsx_trace(chip);
1600 return STATUS_FAIL;
1601 }
1602
1603 if (CHK_MS4BIT(ms_card))
1604 data[0] = 0x88;
1605 else
1606 data[0] = 0x80;
1607
1608 data[1] = 0;
1609 data[2] = (u8)(block_addr >> 8);
1610 data[3] = (u8)block_addr;
1611 data[4] = 0x20;
1612 data[5] = page_num;
1613
1614 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1615 if (retval != STATUS_SUCCESS) {
1616 rtsx_trace(chip);
1617 return STATUS_FAIL;
1618 }
1619
1620 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1621 if (retval != STATUS_SUCCESS) {
1622 rtsx_trace(chip);
1623 return STATUS_FAIL;
1624 }
1625
1626 ms_set_err_code(chip, MS_NO_ERROR);
1627 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1628 if (retval != STATUS_SUCCESS) {
1629 rtsx_trace(chip);
1630 return STATUS_FAIL;
1631 }
1632
1633 if (val & INT_REG_CMDNK) {
1634 ms_set_err_code(chip, MS_CMD_NK);
1635 rtsx_trace(chip);
1636 return STATUS_FAIL;
1637 }
1638
1639 if (val & INT_REG_CED) {
1640 if (val & INT_REG_ERR) {
1641 if (!(val & INT_REG_BREQ)) {
1642 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1643 rtsx_trace(chip);
1644 return STATUS_FAIL;
1645 }
1646 retval = ms_read_status_reg(chip);
1647 if (retval != STATUS_SUCCESS)
1648 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1649
1650 } else {
1651 if (!(val & INT_REG_BREQ)) {
1652 ms_set_err_code(chip, MS_BREQ_ERROR);
1653 rtsx_trace(chip);
1654 return STATUS_FAIL;
1655 }
1656 }
1657 }
1658
1659 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA,
1660 0, NO_WAIT_INT);
1661 if (retval != STATUS_SUCCESS) {
1662 rtsx_trace(chip);
1663 return STATUS_FAIL;
1664 }
1665
1666 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {
1667 rtsx_trace(chip);
1668 return STATUS_FAIL;
1669 }
1670
1671 return STATUS_SUCCESS;
1672 }
1673
1674 static int ms_set_bad_block(struct rtsx_chip *chip, u16 phy_blk)
1675 {
1676 struct ms_info *ms_card = &chip->ms_card;
1677 int retval;
1678 u8 val, data[8], extra[MS_EXTRA_SIZE];
1679
1680 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);
1681 if (retval != STATUS_SUCCESS) {
1682 rtsx_trace(chip);
1683 return STATUS_FAIL;
1684 }
1685
1686 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1687 SystemParm, 7);
1688 if (retval != STATUS_SUCCESS) {
1689 rtsx_trace(chip);
1690 return STATUS_FAIL;
1691 }
1692
1693 ms_set_err_code(chip, MS_NO_ERROR);
1694
1695 if (CHK_MS4BIT(ms_card))
1696 data[0] = 0x88;
1697 else
1698 data[0] = 0x80;
1699
1700 data[1] = 0;
1701 data[2] = (u8)(phy_blk >> 8);
1702 data[3] = (u8)phy_blk;
1703 data[4] = 0x80;
1704 data[5] = 0;
1705 data[6] = extra[0] & 0x7F;
1706 data[7] = 0xFF;
1707
1708 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 7);
1709 if (retval != STATUS_SUCCESS) {
1710 rtsx_trace(chip);
1711 return STATUS_FAIL;
1712 }
1713
1714 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1715 if (retval != STATUS_SUCCESS) {
1716 rtsx_trace(chip);
1717 return STATUS_FAIL;
1718 }
1719
1720 ms_set_err_code(chip, MS_NO_ERROR);
1721 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1722 if (retval != STATUS_SUCCESS) {
1723 rtsx_trace(chip);
1724 return STATUS_FAIL;
1725 }
1726
1727 if (val & INT_REG_CMDNK) {
1728 ms_set_err_code(chip, MS_CMD_NK);
1729 rtsx_trace(chip);
1730 return STATUS_FAIL;
1731 }
1732
1733 if (val & INT_REG_CED) {
1734 if (val & INT_REG_ERR) {
1735 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1736 rtsx_trace(chip);
1737 return STATUS_FAIL;
1738 }
1739 }
1740
1741 return STATUS_SUCCESS;
1742 }
1743
1744 static int ms_erase_block(struct rtsx_chip *chip, u16 phy_blk)
1745 {
1746 struct ms_info *ms_card = &chip->ms_card;
1747 int retval, i = 0;
1748 u8 val, data[6];
1749
1750 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1751 SystemParm, 6);
1752 if (retval != STATUS_SUCCESS) {
1753 rtsx_trace(chip);
1754 return STATUS_FAIL;
1755 }
1756
1757 ms_set_err_code(chip, MS_NO_ERROR);
1758
1759 if (CHK_MS4BIT(ms_card))
1760 data[0] = 0x88;
1761 else
1762 data[0] = 0x80;
1763
1764 data[1] = 0;
1765 data[2] = (u8)(phy_blk >> 8);
1766 data[3] = (u8)phy_blk;
1767 data[4] = 0;
1768 data[5] = 0;
1769
1770 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1771 if (retval != STATUS_SUCCESS) {
1772 rtsx_trace(chip);
1773 return STATUS_FAIL;
1774 }
1775
1776 ERASE_RTY:
1777 retval = ms_send_cmd(chip, BLOCK_ERASE, WAIT_INT);
1778 if (retval != STATUS_SUCCESS) {
1779 rtsx_trace(chip);
1780 return STATUS_FAIL;
1781 }
1782
1783 ms_set_err_code(chip, MS_NO_ERROR);
1784 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1785 if (retval != STATUS_SUCCESS) {
1786 rtsx_trace(chip);
1787 return STATUS_FAIL;
1788 }
1789
1790 if (val & INT_REG_CMDNK) {
1791 if (i < 3) {
1792 i++;
1793 goto ERASE_RTY;
1794 }
1795
1796 ms_set_err_code(chip, MS_CMD_NK);
1797 ms_set_bad_block(chip, phy_blk);
1798 rtsx_trace(chip);
1799 return STATUS_FAIL;
1800 }
1801
1802 if (val & INT_REG_CED) {
1803 if (val & INT_REG_ERR) {
1804 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1805 rtsx_trace(chip);
1806 return STATUS_FAIL;
1807 }
1808 }
1809
1810 return STATUS_SUCCESS;
1811 }
1812
1813 static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len)
1814 {
1815 if (!extra || (extra_len < MS_EXTRA_SIZE))
1816 return;
1817
1818 memset(extra, 0xFF, MS_EXTRA_SIZE);
1819
1820 if (type == setPS_NG) {
1821 /* set page status as 1:NG,and block status keep 1:OK */
1822 extra[0] = 0xB8;
1823 } else {
1824 /* set page status as 0:Data Error,and block status keep 1:OK */
1825 extra[0] = 0x98;
1826 }
1827
1828 extra[2] = (u8)(log_blk >> 8);
1829 extra[3] = (u8)log_blk;
1830 }
1831
1832 static int ms_init_page(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk,
1833 u8 start_page, u8 end_page)
1834 {
1835 int retval;
1836 u8 extra[MS_EXTRA_SIZE], i;
1837
1838 memset(extra, 0xff, MS_EXTRA_SIZE);
1839
1840 extra[0] = 0xf8; /* Block, page OK, data erased */
1841 extra[1] = 0xff;
1842 extra[2] = (u8)(log_blk >> 8);
1843 extra[3] = (u8)log_blk;
1844
1845 for (i = start_page; i < end_page; i++) {
1846 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1847 ms_set_err_code(chip, MS_NO_CARD);
1848 rtsx_trace(chip);
1849 return STATUS_FAIL;
1850 }
1851
1852 retval = ms_write_extra_data(chip, phy_blk, i,
1853 extra, MS_EXTRA_SIZE);
1854 if (retval != STATUS_SUCCESS) {
1855 rtsx_trace(chip);
1856 return STATUS_FAIL;
1857 }
1858 }
1859
1860 return STATUS_SUCCESS;
1861 }
1862
1863 static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
1864 u16 log_blk, u8 start_page, u8 end_page)
1865 {
1866 struct ms_info *ms_card = &chip->ms_card;
1867 bool uncorrect_flag = false;
1868 int retval, rty_cnt;
1869 u8 extra[MS_EXTRA_SIZE], val, i, j, data[16];
1870
1871 dev_dbg(rtsx_dev(chip), "Copy page from 0x%x to 0x%x, logical block is 0x%x\n",
1872 old_blk, new_blk, log_blk);
1873 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d\n",
1874 start_page, end_page);
1875
1876 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE);
1877 if (retval != STATUS_SUCCESS) {
1878 rtsx_trace(chip);
1879 return STATUS_FAIL;
1880 }
1881
1882 retval = ms_read_status_reg(chip);
1883 if (retval != STATUS_SUCCESS) {
1884 rtsx_trace(chip);
1885 return STATUS_FAIL;
1886 }
1887
1888 retval = rtsx_read_register(chip, PPBUF_BASE2, &val);
1889 if (retval) {
1890 rtsx_trace(chip);
1891 return retval;
1892 }
1893
1894 if (val & BUF_FULL) {
1895 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);
1896 if (retval != STATUS_SUCCESS) {
1897 rtsx_trace(chip);
1898 return STATUS_FAIL;
1899 }
1900
1901 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1902 if (retval != STATUS_SUCCESS) {
1903 rtsx_trace(chip);
1904 return STATUS_FAIL;
1905 }
1906
1907 if (!(val & INT_REG_CED)) {
1908 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1909 rtsx_trace(chip);
1910 return STATUS_FAIL;
1911 }
1912 }
1913
1914 for (i = start_page; i < end_page; i++) {
1915 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1916 ms_set_err_code(chip, MS_NO_CARD);
1917 rtsx_trace(chip);
1918 return STATUS_FAIL;
1919 }
1920
1921 ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE);
1922
1923 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1924 MS_EXTRA_SIZE, SystemParm, 6);
1925 if (retval != STATUS_SUCCESS) {
1926 rtsx_trace(chip);
1927 return STATUS_FAIL;
1928 }
1929
1930 ms_set_err_code(chip, MS_NO_ERROR);
1931
1932 if (CHK_MS4BIT(ms_card))
1933 data[0] = 0x88;
1934 else
1935 data[0] = 0x80;
1936
1937 data[1] = 0;
1938 data[2] = (u8)(old_blk >> 8);
1939 data[3] = (u8)old_blk;
1940 data[4] = 0x20;
1941 data[5] = i;
1942
1943 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
1944 data, 6);
1945 if (retval != STATUS_SUCCESS) {
1946 rtsx_trace(chip);
1947 return STATUS_FAIL;
1948 }
1949
1950 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1951 if (retval != STATUS_SUCCESS) {
1952 rtsx_trace(chip);
1953 return STATUS_FAIL;
1954 }
1955
1956 ms_set_err_code(chip, MS_NO_ERROR);
1957 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1958 if (retval != STATUS_SUCCESS) {
1959 rtsx_trace(chip);
1960 return STATUS_FAIL;
1961 }
1962
1963 if (val & INT_REG_CMDNK) {
1964 ms_set_err_code(chip, MS_CMD_NK);
1965 rtsx_trace(chip);
1966 return STATUS_FAIL;
1967 }
1968
1969 if (val & INT_REG_CED) {
1970 if (val & INT_REG_ERR) {
1971 retval = ms_read_status_reg(chip);
1972 if (retval != STATUS_SUCCESS) {
1973 uncorrect_flag = true;
1974 dev_dbg(rtsx_dev(chip), "Uncorrectable error\n");
1975 } else {
1976 uncorrect_flag = false;
1977 }
1978
1979 retval = ms_transfer_tpc(chip,
1980 MS_TM_NORMAL_READ,
1981 READ_PAGE_DATA,
1982 0, NO_WAIT_INT);
1983 if (retval != STATUS_SUCCESS) {
1984 rtsx_trace(chip);
1985 return STATUS_FAIL;
1986 }
1987
1988 if (uncorrect_flag) {
1989 ms_set_page_status(log_blk, setPS_NG,
1990 extra,
1991 MS_EXTRA_SIZE);
1992 if (i == 0)
1993 extra[0] &= 0xEF;
1994
1995 ms_write_extra_data(chip, old_blk, i,
1996 extra,
1997 MS_EXTRA_SIZE);
1998 dev_dbg(rtsx_dev(chip), "page %d : extra[0] = 0x%x\n",
1999 i, extra[0]);
2000 MS_SET_BAD_BLOCK_FLG(ms_card);
2001
2002 ms_set_page_status(log_blk, setPS_Error,
2003 extra,
2004 MS_EXTRA_SIZE);
2005 ms_write_extra_data(chip, new_blk, i,
2006 extra,
2007 MS_EXTRA_SIZE);
2008 continue;
2009 }
2010
2011 for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT;
2012 rty_cnt++) {
2013 retval = ms_transfer_tpc(
2014 chip,
2015 MS_TM_NORMAL_WRITE,
2016 WRITE_PAGE_DATA,
2017 0, NO_WAIT_INT);
2018 if (retval == STATUS_SUCCESS)
2019 break;
2020 }
2021 if (rty_cnt == MS_MAX_RETRY_COUNT) {
2022 rtsx_trace(chip);
2023 return STATUS_FAIL;
2024 }
2025 }
2026
2027 if (!(val & INT_REG_BREQ)) {
2028 ms_set_err_code(chip, MS_BREQ_ERROR);
2029 rtsx_trace(chip);
2030 return STATUS_FAIL;
2031 }
2032 }
2033
2034 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
2035 SystemParm, (6 + MS_EXTRA_SIZE));
2036
2037 ms_set_err_code(chip, MS_NO_ERROR);
2038
2039 if (CHK_MS4BIT(ms_card))
2040 data[0] = 0x88;
2041 else
2042 data[0] = 0x80;
2043
2044 data[1] = 0;
2045 data[2] = (u8)(new_blk >> 8);
2046 data[3] = (u8)new_blk;
2047 data[4] = 0x20;
2048 data[5] = i;
2049
2050 if ((extra[0] & 0x60) != 0x60)
2051 data[6] = extra[0];
2052 else
2053 data[6] = 0xF8;
2054
2055 data[6 + 1] = 0xFF;
2056 data[6 + 2] = (u8)(log_blk >> 8);
2057 data[6 + 3] = (u8)log_blk;
2058
2059 for (j = 4; j <= MS_EXTRA_SIZE; j++)
2060 data[6 + j] = 0xFF;
2061
2062 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),
2063 NO_WAIT_INT, data, 16);
2064 if (retval != STATUS_SUCCESS) {
2065 rtsx_trace(chip);
2066 return STATUS_FAIL;
2067 }
2068
2069 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
2070 if (retval != STATUS_SUCCESS) {
2071 rtsx_trace(chip);
2072 return STATUS_FAIL;
2073 }
2074
2075 ms_set_err_code(chip, MS_NO_ERROR);
2076 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
2077 if (retval != STATUS_SUCCESS) {
2078 rtsx_trace(chip);
2079 return STATUS_FAIL;
2080 }
2081
2082 if (val & INT_REG_CMDNK) {
2083 ms_set_err_code(chip, MS_CMD_NK);
2084 rtsx_trace(chip);
2085 return STATUS_FAIL;
2086 }
2087
2088 if (val & INT_REG_CED) {
2089 if (val & INT_REG_ERR) {
2090 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
2091 rtsx_trace(chip);
2092 return STATUS_FAIL;
2093 }
2094 }
2095
2096 if (i == 0) {
2097 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
2098 MS_EXTRA_SIZE, SystemParm,
2099 7);
2100 if (retval != STATUS_SUCCESS) {
2101 rtsx_trace(chip);
2102 return STATUS_FAIL;
2103 }
2104
2105 ms_set_err_code(chip, MS_NO_ERROR);
2106
2107 if (CHK_MS4BIT(ms_card))
2108 data[0] = 0x88;
2109 else
2110 data[0] = 0x80;
2111
2112 data[1] = 0;
2113 data[2] = (u8)(old_blk >> 8);
2114 data[3] = (u8)old_blk;
2115 data[4] = 0x80;
2116 data[5] = 0;
2117 data[6] = 0xEF;
2118 data[7] = 0xFF;
2119
2120 retval = ms_write_bytes(chip, WRITE_REG, 7,
2121 NO_WAIT_INT, data, 8);
2122 if (retval != STATUS_SUCCESS) {
2123 rtsx_trace(chip);
2124 return STATUS_FAIL;
2125 }
2126
2127 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
2128 if (retval != STATUS_SUCCESS) {
2129 rtsx_trace(chip);
2130 return STATUS_FAIL;
2131 }
2132
2133 ms_set_err_code(chip, MS_NO_ERROR);
2134 retval = ms_read_bytes(chip, GET_INT, 1,
2135 NO_WAIT_INT, &val, 1);
2136 if (retval != STATUS_SUCCESS) {
2137 rtsx_trace(chip);
2138 return STATUS_FAIL;
2139 }
2140
2141 if (val & INT_REG_CMDNK) {
2142 ms_set_err_code(chip, MS_CMD_NK);
2143 rtsx_trace(chip);
2144 return STATUS_FAIL;
2145 }
2146
2147 if (val & INT_REG_CED) {
2148 if (val & INT_REG_ERR) {
2149 ms_set_err_code(chip,
2150 MS_FLASH_WRITE_ERROR);
2151 rtsx_trace(chip);
2152 return STATUS_FAIL;
2153 }
2154 }
2155 }
2156 }
2157
2158 return STATUS_SUCCESS;
2159 }
2160
2161 static int reset_ms(struct rtsx_chip *chip)
2162 {
2163 struct ms_info *ms_card = &chip->ms_card;
2164 int retval;
2165 u16 i, reg_addr, block_size;
2166 u8 val, extra[MS_EXTRA_SIZE], j, *ptr;
2167 #ifndef SUPPORT_MAGIC_GATE
2168 u16 eblock_cnt;
2169 #endif
2170
2171 retval = ms_prepare_reset(chip);
2172 if (retval != STATUS_SUCCESS) {
2173 rtsx_trace(chip);
2174 return STATUS_FAIL;
2175 }
2176
2177 ms_card->ms_type |= TYPE_MS;
2178
2179 retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT);
2180 if (retval != STATUS_SUCCESS) {
2181 rtsx_trace(chip);
2182 return STATUS_FAIL;
2183 }
2184
2185 retval = ms_read_status_reg(chip);
2186 if (retval != STATUS_SUCCESS) {
2187 rtsx_trace(chip);
2188 return STATUS_FAIL;
2189 }
2190
2191 retval = rtsx_read_register(chip, PPBUF_BASE2, &val);
2192 if (retval) {
2193 rtsx_trace(chip);
2194 return retval;
2195 }
2196 if (val & WRT_PRTCT)
2197 chip->card_wp |= MS_CARD;
2198 else
2199 chip->card_wp &= ~MS_CARD;
2200
2201 i = 0;
2202
2203 RE_SEARCH:
2204 /* Search Boot Block */
2205 while (i < (MAX_DEFECTIVE_BLOCK + 2)) {
2206 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
2207 ms_set_err_code(chip, MS_NO_CARD);
2208 rtsx_trace(chip);
2209 return STATUS_FAIL;
2210 }
2211
2212 retval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE);
2213 if (retval != STATUS_SUCCESS) {
2214 i++;
2215 continue;
2216 }
2217
2218 if (extra[0] & BLOCK_OK) {
2219 if (!(extra[1] & NOT_BOOT_BLOCK)) {
2220 ms_card->boot_block = i;
2221 break;
2222 }
2223 }
2224 i++;
2225 }
2226
2227 if (i == (MAX_DEFECTIVE_BLOCK + 2)) {
2228 dev_dbg(rtsx_dev(chip), "No boot block found!");
2229 rtsx_trace(chip);
2230 return STATUS_FAIL;
2231 }
2232
2233 for (j = 0; j < 3; j++) {
2234 retval = ms_read_page(chip, ms_card->boot_block, j);
2235 if (retval != STATUS_SUCCESS) {
2236 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {
2237 i = ms_card->boot_block + 1;
2238 ms_set_err_code(chip, MS_NO_ERROR);
2239 goto RE_SEARCH;
2240 }
2241 }
2242 }
2243
2244 retval = ms_read_page(chip, ms_card->boot_block, 0);
2245 if (retval != STATUS_SUCCESS) {
2246 rtsx_trace(chip);
2247 return STATUS_FAIL;
2248 }
2249
2250 /* Read MS system information as sys_info */
2251 rtsx_init_cmd(chip);
2252
2253 for (i = 0; i < 96; i++)
2254 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0);
2255
2256 retval = rtsx_send_cmd(chip, MS_CARD, 100);
2257 if (retval < 0) {
2258 rtsx_trace(chip);
2259 return STATUS_FAIL;
2260 }
2261
2262 ptr = rtsx_get_cmd_data(chip);
2263 memcpy(ms_card->raw_sys_info, ptr, 96);
2264
2265 /* Read useful block contents */
2266 rtsx_init_cmd(chip);
2267
2268 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0);
2269 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0);
2270
2271 for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3;
2272 reg_addr++)
2273 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
2274
2275 for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++)
2276 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
2277
2278 rtsx_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0);
2279 rtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0);
2280
2281 retval = rtsx_send_cmd(chip, MS_CARD, 100);
2282 if (retval < 0) {
2283 rtsx_trace(chip);
2284 return STATUS_FAIL;
2285 }
2286
2287 ptr = rtsx_get_cmd_data(chip);
2288
2289 dev_dbg(rtsx_dev(chip), "Boot block data:\n");
2290 dev_dbg(rtsx_dev(chip), "%*ph\n", 16, ptr);
2291
2292 /* Block ID error
2293 * HEADER_ID0, HEADER_ID1
2294 */
2295 if (ptr[0] != 0x00 || ptr[1] != 0x01) {
2296 i = ms_card->boot_block + 1;
2297 goto RE_SEARCH;
2298 }
2299
2300 /* Page size error
2301 * PAGE_SIZE_0, PAGE_SIZE_1
2302 */
2303 if (ptr[12] != 0x02 || ptr[13] != 0x00) {
2304 i = ms_card->boot_block + 1;
2305 goto RE_SEARCH;
2306 }
2307
2308 if ((ptr[14] == 1) || (ptr[14] == 3))
2309 chip->card_wp |= MS_CARD;
2310
2311 /* BLOCK_SIZE_0, BLOCK_SIZE_1 */
2312 block_size = ((u16)ptr[6] << 8) | ptr[7];
2313 if (block_size == 0x0010) {
2314 /* Block size 16KB */
2315 ms_card->block_shift = 5;
2316 ms_card->page_off = 0x1F;
2317 } else if (block_size == 0x0008) {
2318 /* Block size 8KB */
2319 ms_card->block_shift = 4;
2320 ms_card->page_off = 0x0F;
2321 }
2322
2323 /* BLOCK_COUNT_0, BLOCK_COUNT_1 */
2324 ms_card->total_block = ((u16)ptr[8] << 8) | ptr[9];
2325
2326 #ifdef SUPPORT_MAGIC_GATE
2327 j = ptr[10];
2328
2329 if (ms_card->block_shift == 4) { /* 4MB or 8MB */
2330 if (j < 2) { /* Effective block for 4MB: 0x1F0 */
2331 ms_card->capacity = 0x1EE0;
2332 } else { /* Effective block for 8MB: 0x3E0 */
2333 ms_card->capacity = 0x3DE0;
2334 }
2335 } else { /* 16MB, 32MB, 64MB or 128MB */
2336 if (j < 5) { /* Effective block for 16MB: 0x3E0 */
2337 ms_card->capacity = 0x7BC0;
2338 } else if (j < 0xA) { /* Effective block for 32MB: 0x7C0 */
2339 ms_card->capacity = 0xF7C0;
2340 } else if (j < 0x11) { /* Effective block for 64MB: 0xF80 */
2341 ms_card->capacity = 0x1EF80;
2342 } else { /* Effective block for 128MB: 0x1F00 */
2343 ms_card->capacity = 0x3DF00;
2344 }
2345 }
2346 #else
2347 /* EBLOCK_COUNT_0, EBLOCK_COUNT_1 */
2348 eblock_cnt = ((u16)ptr[10] << 8) | ptr[11];
2349
2350 ms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift;
2351 #endif
2352
2353 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
2354
2355 /* Switch I/F Mode */
2356 if (ptr[15]) {
2357 retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1);
2358 if (retval != STATUS_SUCCESS) {
2359 rtsx_trace(chip);
2360 return STATUS_FAIL;
2361 }
2362
2363 retval = rtsx_write_register(chip, PPBUF_BASE2, 0xFF, 0x88);
2364 if (retval) {
2365 rtsx_trace(chip);
2366 return retval;
2367 }
2368 retval = rtsx_write_register(chip, PPBUF_BASE2 + 1, 0xFF, 0);
2369 if (retval) {
2370 rtsx_trace(chip);
2371 return retval;
2372 }
2373
2374 retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1,
2375 NO_WAIT_INT);
2376 if (retval != STATUS_SUCCESS) {
2377 rtsx_trace(chip);
2378 return STATUS_FAIL;
2379 }
2380
2381 retval = rtsx_write_register(chip, MS_CFG,
2382 0x58 | MS_NO_CHECK_INT,
2383 MS_BUS_WIDTH_4 |
2384 PUSH_TIME_ODD |
2385 MS_NO_CHECK_INT);
2386 if (retval) {
2387 rtsx_trace(chip);
2388 return retval;
2389 }
2390
2391 ms_card->ms_type |= MS_4BIT;
2392 }
2393
2394 if (CHK_MS4BIT(ms_card))
2395 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
2396 else
2397 chip->card_bus_width[chip->card2lun[MS_CARD]] = 1;
2398
2399 return STATUS_SUCCESS;
2400 }
2401
2402 static int ms_init_l2p_tbl(struct rtsx_chip *chip)
2403 {
2404 struct ms_info *ms_card = &chip->ms_card;
2405 int size, i, seg_no, retval;
2406 u16 defect_block, reg_addr;
2407 u8 val1, val2;
2408
2409 ms_card->segment_cnt = ms_card->total_block >> 9;
2410 dev_dbg(rtsx_dev(chip), "ms_card->segment_cnt = %d\n",
2411 ms_card->segment_cnt);
2412
2413 size = ms_card->segment_cnt * sizeof(struct zone_entry);
2414 ms_card->segment = vzalloc(size);
2415 if (!ms_card->segment) {
2416 rtsx_trace(chip);
2417 return STATUS_FAIL;
2418 }
2419
2420 retval = ms_read_page(chip, ms_card->boot_block, 1);
2421 if (retval != STATUS_SUCCESS) {
2422 rtsx_trace(chip);
2423 goto INIT_FAIL;
2424 }
2425
2426 reg_addr = PPBUF_BASE2;
2427 for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) {
2428 int block_no;
2429
2430 retval = rtsx_read_register(chip, reg_addr++, &val1);
2431 if (retval != STATUS_SUCCESS) {
2432 rtsx_trace(chip);
2433 goto INIT_FAIL;
2434 }
2435
2436 retval = rtsx_read_register(chip, reg_addr++, &val2);
2437 if (retval != STATUS_SUCCESS) {
2438 rtsx_trace(chip);
2439 goto INIT_FAIL;
2440 }
2441
2442 defect_block = ((u16)val1 << 8) | val2;
2443 if (defect_block == 0xFFFF)
2444 break;
2445
2446 seg_no = defect_block / 512;
2447
2448 block_no = ms_card->segment[seg_no].disable_count++;
2449 ms_card->segment[seg_no].defect_list[block_no] = defect_block;
2450 }
2451
2452 for (i = 0; i < ms_card->segment_cnt; i++) {
2453 ms_card->segment[i].build_flag = 0;
2454 ms_card->segment[i].l2p_table = NULL;
2455 ms_card->segment[i].free_table = NULL;
2456 ms_card->segment[i].get_index = 0;
2457 ms_card->segment[i].set_index = 0;
2458 ms_card->segment[i].unused_blk_cnt = 0;
2459
2460 dev_dbg(rtsx_dev(chip), "defective block count of segment %d is %d\n",
2461 i, ms_card->segment[i].disable_count);
2462 }
2463
2464 return STATUS_SUCCESS;
2465
2466 INIT_FAIL:
2467 vfree(ms_card->segment);
2468 ms_card->segment = NULL;
2469
2470 return STATUS_FAIL;
2471 }
2472
2473 static u16 ms_get_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off)
2474 {
2475 struct ms_info *ms_card = &chip->ms_card;
2476 struct zone_entry *segment;
2477
2478 if (!ms_card->segment)
2479 return 0xFFFF;
2480
2481 segment = &ms_card->segment[seg_no];
2482
2483 if (segment->l2p_table)
2484 return segment->l2p_table[log_off];
2485
2486 return 0xFFFF;
2487 }
2488
2489 static void ms_set_l2p_tbl(struct rtsx_chip *chip,
2490 int seg_no, u16 log_off, u16 phy_blk)
2491 {
2492 struct ms_info *ms_card = &chip->ms_card;
2493 struct zone_entry *segment;
2494
2495 if (!ms_card->segment)
2496 return;
2497
2498 segment = &ms_card->segment[seg_no];
2499 if (segment->l2p_table)
2500 segment->l2p_table[log_off] = phy_blk;
2501 }
2502
2503 static void ms_set_unused_block(struct rtsx_chip *chip, u16 phy_blk)
2504 {
2505 struct ms_info *ms_card = &chip->ms_card;
2506 struct zone_entry *segment;
2507 int seg_no;
2508
2509 seg_no = (int)phy_blk >> 9;
2510 segment = &ms_card->segment[seg_no];
2511
2512 segment->free_table[segment->set_index++] = phy_blk;
2513 if (segment->set_index >= MS_FREE_TABLE_CNT)
2514 segment->set_index = 0;
2515
2516 segment->unused_blk_cnt++;
2517 }
2518
2519 static u16 ms_get_unused_block(struct rtsx_chip *chip, int seg_no)
2520 {
2521 struct ms_info *ms_card = &chip->ms_card;
2522 struct zone_entry *segment;
2523 u16 phy_blk;
2524
2525 segment = &ms_card->segment[seg_no];
2526
2527 if (segment->unused_blk_cnt <= 0)
2528 return 0xFFFF;
2529
2530 phy_blk = segment->free_table[segment->get_index];
2531 segment->free_table[segment->get_index++] = 0xFFFF;
2532 if (segment->get_index >= MS_FREE_TABLE_CNT)
2533 segment->get_index = 0;
2534
2535 segment->unused_blk_cnt--;
2536
2537 return phy_blk;
2538 }
2539
2540 static const unsigned short ms_start_idx[] = {0, 494, 990, 1486, 1982, 2478,
2541 2974, 3470, 3966, 4462, 4958,
2542 5454, 5950, 6446, 6942, 7438,
2543 7934};
2544
2545 static int ms_arbitrate_l2p(struct rtsx_chip *chip, u16 phy_blk,
2546 u16 log_off, u8 us1, u8 us2)
2547 {
2548 struct ms_info *ms_card = &chip->ms_card;
2549 struct zone_entry *segment;
2550 int seg_no;
2551 u16 tmp_blk;
2552
2553 seg_no = (int)phy_blk >> 9;
2554 segment = &ms_card->segment[seg_no];
2555 tmp_blk = segment->l2p_table[log_off];
2556
2557 if (us1 != us2) {
2558 if (us1 == 0) {
2559 if (!(chip->card_wp & MS_CARD))
2560 ms_erase_block(chip, tmp_blk);
2561
2562 ms_set_unused_block(chip, tmp_blk);
2563 segment->l2p_table[log_off] = phy_blk;
2564 } else {
2565 if (!(chip->card_wp & MS_CARD))
2566 ms_erase_block(chip, phy_blk);
2567
2568 ms_set_unused_block(chip, phy_blk);
2569 }
2570 } else {
2571 if (phy_blk < tmp_blk) {
2572 if (!(chip->card_wp & MS_CARD))
2573 ms_erase_block(chip, phy_blk);
2574
2575 ms_set_unused_block(chip, phy_blk);
2576 } else {
2577 if (!(chip->card_wp & MS_CARD))
2578 ms_erase_block(chip, tmp_blk);
2579
2580 ms_set_unused_block(chip, tmp_blk);
2581 segment->l2p_table[log_off] = phy_blk;
2582 }
2583 }
2584
2585 return STATUS_SUCCESS;
2586 }
2587
2588 static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no)
2589 {
2590 struct ms_info *ms_card = &chip->ms_card;
2591 struct zone_entry *segment;
2592 bool defect_flag;
2593 int retval, table_size, disable_cnt, i;
2594 u16 start, end, phy_blk, log_blk, tmp_blk, idx;
2595 u8 extra[MS_EXTRA_SIZE], us1, us2;
2596
2597 dev_dbg(rtsx_dev(chip), "%s: %d\n", __func__, seg_no);
2598
2599 if (!ms_card->segment) {
2600 retval = ms_init_l2p_tbl(chip);
2601 if (retval != STATUS_SUCCESS) {
2602 rtsx_trace(chip);
2603 return retval;
2604 }
2605 }
2606
2607 if (ms_card->segment[seg_no].build_flag) {
2608 dev_dbg(rtsx_dev(chip), "l2p table of segment %d has been built\n",
2609 seg_no);
2610 return STATUS_SUCCESS;
2611 }
2612
2613 if (seg_no == 0)
2614 table_size = 494;
2615 else
2616 table_size = 496;
2617
2618 segment = &ms_card->segment[seg_no];
2619
2620 if (!segment->l2p_table) {
2621 segment->l2p_table = vmalloc(table_size * 2);
2622 if (!segment->l2p_table) {
2623 rtsx_trace(chip);
2624 goto BUILD_FAIL;
2625 }
2626 }
2627 memset((u8 *)(segment->l2p_table), 0xff, table_size * 2);
2628
2629 if (!segment->free_table) {
2630 segment->free_table = vmalloc(MS_FREE_TABLE_CNT * 2);
2631 if (!segment->free_table) {
2632 rtsx_trace(chip);
2633 goto BUILD_FAIL;
2634 }
2635 }
2636 memset((u8 *)(segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2);
2637
2638 start = (u16)seg_no << 9;
2639 end = (u16)(seg_no + 1) << 9;
2640
2641 disable_cnt = segment->disable_count;
2642
2643 segment->get_index = 0;
2644 segment->set_index = 0;
2645 segment->unused_blk_cnt = 0;
2646
2647 for (phy_blk = start; phy_blk < end; phy_blk++) {
2648 if (disable_cnt) {
2649 defect_flag = false;
2650 for (i = 0; i < segment->disable_count; i++) {
2651 if (phy_blk == segment->defect_list[i]) {
2652 defect_flag = true;
2653 break;
2654 }
2655 }
2656 if (defect_flag) {
2657 disable_cnt--;
2658 continue;
2659 }
2660 }
2661
2662 retval = ms_read_extra_data(chip, phy_blk, 0,
2663 extra, MS_EXTRA_SIZE);
2664 if (retval != STATUS_SUCCESS) {
2665 dev_dbg(rtsx_dev(chip), "read extra data fail\n");
2666 ms_set_bad_block(chip, phy_blk);
2667 continue;
2668 }
2669
2670 if (seg_no == ms_card->segment_cnt - 1) {
2671 if (!(extra[1] & NOT_TRANSLATION_TABLE)) {
2672 if (!(chip->card_wp & MS_CARD)) {
2673 retval = ms_erase_block(chip, phy_blk);
2674 if (retval != STATUS_SUCCESS)
2675 continue;
2676 extra[2] = 0xff;
2677 extra[3] = 0xff;
2678 }
2679 }
2680 }
2681
2682 if (!(extra[0] & BLOCK_OK))
2683 continue;
2684 if (!(extra[1] & NOT_BOOT_BLOCK))
2685 continue;
2686 if ((extra[0] & PAGE_OK) != PAGE_OK)
2687 continue;
2688
2689 log_blk = ((u16)extra[2] << 8) | extra[3];
2690
2691 if (log_blk == 0xFFFF) {
2692 if (!(chip->card_wp & MS_CARD)) {
2693 retval = ms_erase_block(chip, phy_blk);
2694 if (retval != STATUS_SUCCESS)
2695 continue;
2696 }
2697 ms_set_unused_block(chip, phy_blk);
2698 continue;
2699 }
2700
2701 if ((log_blk < ms_start_idx[seg_no]) ||
2702 (log_blk >= ms_start_idx[seg_no + 1])) {
2703 if (!(chip->card_wp & MS_CARD)) {
2704 retval = ms_erase_block(chip, phy_blk);
2705 if (retval != STATUS_SUCCESS)
2706 continue;
2707 }
2708 ms_set_unused_block(chip, phy_blk);
2709 continue;
2710 }
2711
2712 idx = log_blk - ms_start_idx[seg_no];
2713
2714 if (segment->l2p_table[idx] == 0xFFFF) {
2715 segment->l2p_table[idx] = phy_blk;
2716 continue;
2717 }
2718
2719 us1 = extra[0] & 0x10;
2720 tmp_blk = segment->l2p_table[idx];
2721 retval = ms_read_extra_data(chip, tmp_blk, 0,
2722 extra, MS_EXTRA_SIZE);
2723 if (retval != STATUS_SUCCESS)
2724 continue;
2725 us2 = extra[0] & 0x10;
2726
2727 (void)ms_arbitrate_l2p(chip, phy_blk,
2728 log_blk - ms_start_idx[seg_no], us1, us2);
2729 continue;
2730 }
2731
2732 segment->build_flag = 1;
2733
2734 dev_dbg(rtsx_dev(chip), "unused block count: %d\n",
2735 segment->unused_blk_cnt);
2736
2737 /* Logical Address Confirmation Process */
2738 if (seg_no == ms_card->segment_cnt - 1) {
2739 if (segment->unused_blk_cnt < 2)
2740 chip->card_wp |= MS_CARD;
2741 } else {
2742 if (segment->unused_blk_cnt < 1)
2743 chip->card_wp |= MS_CARD;
2744 }
2745
2746 if (chip->card_wp & MS_CARD)
2747 return STATUS_SUCCESS;
2748
2749 for (log_blk = ms_start_idx[seg_no];
2750 log_blk < ms_start_idx[seg_no + 1]; log_blk++) {
2751 idx = log_blk - ms_start_idx[seg_no];
2752 if (segment->l2p_table[idx] == 0xFFFF) {
2753 phy_blk = ms_get_unused_block(chip, seg_no);
2754 if (phy_blk == 0xFFFF) {
2755 chip->card_wp |= MS_CARD;
2756 return STATUS_SUCCESS;
2757 }
2758 retval = ms_init_page(chip, phy_blk, log_blk, 0, 1);
2759 if (retval != STATUS_SUCCESS) {
2760 rtsx_trace(chip);
2761 goto BUILD_FAIL;
2762 }
2763
2764 segment->l2p_table[idx] = phy_blk;
2765 if (seg_no == ms_card->segment_cnt - 1) {
2766 if (segment->unused_blk_cnt < 2) {
2767 chip->card_wp |= MS_CARD;
2768 return STATUS_SUCCESS;
2769 }
2770 } else {
2771 if (segment->unused_blk_cnt < 1) {
2772 chip->card_wp |= MS_CARD;
2773 return STATUS_SUCCESS;
2774 }
2775 }
2776 }
2777 }
2778
2779 /* Make boot block be the first normal block */
2780 if (seg_no == 0) {
2781 for (log_blk = 0; log_blk < 494; log_blk++) {
2782 tmp_blk = segment->l2p_table[log_blk];
2783 if (tmp_blk < ms_card->boot_block) {
2784 dev_dbg(rtsx_dev(chip), "Boot block is not the first normal block.\n");
2785
2786 if (chip->card_wp & MS_CARD)
2787 break;
2788
2789 phy_blk = ms_get_unused_block(chip, 0);
2790 retval = ms_copy_page(chip, tmp_blk, phy_blk,
2791 log_blk, 0,
2792 ms_card->page_off + 1);
2793 if (retval != STATUS_SUCCESS) {
2794 rtsx_trace(chip);
2795 return STATUS_FAIL;
2796 }
2797
2798 segment->l2p_table[log_blk] = phy_blk;
2799
2800 retval = ms_set_bad_block(chip, tmp_blk);
2801 if (retval != STATUS_SUCCESS) {
2802 rtsx_trace(chip);
2803 return STATUS_FAIL;
2804 }
2805 }
2806 }
2807 }
2808
2809 return STATUS_SUCCESS;
2810
2811 BUILD_FAIL:
2812 segment->build_flag = 0;
2813 vfree(segment->l2p_table);
2814 segment->l2p_table = NULL;
2815 vfree(segment->free_table);
2816 segment->free_table = NULL;
2817
2818 return STATUS_FAIL;
2819 }
2820
2821 int reset_ms_card(struct rtsx_chip *chip)
2822 {
2823 struct ms_info *ms_card = &chip->ms_card;
2824 int retval;
2825
2826 memset(ms_card, 0, sizeof(struct ms_info));
2827
2828 retval = enable_card_clock(chip, MS_CARD);
2829 if (retval != STATUS_SUCCESS) {
2830 rtsx_trace(chip);
2831 return STATUS_FAIL;
2832 }
2833
2834 retval = select_card(chip, MS_CARD);
2835 if (retval != STATUS_SUCCESS) {
2836 rtsx_trace(chip);
2837 return STATUS_FAIL;
2838 }
2839
2840 ms_card->ms_type = 0;
2841
2842 retval = reset_ms_pro(chip);
2843 if (retval != STATUS_SUCCESS) {
2844 if (ms_card->check_ms_flow) {
2845 retval = reset_ms(chip);
2846 if (retval != STATUS_SUCCESS) {
2847 rtsx_trace(chip);
2848 return STATUS_FAIL;
2849 }
2850 } else {
2851 rtsx_trace(chip);
2852 return STATUS_FAIL;
2853 }
2854 }
2855
2856 retval = ms_set_init_para(chip);
2857 if (retval != STATUS_SUCCESS) {
2858 rtsx_trace(chip);
2859 return STATUS_FAIL;
2860 }
2861
2862 if (!CHK_MSPRO(ms_card)) {
2863 /* Build table for the last segment,
2864 * to check if L2P table block exists, erasing it
2865 */
2866 retval = ms_build_l2p_tbl(chip, ms_card->total_block / 512 - 1);
2867 if (retval != STATUS_SUCCESS) {
2868 rtsx_trace(chip);
2869 return STATUS_FAIL;
2870 }
2871 }
2872
2873 dev_dbg(rtsx_dev(chip), "ms_card->ms_type = 0x%x\n", ms_card->ms_type);
2874
2875 return STATUS_SUCCESS;
2876 }
2877
2878 static int mspro_set_rw_cmd(struct rtsx_chip *chip,
2879 u32 start_sec, u16 sec_cnt, u8 cmd)
2880 {
2881 int retval, i;
2882 u8 data[8];
2883
2884 data[0] = cmd;
2885 data[1] = (u8)(sec_cnt >> 8);
2886 data[2] = (u8)sec_cnt;
2887 data[3] = (u8)(start_sec >> 24);
2888 data[4] = (u8)(start_sec >> 16);
2889 data[5] = (u8)(start_sec >> 8);
2890 data[6] = (u8)start_sec;
2891 data[7] = 0;
2892
2893 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2894 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7,
2895 WAIT_INT, data, 8);
2896 if (retval == STATUS_SUCCESS)
2897 break;
2898 }
2899 if (i == MS_MAX_RETRY_COUNT) {
2900 rtsx_trace(chip);
2901 return STATUS_FAIL;
2902 }
2903
2904 return STATUS_SUCCESS;
2905 }
2906
2907 void mspro_stop_seq_mode(struct rtsx_chip *chip)
2908 {
2909 struct ms_info *ms_card = &chip->ms_card;
2910 int retval;
2911
2912 if (ms_card->seq_mode) {
2913 retval = ms_switch_clock(chip);
2914 if (retval != STATUS_SUCCESS)
2915 return;
2916
2917 ms_card->seq_mode = 0;
2918 ms_card->total_sec_cnt = 0;
2919 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2920
2921 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
2922 }
2923 }
2924
2925 static inline int ms_auto_tune_clock(struct rtsx_chip *chip)
2926 {
2927 struct ms_info *ms_card = &chip->ms_card;
2928 int retval;
2929
2930 if (chip->asic_code) {
2931 if (ms_card->ms_clock > 30)
2932 ms_card->ms_clock -= 20;
2933 } else {
2934 if (ms_card->ms_clock == CLK_80)
2935 ms_card->ms_clock = CLK_60;
2936 else if (ms_card->ms_clock == CLK_60)
2937 ms_card->ms_clock = CLK_40;
2938 }
2939
2940 retval = ms_switch_clock(chip);
2941 if (retval != STATUS_SUCCESS) {
2942 rtsx_trace(chip);
2943 return STATUS_FAIL;
2944 }
2945
2946 return STATUS_SUCCESS;
2947 }
2948
2949 static int mspro_rw_multi_sector(struct scsi_cmnd *srb,
2950 struct rtsx_chip *chip, u32 start_sector,
2951 u16 sector_cnt)
2952 {
2953 struct ms_info *ms_card = &chip->ms_card;
2954 bool mode_2k = false;
2955 int retval;
2956 u16 count;
2957 u8 val, trans_mode, rw_tpc, rw_cmd;
2958
2959 ms_set_err_code(chip, MS_NO_ERROR);
2960
2961 ms_card->cleanup_counter = 0;
2962
2963 if (CHK_MSHG(ms_card)) {
2964 if ((start_sector % 4) || (sector_cnt % 4)) {
2965 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2966 rw_tpc = PRO_READ_LONG_DATA;
2967 rw_cmd = PRO_READ_DATA;
2968 } else {
2969 rw_tpc = PRO_WRITE_LONG_DATA;
2970 rw_cmd = PRO_WRITE_DATA;
2971 }
2972 } else {
2973 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2974 rw_tpc = PRO_READ_QUAD_DATA;
2975 rw_cmd = PRO_READ_2K_DATA;
2976 } else {
2977 rw_tpc = PRO_WRITE_QUAD_DATA;
2978 rw_cmd = PRO_WRITE_2K_DATA;
2979 }
2980 mode_2k = true;
2981 }
2982 } else {
2983 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2984 rw_tpc = PRO_READ_LONG_DATA;
2985 rw_cmd = PRO_READ_DATA;
2986 } else {
2987 rw_tpc = PRO_WRITE_LONG_DATA;
2988 rw_cmd = PRO_WRITE_DATA;
2989 }
2990 }
2991
2992 retval = ms_switch_clock(chip);
2993 if (retval != STATUS_SUCCESS) {
2994 rtsx_trace(chip);
2995 return STATUS_FAIL;
2996 }
2997
2998 if (srb->sc_data_direction == DMA_FROM_DEVICE)
2999 trans_mode = MS_TM_AUTO_READ;
3000 else
3001 trans_mode = MS_TM_AUTO_WRITE;
3002
3003 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
3004 if (retval) {
3005 rtsx_trace(chip);
3006 return retval;
3007 }
3008
3009 if (ms_card->seq_mode) {
3010 if ((ms_card->pre_dir != srb->sc_data_direction) ||
3011 ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) !=
3012 start_sector) ||
3013 (mode_2k && (ms_card->seq_mode & MODE_512_SEQ)) ||
3014 (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ)) ||
3015 !(val & MS_INT_BREQ) ||
3016 ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) {
3017 ms_card->seq_mode = 0;
3018 ms_card->total_sec_cnt = 0;
3019 if (val & MS_INT_BREQ) {
3020 retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT);
3021 if (retval != STATUS_SUCCESS) {
3022 rtsx_trace(chip);
3023 return STATUS_FAIL;
3024 }
3025
3026 rtsx_write_register(chip, RBCTL, RB_FLUSH,
3027 RB_FLUSH);
3028 }
3029 }
3030 }
3031
3032 if (!ms_card->seq_mode) {
3033 ms_card->total_sec_cnt = 0;
3034 if (sector_cnt >= SEQ_START_CRITERIA) {
3035 if ((ms_card->capacity - start_sector) > 0xFE00)
3036 count = 0xFE00;
3037 else
3038 count = (u16)(ms_card->capacity - start_sector);
3039
3040 if (count > sector_cnt) {
3041 if (mode_2k)
3042 ms_card->seq_mode = MODE_2K_SEQ;
3043 else
3044 ms_card->seq_mode = MODE_512_SEQ;
3045 }
3046 } else {
3047 count = sector_cnt;
3048 }
3049 retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd);
3050 if (retval != STATUS_SUCCESS) {
3051 ms_card->seq_mode = 0;
3052 rtsx_trace(chip);
3053 return STATUS_FAIL;
3054 }
3055 }
3056
3057 retval = ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt,
3058 WAIT_INT, mode_2k, scsi_sg_count(srb),
3059 scsi_sglist(srb), scsi_bufflen(srb));
3060 if (retval != STATUS_SUCCESS) {
3061 ms_card->seq_mode = 0;
3062 rtsx_read_register(chip, MS_TRANS_CFG, &val);
3063 rtsx_clear_ms_error(chip);
3064
3065 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3066 chip->rw_need_retry = 0;
3067 dev_dbg(rtsx_dev(chip), "No card exist, exit mspro_rw_multi_sector\n");
3068 rtsx_trace(chip);
3069 return STATUS_FAIL;
3070 }
3071
3072 if (val & MS_INT_BREQ)
3073 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
3074
3075 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
3076 dev_dbg(rtsx_dev(chip), "MSPro CRC error, tune clock!\n");
3077 chip->rw_need_retry = 1;
3078 ms_auto_tune_clock(chip);
3079 }
3080
3081 rtsx_trace(chip);
3082 return retval;
3083 }
3084
3085 if (ms_card->seq_mode) {
3086 ms_card->pre_sec_addr = start_sector;
3087 ms_card->pre_sec_cnt = sector_cnt;
3088 ms_card->pre_dir = srb->sc_data_direction;
3089 ms_card->total_sec_cnt += sector_cnt;
3090 }
3091
3092 return STATUS_SUCCESS;
3093 }
3094
3095 static int mspro_read_format_progress(struct rtsx_chip *chip,
3096 const int short_data_len)
3097 {
3098 struct ms_info *ms_card = &chip->ms_card;
3099 int retval, i;
3100 u32 total_progress, cur_progress;
3101 u8 cnt, tmp;
3102 u8 data[8];
3103
3104 dev_dbg(rtsx_dev(chip), "mspro_read_format_progress, short_data_len = %d\n",
3105 short_data_len);
3106
3107 retval = ms_switch_clock(chip);
3108 if (retval != STATUS_SUCCESS) {
3109 ms_card->format_status = FORMAT_FAIL;
3110 rtsx_trace(chip);
3111 return STATUS_FAIL;
3112 }
3113
3114 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
3115 if (retval != STATUS_SUCCESS) {
3116 ms_card->format_status = FORMAT_FAIL;
3117 rtsx_trace(chip);
3118 return STATUS_FAIL;
3119 }
3120
3121 if (!(tmp & MS_INT_BREQ)) {
3122 if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK |
3123 MS_INT_ERR)) == MS_INT_CED) {
3124 ms_card->format_status = FORMAT_SUCCESS;
3125 return STATUS_SUCCESS;
3126 }
3127 ms_card->format_status = FORMAT_FAIL;
3128 rtsx_trace(chip);
3129 return STATUS_FAIL;
3130 }
3131
3132 if (short_data_len >= 256)
3133 cnt = 0;
3134 else
3135 cnt = (u8)short_data_len;
3136
3137 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT,
3138 MS_NO_CHECK_INT);
3139 if (retval != STATUS_SUCCESS) {
3140 ms_card->format_status = FORMAT_FAIL;
3141 rtsx_trace(chip);
3142 return STATUS_FAIL;
3143 }
3144
3145 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT,
3146 data, 8);
3147 if (retval != STATUS_SUCCESS) {
3148 ms_card->format_status = FORMAT_FAIL;
3149 rtsx_trace(chip);
3150 return STATUS_FAIL;
3151 }
3152
3153 total_progress = (data[0] << 24) | (data[1] << 16) |
3154 (data[2] << 8) | data[3];
3155 cur_progress = (data[4] << 24) | (data[5] << 16) |
3156 (data[6] << 8) | data[7];
3157
3158 dev_dbg(rtsx_dev(chip), "total_progress = %d, cur_progress = %d\n",
3159 total_progress, cur_progress);
3160
3161 if (total_progress == 0) {
3162 ms_card->progress = 0;
3163 } else {
3164 u64 ulltmp = (u64)cur_progress * (u64)65535;
3165
3166 do_div(ulltmp, total_progress);
3167 ms_card->progress = (u16)ulltmp;
3168 }
3169 dev_dbg(rtsx_dev(chip), "progress = %d\n", ms_card->progress);
3170
3171 for (i = 0; i < 5000; i++) {
3172 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
3173 if (retval != STATUS_SUCCESS) {
3174 ms_card->format_status = FORMAT_FAIL;
3175 rtsx_trace(chip);
3176 return STATUS_FAIL;
3177 }
3178 if (tmp & (MS_INT_CED | MS_INT_CMDNK |
3179 MS_INT_BREQ | MS_INT_ERR))
3180 break;
3181
3182 wait_timeout(1);
3183 }
3184
3185 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0);
3186 if (retval != STATUS_SUCCESS) {
3187 ms_card->format_status = FORMAT_FAIL;
3188 rtsx_trace(chip);
3189 return STATUS_FAIL;
3190 }
3191
3192 if (i == 5000) {
3193 ms_card->format_status = FORMAT_FAIL;
3194 rtsx_trace(chip);
3195 return STATUS_FAIL;
3196 }
3197
3198 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) {
3199 ms_card->format_status = FORMAT_FAIL;
3200 rtsx_trace(chip);
3201 return STATUS_FAIL;
3202 }
3203
3204 if (tmp & MS_INT_CED) {
3205 ms_card->format_status = FORMAT_SUCCESS;
3206 ms_card->pro_under_formatting = 0;
3207 } else if (tmp & MS_INT_BREQ) {
3208 ms_card->format_status = FORMAT_IN_PROGRESS;
3209 } else {
3210 ms_card->format_status = FORMAT_FAIL;
3211 ms_card->pro_under_formatting = 0;
3212 rtsx_trace(chip);
3213 return STATUS_FAIL;
3214 }
3215
3216 return STATUS_SUCCESS;
3217 }
3218
3219 void mspro_polling_format_status(struct rtsx_chip *chip)
3220 {
3221 struct ms_info *ms_card = &chip->ms_card;
3222 int i;
3223
3224 if (ms_card->pro_under_formatting &&
3225 (rtsx_get_stat(chip) != RTSX_STAT_SS)) {
3226 rtsx_set_stat(chip, RTSX_STAT_RUN);
3227
3228 for (i = 0; i < 65535; i++) {
3229 mspro_read_format_progress(chip, MS_SHORT_DATA_LEN);
3230 if (ms_card->format_status != FORMAT_IN_PROGRESS)
3231 break;
3232 }
3233 }
3234 }
3235
3236 int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip,
3237 int short_data_len, bool quick_format)
3238 {
3239 struct ms_info *ms_card = &chip->ms_card;
3240 int retval, i;
3241 u8 buf[8], tmp;
3242 u16 para;
3243
3244 retval = ms_switch_clock(chip);
3245 if (retval != STATUS_SUCCESS) {
3246 rtsx_trace(chip);
3247 return STATUS_FAIL;
3248 }
3249
3250 retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01);
3251 if (retval != STATUS_SUCCESS) {
3252 rtsx_trace(chip);
3253 return STATUS_FAIL;
3254 }
3255
3256 memset(buf, 0, 2);
3257 switch (short_data_len) {
3258 case 32:
3259 buf[0] = 0;
3260 break;
3261 case 64:
3262 buf[0] = 1;
3263 break;
3264 case 128:
3265 buf[0] = 2;
3266 break;
3267 case 256:
3268 default:
3269 buf[0] = 3;
3270 break;
3271 }
3272
3273 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3274 retval = ms_write_bytes(chip, PRO_WRITE_REG, 1,
3275 NO_WAIT_INT, buf, 2);
3276 if (retval == STATUS_SUCCESS)
3277 break;
3278 }
3279 if (i == MS_MAX_RETRY_COUNT) {
3280 rtsx_trace(chip);
3281 return STATUS_FAIL;
3282 }
3283
3284 if (quick_format)
3285 para = 0x0000;
3286 else
3287 para = 0x0001;
3288
3289 retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT);
3290 if (retval != STATUS_SUCCESS) {
3291 rtsx_trace(chip);
3292 return STATUS_FAIL;
3293 }
3294
3295 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
3296 if (retval) {
3297 rtsx_trace(chip);
3298 return retval;
3299 }
3300
3301 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) {
3302 rtsx_trace(chip);
3303 return STATUS_FAIL;
3304 }
3305
3306 if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) {
3307 ms_card->pro_under_formatting = 1;
3308 ms_card->progress = 0;
3309 ms_card->format_status = FORMAT_IN_PROGRESS;
3310 return STATUS_SUCCESS;
3311 }
3312
3313 if (tmp & MS_INT_CED) {
3314 ms_card->pro_under_formatting = 0;
3315 ms_card->progress = 0;
3316 ms_card->format_status = FORMAT_SUCCESS;
3317 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE);
3318 return STATUS_SUCCESS;
3319 }
3320
3321 rtsx_trace(chip);
3322 return STATUS_FAIL;
3323 }
3324
3325 static int ms_read_multiple_pages(struct rtsx_chip *chip, u16 phy_blk,
3326 u16 log_blk, u8 start_page, u8 end_page,
3327 u8 *buf, unsigned int *index,
3328 unsigned int *offset)
3329 {
3330 struct ms_info *ms_card = &chip->ms_card;
3331 int retval, i;
3332 u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6];
3333 u8 *ptr;
3334
3335 retval = ms_read_extra_data(chip, phy_blk, start_page,
3336 extra, MS_EXTRA_SIZE);
3337 if (retval == STATUS_SUCCESS) {
3338 if ((extra[1] & 0x30) != 0x30) {
3339 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3340 rtsx_trace(chip);
3341 return STATUS_FAIL;
3342 }
3343 }
3344
3345 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3346 SystemParm, 6);
3347 if (retval != STATUS_SUCCESS) {
3348 rtsx_trace(chip);
3349 return STATUS_FAIL;
3350 }
3351
3352 if (CHK_MS4BIT(ms_card))
3353 data[0] = 0x88;
3354 else
3355 data[0] = 0x80;
3356
3357 data[1] = 0;
3358 data[2] = (u8)(phy_blk >> 8);
3359 data[3] = (u8)phy_blk;
3360 data[4] = 0;
3361 data[5] = start_page;
3362
3363 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3364 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
3365 data, 6);
3366 if (retval == STATUS_SUCCESS)
3367 break;
3368 }
3369 if (i == MS_MAX_RETRY_COUNT) {
3370 rtsx_trace(chip);
3371 return STATUS_FAIL;
3372 }
3373
3374 ms_set_err_code(chip, MS_NO_ERROR);
3375
3376 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
3377 if (retval != STATUS_SUCCESS) {
3378 rtsx_trace(chip);
3379 return STATUS_FAIL;
3380 }
3381
3382 ptr = buf;
3383
3384 for (page_addr = start_page; page_addr < end_page; page_addr++) {
3385 ms_set_err_code(chip, MS_NO_ERROR);
3386
3387 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3388 ms_set_err_code(chip, MS_NO_CARD);
3389 rtsx_trace(chip);
3390 return STATUS_FAIL;
3391 }
3392
3393 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3394 if (retval != STATUS_SUCCESS) {
3395 rtsx_trace(chip);
3396 return STATUS_FAIL;
3397 }
3398
3399 if (val & INT_REG_CMDNK) {
3400 ms_set_err_code(chip, MS_CMD_NK);
3401 rtsx_trace(chip);
3402 return STATUS_FAIL;
3403 }
3404 if (val & INT_REG_ERR) {
3405 if (val & INT_REG_BREQ) {
3406 retval = ms_read_status_reg(chip);
3407 if (retval != STATUS_SUCCESS) {
3408 if (!(chip->card_wp & MS_CARD)) {
3409 reset_ms(chip);
3410 ms_set_page_status
3411 (log_blk, setPS_NG,
3412 extra,
3413 MS_EXTRA_SIZE);
3414 ms_write_extra_data
3415 (chip, phy_blk,
3416 page_addr, extra,
3417 MS_EXTRA_SIZE);
3418 }
3419 ms_set_err_code(chip,
3420 MS_FLASH_READ_ERROR);
3421 rtsx_trace(chip);
3422 return STATUS_FAIL;
3423 }
3424 } else {
3425 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3426 rtsx_trace(chip);
3427 return STATUS_FAIL;
3428 }
3429 } else {
3430 if (!(val & INT_REG_BREQ)) {
3431 ms_set_err_code(chip, MS_BREQ_ERROR);
3432 rtsx_trace(chip);
3433 return STATUS_FAIL;
3434 }
3435 }
3436
3437 if (page_addr == (end_page - 1)) {
3438 if (!(val & INT_REG_CED)) {
3439 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT);
3440 if (retval != STATUS_SUCCESS) {
3441 rtsx_trace(chip);
3442 return STATUS_FAIL;
3443 }
3444 }
3445
3446 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT,
3447 &val, 1);
3448 if (retval != STATUS_SUCCESS) {
3449 rtsx_trace(chip);
3450 return STATUS_FAIL;
3451 }
3452
3453 if (!(val & INT_REG_CED)) {
3454 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3455 rtsx_trace(chip);
3456 return STATUS_FAIL;
3457 }
3458
3459 trans_cfg = NO_WAIT_INT;
3460 } else {
3461 trans_cfg = WAIT_INT;
3462 }
3463
3464 rtsx_init_cmd(chip);
3465
3466 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA);
3467 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG,
3468 0xFF, trans_cfg);
3469 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3470 0x01, RING_BUFFER);
3471
3472 trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512);
3473
3474 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3475 MS_TRANSFER_START | MS_TM_NORMAL_READ);
3476 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
3477 MS_TRANSFER_END, MS_TRANSFER_END);
3478
3479 rtsx_send_cmd_no_wait(chip);
3480
3481 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 512,
3482 scsi_sg_count(chip->srb),
3483 index, offset,
3484 DMA_FROM_DEVICE,
3485 chip->ms_timeout);
3486 if (retval < 0) {
3487 if (retval == -ETIMEDOUT) {
3488 ms_set_err_code(chip, MS_TO_ERROR);
3489 rtsx_clear_ms_error(chip);
3490 rtsx_trace(chip);
3491 return STATUS_TIMEDOUT;
3492 }
3493
3494 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
3495 if (retval != STATUS_SUCCESS) {
3496 ms_set_err_code(chip, MS_TO_ERROR);
3497 rtsx_clear_ms_error(chip);
3498 rtsx_trace(chip);
3499 return STATUS_TIMEDOUT;
3500 }
3501 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
3502 ms_set_err_code(chip, MS_CRC16_ERROR);
3503 rtsx_clear_ms_error(chip);
3504 rtsx_trace(chip);
3505 return STATUS_FAIL;
3506 }
3507 }
3508
3509 if (scsi_sg_count(chip->srb) == 0)
3510 ptr += 512;
3511 }
3512
3513 return STATUS_SUCCESS;
3514 }
3515
3516 static int ms_write_multiple_pages(struct rtsx_chip *chip, u16 old_blk,
3517 u16 new_blk, u16 log_blk, u8 start_page,
3518 u8 end_page, u8 *buf, unsigned int *index,
3519 unsigned int *offset)
3520 {
3521 struct ms_info *ms_card = &chip->ms_card;
3522 int retval, i;
3523 u8 page_addr, val, data[16];
3524 u8 *ptr;
3525
3526 if (!start_page) {
3527 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3528 SystemParm, 7);
3529 if (retval != STATUS_SUCCESS) {
3530 rtsx_trace(chip);
3531 return STATUS_FAIL;
3532 }
3533
3534 if (CHK_MS4BIT(ms_card))
3535 data[0] = 0x88;
3536 else
3537 data[0] = 0x80;
3538
3539 data[1] = 0;
3540 data[2] = (u8)(old_blk >> 8);
3541 data[3] = (u8)old_blk;
3542 data[4] = 0x80;
3543 data[5] = 0;
3544 data[6] = 0xEF;
3545 data[7] = 0xFF;
3546
3547 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT,
3548 data, 8);
3549 if (retval != STATUS_SUCCESS) {
3550 rtsx_trace(chip);
3551 return STATUS_FAIL;
3552 }
3553
3554 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3555 if (retval != STATUS_SUCCESS) {
3556 rtsx_trace(chip);
3557 return STATUS_FAIL;
3558 }
3559
3560 ms_set_err_code(chip, MS_NO_ERROR);
3561 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1,
3562 NO_WAIT_INT);
3563 if (retval != STATUS_SUCCESS) {
3564 rtsx_trace(chip);
3565 return STATUS_FAIL;
3566 }
3567 }
3568
3569 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3570 SystemParm, (6 + MS_EXTRA_SIZE));
3571 if (retval != STATUS_SUCCESS) {
3572 rtsx_trace(chip);
3573 return STATUS_FAIL;
3574 }
3575
3576 ms_set_err_code(chip, MS_NO_ERROR);
3577
3578 if (CHK_MS4BIT(ms_card))
3579 data[0] = 0x88;
3580 else
3581 data[0] = 0x80;
3582
3583 data[1] = 0;
3584 data[2] = (u8)(new_blk >> 8);
3585 data[3] = (u8)new_blk;
3586 if ((end_page - start_page) == 1)
3587 data[4] = 0x20;
3588 else
3589 data[4] = 0;
3590
3591 data[5] = start_page;
3592 data[6] = 0xF8;
3593 data[7] = 0xFF;
3594 data[8] = (u8)(log_blk >> 8);
3595 data[9] = (u8)log_blk;
3596
3597 for (i = 0x0A; i < 0x10; i++)
3598 data[i] = 0xFF;
3599
3600 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3601 retval = ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE,
3602 NO_WAIT_INT, data, 16);
3603 if (retval == STATUS_SUCCESS)
3604 break;
3605 }
3606 if (i == MS_MAX_RETRY_COUNT) {
3607 rtsx_trace(chip);
3608 return STATUS_FAIL;
3609 }
3610
3611 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3612 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3613 if (retval == STATUS_SUCCESS)
3614 break;
3615 }
3616 if (i == MS_MAX_RETRY_COUNT) {
3617 rtsx_trace(chip);
3618 return STATUS_FAIL;
3619 }
3620
3621 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3622 if (retval != STATUS_SUCCESS) {
3623 rtsx_trace(chip);
3624 return STATUS_FAIL;
3625 }
3626
3627 ptr = buf;
3628 for (page_addr = start_page; page_addr < end_page; page_addr++) {
3629 ms_set_err_code(chip, MS_NO_ERROR);
3630
3631 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3632 ms_set_err_code(chip, MS_NO_CARD);
3633 rtsx_trace(chip);
3634 return STATUS_FAIL;
3635 }
3636
3637 if (val & INT_REG_CMDNK) {
3638 ms_set_err_code(chip, MS_CMD_NK);
3639 rtsx_trace(chip);
3640 return STATUS_FAIL;
3641 }
3642 if (val & INT_REG_ERR) {
3643 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3644 rtsx_trace(chip);
3645 return STATUS_FAIL;
3646 }
3647 if (!(val & INT_REG_BREQ)) {
3648 ms_set_err_code(chip, MS_BREQ_ERROR);
3649 rtsx_trace(chip);
3650 return STATUS_FAIL;
3651 }
3652
3653 udelay(30);
3654
3655 rtsx_init_cmd(chip);
3656
3657 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC,
3658 0xFF, WRITE_PAGE_DATA);
3659 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG,
3660 0xFF, WAIT_INT);
3661 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3662 0x01, RING_BUFFER);
3663
3664 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
3665
3666 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3667 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
3668 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
3669 MS_TRANSFER_END, MS_TRANSFER_END);
3670
3671 rtsx_send_cmd_no_wait(chip);
3672
3673 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 512,
3674 scsi_sg_count(chip->srb),
3675 index, offset,
3676 DMA_TO_DEVICE,
3677 chip->ms_timeout);
3678 if (retval < 0) {
3679 ms_set_err_code(chip, MS_TO_ERROR);
3680 rtsx_clear_ms_error(chip);
3681
3682 if (retval == -ETIMEDOUT) {
3683 rtsx_trace(chip);
3684 return STATUS_TIMEDOUT;
3685 }
3686 rtsx_trace(chip);
3687 return STATUS_FAIL;
3688 }
3689
3690 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3691 if (retval != STATUS_SUCCESS) {
3692 rtsx_trace(chip);
3693 return STATUS_FAIL;
3694 }
3695
3696 if ((end_page - start_page) == 1) {
3697 if (!(val & INT_REG_CED)) {
3698 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3699 rtsx_trace(chip);
3700 return STATUS_FAIL;
3701 }
3702 } else {
3703 if (page_addr == (end_page - 1)) {
3704 if (!(val & INT_REG_CED)) {
3705 retval = ms_send_cmd(chip, BLOCK_END,
3706 WAIT_INT);
3707 if (retval != STATUS_SUCCESS) {
3708 rtsx_trace(chip);
3709 return STATUS_FAIL;
3710 }
3711 }
3712
3713 retval = ms_read_bytes(chip, GET_INT, 1,
3714 NO_WAIT_INT, &val, 1);
3715 if (retval != STATUS_SUCCESS) {
3716 rtsx_trace(chip);
3717 return STATUS_FAIL;
3718 }
3719 }
3720
3721 if ((page_addr == (end_page - 1)) ||
3722 (page_addr == ms_card->page_off)) {
3723 if (!(val & INT_REG_CED)) {
3724 ms_set_err_code(chip,
3725 MS_FLASH_WRITE_ERROR);
3726 rtsx_trace(chip);
3727 return STATUS_FAIL;
3728 }
3729 }
3730 }
3731
3732 if (scsi_sg_count(chip->srb) == 0)
3733 ptr += 512;
3734 }
3735
3736 return STATUS_SUCCESS;
3737 }
3738
3739 static int ms_finish_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3740 u16 log_blk, u8 page_off)
3741 {
3742 struct ms_info *ms_card = &chip->ms_card;
3743 int retval, seg_no;
3744
3745 retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
3746 page_off, ms_card->page_off + 1);
3747 if (retval != STATUS_SUCCESS) {
3748 rtsx_trace(chip);
3749 return STATUS_FAIL;
3750 }
3751
3752 seg_no = old_blk >> 9;
3753
3754 if (MS_TST_BAD_BLOCK_FLG(ms_card)) {
3755 MS_CLR_BAD_BLOCK_FLG(ms_card);
3756 ms_set_bad_block(chip, old_blk);
3757 } else {
3758 retval = ms_erase_block(chip, old_blk);
3759 if (retval == STATUS_SUCCESS)
3760 ms_set_unused_block(chip, old_blk);
3761 }
3762
3763 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk);
3764
3765 return STATUS_SUCCESS;
3766 }
3767
3768 static int ms_prepare_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3769 u16 log_blk, u8 start_page)
3770 {
3771 int retval;
3772
3773 if (start_page) {
3774 retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
3775 0, start_page);
3776 if (retval != STATUS_SUCCESS) {
3777 rtsx_trace(chip);
3778 return STATUS_FAIL;
3779 }
3780 }
3781
3782 return STATUS_SUCCESS;
3783 }
3784
3785 #ifdef MS_DELAY_WRITE
3786 int ms_delay_write(struct rtsx_chip *chip)
3787 {
3788 struct ms_info *ms_card = &chip->ms_card;
3789 struct ms_delay_write_tag *delay_write = &ms_card->delay_write;
3790 int retval;
3791
3792 if (delay_write->delay_write_flag) {
3793 retval = ms_set_init_para(chip);
3794 if (retval != STATUS_SUCCESS) {
3795 rtsx_trace(chip);
3796 return STATUS_FAIL;
3797 }
3798
3799 delay_write->delay_write_flag = 0;
3800 retval = ms_finish_write(chip,
3801 delay_write->old_phyblock,
3802 delay_write->new_phyblock,
3803 delay_write->logblock,
3804 delay_write->pageoff);
3805 if (retval != STATUS_SUCCESS) {
3806 rtsx_trace(chip);
3807 return STATUS_FAIL;
3808 }
3809 }
3810
3811 return STATUS_SUCCESS;
3812 }
3813 #endif
3814
3815 static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3816 {
3817 if (srb->sc_data_direction == DMA_FROM_DEVICE)
3818 set_sense_type(chip, SCSI_LUN(srb),
3819 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3820 else
3821 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
3822 }
3823
3824 static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip,
3825 u32 start_sector, u16 sector_cnt)
3826 {
3827 struct ms_info *ms_card = &chip->ms_card;
3828 unsigned int lun = SCSI_LUN(srb);
3829 int retval, seg_no;
3830 unsigned int index = 0, offset = 0;
3831 u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt;
3832 u8 start_page, end_page = 0, page_cnt;
3833 u8 *ptr;
3834 #ifdef MS_DELAY_WRITE
3835 struct ms_delay_write_tag *delay_write = &ms_card->delay_write;
3836 #endif
3837
3838 ms_set_err_code(chip, MS_NO_ERROR);
3839
3840 ms_card->cleanup_counter = 0;
3841
3842 ptr = (u8 *)scsi_sglist(srb);
3843
3844 retval = ms_switch_clock(chip);
3845 if (retval != STATUS_SUCCESS) {
3846 ms_rw_fail(srb, chip);
3847 rtsx_trace(chip);
3848 return STATUS_FAIL;
3849 }
3850
3851 log_blk = (u16)(start_sector >> ms_card->block_shift);
3852 start_page = (u8)(start_sector & ms_card->page_off);
3853
3854 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) {
3855 if (log_blk < ms_start_idx[seg_no + 1])
3856 break;
3857 }
3858
3859 if (ms_card->segment[seg_no].build_flag == 0) {
3860 retval = ms_build_l2p_tbl(chip, seg_no);
3861 if (retval != STATUS_SUCCESS) {
3862 chip->card_fail |= MS_CARD;
3863 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3864 rtsx_trace(chip);
3865 return STATUS_FAIL;
3866 }
3867 }
3868
3869 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3870 #ifdef MS_DELAY_WRITE
3871 if (delay_write->delay_write_flag &&
3872 (delay_write->logblock == log_blk) &&
3873 (start_page > delay_write->pageoff)) {
3874 delay_write->delay_write_flag = 0;
3875 retval = ms_copy_page(chip,
3876 delay_write->old_phyblock,
3877 delay_write->new_phyblock,
3878 log_blk,
3879 delay_write->pageoff, start_page);
3880 if (retval != STATUS_SUCCESS) {
3881 set_sense_type(chip, lun,
3882 SENSE_TYPE_MEDIA_WRITE_ERR);
3883 rtsx_trace(chip);
3884 return STATUS_FAIL;
3885 }
3886 old_blk = delay_write->old_phyblock;
3887 new_blk = delay_write->new_phyblock;
3888 } else if (delay_write->delay_write_flag &&
3889 (delay_write->logblock == log_blk) &&
3890 (start_page == delay_write->pageoff)) {
3891 delay_write->delay_write_flag = 0;
3892 old_blk = delay_write->old_phyblock;
3893 new_blk = delay_write->new_phyblock;
3894 } else {
3895 retval = ms_delay_write(chip);
3896 if (retval != STATUS_SUCCESS) {
3897 set_sense_type(chip, lun,
3898 SENSE_TYPE_MEDIA_WRITE_ERR);
3899 rtsx_trace(chip);
3900 return STATUS_FAIL;
3901 }
3902 #endif
3903 old_blk = ms_get_l2p_tbl
3904 (chip, seg_no,
3905 log_blk - ms_start_idx[seg_no]);
3906 new_blk = ms_get_unused_block(chip, seg_no);
3907 if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) {
3908 set_sense_type(chip, lun,
3909 SENSE_TYPE_MEDIA_WRITE_ERR);
3910 rtsx_trace(chip);
3911 return STATUS_FAIL;
3912 }
3913
3914 retval = ms_prepare_write(chip, old_blk, new_blk,
3915 log_blk, start_page);
3916 if (retval != STATUS_SUCCESS) {
3917 if (detect_card_cd(chip, MS_CARD) !=
3918 STATUS_SUCCESS) {
3919 set_sense_type
3920 (chip, lun,
3921 SENSE_TYPE_MEDIA_NOT_PRESENT);
3922 rtsx_trace(chip);
3923 return STATUS_FAIL;
3924 }
3925 set_sense_type(chip, lun,
3926 SENSE_TYPE_MEDIA_WRITE_ERR);
3927 rtsx_trace(chip);
3928 return STATUS_FAIL;
3929 }
3930 #ifdef MS_DELAY_WRITE
3931 }
3932 #endif
3933 } else {
3934 #ifdef MS_DELAY_WRITE
3935 retval = ms_delay_write(chip);
3936 if (retval != STATUS_SUCCESS) {
3937 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3938 set_sense_type(chip, lun,
3939 SENSE_TYPE_MEDIA_NOT_PRESENT);
3940 rtsx_trace(chip);
3941 return STATUS_FAIL;
3942 }
3943 set_sense_type(chip, lun,
3944 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3945 rtsx_trace(chip);
3946 return STATUS_FAIL;
3947 }
3948 #endif
3949 old_blk = ms_get_l2p_tbl(chip, seg_no,
3950 log_blk - ms_start_idx[seg_no]);
3951 if (old_blk == 0xFFFF) {
3952 set_sense_type(chip, lun,
3953 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3954 rtsx_trace(chip);
3955 return STATUS_FAIL;
3956 }
3957 }
3958
3959 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",
3960 seg_no, old_blk, new_blk);
3961
3962 while (total_sec_cnt) {
3963 if ((start_page + total_sec_cnt) > (ms_card->page_off + 1))
3964 end_page = ms_card->page_off + 1;
3965 else
3966 end_page = start_page + (u8)total_sec_cnt;
3967
3968 page_cnt = end_page - start_page;
3969
3970 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d, page_cnt = %d\n",
3971 start_page, end_page, page_cnt);
3972
3973 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3974 retval = ms_read_multiple_pages(chip,
3975 old_blk, log_blk,
3976 start_page, end_page,
3977 ptr, &index, &offset);
3978 } else {
3979 retval = ms_write_multiple_pages(chip, old_blk, new_blk,
3980 log_blk, start_page,
3981 end_page, ptr, &index,
3982 &offset);
3983 }
3984
3985 if (retval != STATUS_SUCCESS) {
3986 toggle_gpio(chip, 1);
3987 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3988 set_sense_type(chip, lun,
3989 SENSE_TYPE_MEDIA_NOT_PRESENT);
3990 rtsx_trace(chip);
3991 return STATUS_FAIL;
3992 }
3993 ms_rw_fail(srb, chip);
3994 rtsx_trace(chip);
3995 return STATUS_FAIL;
3996 }
3997
3998 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3999 if (end_page == (ms_card->page_off + 1)) {
4000 retval = ms_erase_block(chip, old_blk);
4001 if (retval == STATUS_SUCCESS)
4002 ms_set_unused_block(chip, old_blk);
4003
4004 ms_set_l2p_tbl(chip, seg_no,
4005 log_blk - ms_start_idx[seg_no],
4006 new_blk);
4007 }
4008 }
4009
4010 total_sec_cnt -= page_cnt;
4011 if (scsi_sg_count(srb) == 0)
4012 ptr += page_cnt * 512;
4013
4014 if (total_sec_cnt == 0)
4015 break;
4016
4017 log_blk++;
4018
4019 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1;
4020 seg_no++) {
4021 if (log_blk < ms_start_idx[seg_no + 1])
4022 break;
4023 }
4024
4025 if (ms_card->segment[seg_no].build_flag == 0) {
4026 retval = ms_build_l2p_tbl(chip, seg_no);
4027 if (retval != STATUS_SUCCESS) {
4028 chip->card_fail |= MS_CARD;
4029 set_sense_type(chip, lun,
4030 SENSE_TYPE_MEDIA_NOT_PRESENT);
4031 rtsx_trace(chip);
4032 return STATUS_FAIL;
4033 }
4034 }
4035
4036 old_blk = ms_get_l2p_tbl(chip, seg_no,
4037 log_blk - ms_start_idx[seg_no]);
4038 if (old_blk == 0xFFFF) {
4039 ms_rw_fail(srb, chip);
4040 rtsx_trace(chip);
4041 return STATUS_FAIL;
4042 }
4043
4044 if (srb->sc_data_direction == DMA_TO_DEVICE) {
4045 new_blk = ms_get_unused_block(chip, seg_no);
4046 if (new_blk == 0xFFFF) {
4047 ms_rw_fail(srb, chip);
4048 rtsx_trace(chip);
4049 return STATUS_FAIL;
4050 }
4051 }
4052
4053 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",
4054 seg_no, old_blk, new_blk);
4055
4056 start_page = 0;
4057 }
4058
4059 if (srb->sc_data_direction == DMA_TO_DEVICE) {
4060 if (end_page < (ms_card->page_off + 1)) {
4061 #ifdef MS_DELAY_WRITE
4062 delay_write->delay_write_flag = 1;
4063 delay_write->old_phyblock = old_blk;
4064 delay_write->new_phyblock = new_blk;
4065 delay_write->logblock = log_blk;
4066 delay_write->pageoff = end_page;
4067 #else
4068 retval = ms_finish_write(chip, old_blk, new_blk,
4069 log_blk, end_page);
4070 if (retval != STATUS_SUCCESS) {
4071 if (detect_card_cd(chip, MS_CARD) !=
4072 STATUS_SUCCESS) {
4073 set_sense_type
4074 (chip, lun,
4075 SENSE_TYPE_MEDIA_NOT_PRESENT);
4076 rtsx_trace(chip);
4077 return STATUS_FAIL;
4078 }
4079
4080 ms_rw_fail(srb, chip);
4081 rtsx_trace(chip);
4082 return STATUS_FAIL;
4083 }
4084 #endif
4085 }
4086 }
4087
4088 scsi_set_resid(srb, 0);
4089
4090 return STATUS_SUCCESS;
4091 }
4092
4093 int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
4094 u32 start_sector, u16 sector_cnt)
4095 {
4096 struct ms_info *ms_card = &chip->ms_card;
4097 int retval;
4098
4099 if (CHK_MSPRO(ms_card))
4100 retval = mspro_rw_multi_sector(srb, chip, start_sector,
4101 sector_cnt);
4102 else
4103 retval = ms_rw_multi_sector(srb, chip, start_sector,
4104 sector_cnt);
4105
4106 return retval;
4107 }
4108
4109 void ms_free_l2p_tbl(struct rtsx_chip *chip)
4110 {
4111 struct ms_info *ms_card = &chip->ms_card;
4112 int i = 0;
4113
4114 if (ms_card->segment) {
4115 for (i = 0; i < ms_card->segment_cnt; i++) {
4116 vfree(ms_card->segment[i].l2p_table);
4117 ms_card->segment[i].l2p_table = NULL;
4118 vfree(ms_card->segment[i].free_table);
4119 ms_card->segment[i].free_table = NULL;
4120 }
4121 vfree(ms_card->segment);
4122 ms_card->segment = NULL;
4123 }
4124 }
4125
4126 #ifdef SUPPORT_MAGIC_GATE
4127
4128 #ifdef READ_BYTES_WAIT_INT
4129 static int ms_poll_int(struct rtsx_chip *chip)
4130 {
4131 int retval;
4132 u8 val;
4133
4134 rtsx_init_cmd(chip);
4135
4136 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANS_CFG, MS_INT_CED, MS_INT_CED);
4137
4138 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
4139 if (retval != STATUS_SUCCESS) {
4140 rtsx_trace(chip);
4141 return STATUS_FAIL;
4142 }
4143
4144 val = *rtsx_get_cmd_data(chip);
4145 if (val & MS_INT_ERR) {
4146 rtsx_trace(chip);
4147 return STATUS_FAIL;
4148 }
4149
4150 return STATUS_SUCCESS;
4151 }
4152 #endif
4153
4154 #ifdef MS_SAMPLE_INT_ERR
4155 static int check_ms_err(struct rtsx_chip *chip)
4156 {
4157 int retval;
4158 u8 val;
4159
4160 retval = rtsx_read_register(chip, MS_TRANSFER, &val);
4161 if (retval != STATUS_SUCCESS)
4162 return 1;
4163 if (val & MS_TRANSFER_ERR)
4164 return 1;
4165
4166 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
4167 if (retval != STATUS_SUCCESS)
4168 return 1;
4169
4170 if (val & (MS_INT_ERR | MS_INT_CMDNK))
4171 return 1;
4172
4173 return 0;
4174 }
4175 #else
4176 static int check_ms_err(struct rtsx_chip *chip)
4177 {
4178 int retval;
4179 u8 val;
4180
4181 retval = rtsx_read_register(chip, MS_TRANSFER, &val);
4182 if (retval != STATUS_SUCCESS)
4183 return 1;
4184 if (val & MS_TRANSFER_ERR)
4185 return 1;
4186
4187 return 0;
4188 }
4189 #endif
4190
4191 static int mg_send_ex_cmd(struct rtsx_chip *chip, u8 cmd, u8 entry_num)
4192 {
4193 int retval, i;
4194 u8 data[8];
4195
4196 data[0] = cmd;
4197 data[1] = 0;
4198 data[2] = 0;
4199 data[3] = 0;
4200 data[4] = 0;
4201 data[5] = 0;
4202 data[6] = entry_num;
4203 data[7] = 0;
4204
4205 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
4206 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT,
4207 data, 8);
4208 if (retval == STATUS_SUCCESS)
4209 break;
4210 }
4211 if (i == MS_MAX_RETRY_COUNT) {
4212 rtsx_trace(chip);
4213 return STATUS_FAIL;
4214 }
4215
4216 if (check_ms_err(chip)) {
4217 rtsx_clear_ms_error(chip);
4218 rtsx_trace(chip);
4219 return STATUS_FAIL;
4220 }
4221
4222 return STATUS_SUCCESS;
4223 }
4224
4225 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type,
4226 u8 mg_entry_num)
4227 {
4228 int retval;
4229 u8 buf[6];
4230
4231 if (type == 0)
4232 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_TPCParm, 1);
4233 else
4234 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
4235
4236 if (retval != STATUS_SUCCESS) {
4237 rtsx_trace(chip);
4238 return STATUS_FAIL;
4239 }
4240
4241 buf[0] = 0;
4242 buf[1] = 0;
4243 if (type == 1) {
4244 buf[2] = 0;
4245 buf[3] = 0;
4246 buf[4] = 0;
4247 buf[5] = mg_entry_num;
4248 }
4249 retval = ms_write_bytes(chip, PRO_WRITE_REG, (type == 0) ? 1 : 6,
4250 NO_WAIT_INT, buf, 6);
4251 if (retval != STATUS_SUCCESS) {
4252 rtsx_trace(chip);
4253 return STATUS_FAIL;
4254 }
4255
4256 return STATUS_SUCCESS;
4257 }
4258
4259 int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4260 {
4261 int retval;
4262 int i;
4263 unsigned int lun = SCSI_LUN(srb);
4264 u8 buf1[32], buf2[12];
4265
4266 if (scsi_bufflen(srb) < 12) {
4267 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4268 rtsx_trace(chip);
4269 return STATUS_FAIL;
4270 }
4271
4272 ms_cleanup_work(chip);
4273
4274 retval = ms_switch_clock(chip);
4275 if (retval != STATUS_SUCCESS) {
4276 rtsx_trace(chip);
4277 return STATUS_FAIL;
4278 }
4279
4280 retval = mg_send_ex_cmd(chip, MG_SET_LID, 0);
4281 if (retval != STATUS_SUCCESS) {
4282 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4283 rtsx_trace(chip);
4284 return STATUS_FAIL;
4285 }
4286
4287 memset(buf1, 0, 32);
4288 rtsx_stor_get_xfer_buf(buf2, min_t(int, 12, scsi_bufflen(srb)), srb);
4289 for (i = 0; i < 8; i++)
4290 buf1[8 + i] = buf2[4 + i];
4291
4292 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT,
4293 buf1, 32);
4294 if (retval != STATUS_SUCCESS) {
4295 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4296 rtsx_trace(chip);
4297 return STATUS_FAIL;
4298 }
4299 if (check_ms_err(chip)) {
4300 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4301 rtsx_clear_ms_error(chip);
4302 rtsx_trace(chip);
4303 return STATUS_FAIL;
4304 }
4305
4306 return STATUS_SUCCESS;
4307 }
4308
4309 int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4310 {
4311 int retval = STATUS_FAIL;
4312 int bufflen;
4313 unsigned int lun = SCSI_LUN(srb);
4314 u8 *buf = NULL;
4315
4316 ms_cleanup_work(chip);
4317
4318 retval = ms_switch_clock(chip);
4319 if (retval != STATUS_SUCCESS) {
4320 rtsx_trace(chip);
4321 return STATUS_FAIL;
4322 }
4323
4324 buf = kmalloc(1540, GFP_KERNEL);
4325 if (!buf) {
4326 rtsx_trace(chip);
4327 return STATUS_ERROR;
4328 }
4329
4330 buf[0] = 0x04;
4331 buf[1] = 0x1A;
4332 buf[2] = 0x00;
4333 buf[3] = 0x00;
4334
4335 retval = mg_send_ex_cmd(chip, MG_GET_LEKB, 0);
4336 if (retval != STATUS_SUCCESS) {
4337 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4338 rtsx_trace(chip);
4339 goto free_buffer;
4340 }
4341
4342 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
4343 3, WAIT_INT, 0, 0, buf + 4, 1536);
4344 if (retval != STATUS_SUCCESS) {
4345 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4346 rtsx_clear_ms_error(chip);
4347 rtsx_trace(chip);
4348 goto free_buffer;
4349 }
4350 if (check_ms_err(chip)) {
4351 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4352 rtsx_clear_ms_error(chip);
4353 rtsx_trace(chip);
4354 retval = STATUS_FAIL;
4355 goto free_buffer;
4356 }
4357
4358 bufflen = min_t(int, 1052, scsi_bufflen(srb));
4359 rtsx_stor_set_xfer_buf(buf, bufflen, srb);
4360
4361 free_buffer:
4362 kfree(buf);
4363 return retval;
4364 }
4365
4366 int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4367 {
4368 struct ms_info *ms_card = &chip->ms_card;
4369 int retval;
4370 int bufflen;
4371 int i;
4372 unsigned int lun = SCSI_LUN(srb);
4373 u8 buf[32];
4374
4375 ms_cleanup_work(chip);
4376
4377 retval = ms_switch_clock(chip);
4378 if (retval != STATUS_SUCCESS) {
4379 rtsx_trace(chip);
4380 return STATUS_FAIL;
4381 }
4382
4383 retval = mg_send_ex_cmd(chip, MG_GET_ID, 0);
4384 if (retval != STATUS_SUCCESS) {
4385 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4386 rtsx_trace(chip);
4387 return STATUS_FAIL;
4388 }
4389
4390 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT,
4391 buf, 32);
4392 if (retval != STATUS_SUCCESS) {
4393 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4394 rtsx_trace(chip);
4395 return STATUS_FAIL;
4396 }
4397 if (check_ms_err(chip)) {
4398 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4399 rtsx_clear_ms_error(chip);
4400 rtsx_trace(chip);
4401 return STATUS_FAIL;
4402 }
4403
4404 memcpy(ms_card->magic_gate_id, buf, 16);
4405
4406 #ifdef READ_BYTES_WAIT_INT
4407 retval = ms_poll_int(chip);
4408 if (retval != STATUS_SUCCESS) {
4409 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4410 rtsx_trace(chip);
4411 return STATUS_FAIL;
4412 }
4413 #endif
4414
4415 retval = mg_send_ex_cmd(chip, MG_SET_RD, 0);
4416 if (retval != STATUS_SUCCESS) {
4417 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4418 rtsx_trace(chip);
4419 return STATUS_FAIL;
4420 }
4421
4422 bufflen = min_t(int, 12, scsi_bufflen(srb));
4423 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
4424
4425 for (i = 0; i < 8; i++)
4426 buf[i] = buf[4 + i];
4427
4428 for (i = 0; i < 24; i++)
4429 buf[8 + i] = 0;
4430
4431 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA,
4432 32, WAIT_INT, buf, 32);
4433 if (retval != STATUS_SUCCESS) {
4434 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4435 rtsx_trace(chip);
4436 return STATUS_FAIL;
4437 }
4438 if (check_ms_err(chip)) {
4439 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4440 rtsx_clear_ms_error(chip);
4441 rtsx_trace(chip);
4442 return STATUS_FAIL;
4443 }
4444
4445 ms_card->mg_auth = 0;
4446
4447 return STATUS_SUCCESS;
4448 }
4449
4450 int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4451 {
4452 struct ms_info *ms_card = &chip->ms_card;
4453 int retval;
4454 int bufflen;
4455 unsigned int lun = SCSI_LUN(srb);
4456 u8 buf1[32], buf2[36];
4457
4458 ms_cleanup_work(chip);
4459
4460 retval = ms_switch_clock(chip);
4461 if (retval != STATUS_SUCCESS) {
4462 rtsx_trace(chip);
4463 return STATUS_FAIL;
4464 }
4465
4466 retval = mg_send_ex_cmd(chip, MG_MAKE_RMS, 0);
4467 if (retval != STATUS_SUCCESS) {
4468 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4469 rtsx_trace(chip);
4470 return STATUS_FAIL;
4471 }
4472
4473 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT,
4474 buf1, 32);
4475 if (retval != STATUS_SUCCESS) {
4476 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4477 rtsx_trace(chip);
4478 return STATUS_FAIL;
4479 }
4480 if (check_ms_err(chip)) {
4481 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4482 rtsx_clear_ms_error(chip);
4483 rtsx_trace(chip);
4484 return STATUS_FAIL;
4485 }
4486
4487 buf2[0] = 0x00;
4488 buf2[1] = 0x22;
4489 buf2[2] = 0x00;
4490 buf2[3] = 0x00;
4491
4492 memcpy(buf2 + 4, ms_card->magic_gate_id, 16);
4493 memcpy(buf2 + 20, buf1, 16);
4494
4495 bufflen = min_t(int, 36, scsi_bufflen(srb));
4496 rtsx_stor_set_xfer_buf(buf2, bufflen, srb);
4497
4498 #ifdef READ_BYTES_WAIT_INT
4499 retval = ms_poll_int(chip);
4500 if (retval != STATUS_SUCCESS) {
4501 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4502 rtsx_trace(chip);
4503 return STATUS_FAIL;
4504 }
4505 #endif
4506
4507 return STATUS_SUCCESS;
4508 }
4509
4510 int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4511 {
4512 struct ms_info *ms_card = &chip->ms_card;
4513 int retval;
4514 int i;
4515 int bufflen;
4516 unsigned int lun = SCSI_LUN(srb);
4517 u8 buf[32];
4518
4519 ms_cleanup_work(chip);
4520
4521 retval = ms_switch_clock(chip);
4522 if (retval != STATUS_SUCCESS) {
4523 rtsx_trace(chip);
4524 return STATUS_FAIL;
4525 }
4526
4527 retval = mg_send_ex_cmd(chip, MG_MAKE_KSE, 0);
4528 if (retval != STATUS_SUCCESS) {
4529 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4530 rtsx_trace(chip);
4531 return STATUS_FAIL;
4532 }
4533
4534 bufflen = min_t(int, 12, scsi_bufflen(srb));
4535 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
4536
4537 for (i = 0; i < 8; i++)
4538 buf[i] = buf[4 + i];
4539
4540 for (i = 0; i < 24; i++)
4541 buf[8 + i] = 0;
4542
4543 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT,
4544 buf, 32);
4545 if (retval != STATUS_SUCCESS) {
4546 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4547 rtsx_trace(chip);
4548 return STATUS_FAIL;
4549 }
4550 if (check_ms_err(chip)) {
4551 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4552 rtsx_clear_ms_error(chip);
4553 rtsx_trace(chip);
4554 return STATUS_FAIL;
4555 }
4556
4557 ms_card->mg_auth = 1;
4558
4559 return STATUS_SUCCESS;
4560 }
4561
4562 int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4563 {
4564 struct ms_info *ms_card = &chip->ms_card;
4565 int retval;
4566 int bufflen;
4567 unsigned int lun = SCSI_LUN(srb);
4568 u8 *buf = NULL;
4569
4570 ms_cleanup_work(chip);
4571
4572 retval = ms_switch_clock(chip);
4573 if (retval != STATUS_SUCCESS) {
4574 rtsx_trace(chip);
4575 return STATUS_FAIL;
4576 }
4577
4578 buf = kmalloc(1028, GFP_KERNEL);
4579 if (!buf) {
4580 rtsx_trace(chip);
4581 return STATUS_ERROR;
4582 }
4583
4584 buf[0] = 0x04;
4585 buf[1] = 0x02;
4586 buf[2] = 0x00;
4587 buf[3] = 0x00;
4588
4589 retval = mg_send_ex_cmd(chip, MG_GET_IBD, ms_card->mg_entry_num);
4590 if (retval != STATUS_SUCCESS) {
4591 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4592 rtsx_trace(chip);
4593 goto free_buffer;
4594 }
4595
4596 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
4597 2, WAIT_INT, 0, 0, buf + 4, 1024);
4598 if (retval != STATUS_SUCCESS) {
4599 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4600 rtsx_clear_ms_error(chip);
4601 rtsx_trace(chip);
4602 goto free_buffer;
4603 }
4604 if (check_ms_err(chip)) {
4605 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4606 rtsx_clear_ms_error(chip);
4607 rtsx_trace(chip);
4608 retval = STATUS_FAIL;
4609 goto free_buffer;
4610 }
4611
4612 bufflen = min_t(int, 1028, scsi_bufflen(srb));
4613 rtsx_stor_set_xfer_buf(buf, bufflen, srb);
4614
4615 free_buffer:
4616 kfree(buf);
4617 return retval;
4618 }
4619
4620 int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4621 {
4622 struct ms_info *ms_card = &chip->ms_card;
4623 int retval;
4624 int bufflen;
4625 #ifdef MG_SET_ICV_SLOW
4626 int i;
4627 #endif
4628 unsigned int lun = SCSI_LUN(srb);
4629 u8 *buf = NULL;
4630
4631 ms_cleanup_work(chip);
4632
4633 retval = ms_switch_clock(chip);
4634 if (retval != STATUS_SUCCESS) {
4635 rtsx_trace(chip);
4636 return STATUS_FAIL;
4637 }
4638
4639 buf = kmalloc(1028, GFP_KERNEL);
4640 if (!buf) {
4641 rtsx_trace(chip);
4642 return STATUS_ERROR;
4643 }
4644
4645 bufflen = min_t(int, 1028, scsi_bufflen(srb));
4646 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
4647
4648 retval = mg_send_ex_cmd(chip, MG_SET_IBD, ms_card->mg_entry_num);
4649 if (retval != STATUS_SUCCESS) {
4650 if (ms_card->mg_auth == 0) {
4651 if ((buf[5] & 0xC0) != 0)
4652 set_sense_type
4653 (chip, lun,
4654 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4655 else
4656 set_sense_type(chip, lun,
4657 SENSE_TYPE_MG_WRITE_ERR);
4658 } else {
4659 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4660 }
4661 rtsx_trace(chip);
4662 goto SetICVFinish;
4663 }
4664
4665 #ifdef MG_SET_ICV_SLOW
4666 for (i = 0; i < 2; i++) {
4667 udelay(50);
4668
4669 rtsx_init_cmd(chip);
4670
4671 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC,
4672 0xFF, PRO_WRITE_LONG_DATA);
4673 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT);
4674 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
4675 0x01, RING_BUFFER);
4676
4677 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
4678
4679 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
4680 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
4681 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
4682 MS_TRANSFER_END, MS_TRANSFER_END);
4683
4684 rtsx_send_cmd_no_wait(chip);
4685
4686 retval = rtsx_transfer_data(chip, MS_CARD, buf + 4 + i * 512,
4687 512, 0, DMA_TO_DEVICE, 3000);
4688 if ((retval < 0) || check_ms_err(chip)) {
4689 rtsx_clear_ms_error(chip);
4690 if (ms_card->mg_auth == 0) {
4691 if ((buf[5] & 0xC0) != 0)
4692 set_sense_type
4693 (chip, lun,
4694 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4695 else
4696 set_sense_type(chip, lun,
4697 SENSE_TYPE_MG_WRITE_ERR);
4698 } else {
4699 set_sense_type(chip, lun,
4700 SENSE_TYPE_MG_WRITE_ERR);
4701 }
4702 retval = STATUS_FAIL;
4703 rtsx_trace(chip);
4704 goto SetICVFinish;
4705 }
4706 }
4707 #else
4708 retval = ms_transfer_data(chip, MS_TM_AUTO_WRITE, PRO_WRITE_LONG_DATA,
4709 2, WAIT_INT, 0, 0, buf + 4, 1024);
4710 if ((retval != STATUS_SUCCESS) || check_ms_err(chip)) {
4711 rtsx_clear_ms_error(chip);
4712 if (ms_card->mg_auth == 0) {
4713 if ((buf[5] & 0xC0) != 0)
4714 set_sense_type
4715 (chip, lun,
4716 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4717 else
4718 set_sense_type(chip, lun,
4719 SENSE_TYPE_MG_WRITE_ERR);
4720 } else {
4721 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4722 }
4723 rtsx_trace(chip);
4724 goto SetICVFinish;
4725 }
4726 #endif
4727
4728 SetICVFinish:
4729 kfree(buf);
4730 return retval;
4731 }
4732
4733 #endif /* SUPPORT_MAGIC_GATE */
4734
4735 void ms_cleanup_work(struct rtsx_chip *chip)
4736 {
4737 struct ms_info *ms_card = &chip->ms_card;
4738
4739 if (CHK_MSPRO(ms_card)) {
4740 if (ms_card->seq_mode) {
4741 dev_dbg(rtsx_dev(chip), "MS Pro: stop transmission\n");
4742 mspro_stop_seq_mode(chip);
4743 ms_card->cleanup_counter = 0;
4744 }
4745 if (CHK_MSHG(ms_card)) {
4746 rtsx_write_register(chip, MS_CFG,
4747 MS_2K_SECTOR_MODE, 0x00);
4748 }
4749 }
4750 #ifdef MS_DELAY_WRITE
4751 else if ((!CHK_MSPRO(ms_card)) &&
4752 ms_card->delay_write.delay_write_flag) {
4753 dev_dbg(rtsx_dev(chip), "MS: delay write\n");
4754 ms_delay_write(chip);
4755 ms_card->cleanup_counter = 0;
4756 }
4757 #endif
4758 }
4759
4760 int ms_power_off_card3v3(struct rtsx_chip *chip)
4761 {
4762 int retval;
4763
4764 retval = disable_card_clock(chip, MS_CARD);
4765 if (retval != STATUS_SUCCESS) {
4766 rtsx_trace(chip);
4767 return STATUS_FAIL;
4768 }
4769
4770 if (chip->asic_code) {
4771 retval = ms_pull_ctl_disable(chip);
4772 if (retval != STATUS_SUCCESS) {
4773 rtsx_trace(chip);
4774 return STATUS_FAIL;
4775 }
4776 } else {
4777 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
4778 FPGA_MS_PULL_CTL_BIT | 0x20,
4779 FPGA_MS_PULL_CTL_BIT);
4780 if (retval) {
4781 rtsx_trace(chip);
4782 return retval;
4783 }
4784 }
4785 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
4786 if (retval) {
4787 rtsx_trace(chip);
4788 return retval;
4789 }
4790 if (!chip->ft2_fast_mode) {
4791 retval = card_power_off(chip, MS_CARD);
4792 if (retval != STATUS_SUCCESS) {
4793 rtsx_trace(chip);
4794 return STATUS_FAIL;
4795 }
4796 }
4797
4798 return STATUS_SUCCESS;
4799 }
4800
4801 int release_ms_card(struct rtsx_chip *chip)
4802 {
4803 struct ms_info *ms_card = &chip->ms_card;
4804 int retval;
4805
4806 #ifdef MS_DELAY_WRITE
4807 ms_card->delay_write.delay_write_flag = 0;
4808 #endif
4809 ms_card->pro_under_formatting = 0;
4810
4811 chip->card_ready &= ~MS_CARD;
4812 chip->card_fail &= ~MS_CARD;
4813 chip->card_wp &= ~MS_CARD;
4814
4815 ms_free_l2p_tbl(chip);
4816
4817 memset(ms_card->raw_sys_info, 0, 96);
4818 #ifdef SUPPORT_PCGL_1P18
4819 memset(ms_card->raw_model_name, 0, 48);
4820 #endif
4821
4822 retval = ms_power_off_card3v3(chip);
4823 if (retval != STATUS_SUCCESS) {
4824 rtsx_trace(chip);
4825 return STATUS_FAIL;
4826 }
4827
4828 return STATUS_SUCCESS;
4829 }
Linux with added FPC-III support