drivers/clocksource/timer-prima2.c

   1 /*
   2  * System timer for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/clockchips.h>
  12 #include <linux/clocksource.h>
  13 #include <linux/bitops.h>
  14 #include <linux/irq.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/slab.h>
  18 #include <linux/of.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_address.h>
  21 #include <linux/sched_clock.h>
  22 #include <asm/mach/time.h>
  23
  24 #define PRIMA2_CLOCK_FREQ 1000000
  25
  26 #define SIRFSOC_TIMER_COUNTER_LO        0x0000
  27 #define SIRFSOC_TIMER_COUNTER_HI        0x0004
  28 #define SIRFSOC_TIMER_MATCH_0           0x0008
  29 #define SIRFSOC_TIMER_MATCH_1           0x000C
  30 #define SIRFSOC_TIMER_MATCH_2           0x0010
  31 #define SIRFSOC_TIMER_MATCH_3           0x0014
  32 #define SIRFSOC_TIMER_MATCH_4           0x0018
  33 #define SIRFSOC_TIMER_MATCH_5           0x001C
  34 #define SIRFSOC_TIMER_STATUS            0x0020
  35 #define SIRFSOC_TIMER_INT_EN            0x0024
  36 #define SIRFSOC_TIMER_WATCHDOG_EN       0x0028
  37 #define SIRFSOC_TIMER_DIV               0x002C
  38 #define SIRFSOC_TIMER_LATCH             0x0030
  39 #define SIRFSOC_TIMER_LATCHED_LO        0x0034
  40 #define SIRFSOC_TIMER_LATCHED_HI        0x0038
  41
  42 #define SIRFSOC_TIMER_WDT_INDEX         5
  43
  44 #define SIRFSOC_TIMER_LATCH_BIT  BIT(0)
  45
  46 #define SIRFSOC_TIMER_REG_CNT 11
  47
  48 static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
  49         SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
  50         SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
  51         SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
  52         SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
  53 };
  54
  55 static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
  56
  57 static void __iomem *sirfsoc_timer_base;
  58
  59 /* timer0 interrupt handler */
  60 static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
  61 {
  62         struct clock_event_device *ce = dev_id;
  63
  64         WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) &
  65                 BIT(0)));
  66
  67         /* clear timer0 interrupt */
  68         writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
  69
  70         ce->event_handler(ce);
  71
  72         return IRQ_HANDLED;
  73 }
  74
  75 /* read 64-bit timer counter */
  76 static cycle_t sirfsoc_timer_read(struct clocksource *cs)
  77 {
  78         u64 cycles;
  79
  80         /* latch the 64-bit timer counter */
  81         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
  82                 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
  83         cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
  84         cycles = (cycles << 32) |
  85                 readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
  86
  87         return cycles;
  88 }
  89
  90 static int sirfsoc_timer_set_next_event(unsigned long delta,
  91         struct clock_event_device *ce)
  92 {
  93         unsigned long now, next;
  94
  95         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
  96                 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
  97         now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
  98         next = now + delta;
  99         writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
 100         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
 101                 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
 102         now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
 103
 104         return next - now > delta ? -ETIME : 0;
 105 }
 106
 107 static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
 108         struct clock_event_device *ce)
 109 {
 110         u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
 111         switch (mode) {
 112         case CLOCK_EVT_MODE_PERIODIC:
 113                 WARN_ON(1);
 114                 break;
 115         case CLOCK_EVT_MODE_ONESHOT:
 116                 writel_relaxed(val | BIT(0),
 117                         sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
 118                 break;
 119         case CLOCK_EVT_MODE_SHUTDOWN:
 120                 writel_relaxed(val & ~BIT(0),
 121                         sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
 122                 break;
 123         case CLOCK_EVT_MODE_UNUSED:
 124         case CLOCK_EVT_MODE_RESUME:
 125                 break;
 126         }
 127 }
 128
 129 static void sirfsoc_clocksource_suspend(struct clocksource *cs)
 130 {
 131         int i;
 132
 133         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
 134                 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
 135
 136         for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
 137                 sirfsoc_timer_reg_val[i] =
 138                         readl_relaxed(sirfsoc_timer_base +
 139                                 sirfsoc_timer_reg_list[i]);
 140 }
 141
 142 static void sirfsoc_clocksource_resume(struct clocksource *cs)
 143 {
 144         int i;
 145
 146         for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
 147                 writel_relaxed(sirfsoc_timer_reg_val[i],
 148                         sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
 149
 150         writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
 151                 sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
 152         writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
 153                 sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
 154 }
 155
 156 static struct clock_event_device sirfsoc_clockevent = {
 157         .name = "sirfsoc_clockevent",
 158         .rating = 200,
 159         .features = CLOCK_EVT_FEAT_ONESHOT,
 160         .set_mode = sirfsoc_timer_set_mode,
 161         .set_next_event = sirfsoc_timer_set_next_event,
 162 };
 163
 164 static struct clocksource sirfsoc_clocksource = {
 165         .name = "sirfsoc_clocksource",
 166         .rating = 200,
 167         .mask = CLOCKSOURCE_MASK(64),
 168         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 169         .read = sirfsoc_timer_read,
 170         .suspend = sirfsoc_clocksource_suspend,
 171         .resume = sirfsoc_clocksource_resume,
 172 };
 173
 174 static struct irqaction sirfsoc_timer_irq = {
 175         .name = "sirfsoc_timer0",
 176         .flags = IRQF_TIMER,
 177         .irq = 0,
 178         .handler = sirfsoc_timer_interrupt,
 179         .dev_id = &sirfsoc_clockevent,
 180 };
 181
 182 /* Overwrite weak default sched_clock with more precise one */
 183 static u64 notrace sirfsoc_read_sched_clock(void)
 184 {
 185         return sirfsoc_timer_read(NULL);
 186 }
 187
 188 static void __init sirfsoc_clockevent_init(void)
 189 {
 190         sirfsoc_clockevent.cpumask = cpumask_of(0);
 191         clockevents_config_and_register(&sirfsoc_clockevent, PRIMA2_CLOCK_FREQ,
 192                                         2, -2);
 193 }
 194
 195 /* initialize the kernel jiffy timer source */
 196 static void __init sirfsoc_prima2_timer_init(struct device_node *np)
 197 {
 198         unsigned long rate;
 199         struct clk *clk;
 200
 201         clk = of_clk_get(np, 0);
 202         BUG_ON(IS_ERR(clk));
 203         rate = clk_get_rate(clk);
 204
 205         BUG_ON(rate < PRIMA2_CLOCK_FREQ);
 206         BUG_ON(rate % PRIMA2_CLOCK_FREQ);
 207
 208         sirfsoc_timer_base = of_iomap(np, 0);
 209         if (!sirfsoc_timer_base)
 210                 panic("unable to map timer cpu registers\n");
 211
 212         sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
 213
 214         writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1,
 215                 sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
 216         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
 217         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
 218         writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
 219
 220         BUG_ON(clocksource_register_hz(&sirfsoc_clocksource,
 221                                        PRIMA2_CLOCK_FREQ));
 222
 223         sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);
 224
 225         BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
 226
 227         sirfsoc_clockevent_init();
 228 }
 229 CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer,
 230         "sirf,prima2-tick", sirfsoc_prima2_timer_init);