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bna: fix interrupts storm caused by erroneous packets
[linux/fpc-iii.git] / drivers / bus / mvebu-mbus.c
blob6f047dcb94c22b3ea67349bf1c4b95be6b91037a
1 /*
2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
3 * 370/XP, Dove, Orion5x and MV78xx0)
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 *
9 * The Marvell EBU SoCs have a configurable physical address space:
10 * the physical address at which certain devices (PCIe, NOR, NAND,
11 * etc.) sit can be configured. The configuration takes place through
12 * two sets of registers:
13 *
14 * - One to configure the access of the CPU to the devices. Depending
15 * on the families, there are between 8 and 20 configurable windows,
16 * each can be use to create a physical memory window that maps to a
17 * specific device. Devices are identified by a tuple (target,
18 * attribute).
19 *
20 * - One to configure the access to the CPU to the SDRAM. There are
21 * either 2 (for Dove) or 4 (for other families) windows to map the
22 * SDRAM into the physical address space.
23 *
24 * This driver:
25 *
26 * - Reads out the SDRAM address decoding windows at initialization
27 * time, and fills the mvebu_mbus_dram_info structure with these
28 * informations. The exported function mv_mbus_dram_info() allow
29 * device drivers to get those informations related to the SDRAM
30 * address decoding windows. This is because devices also have their
31 * own windows (configured through registers that are part of each
32 * device register space), and therefore the drivers for Marvell
33 * devices have to configure those device -> SDRAM windows to ensure
34 * that DMA works properly.
35 *
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
38 * device accesses. This API is mvebu_mbus_add_window_by_id(),
39 * mvebu_mbus_add_window_remap_by_id() and
40 * mvebu_mbus_del_window().
41 *
42 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
43 * see the list of CPU -> SDRAM windows and their configuration
44 * (file 'sdram') and the list of CPU -> devices windows and their
45 * configuration (file 'devices').
46 */
47
48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
50 #include <linux/kernel.h>
51 #include <linux/module.h>
52 #include <linux/init.h>
53 #include <linux/mbus.h>
54 #include <linux/io.h>
55 #include <linux/ioport.h>
56 #include <linux/of.h>
57 #include <linux/of_address.h>
58 #include <linux/debugfs.h>
59 #include <linux/log2.h>
60 #include <linux/syscore_ops.h>
61
62 /*
63 * DDR target is the same on all platforms.
64 */
65 #define TARGET_DDR 0
66
67 /*
68 * CPU Address Decode Windows registers
69 */
70 #define WIN_CTRL_OFF 0x0000
71 #define WIN_CTRL_ENABLE BIT(0)
72 /* Only on HW I/O coherency capable platforms */
73 #define WIN_CTRL_SYNCBARRIER BIT(1)
74 #define WIN_CTRL_TGT_MASK 0xf0
75 #define WIN_CTRL_TGT_SHIFT 4
76 #define WIN_CTRL_ATTR_MASK 0xff00
77 #define WIN_CTRL_ATTR_SHIFT 8
78 #define WIN_CTRL_SIZE_MASK 0xffff0000
79 #define WIN_CTRL_SIZE_SHIFT 16
80 #define WIN_BASE_OFF 0x0004
81 #define WIN_BASE_LOW 0xffff0000
82 #define WIN_BASE_HIGH 0xf
83 #define WIN_REMAP_LO_OFF 0x0008
84 #define WIN_REMAP_LOW 0xffff0000
85 #define WIN_REMAP_HI_OFF 0x000c
86
87 #define UNIT_SYNC_BARRIER_OFF 0x84
88 #define UNIT_SYNC_BARRIER_ALL 0xFFFF
89
90 #define ATTR_HW_COHERENCY (0x1 << 4)
91
92 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
93 #define DDR_BASE_CS_HIGH_MASK 0xf
94 #define DDR_BASE_CS_LOW_MASK 0xff000000
95 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
96 #define DDR_SIZE_ENABLED BIT(0)
97 #define DDR_SIZE_CS_MASK 0x1c
98 #define DDR_SIZE_CS_SHIFT 2
99 #define DDR_SIZE_MASK 0xff000000
100
101 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
102
103 /* Relative to mbusbridge_base */
104 #define MBUS_BRIDGE_CTRL_OFF 0x0
105 #define MBUS_BRIDGE_BASE_OFF 0x4
106
107 /* Maximum number of windows, for all known platforms */
108 #define MBUS_WINS_MAX 20
109
110 struct mvebu_mbus_state;
111
112 struct mvebu_mbus_soc_data {
113 unsigned int num_wins;
114 bool has_mbus_bridge;
115 unsigned int (*win_cfg_offset)(const int win);
116 unsigned int (*win_remap_offset)(const int win);
117 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
118 int (*save_cpu_target)(struct mvebu_mbus_state *s,
119 u32 *store_addr);
120 int (*show_cpu_target)(struct mvebu_mbus_state *s,
121 struct seq_file *seq, void *v);
122 };
123
124 /*
125 * Used to store the state of one MBus window accross suspend/resume.
126 */
127 struct mvebu_mbus_win_data {
128 u32 ctrl;
129 u32 base;
130 u32 remap_lo;
131 u32 remap_hi;
132 };
133
134 struct mvebu_mbus_state {
135 void __iomem *mbuswins_base;
136 void __iomem *sdramwins_base;
137 void __iomem *mbusbridge_base;
138 phys_addr_t sdramwins_phys_base;
139 struct dentry *debugfs_root;
140 struct dentry *debugfs_sdram;
141 struct dentry *debugfs_devs;
142 struct resource pcie_mem_aperture;
143 struct resource pcie_io_aperture;
144 const struct mvebu_mbus_soc_data *soc;
145 int hw_io_coherency;
146
147 /* Used during suspend/resume */
148 u32 mbus_bridge_ctrl;
149 u32 mbus_bridge_base;
150 struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
151 };
152
153 static struct mvebu_mbus_state mbus_state;
154
155 static struct mbus_dram_target_info mvebu_mbus_dram_info;
156 const struct mbus_dram_target_info *mv_mbus_dram_info(void)
157 {
158 return &mvebu_mbus_dram_info;
159 }
160 EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
161
162 /* Checks whether the given window has remap capability */
163 static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus,
164 const int win)
165 {
166 return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP;
167 }
168
169 /*
170 * Functions to manipulate the address decoding windows
171 */
172
173 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
174 int win, int *enabled, u64 *base,
175 u32 *size, u8 *target, u8 *attr,
176 u64 *remap)
177 {
178 void __iomem *addr = mbus->mbuswins_base +
179 mbus->soc->win_cfg_offset(win);
180 u32 basereg = readl(addr + WIN_BASE_OFF);
181 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
182
183 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
184 *enabled = 0;
185 return;
186 }
187
188 *enabled = 1;
189 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
190 *base |= (basereg & WIN_BASE_LOW);
191 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
192
193 if (target)
194 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
195
196 if (attr)
197 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
198
199 if (remap) {
200 if (mvebu_mbus_window_is_remappable(mbus, win)) {
201 u32 remap_low, remap_hi;
202 void __iomem *addr_rmp = mbus->mbuswins_base +
203 mbus->soc->win_remap_offset(win);
204 remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF);
205 remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
206 *remap = ((u64)remap_hi << 32) | remap_low;
207 } else
208 *remap = 0;
209 }
210 }
211
212 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
213 int win)
214 {
215 void __iomem *addr;
216
217 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
218 writel(0, addr + WIN_BASE_OFF);
219 writel(0, addr + WIN_CTRL_OFF);
220
221 if (mvebu_mbus_window_is_remappable(mbus, win)) {
222 addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win);
223 writel(0, addr + WIN_REMAP_LO_OFF);
224 writel(0, addr + WIN_REMAP_HI_OFF);
225 }
226 }
227
228 /* Checks whether the given window number is available */
229
230 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
231 const int win)
232 {
233 void __iomem *addr = mbus->mbuswins_base +
234 mbus->soc->win_cfg_offset(win);
235 u32 ctrl = readl(addr + WIN_CTRL_OFF);
236
237 return !(ctrl & WIN_CTRL_ENABLE);
238 }
239
240 /*
241 * Checks whether the given (base, base+size) area doesn't overlap an
242 * existing region
243 */
244 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
245 phys_addr_t base, size_t size,
246 u8 target, u8 attr)
247 {
248 u64 end = (u64)base + size;
249 int win;
250
251 for (win = 0; win < mbus->soc->num_wins; win++) {
252 u64 wbase, wend;
253 u32 wsize;
254 u8 wtarget, wattr;
255 int enabled;
256
257 mvebu_mbus_read_window(mbus, win,
258 &enabled, &wbase, &wsize,
259 &wtarget, &wattr, NULL);
260
261 if (!enabled)
262 continue;
263
264 wend = wbase + wsize;
265
266 /*
267 * Check if the current window overlaps with the
268 * proposed physical range
269 */
270 if ((u64)base < wend && end > wbase)
271 return 0;
272 }
273
274 return 1;
275 }
276
277 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
278 phys_addr_t base, size_t size)
279 {
280 int win;
281
282 for (win = 0; win < mbus->soc->num_wins; win++) {
283 u64 wbase;
284 u32 wsize;
285 int enabled;
286
287 mvebu_mbus_read_window(mbus, win,
288 &enabled, &wbase, &wsize,
289 NULL, NULL, NULL);
290
291 if (!enabled)
292 continue;
293
294 if (base == wbase && size == wsize)
295 return win;
296 }
297
298 return -ENODEV;
299 }
300
301 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
302 int win, phys_addr_t base, size_t size,
303 phys_addr_t remap, u8 target,
304 u8 attr)
305 {
306 void __iomem *addr = mbus->mbuswins_base +
307 mbus->soc->win_cfg_offset(win);
308 u32 ctrl, remap_addr;
309
310 if (!is_power_of_2(size)) {
311 WARN(true, "Invalid MBus window size: 0x%zx\n", size);
312 return -EINVAL;
313 }
314
315 if ((base & (phys_addr_t)(size - 1)) != 0) {
316 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
317 size);
318 return -EINVAL;
319 }
320
321 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
322 (attr << WIN_CTRL_ATTR_SHIFT) |
323 (target << WIN_CTRL_TGT_SHIFT) |
324 WIN_CTRL_ENABLE;
325 if (mbus->hw_io_coherency)
326 ctrl |= WIN_CTRL_SYNCBARRIER;
327
328 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
329 writel(ctrl, addr + WIN_CTRL_OFF);
330
331 if (mvebu_mbus_window_is_remappable(mbus, win)) {
332 void __iomem *addr_rmp = mbus->mbuswins_base +
333 mbus->soc->win_remap_offset(win);
334
335 if (remap == MVEBU_MBUS_NO_REMAP)
336 remap_addr = base;
337 else
338 remap_addr = remap;
339 writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF);
340 writel(0, addr_rmp + WIN_REMAP_HI_OFF);
341 }
342
343 return 0;
344 }
345
346 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
347 phys_addr_t base, size_t size,
348 phys_addr_t remap, u8 target,
349 u8 attr)
350 {
351 int win;
352
353 if (remap == MVEBU_MBUS_NO_REMAP) {
354 for (win = 0; win < mbus->soc->num_wins; win++) {
355 if (mvebu_mbus_window_is_remappable(mbus, win))
356 continue;
357
358 if (mvebu_mbus_window_is_free(mbus, win))
359 return mvebu_mbus_setup_window(mbus, win, base,
360 size, remap,
361 target, attr);
362 }
363 }
364
365 for (win = 0; win < mbus->soc->num_wins; win++) {
366 /* Skip window if need remap but is not supported */
367 if ((remap != MVEBU_MBUS_NO_REMAP) &&
368 !mvebu_mbus_window_is_remappable(mbus, win))
369 continue;
370
371 if (mvebu_mbus_window_is_free(mbus, win))
372 return mvebu_mbus_setup_window(mbus, win, base, size,
373 remap, target, attr);
374 }
375
376 return -ENOMEM;
377 }
378
379 /*
380 * Debugfs debugging
381 */
382
383 /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
384 static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
385 struct seq_file *seq, void *v)
386 {
387 int i;
388
389 for (i = 0; i < 4; i++) {
390 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
391 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
392 u64 base;
393 u32 size;
394
395 if (!(sizereg & DDR_SIZE_ENABLED)) {
396 seq_printf(seq, "[%d] disabled\n", i);
397 continue;
398 }
399
400 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
401 base |= basereg & DDR_BASE_CS_LOW_MASK;
402 size = (sizereg | ~DDR_SIZE_MASK);
403
404 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
405 i, (unsigned long long)base,
406 (unsigned long long)base + size + 1,
407 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
408 }
409
410 return 0;
411 }
412
413 /* Special function for Dove */
414 static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
415 struct seq_file *seq, void *v)
416 {
417 int i;
418
419 for (i = 0; i < 2; i++) {
420 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
421 u64 base;
422 u32 size;
423
424 if (!(map & 1)) {
425 seq_printf(seq, "[%d] disabled\n", i);
426 continue;
427 }
428
429 base = map & 0xff800000;
430 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
431
432 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
433 i, (unsigned long long)base,
434 (unsigned long long)base + size, i);
435 }
436
437 return 0;
438 }
439
440 static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
441 {
442 struct mvebu_mbus_state *mbus = &mbus_state;
443 return mbus->soc->show_cpu_target(mbus, seq, v);
444 }
445
446 static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
447 {
448 return single_open(file, mvebu_sdram_debug_show, inode->i_private);
449 }
450
451 static const struct file_operations mvebu_sdram_debug_fops = {
452 .open = mvebu_sdram_debug_open,
453 .read = seq_read,
454 .llseek = seq_lseek,
455 .release = single_release,
456 };
457
458 static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
459 {
460 struct mvebu_mbus_state *mbus = &mbus_state;
461 int win;
462
463 for (win = 0; win < mbus->soc->num_wins; win++) {
464 u64 wbase, wremap;
465 u32 wsize;
466 u8 wtarget, wattr;
467 int enabled;
468
469 mvebu_mbus_read_window(mbus, win,
470 &enabled, &wbase, &wsize,
471 &wtarget, &wattr, &wremap);
472
473 if (!enabled) {
474 seq_printf(seq, "[%02d] disabled\n", win);
475 continue;
476 }
477
478 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
479 win, (unsigned long long)wbase,
480 (unsigned long long)(wbase + wsize), wtarget, wattr);
481
482 if (!is_power_of_2(wsize) ||
483 ((wbase & (u64)(wsize - 1)) != 0))
484 seq_puts(seq, " (Invalid base/size!!)");
485
486 if (mvebu_mbus_window_is_remappable(mbus, win)) {
487 seq_printf(seq, " (remap %016llx)\n",
488 (unsigned long long)wremap);
489 } else
490 seq_printf(seq, "\n");
491 }
492
493 return 0;
494 }
495
496 static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
497 {
498 return single_open(file, mvebu_devs_debug_show, inode->i_private);
499 }
500
501 static const struct file_operations mvebu_devs_debug_fops = {
502 .open = mvebu_devs_debug_open,
503 .read = seq_read,
504 .llseek = seq_lseek,
505 .release = single_release,
506 };
507
508 /*
509 * SoC-specific functions and definitions
510 */
511
512 static unsigned int generic_mbus_win_cfg_offset(int win)
513 {
514 return win << 4;
515 }
516
517 static unsigned int armada_370_xp_mbus_win_cfg_offset(int win)
518 {
519 /* The register layout is a bit annoying and the below code
520 * tries to cope with it.
521 * - At offset 0x0, there are the registers for the first 8
522 * windows, with 4 registers of 32 bits per window (ctrl,
523 * base, remap low, remap high)
524 * - Then at offset 0x80, there is a hole of 0x10 bytes for
525 * the internal registers base address and internal units
526 * sync barrier register.
527 * - Then at offset 0x90, there the registers for 12
528 * windows, with only 2 registers of 32 bits per window
529 * (ctrl, base).
530 */
531 if (win < 8)
532 return win << 4;
533 else
534 return 0x90 + ((win - 8) << 3);
535 }
536
537 static unsigned int mv78xx0_mbus_win_cfg_offset(int win)
538 {
539 if (win < 8)
540 return win << 4;
541 else
542 return 0x900 + ((win - 8) << 4);
543 }
544
545 static unsigned int generic_mbus_win_remap_2_offset(int win)
546 {
547 if (win < 2)
548 return generic_mbus_win_cfg_offset(win);
549 else
550 return MVEBU_MBUS_NO_REMAP;
551 }
552
553 static unsigned int generic_mbus_win_remap_4_offset(int win)
554 {
555 if (win < 4)
556 return generic_mbus_win_cfg_offset(win);
557 else
558 return MVEBU_MBUS_NO_REMAP;
559 }
560
561 static unsigned int generic_mbus_win_remap_8_offset(int win)
562 {
563 if (win < 8)
564 return generic_mbus_win_cfg_offset(win);
565 else
566 return MVEBU_MBUS_NO_REMAP;
567 }
568
569 static unsigned int armada_xp_mbus_win_remap_offset(int win)
570 {
571 if (win < 8)
572 return generic_mbus_win_cfg_offset(win);
573 else if (win == 13)
574 return 0xF0 - WIN_REMAP_LO_OFF;
575 else
576 return MVEBU_MBUS_NO_REMAP;
577 }
578
579 static void __init
580 mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
581 {
582 int i;
583 int cs;
584
585 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
586
587 for (i = 0, cs = 0; i < 4; i++) {
588 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
589 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
590
591 /*
592 * We only take care of entries for which the chip
593 * select is enabled, and that don't have high base
594 * address bits set (devices can only access the first
595 * 32 bits of the memory).
596 */
597 if ((size & DDR_SIZE_ENABLED) &&
598 !(base & DDR_BASE_CS_HIGH_MASK)) {
599 struct mbus_dram_window *w;
600
601 w = &mvebu_mbus_dram_info.cs[cs++];
602 w->cs_index = i;
603 w->mbus_attr = 0xf & ~(1 << i);
604 if (mbus->hw_io_coherency)
605 w->mbus_attr |= ATTR_HW_COHERENCY;
606 w->base = base & DDR_BASE_CS_LOW_MASK;
607 w->size = (size | ~DDR_SIZE_MASK) + 1;
608 }
609 }
610 mvebu_mbus_dram_info.num_cs = cs;
611 }
612
613 static int
614 mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
615 u32 *store_addr)
616 {
617 int i;
618
619 for (i = 0; i < 4; i++) {
620 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
621 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
622
623 writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
624 store_addr++);
625 writel(base, store_addr++);
626 writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
627 store_addr++);
628 writel(size, store_addr++);
629 }
630
631 /* We've written 16 words to the store address */
632 return 16;
633 }
634
635 static void __init
636 mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
637 {
638 int i;
639 int cs;
640
641 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
642
643 for (i = 0, cs = 0; i < 2; i++) {
644 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
645
646 /*
647 * Chip select enabled?
648 */
649 if (map & 1) {
650 struct mbus_dram_window *w;
651
652 w = &mvebu_mbus_dram_info.cs[cs++];
653 w->cs_index = i;
654 w->mbus_attr = 0; /* CS address decoding done inside */
655 /* the DDR controller, no need to */
656 /* provide attributes */
657 w->base = map & 0xff800000;
658 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
659 }
660 }
661
662 mvebu_mbus_dram_info.num_cs = cs;
663 }
664
665 static int
666 mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
667 u32 *store_addr)
668 {
669 int i;
670
671 for (i = 0; i < 2; i++) {
672 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
673
674 writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
675 store_addr++);
676 writel(map, store_addr++);
677 }
678
679 /* We've written 4 words to the store address */
680 return 4;
681 }
682
683 int mvebu_mbus_save_cpu_target(u32 *store_addr)
684 {
685 return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
686 }
687
688 static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
689 .num_wins = 20,
690 .has_mbus_bridge = true,
691 .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
692 .win_remap_offset = generic_mbus_win_remap_8_offset,
693 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
694 .show_cpu_target = mvebu_sdram_debug_show_orion,
695 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
696 };
697
698 static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
699 .num_wins = 20,
700 .has_mbus_bridge = true,
701 .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
702 .win_remap_offset = armada_xp_mbus_win_remap_offset,
703 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
704 .show_cpu_target = mvebu_sdram_debug_show_orion,
705 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
706 };
707
708 static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
709 .num_wins = 8,
710 .win_cfg_offset = generic_mbus_win_cfg_offset,
711 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
712 .win_remap_offset = generic_mbus_win_remap_4_offset,
713 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
714 .show_cpu_target = mvebu_sdram_debug_show_orion,
715 };
716
717 static const struct mvebu_mbus_soc_data dove_mbus_data = {
718 .num_wins = 8,
719 .win_cfg_offset = generic_mbus_win_cfg_offset,
720 .save_cpu_target = mvebu_mbus_dove_save_cpu_target,
721 .win_remap_offset = generic_mbus_win_remap_4_offset,
722 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
723 .show_cpu_target = mvebu_sdram_debug_show_dove,
724 };
725
726 /*
727 * Some variants of Orion5x have 4 remappable windows, some other have
728 * only two of them.
729 */
730 static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
731 .num_wins = 8,
732 .win_cfg_offset = generic_mbus_win_cfg_offset,
733 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
734 .win_remap_offset = generic_mbus_win_remap_4_offset,
735 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
736 .show_cpu_target = mvebu_sdram_debug_show_orion,
737 };
738
739 static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
740 .num_wins = 8,
741 .win_cfg_offset = generic_mbus_win_cfg_offset,
742 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
743 .win_remap_offset = generic_mbus_win_remap_2_offset,
744 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
745 .show_cpu_target = mvebu_sdram_debug_show_orion,
746 };
747
748 static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
749 .num_wins = 14,
750 .win_cfg_offset = mv78xx0_mbus_win_cfg_offset,
751 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
752 .win_remap_offset = generic_mbus_win_remap_8_offset,
753 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
754 .show_cpu_target = mvebu_sdram_debug_show_orion,
755 };
756
757 static const struct of_device_id of_mvebu_mbus_ids[] = {
758 { .compatible = "marvell,armada370-mbus",
759 .data = &armada_370_mbus_data, },
760 { .compatible = "marvell,armada375-mbus",
761 .data = &armada_xp_mbus_data, },
762 { .compatible = "marvell,armada380-mbus",
763 .data = &armada_xp_mbus_data, },
764 { .compatible = "marvell,armadaxp-mbus",
765 .data = &armada_xp_mbus_data, },
766 { .compatible = "marvell,kirkwood-mbus",
767 .data = &kirkwood_mbus_data, },
768 { .compatible = "marvell,dove-mbus",
769 .data = &dove_mbus_data, },
770 { .compatible = "marvell,orion5x-88f5281-mbus",
771 .data = &orion5x_4win_mbus_data, },
772 { .compatible = "marvell,orion5x-88f5182-mbus",
773 .data = &orion5x_2win_mbus_data, },
774 { .compatible = "marvell,orion5x-88f5181-mbus",
775 .data = &orion5x_2win_mbus_data, },
776 { .compatible = "marvell,orion5x-88f6183-mbus",
777 .data = &orion5x_4win_mbus_data, },
778 { .compatible = "marvell,mv78xx0-mbus",
779 .data = &mv78xx0_mbus_data, },
780 { },
781 };
782
783 /*
784 * Public API of the driver
785 */
786 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
787 unsigned int attribute,
788 phys_addr_t base, size_t size,
789 phys_addr_t remap)
790 {
791 struct mvebu_mbus_state *s = &mbus_state;
792
793 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
794 pr_err("cannot add window '%x:%x', conflicts with another window\n",
795 target, attribute);
796 return -EINVAL;
797 }
798
799 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
800 }
801
802 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
803 phys_addr_t base, size_t size)
804 {
805 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
806 size, MVEBU_MBUS_NO_REMAP);
807 }
808
809 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
810 {
811 int win;
812
813 win = mvebu_mbus_find_window(&mbus_state, base, size);
814 if (win < 0)
815 return win;
816
817 mvebu_mbus_disable_window(&mbus_state, win);
818 return 0;
819 }
820
821 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
822 {
823 if (!res)
824 return;
825 *res = mbus_state.pcie_mem_aperture;
826 }
827
828 void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
829 {
830 if (!res)
831 return;
832 *res = mbus_state.pcie_io_aperture;
833 }
834
835 static __init int mvebu_mbus_debugfs_init(void)
836 {
837 struct mvebu_mbus_state *s = &mbus_state;
838
839 /*
840 * If no base has been initialized, doesn't make sense to
841 * register the debugfs entries. We may be on a multiplatform
842 * kernel that isn't running a Marvell EBU SoC.
843 */
844 if (!s->mbuswins_base)
845 return 0;
846
847 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
848 if (s->debugfs_root) {
849 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
850 s->debugfs_root, NULL,
851 &mvebu_sdram_debug_fops);
852 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
853 s->debugfs_root, NULL,
854 &mvebu_devs_debug_fops);
855 }
856
857 return 0;
858 }
859 fs_initcall(mvebu_mbus_debugfs_init);
860
861 static int mvebu_mbus_suspend(void)
862 {
863 struct mvebu_mbus_state *s = &mbus_state;
864 int win;
865
866 if (!s->mbusbridge_base)
867 return -ENODEV;
868
869 for (win = 0; win < s->soc->num_wins; win++) {
870 void __iomem *addr = s->mbuswins_base +
871 s->soc->win_cfg_offset(win);
872 void __iomem *addr_rmp;
873
874 s->wins[win].base = readl(addr + WIN_BASE_OFF);
875 s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
876
877 if (!mvebu_mbus_window_is_remappable(s, win))
878 continue;
879
880 addr_rmp = s->mbuswins_base +
881 s->soc->win_remap_offset(win);
882
883 s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF);
884 s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
885 }
886
887 s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
888 MBUS_BRIDGE_CTRL_OFF);
889 s->mbus_bridge_base = readl(s->mbusbridge_base +
890 MBUS_BRIDGE_BASE_OFF);
891
892 return 0;
893 }
894
895 static void mvebu_mbus_resume(void)
896 {
897 struct mvebu_mbus_state *s = &mbus_state;
898 int win;
899
900 writel(s->mbus_bridge_ctrl,
901 s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
902 writel(s->mbus_bridge_base,
903 s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
904
905 for (win = 0; win < s->soc->num_wins; win++) {
906 void __iomem *addr = s->mbuswins_base +
907 s->soc->win_cfg_offset(win);
908 void __iomem *addr_rmp;
909
910 writel(s->wins[win].base, addr + WIN_BASE_OFF);
911 writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
912
913 if (!mvebu_mbus_window_is_remappable(s, win))
914 continue;
915
916 addr_rmp = s->mbuswins_base +
917 s->soc->win_remap_offset(win);
918
919 writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF);
920 writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF);
921 }
922 }
923
924 struct syscore_ops mvebu_mbus_syscore_ops = {
925 .suspend = mvebu_mbus_suspend,
926 .resume = mvebu_mbus_resume,
927 };
928
929 static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
930 phys_addr_t mbuswins_phys_base,
931 size_t mbuswins_size,
932 phys_addr_t sdramwins_phys_base,
933 size_t sdramwins_size,
934 phys_addr_t mbusbridge_phys_base,
935 size_t mbusbridge_size,
936 bool is_coherent)
937 {
938 int win;
939
940 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
941 if (!mbus->mbuswins_base)
942 return -ENOMEM;
943
944 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
945 if (!mbus->sdramwins_base) {
946 iounmap(mbus_state.mbuswins_base);
947 return -ENOMEM;
948 }
949
950 mbus->sdramwins_phys_base = sdramwins_phys_base;
951
952 if (mbusbridge_phys_base) {
953 mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
954 mbusbridge_size);
955 if (!mbus->mbusbridge_base) {
956 iounmap(mbus->sdramwins_base);
957 iounmap(mbus->mbuswins_base);
958 return -ENOMEM;
959 }
960 } else
961 mbus->mbusbridge_base = NULL;
962
963 for (win = 0; win < mbus->soc->num_wins; win++)
964 mvebu_mbus_disable_window(mbus, win);
965
966 mbus->soc->setup_cpu_target(mbus);
967
968 if (is_coherent)
969 writel(UNIT_SYNC_BARRIER_ALL,
970 mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF);
971
972 register_syscore_ops(&mvebu_mbus_syscore_ops);
973
974 return 0;
975 }
976
977 int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
978 size_t mbuswins_size,
979 phys_addr_t sdramwins_phys_base,
980 size_t sdramwins_size)
981 {
982 const struct of_device_id *of_id;
983
984 for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
985 if (!strcmp(of_id->compatible, soc))
986 break;
987
988 if (!of_id->compatible[0]) {
989 pr_err("could not find a matching SoC family\n");
990 return -ENODEV;
991 }
992
993 mbus_state.soc = of_id->data;
994
995 return mvebu_mbus_common_init(&mbus_state,
996 mbuswins_phys_base,
997 mbuswins_size,
998 sdramwins_phys_base,
999 sdramwins_size, 0, 0, false);
1000 }
1001
1002 #ifdef CONFIG_OF
1003 /*
1004 * The window IDs in the ranges DT property have the following format:
1005 * - bits 28 to 31: MBus custom field
1006 * - bits 24 to 27: window target ID
1007 * - bits 16 to 23: window attribute ID
1008 * - bits 0 to 15: unused
1009 */
1010 #define CUSTOM(id) (((id) & 0xF0000000) >> 24)
1011 #define TARGET(id) (((id) & 0x0F000000) >> 24)
1012 #define ATTR(id) (((id) & 0x00FF0000) >> 16)
1013
1014 static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
1015 u32 base, u32 size,
1016 u8 target, u8 attr)
1017 {
1018 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
1019 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
1020 target, attr);
1021 return -EBUSY;
1022 }
1023
1024 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
1025 target, attr)) {
1026 pr_err("cannot add window '%04x:%04x', too many windows\n",
1027 target, attr);
1028 return -ENOMEM;
1029 }
1030 return 0;
1031 }
1032
1033 static int __init
1034 mbus_parse_ranges(struct device_node *node,
1035 int *addr_cells, int *c_addr_cells, int *c_size_cells,
1036 int *cell_count, const __be32 **ranges_start,
1037 const __be32 **ranges_end)
1038 {
1039 const __be32 *prop;
1040 int ranges_len, tuple_len;
1041
1042 /* Allow a node with no 'ranges' property */
1043 *ranges_start = of_get_property(node, "ranges", &ranges_len);
1044 if (*ranges_start == NULL) {
1045 *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
1046 *ranges_start = *ranges_end = NULL;
1047 return 0;
1048 }
1049 *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
1050
1051 *addr_cells = of_n_addr_cells(node);
1052
1053 prop = of_get_property(node, "#address-cells", NULL);
1054 *c_addr_cells = be32_to_cpup(prop);
1055
1056 prop = of_get_property(node, "#size-cells", NULL);
1057 *c_size_cells = be32_to_cpup(prop);
1058
1059 *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
1060 tuple_len = (*cell_count) * sizeof(__be32);
1061
1062 if (ranges_len % tuple_len) {
1063 pr_warn("malformed ranges entry '%s'\n", node->name);
1064 return -EINVAL;
1065 }
1066 return 0;
1067 }
1068
1069 static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
1070 struct device_node *np)
1071 {
1072 int addr_cells, c_addr_cells, c_size_cells;
1073 int i, ret, cell_count;
1074 const __be32 *r, *ranges_start, *ranges_end;
1075
1076 ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
1077 &c_size_cells, &cell_count,
1078 &ranges_start, &ranges_end);
1079 if (ret < 0)
1080 return ret;
1081
1082 for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
1083 u32 windowid, base, size;
1084 u8 target, attr;
1085
1086 /*
1087 * An entry with a non-zero custom field do not
1088 * correspond to a static window, so skip it.
1089 */
1090 windowid = of_read_number(r, 1);
1091 if (CUSTOM(windowid))
1092 continue;
1093
1094 target = TARGET(windowid);
1095 attr = ATTR(windowid);
1096
1097 base = of_read_number(r + c_addr_cells, addr_cells);
1098 size = of_read_number(r + c_addr_cells + addr_cells,
1099 c_size_cells);
1100 ret = mbus_dt_setup_win(mbus, base, size, target, attr);
1101 if (ret < 0)
1102 return ret;
1103 }
1104 return 0;
1105 }
1106
1107 static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
1108 struct resource *mem,
1109 struct resource *io)
1110 {
1111 u32 reg[2];
1112 int ret;
1113
1114 /*
1115 * These are optional, so we make sure that resource_size(x) will
1116 * return 0.
1117 */
1118 memset(mem, 0, sizeof(struct resource));
1119 mem->end = -1;
1120 memset(io, 0, sizeof(struct resource));
1121 io->end = -1;
1122
1123 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
1124 if (!ret) {
1125 mem->start = reg[0];
1126 mem->end = mem->start + reg[1] - 1;
1127 mem->flags = IORESOURCE_MEM;
1128 }
1129
1130 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
1131 if (!ret) {
1132 io->start = reg[0];
1133 io->end = io->start + reg[1] - 1;
1134 io->flags = IORESOURCE_IO;
1135 }
1136 }
1137
1138 int __init mvebu_mbus_dt_init(bool is_coherent)
1139 {
1140 struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
1141 struct device_node *np, *controller;
1142 const struct of_device_id *of_id;
1143 const __be32 *prop;
1144 int ret;
1145
1146 np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
1147 if (!np) {
1148 pr_err("could not find a matching SoC family\n");
1149 return -ENODEV;
1150 }
1151
1152 mbus_state.soc = of_id->data;
1153
1154 prop = of_get_property(np, "controller", NULL);
1155 if (!prop) {
1156 pr_err("required 'controller' property missing\n");
1157 return -EINVAL;
1158 }
1159
1160 controller = of_find_node_by_phandle(be32_to_cpup(prop));
1161 if (!controller) {
1162 pr_err("could not find an 'mbus-controller' node\n");
1163 return -ENODEV;
1164 }
1165
1166 if (of_address_to_resource(controller, 0, &mbuswins_res)) {
1167 pr_err("cannot get MBUS register address\n");
1168 return -EINVAL;
1169 }
1170
1171 if (of_address_to_resource(controller, 1, &sdramwins_res)) {
1172 pr_err("cannot get SDRAM register address\n");
1173 return -EINVAL;
1174 }
1175
1176 /*
1177 * Set the resource to 0 so that it can be left unmapped by
1178 * mvebu_mbus_common_init() if the DT doesn't carry the
1179 * necessary information. This is needed to preserve backward
1180 * compatibility.
1181 */
1182 memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
1183
1184 if (mbus_state.soc->has_mbus_bridge) {
1185 if (of_address_to_resource(controller, 2, &mbusbridge_res))
1186 pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
1187 }
1188
1189 mbus_state.hw_io_coherency = is_coherent;
1190
1191 /* Get optional pcie-{mem,io}-aperture properties */
1192 mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
1193 &mbus_state.pcie_io_aperture);
1194
1195 ret = mvebu_mbus_common_init(&mbus_state,
1196 mbuswins_res.start,
1197 resource_size(&mbuswins_res),
1198 sdramwins_res.start,
1199 resource_size(&sdramwins_res),
1200 mbusbridge_res.start,
1201 resource_size(&mbusbridge_res),
1202 is_coherent);
1203 if (ret)
1204 return ret;
1205
1206 /* Setup statically declared windows in the DT */
1207 return mbus_dt_setup(&mbus_state, np);
1208 }
1209 #endif
Linux with added FPC-III support