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bna: fix interrupts storm caused by erroneous packets
[linux/fpc-iii.git] / drivers / pci / probe.c
blobc91185721345b65f3e915a6539186f138c21781e
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/of_pci.h>
10 #include <linux/pci_hotplug.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/cpumask.h>
14 #include <linux/pci-aspm.h>
15 #include <asm-generic/pci-bridge.h>
16 #include "pci.h"
17
18 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
19 #define CARDBUS_RESERVE_BUSNR 3
20
21 static struct resource busn_resource = {
22 .name = "PCI busn",
23 .start = 0,
24 .end = 255,
25 .flags = IORESOURCE_BUS,
26 };
27
28 /* Ugh. Need to stop exporting this to modules. */
29 LIST_HEAD(pci_root_buses);
30 EXPORT_SYMBOL(pci_root_buses);
31
32 static LIST_HEAD(pci_domain_busn_res_list);
33
34 struct pci_domain_busn_res {
35 struct list_head list;
36 struct resource res;
37 int domain_nr;
38 };
39
40 static struct resource *get_pci_domain_busn_res(int domain_nr)
41 {
42 struct pci_domain_busn_res *r;
43
44 list_for_each_entry(r, &pci_domain_busn_res_list, list)
45 if (r->domain_nr == domain_nr)
46 return &r->res;
47
48 r = kzalloc(sizeof(*r), GFP_KERNEL);
49 if (!r)
50 return NULL;
51
52 r->domain_nr = domain_nr;
53 r->res.start = 0;
54 r->res.end = 0xff;
55 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
56
57 list_add_tail(&r->list, &pci_domain_busn_res_list);
58
59 return &r->res;
60 }
61
62 static int find_anything(struct device *dev, void *data)
63 {
64 return 1;
65 }
66
67 /*
68 * Some device drivers need know if pci is initiated.
69 * Basically, we think pci is not initiated when there
70 * is no device to be found on the pci_bus_type.
71 */
72 int no_pci_devices(void)
73 {
74 struct device *dev;
75 int no_devices;
76
77 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
78 no_devices = (dev == NULL);
79 put_device(dev);
80 return no_devices;
81 }
82 EXPORT_SYMBOL(no_pci_devices);
83
84 /*
85 * PCI Bus Class
86 */
87 static void release_pcibus_dev(struct device *dev)
88 {
89 struct pci_bus *pci_bus = to_pci_bus(dev);
90
91 put_device(pci_bus->bridge);
92 pci_bus_remove_resources(pci_bus);
93 pci_release_bus_of_node(pci_bus);
94 kfree(pci_bus);
95 }
96
97 static struct class pcibus_class = {
98 .name = "pci_bus",
99 .dev_release = &release_pcibus_dev,
100 .dev_groups = pcibus_groups,
101 };
102
103 static int __init pcibus_class_init(void)
104 {
105 return class_register(&pcibus_class);
106 }
107 postcore_initcall(pcibus_class_init);
108
109 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
110 {
111 u64 size = mask & maxbase; /* Find the significant bits */
112 if (!size)
113 return 0;
114
115 /* Get the lowest of them to find the decode size, and
116 from that the extent. */
117 size = (size & ~(size-1)) - 1;
118
119 /* base == maxbase can be valid only if the BAR has
120 already been programmed with all 1s. */
121 if (base == maxbase && ((base | size) & mask) != mask)
122 return 0;
123
124 return size;
125 }
126
127 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
128 {
129 u32 mem_type;
130 unsigned long flags;
131
132 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
133 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
134 flags |= IORESOURCE_IO;
135 return flags;
136 }
137
138 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
139 flags |= IORESOURCE_MEM;
140 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
141 flags |= IORESOURCE_PREFETCH;
142
143 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
144 switch (mem_type) {
145 case PCI_BASE_ADDRESS_MEM_TYPE_32:
146 break;
147 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
148 /* 1M mem BAR treated as 32-bit BAR */
149 break;
150 case PCI_BASE_ADDRESS_MEM_TYPE_64:
151 flags |= IORESOURCE_MEM_64;
152 break;
153 default:
154 /* mem unknown type treated as 32-bit BAR */
155 break;
156 }
157 return flags;
158 }
159
160 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
161
162 /**
163 * pci_read_base - read a PCI BAR
164 * @dev: the PCI device
165 * @type: type of the BAR
166 * @res: resource buffer to be filled in
167 * @pos: BAR position in the config space
168 *
169 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
170 */
171 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
172 struct resource *res, unsigned int pos)
173 {
174 u32 l, sz, mask;
175 u64 l64, sz64, mask64;
176 u16 orig_cmd;
177 struct pci_bus_region region, inverted_region;
178
179 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
180
181 /* No printks while decoding is disabled! */
182 if (!dev->mmio_always_on) {
183 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
184 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
185 pci_write_config_word(dev, PCI_COMMAND,
186 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
187 }
188 }
189
190 res->name = pci_name(dev);
191
192 pci_read_config_dword(dev, pos, &l);
193 pci_write_config_dword(dev, pos, l | mask);
194 pci_read_config_dword(dev, pos, &sz);
195 pci_write_config_dword(dev, pos, l);
196
197 /*
198 * All bits set in sz means the device isn't working properly.
199 * If the BAR isn't implemented, all bits must be 0. If it's a
200 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
201 * 1 must be clear.
202 */
203 if (sz == 0xffffffff)
204 sz = 0;
205
206 /*
207 * I don't know how l can have all bits set. Copied from old code.
208 * Maybe it fixes a bug on some ancient platform.
209 */
210 if (l == 0xffffffff)
211 l = 0;
212
213 if (type == pci_bar_unknown) {
214 res->flags = decode_bar(dev, l);
215 res->flags |= IORESOURCE_SIZEALIGN;
216 if (res->flags & IORESOURCE_IO) {
217 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
218 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
219 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
220 } else {
221 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
222 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
223 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
224 }
225 } else {
226 res->flags |= (l & IORESOURCE_ROM_ENABLE);
227 l64 = l & PCI_ROM_ADDRESS_MASK;
228 sz64 = sz & PCI_ROM_ADDRESS_MASK;
229 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
230 }
231
232 if (res->flags & IORESOURCE_MEM_64) {
233 pci_read_config_dword(dev, pos + 4, &l);
234 pci_write_config_dword(dev, pos + 4, ~0);
235 pci_read_config_dword(dev, pos + 4, &sz);
236 pci_write_config_dword(dev, pos + 4, l);
237
238 l64 |= ((u64)l << 32);
239 sz64 |= ((u64)sz << 32);
240 mask64 |= ((u64)~0 << 32);
241 }
242
243 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
244 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
245
246 if (!sz64)
247 goto fail;
248
249 sz64 = pci_size(l64, sz64, mask64);
250 if (!sz64) {
251 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
252 pos);
253 goto fail;
254 }
255
256 if (res->flags & IORESOURCE_MEM_64) {
257 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
258 && sz64 > 0x100000000ULL) {
259 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
260 res->start = 0;
261 res->end = 0;
262 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
263 pos, (unsigned long long)sz64);
264 goto out;
265 }
266
267 if ((sizeof(pci_bus_addr_t) < 8) && l) {
268 /* Above 32-bit boundary; try to reallocate */
269 res->flags |= IORESOURCE_UNSET;
270 res->start = 0;
271 res->end = sz64;
272 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
273 pos, (unsigned long long)l64);
274 goto out;
275 }
276 }
277
278 region.start = l64;
279 region.end = l64 + sz64;
280
281 pcibios_bus_to_resource(dev->bus, res, &region);
282 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
283
284 /*
285 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
286 * the corresponding resource address (the physical address used by
287 * the CPU. Converting that resource address back to a bus address
288 * should yield the original BAR value:
289 *
290 * resource_to_bus(bus_to_resource(A)) == A
291 *
292 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
293 * be claimed by the device.
294 */
295 if (inverted_region.start != region.start) {
296 res->flags |= IORESOURCE_UNSET;
297 res->start = 0;
298 res->end = region.end - region.start;
299 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
300 pos, (unsigned long long)region.start);
301 }
302
303 goto out;
304
305
306 fail:
307 res->flags = 0;
308 out:
309 if (res->flags)
310 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
311
312 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
313 }
314
315 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
316 {
317 unsigned int pos, reg;
318
319 for (pos = 0; pos < howmany; pos++) {
320 struct resource *res = &dev->resource[pos];
321 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
322 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
323 }
324
325 if (rom) {
326 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
327 dev->rom_base_reg = rom;
328 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
329 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
330 IORESOURCE_SIZEALIGN;
331 __pci_read_base(dev, pci_bar_mem32, res, rom);
332 }
333 }
334
335 static void pci_read_bridge_io(struct pci_bus *child)
336 {
337 struct pci_dev *dev = child->self;
338 u8 io_base_lo, io_limit_lo;
339 unsigned long io_mask, io_granularity, base, limit;
340 struct pci_bus_region region;
341 struct resource *res;
342
343 io_mask = PCI_IO_RANGE_MASK;
344 io_granularity = 0x1000;
345 if (dev->io_window_1k) {
346 /* Support 1K I/O space granularity */
347 io_mask = PCI_IO_1K_RANGE_MASK;
348 io_granularity = 0x400;
349 }
350
351 res = child->resource[0];
352 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
353 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
354 base = (io_base_lo & io_mask) << 8;
355 limit = (io_limit_lo & io_mask) << 8;
356
357 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
358 u16 io_base_hi, io_limit_hi;
359
360 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
361 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
362 base |= ((unsigned long) io_base_hi << 16);
363 limit |= ((unsigned long) io_limit_hi << 16);
364 }
365
366 if (base <= limit) {
367 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
368 region.start = base;
369 region.end = limit + io_granularity - 1;
370 pcibios_bus_to_resource(dev->bus, res, &region);
371 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
372 }
373 }
374
375 static void pci_read_bridge_mmio(struct pci_bus *child)
376 {
377 struct pci_dev *dev = child->self;
378 u16 mem_base_lo, mem_limit_lo;
379 unsigned long base, limit;
380 struct pci_bus_region region;
381 struct resource *res;
382
383 res = child->resource[1];
384 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
385 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
386 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
387 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
388 if (base <= limit) {
389 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
390 region.start = base;
391 region.end = limit + 0xfffff;
392 pcibios_bus_to_resource(dev->bus, res, &region);
393 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
394 }
395 }
396
397 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
398 {
399 struct pci_dev *dev = child->self;
400 u16 mem_base_lo, mem_limit_lo;
401 u64 base64, limit64;
402 pci_bus_addr_t base, limit;
403 struct pci_bus_region region;
404 struct resource *res;
405
406 res = child->resource[2];
407 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
408 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
409 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
410 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
411
412 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
413 u32 mem_base_hi, mem_limit_hi;
414
415 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
416 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
417
418 /*
419 * Some bridges set the base > limit by default, and some
420 * (broken) BIOSes do not initialize them. If we find
421 * this, just assume they are not being used.
422 */
423 if (mem_base_hi <= mem_limit_hi) {
424 base64 |= (u64) mem_base_hi << 32;
425 limit64 |= (u64) mem_limit_hi << 32;
426 }
427 }
428
429 base = (pci_bus_addr_t) base64;
430 limit = (pci_bus_addr_t) limit64;
431
432 if (base != base64) {
433 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
434 (unsigned long long) base64);
435 return;
436 }
437
438 if (base <= limit) {
439 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
440 IORESOURCE_MEM | IORESOURCE_PREFETCH;
441 if (res->flags & PCI_PREF_RANGE_TYPE_64)
442 res->flags |= IORESOURCE_MEM_64;
443 region.start = base;
444 region.end = limit + 0xfffff;
445 pcibios_bus_to_resource(dev->bus, res, &region);
446 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
447 }
448 }
449
450 void pci_read_bridge_bases(struct pci_bus *child)
451 {
452 struct pci_dev *dev = child->self;
453 struct resource *res;
454 int i;
455
456 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
457 return;
458
459 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
460 &child->busn_res,
461 dev->transparent ? " (subtractive decode)" : "");
462
463 pci_bus_remove_resources(child);
464 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
465 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
466
467 pci_read_bridge_io(child);
468 pci_read_bridge_mmio(child);
469 pci_read_bridge_mmio_pref(child);
470
471 if (dev->transparent) {
472 pci_bus_for_each_resource(child->parent, res, i) {
473 if (res && res->flags) {
474 pci_bus_add_resource(child, res,
475 PCI_SUBTRACTIVE_DECODE);
476 dev_printk(KERN_DEBUG, &dev->dev,
477 " bridge window %pR (subtractive decode)\n",
478 res);
479 }
480 }
481 }
482 }
483
484 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
485 {
486 struct pci_bus *b;
487
488 b = kzalloc(sizeof(*b), GFP_KERNEL);
489 if (!b)
490 return NULL;
491
492 INIT_LIST_HEAD(&b->node);
493 INIT_LIST_HEAD(&b->children);
494 INIT_LIST_HEAD(&b->devices);
495 INIT_LIST_HEAD(&b->slots);
496 INIT_LIST_HEAD(&b->resources);
497 b->max_bus_speed = PCI_SPEED_UNKNOWN;
498 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
499 #ifdef CONFIG_PCI_DOMAINS_GENERIC
500 if (parent)
501 b->domain_nr = parent->domain_nr;
502 #endif
503 return b;
504 }
505
506 static void pci_release_host_bridge_dev(struct device *dev)
507 {
508 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
509
510 if (bridge->release_fn)
511 bridge->release_fn(bridge);
512
513 pci_free_resource_list(&bridge->windows);
514
515 kfree(bridge);
516 }
517
518 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
519 {
520 struct pci_host_bridge *bridge;
521
522 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
523 if (!bridge)
524 return NULL;
525
526 INIT_LIST_HEAD(&bridge->windows);
527 bridge->bus = b;
528 return bridge;
529 }
530
531 static const unsigned char pcix_bus_speed[] = {
532 PCI_SPEED_UNKNOWN, /* 0 */
533 PCI_SPEED_66MHz_PCIX, /* 1 */
534 PCI_SPEED_100MHz_PCIX, /* 2 */
535 PCI_SPEED_133MHz_PCIX, /* 3 */
536 PCI_SPEED_UNKNOWN, /* 4 */
537 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
538 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
539 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
540 PCI_SPEED_UNKNOWN, /* 8 */
541 PCI_SPEED_66MHz_PCIX_266, /* 9 */
542 PCI_SPEED_100MHz_PCIX_266, /* A */
543 PCI_SPEED_133MHz_PCIX_266, /* B */
544 PCI_SPEED_UNKNOWN, /* C */
545 PCI_SPEED_66MHz_PCIX_533, /* D */
546 PCI_SPEED_100MHz_PCIX_533, /* E */
547 PCI_SPEED_133MHz_PCIX_533 /* F */
548 };
549
550 const unsigned char pcie_link_speed[] = {
551 PCI_SPEED_UNKNOWN, /* 0 */
552 PCIE_SPEED_2_5GT, /* 1 */
553 PCIE_SPEED_5_0GT, /* 2 */
554 PCIE_SPEED_8_0GT, /* 3 */
555 PCI_SPEED_UNKNOWN, /* 4 */
556 PCI_SPEED_UNKNOWN, /* 5 */
557 PCI_SPEED_UNKNOWN, /* 6 */
558 PCI_SPEED_UNKNOWN, /* 7 */
559 PCI_SPEED_UNKNOWN, /* 8 */
560 PCI_SPEED_UNKNOWN, /* 9 */
561 PCI_SPEED_UNKNOWN, /* A */
562 PCI_SPEED_UNKNOWN, /* B */
563 PCI_SPEED_UNKNOWN, /* C */
564 PCI_SPEED_UNKNOWN, /* D */
565 PCI_SPEED_UNKNOWN, /* E */
566 PCI_SPEED_UNKNOWN /* F */
567 };
568
569 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
570 {
571 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
572 }
573 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
574
575 static unsigned char agp_speeds[] = {
576 AGP_UNKNOWN,
577 AGP_1X,
578 AGP_2X,
579 AGP_4X,
580 AGP_8X
581 };
582
583 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
584 {
585 int index = 0;
586
587 if (agpstat & 4)
588 index = 3;
589 else if (agpstat & 2)
590 index = 2;
591 else if (agpstat & 1)
592 index = 1;
593 else
594 goto out;
595
596 if (agp3) {
597 index += 2;
598 if (index == 5)
599 index = 0;
600 }
601
602 out:
603 return agp_speeds[index];
604 }
605
606 static void pci_set_bus_speed(struct pci_bus *bus)
607 {
608 struct pci_dev *bridge = bus->self;
609 int pos;
610
611 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
612 if (!pos)
613 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
614 if (pos) {
615 u32 agpstat, agpcmd;
616
617 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
618 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
619
620 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
621 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
622 }
623
624 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
625 if (pos) {
626 u16 status;
627 enum pci_bus_speed max;
628
629 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
630 &status);
631
632 if (status & PCI_X_SSTATUS_533MHZ) {
633 max = PCI_SPEED_133MHz_PCIX_533;
634 } else if (status & PCI_X_SSTATUS_266MHZ) {
635 max = PCI_SPEED_133MHz_PCIX_266;
636 } else if (status & PCI_X_SSTATUS_133MHZ) {
637 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
638 max = PCI_SPEED_133MHz_PCIX_ECC;
639 else
640 max = PCI_SPEED_133MHz_PCIX;
641 } else {
642 max = PCI_SPEED_66MHz_PCIX;
643 }
644
645 bus->max_bus_speed = max;
646 bus->cur_bus_speed = pcix_bus_speed[
647 (status & PCI_X_SSTATUS_FREQ) >> 6];
648
649 return;
650 }
651
652 if (pci_is_pcie(bridge)) {
653 u32 linkcap;
654 u16 linksta;
655
656 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
657 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
658
659 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
660 pcie_update_link_speed(bus, linksta);
661 }
662 }
663
664 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
665 struct pci_dev *bridge, int busnr)
666 {
667 struct pci_bus *child;
668 int i;
669 int ret;
670
671 /*
672 * Allocate a new bus, and inherit stuff from the parent..
673 */
674 child = pci_alloc_bus(parent);
675 if (!child)
676 return NULL;
677
678 child->parent = parent;
679 child->ops = parent->ops;
680 child->msi = parent->msi;
681 child->sysdata = parent->sysdata;
682 child->bus_flags = parent->bus_flags;
683
684 /* initialize some portions of the bus device, but don't register it
685 * now as the parent is not properly set up yet.
686 */
687 child->dev.class = &pcibus_class;
688 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
689
690 /*
691 * Set up the primary, secondary and subordinate
692 * bus numbers.
693 */
694 child->number = child->busn_res.start = busnr;
695 child->primary = parent->busn_res.start;
696 child->busn_res.end = 0xff;
697
698 if (!bridge) {
699 child->dev.parent = parent->bridge;
700 goto add_dev;
701 }
702
703 child->self = bridge;
704 child->bridge = get_device(&bridge->dev);
705 child->dev.parent = child->bridge;
706 pci_set_bus_of_node(child);
707 pci_set_bus_speed(child);
708
709 /* Set up default resource pointers and names.. */
710 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
711 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
712 child->resource[i]->name = child->name;
713 }
714 bridge->subordinate = child;
715
716 add_dev:
717 ret = device_register(&child->dev);
718 WARN_ON(ret < 0);
719
720 pcibios_add_bus(child);
721
722 /* Create legacy_io and legacy_mem files for this bus */
723 pci_create_legacy_files(child);
724
725 return child;
726 }
727
728 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
729 int busnr)
730 {
731 struct pci_bus *child;
732
733 child = pci_alloc_child_bus(parent, dev, busnr);
734 if (child) {
735 down_write(&pci_bus_sem);
736 list_add_tail(&child->node, &parent->children);
737 up_write(&pci_bus_sem);
738 }
739 return child;
740 }
741 EXPORT_SYMBOL(pci_add_new_bus);
742
743 static void pci_enable_crs(struct pci_dev *pdev)
744 {
745 u16 root_cap = 0;
746
747 /* Enable CRS Software Visibility if supported */
748 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
749 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
750 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
751 PCI_EXP_RTCTL_CRSSVE);
752 }
753
754 /*
755 * If it's a bridge, configure it and scan the bus behind it.
756 * For CardBus bridges, we don't scan behind as the devices will
757 * be handled by the bridge driver itself.
758 *
759 * We need to process bridges in two passes -- first we scan those
760 * already configured by the BIOS and after we are done with all of
761 * them, we proceed to assigning numbers to the remaining buses in
762 * order to avoid overlaps between old and new bus numbers.
763 */
764 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
765 {
766 struct pci_bus *child;
767 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
768 u32 buses, i, j = 0;
769 u16 bctl;
770 u8 primary, secondary, subordinate;
771 int broken = 0;
772
773 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
774 primary = buses & 0xFF;
775 secondary = (buses >> 8) & 0xFF;
776 subordinate = (buses >> 16) & 0xFF;
777
778 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
779 secondary, subordinate, pass);
780
781 if (!primary && (primary != bus->number) && secondary && subordinate) {
782 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
783 primary = bus->number;
784 }
785
786 /* Check if setup is sensible at all */
787 if (!pass &&
788 (primary != bus->number || secondary <= bus->number ||
789 secondary > subordinate)) {
790 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
791 secondary, subordinate);
792 broken = 1;
793 }
794
795 /* Disable MasterAbortMode during probing to avoid reporting
796 of bus errors (in some architectures) */
797 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
798 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
799 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
800
801 pci_enable_crs(dev);
802
803 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
804 !is_cardbus && !broken) {
805 unsigned int cmax;
806 /*
807 * Bus already configured by firmware, process it in the first
808 * pass and just note the configuration.
809 */
810 if (pass)
811 goto out;
812
813 /*
814 * The bus might already exist for two reasons: Either we are
815 * rescanning the bus or the bus is reachable through more than
816 * one bridge. The second case can happen with the i450NX
817 * chipset.
818 */
819 child = pci_find_bus(pci_domain_nr(bus), secondary);
820 if (!child) {
821 child = pci_add_new_bus(bus, dev, secondary);
822 if (!child)
823 goto out;
824 child->primary = primary;
825 pci_bus_insert_busn_res(child, secondary, subordinate);
826 child->bridge_ctl = bctl;
827 }
828
829 cmax = pci_scan_child_bus(child);
830 if (cmax > subordinate)
831 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
832 subordinate, cmax);
833 /* subordinate should equal child->busn_res.end */
834 if (subordinate > max)
835 max = subordinate;
836 } else {
837 /*
838 * We need to assign a number to this bus which we always
839 * do in the second pass.
840 */
841 if (!pass) {
842 if (pcibios_assign_all_busses() || broken || is_cardbus)
843 /* Temporarily disable forwarding of the
844 configuration cycles on all bridges in
845 this bus segment to avoid possible
846 conflicts in the second pass between two
847 bridges programmed with overlapping
848 bus ranges. */
849 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
850 buses & ~0xffffff);
851 goto out;
852 }
853
854 /* Clear errors */
855 pci_write_config_word(dev, PCI_STATUS, 0xffff);
856
857 /* Prevent assigning a bus number that already exists.
858 * This can happen when a bridge is hot-plugged, so in
859 * this case we only re-scan this bus. */
860 child = pci_find_bus(pci_domain_nr(bus), max+1);
861 if (!child) {
862 child = pci_add_new_bus(bus, dev, max+1);
863 if (!child)
864 goto out;
865 pci_bus_insert_busn_res(child, max+1, 0xff);
866 }
867 max++;
868 buses = (buses & 0xff000000)
869 | ((unsigned int)(child->primary) << 0)
870 | ((unsigned int)(child->busn_res.start) << 8)
871 | ((unsigned int)(child->busn_res.end) << 16);
872
873 /*
874 * yenta.c forces a secondary latency timer of 176.
875 * Copy that behaviour here.
876 */
877 if (is_cardbus) {
878 buses &= ~0xff000000;
879 buses |= CARDBUS_LATENCY_TIMER << 24;
880 }
881
882 /*
883 * We need to blast all three values with a single write.
884 */
885 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
886
887 if (!is_cardbus) {
888 child->bridge_ctl = bctl;
889 max = pci_scan_child_bus(child);
890 } else {
891 /*
892 * For CardBus bridges, we leave 4 bus numbers
893 * as cards with a PCI-to-PCI bridge can be
894 * inserted later.
895 */
896 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
897 struct pci_bus *parent = bus;
898 if (pci_find_bus(pci_domain_nr(bus),
899 max+i+1))
900 break;
901 while (parent->parent) {
902 if ((!pcibios_assign_all_busses()) &&
903 (parent->busn_res.end > max) &&
904 (parent->busn_res.end <= max+i)) {
905 j = 1;
906 }
907 parent = parent->parent;
908 }
909 if (j) {
910 /*
911 * Often, there are two cardbus bridges
912 * -- try to leave one valid bus number
913 * for each one.
914 */
915 i /= 2;
916 break;
917 }
918 }
919 max += i;
920 }
921 /*
922 * Set the subordinate bus number to its real value.
923 */
924 pci_bus_update_busn_res_end(child, max);
925 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
926 }
927
928 sprintf(child->name,
929 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
930 pci_domain_nr(bus), child->number);
931
932 /* Has only triggered on CardBus, fixup is in yenta_socket */
933 while (bus->parent) {
934 if ((child->busn_res.end > bus->busn_res.end) ||
935 (child->number > bus->busn_res.end) ||
936 (child->number < bus->number) ||
937 (child->busn_res.end < bus->number)) {
938 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
939 &child->busn_res,
940 (bus->number > child->busn_res.end &&
941 bus->busn_res.end < child->number) ?
942 "wholly" : "partially",
943 bus->self->transparent ? " transparent" : "",
944 dev_name(&bus->dev),
945 &bus->busn_res);
946 }
947 bus = bus->parent;
948 }
949
950 out:
951 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
952
953 return max;
954 }
955 EXPORT_SYMBOL(pci_scan_bridge);
956
957 /*
958 * Read interrupt line and base address registers.
959 * The architecture-dependent code can tweak these, of course.
960 */
961 static void pci_read_irq(struct pci_dev *dev)
962 {
963 unsigned char irq;
964
965 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
966 dev->pin = irq;
967 if (irq)
968 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
969 dev->irq = irq;
970 }
971
972 void set_pcie_port_type(struct pci_dev *pdev)
973 {
974 int pos;
975 u16 reg16;
976
977 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
978 if (!pos)
979 return;
980 pdev->pcie_cap = pos;
981 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
982 pdev->pcie_flags_reg = reg16;
983 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
984 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
985 }
986
987 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
988 {
989 u32 reg32;
990
991 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
992 if (reg32 & PCI_EXP_SLTCAP_HPC)
993 pdev->is_hotplug_bridge = 1;
994 }
995
996 /**
997 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
998 * @dev: PCI device
999 *
1000 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1001 * when forwarding a type1 configuration request the bridge must check that
1002 * the extended register address field is zero. The bridge is not permitted
1003 * to forward the transactions and must handle it as an Unsupported Request.
1004 * Some bridges do not follow this rule and simply drop the extended register
1005 * bits, resulting in the standard config space being aliased, every 256
1006 * bytes across the entire configuration space. Test for this condition by
1007 * comparing the first dword of each potential alias to the vendor/device ID.
1008 * Known offenders:
1009 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1010 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1011 */
1012 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1013 {
1014 #ifdef CONFIG_PCI_QUIRKS
1015 int pos;
1016 u32 header, tmp;
1017
1018 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1019
1020 for (pos = PCI_CFG_SPACE_SIZE;
1021 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1022 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1023 || header != tmp)
1024 return false;
1025 }
1026
1027 return true;
1028 #else
1029 return false;
1030 #endif
1031 }
1032
1033 /**
1034 * pci_cfg_space_size - get the configuration space size of the PCI device.
1035 * @dev: PCI device
1036 *
1037 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1038 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1039 * access it. Maybe we don't have a way to generate extended config space
1040 * accesses, or the device is behind a reverse Express bridge. So we try
1041 * reading the dword at 0x100 which must either be 0 or a valid extended
1042 * capability header.
1043 */
1044 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1045 {
1046 u32 status;
1047 int pos = PCI_CFG_SPACE_SIZE;
1048
1049 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1050 goto fail;
1051 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1052 goto fail;
1053
1054 return PCI_CFG_SPACE_EXP_SIZE;
1055
1056 fail:
1057 return PCI_CFG_SPACE_SIZE;
1058 }
1059
1060 int pci_cfg_space_size(struct pci_dev *dev)
1061 {
1062 int pos;
1063 u32 status;
1064 u16 class;
1065
1066 class = dev->class >> 8;
1067 if (class == PCI_CLASS_BRIDGE_HOST)
1068 return pci_cfg_space_size_ext(dev);
1069
1070 if (!pci_is_pcie(dev)) {
1071 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1072 if (!pos)
1073 goto fail;
1074
1075 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1076 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1077 goto fail;
1078 }
1079
1080 return pci_cfg_space_size_ext(dev);
1081
1082 fail:
1083 return PCI_CFG_SPACE_SIZE;
1084 }
1085
1086 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1087
1088 /**
1089 * pci_setup_device - fill in class and map information of a device
1090 * @dev: the device structure to fill
1091 *
1092 * Initialize the device structure with information about the device's
1093 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1094 * Called at initialisation of the PCI subsystem and by CardBus services.
1095 * Returns 0 on success and negative if unknown type of device (not normal,
1096 * bridge or CardBus).
1097 */
1098 int pci_setup_device(struct pci_dev *dev)
1099 {
1100 u32 class;
1101 u8 hdr_type;
1102 struct pci_slot *slot;
1103 int pos = 0;
1104 struct pci_bus_region region;
1105 struct resource *res;
1106
1107 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1108 return -EIO;
1109
1110 dev->sysdata = dev->bus->sysdata;
1111 dev->dev.parent = dev->bus->bridge;
1112 dev->dev.bus = &pci_bus_type;
1113 dev->hdr_type = hdr_type & 0x7f;
1114 dev->multifunction = !!(hdr_type & 0x80);
1115 dev->error_state = pci_channel_io_normal;
1116 set_pcie_port_type(dev);
1117
1118 list_for_each_entry(slot, &dev->bus->slots, list)
1119 if (PCI_SLOT(dev->devfn) == slot->number)
1120 dev->slot = slot;
1121
1122 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1123 set this higher, assuming the system even supports it. */
1124 dev->dma_mask = 0xffffffff;
1125
1126 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1127 dev->bus->number, PCI_SLOT(dev->devfn),
1128 PCI_FUNC(dev->devfn));
1129
1130 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1131 dev->revision = class & 0xff;
1132 dev->class = class >> 8; /* upper 3 bytes */
1133
1134 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1135 dev->vendor, dev->device, dev->hdr_type, dev->class);
1136
1137 /* need to have dev->class ready */
1138 dev->cfg_size = pci_cfg_space_size(dev);
1139
1140 /* "Unknown power state" */
1141 dev->current_state = PCI_UNKNOWN;
1142
1143 /* Early fixups, before probing the BARs */
1144 pci_fixup_device(pci_fixup_early, dev);
1145 /* device class may be changed after fixup */
1146 class = dev->class >> 8;
1147
1148 switch (dev->hdr_type) { /* header type */
1149 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1150 if (class == PCI_CLASS_BRIDGE_PCI)
1151 goto bad;
1152 pci_read_irq(dev);
1153 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1154 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1155 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1156
1157 /*
1158 * Do the ugly legacy mode stuff here rather than broken chip
1159 * quirk code. Legacy mode ATA controllers have fixed
1160 * addresses. These are not always echoed in BAR0-3, and
1161 * BAR0-3 in a few cases contain junk!
1162 */
1163 if (class == PCI_CLASS_STORAGE_IDE) {
1164 u8 progif;
1165 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1166 if ((progif & 1) == 0) {
1167 region.start = 0x1F0;
1168 region.end = 0x1F7;
1169 res = &dev->resource[0];
1170 res->flags = LEGACY_IO_RESOURCE;
1171 pcibios_bus_to_resource(dev->bus, res, &region);
1172 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1173 res);
1174 region.start = 0x3F6;
1175 region.end = 0x3F6;
1176 res = &dev->resource[1];
1177 res->flags = LEGACY_IO_RESOURCE;
1178 pcibios_bus_to_resource(dev->bus, res, &region);
1179 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1180 res);
1181 }
1182 if ((progif & 4) == 0) {
1183 region.start = 0x170;
1184 region.end = 0x177;
1185 res = &dev->resource[2];
1186 res->flags = LEGACY_IO_RESOURCE;
1187 pcibios_bus_to_resource(dev->bus, res, &region);
1188 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1189 res);
1190 region.start = 0x376;
1191 region.end = 0x376;
1192 res = &dev->resource[3];
1193 res->flags = LEGACY_IO_RESOURCE;
1194 pcibios_bus_to_resource(dev->bus, res, &region);
1195 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1196 res);
1197 }
1198 }
1199 break;
1200
1201 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1202 if (class != PCI_CLASS_BRIDGE_PCI)
1203 goto bad;
1204 /* The PCI-to-PCI bridge spec requires that subtractive
1205 decoding (i.e. transparent) bridge must have programming
1206 interface code of 0x01. */
1207 pci_read_irq(dev);
1208 dev->transparent = ((dev->class & 0xff) == 1);
1209 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1210 set_pcie_hotplug_bridge(dev);
1211 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1212 if (pos) {
1213 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1214 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1215 }
1216 break;
1217
1218 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1219 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1220 goto bad;
1221 pci_read_irq(dev);
1222 pci_read_bases(dev, 1, 0);
1223 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1224 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1225 break;
1226
1227 default: /* unknown header */
1228 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1229 dev->hdr_type);
1230 return -EIO;
1231
1232 bad:
1233 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1234 dev->class, dev->hdr_type);
1235 dev->class = PCI_CLASS_NOT_DEFINED;
1236 }
1237
1238 /* We found a fine healthy device, go go go... */
1239 return 0;
1240 }
1241
1242 static struct hpp_type0 pci_default_type0 = {
1243 .revision = 1,
1244 .cache_line_size = 8,
1245 .latency_timer = 0x40,
1246 .enable_serr = 0,
1247 .enable_perr = 0,
1248 };
1249
1250 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1251 {
1252 u16 pci_cmd, pci_bctl;
1253
1254 if (!hpp)
1255 hpp = &pci_default_type0;
1256
1257 if (hpp->revision > 1) {
1258 dev_warn(&dev->dev,
1259 "PCI settings rev %d not supported; using defaults\n",
1260 hpp->revision);
1261 hpp = &pci_default_type0;
1262 }
1263
1264 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1265 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1266 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1267 if (hpp->enable_serr)
1268 pci_cmd |= PCI_COMMAND_SERR;
1269 if (hpp->enable_perr)
1270 pci_cmd |= PCI_COMMAND_PARITY;
1271 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1272
1273 /* Program bridge control value */
1274 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1275 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1276 hpp->latency_timer);
1277 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1278 if (hpp->enable_serr)
1279 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1280 if (hpp->enable_perr)
1281 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1282 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1283 }
1284 }
1285
1286 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1287 {
1288 if (hpp)
1289 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1290 }
1291
1292 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1293 {
1294 int pos;
1295 u32 reg32;
1296
1297 if (!hpp)
1298 return;
1299
1300 if (hpp->revision > 1) {
1301 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1302 hpp->revision);
1303 return;
1304 }
1305
1306 /*
1307 * Don't allow _HPX to change MPS or MRRS settings. We manage
1308 * those to make sure they're consistent with the rest of the
1309 * platform.
1310 */
1311 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1312 PCI_EXP_DEVCTL_READRQ;
1313 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1314 PCI_EXP_DEVCTL_READRQ);
1315
1316 /* Initialize Device Control Register */
1317 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1318 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1319
1320 /* Initialize Link Control Register */
1321 if (pcie_cap_has_lnkctl(dev))
1322 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1323 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1324
1325 /* Find Advanced Error Reporting Enhanced Capability */
1326 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1327 if (!pos)
1328 return;
1329
1330 /* Initialize Uncorrectable Error Mask Register */
1331 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
1332 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1333 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1334
1335 /* Initialize Uncorrectable Error Severity Register */
1336 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
1337 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1338 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1339
1340 /* Initialize Correctable Error Mask Register */
1341 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
1342 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1343 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1344
1345 /* Initialize Advanced Error Capabilities and Control Register */
1346 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
1347 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1348 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1349
1350 /*
1351 * FIXME: The following two registers are not supported yet.
1352 *
1353 * o Secondary Uncorrectable Error Severity Register
1354 * o Secondary Uncorrectable Error Mask Register
1355 */
1356 }
1357
1358 static void pci_configure_device(struct pci_dev *dev)
1359 {
1360 struct hotplug_params hpp;
1361 int ret;
1362
1363 memset(&hpp, 0, sizeof(hpp));
1364 ret = pci_get_hp_params(dev, &hpp);
1365 if (ret)
1366 return;
1367
1368 program_hpp_type2(dev, hpp.t2);
1369 program_hpp_type1(dev, hpp.t1);
1370 program_hpp_type0(dev, hpp.t0);
1371 }
1372
1373 static void pci_release_capabilities(struct pci_dev *dev)
1374 {
1375 pci_vpd_release(dev);
1376 pci_iov_release(dev);
1377 pci_free_cap_save_buffers(dev);
1378 }
1379
1380 /**
1381 * pci_release_dev - free a pci device structure when all users of it are finished.
1382 * @dev: device that's been disconnected
1383 *
1384 * Will be called only by the device core when all users of this pci device are
1385 * done.
1386 */
1387 static void pci_release_dev(struct device *dev)
1388 {
1389 struct pci_dev *pci_dev;
1390
1391 pci_dev = to_pci_dev(dev);
1392 pci_release_capabilities(pci_dev);
1393 pci_release_of_node(pci_dev);
1394 pcibios_release_device(pci_dev);
1395 pci_bus_put(pci_dev->bus);
1396 kfree(pci_dev->driver_override);
1397 kfree(pci_dev);
1398 }
1399
1400 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1401 {
1402 struct pci_dev *dev;
1403
1404 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1405 if (!dev)
1406 return NULL;
1407
1408 INIT_LIST_HEAD(&dev->bus_list);
1409 dev->dev.type = &pci_dev_type;
1410 dev->bus = pci_bus_get(bus);
1411
1412 return dev;
1413 }
1414 EXPORT_SYMBOL(pci_alloc_dev);
1415
1416 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1417 int crs_timeout)
1418 {
1419 int delay = 1;
1420
1421 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1422 return false;
1423
1424 /* some broken boards return 0 or ~0 if a slot is empty: */
1425 if (*l == 0xffffffff || *l == 0x00000000 ||
1426 *l == 0x0000ffff || *l == 0xffff0000)
1427 return false;
1428
1429 /*
1430 * Configuration Request Retry Status. Some root ports return the
1431 * actual device ID instead of the synthetic ID (0xFFFF) required
1432 * by the PCIe spec. Ignore the device ID and only check for
1433 * (vendor id == 1).
1434 */
1435 while ((*l & 0xffff) == 0x0001) {
1436 if (!crs_timeout)
1437 return false;
1438
1439 msleep(delay);
1440 delay *= 2;
1441 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1442 return false;
1443 /* Card hasn't responded in 60 seconds? Must be stuck. */
1444 if (delay > crs_timeout) {
1445 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1446 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1447 PCI_FUNC(devfn));
1448 return false;
1449 }
1450 }
1451
1452 return true;
1453 }
1454 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1455
1456 /*
1457 * Read the config data for a PCI device, sanity-check it
1458 * and fill in the dev structure...
1459 */
1460 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1461 {
1462 struct pci_dev *dev;
1463 u32 l;
1464
1465 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1466 return NULL;
1467
1468 dev = pci_alloc_dev(bus);
1469 if (!dev)
1470 return NULL;
1471
1472 dev->devfn = devfn;
1473 dev->vendor = l & 0xffff;
1474 dev->device = (l >> 16) & 0xffff;
1475
1476 pci_set_of_node(dev);
1477
1478 if (pci_setup_device(dev)) {
1479 pci_bus_put(dev->bus);
1480 kfree(dev);
1481 return NULL;
1482 }
1483
1484 return dev;
1485 }
1486
1487 static void pci_init_capabilities(struct pci_dev *dev)
1488 {
1489 /* MSI/MSI-X list */
1490 pci_msi_init_pci_dev(dev);
1491
1492 /* Buffers for saving PCIe and PCI-X capabilities */
1493 pci_allocate_cap_save_buffers(dev);
1494
1495 /* Power Management */
1496 pci_pm_init(dev);
1497
1498 /* Vital Product Data */
1499 pci_vpd_pci22_init(dev);
1500
1501 /* Alternative Routing-ID Forwarding */
1502 pci_configure_ari(dev);
1503
1504 /* Single Root I/O Virtualization */
1505 pci_iov_init(dev);
1506
1507 /* Enable ACS P2P upstream forwarding */
1508 pci_enable_acs(dev);
1509 }
1510
1511 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1512 {
1513 int ret;
1514
1515 pci_configure_device(dev);
1516
1517 device_initialize(&dev->dev);
1518 dev->dev.release = pci_release_dev;
1519
1520 set_dev_node(&dev->dev, pcibus_to_node(bus));
1521 dev->dev.dma_mask = &dev->dma_mask;
1522 dev->dev.dma_parms = &dev->dma_parms;
1523 dev->dev.coherent_dma_mask = 0xffffffffull;
1524 of_pci_dma_configure(dev);
1525
1526 pci_set_dma_max_seg_size(dev, 65536);
1527 pci_set_dma_seg_boundary(dev, 0xffffffff);
1528
1529 /* Fix up broken headers */
1530 pci_fixup_device(pci_fixup_header, dev);
1531
1532 /* moved out from quirk header fixup code */
1533 pci_reassigndev_resource_alignment(dev);
1534
1535 /* Clear the state_saved flag. */
1536 dev->state_saved = false;
1537
1538 /* Initialize various capabilities */
1539 pci_init_capabilities(dev);
1540
1541 /*
1542 * Add the device to our list of discovered devices
1543 * and the bus list for fixup functions, etc.
1544 */
1545 down_write(&pci_bus_sem);
1546 list_add_tail(&dev->bus_list, &bus->devices);
1547 up_write(&pci_bus_sem);
1548
1549 ret = pcibios_add_device(dev);
1550 WARN_ON(ret < 0);
1551
1552 /* Notifier could use PCI capabilities */
1553 dev->match_driver = false;
1554 ret = device_add(&dev->dev);
1555 WARN_ON(ret < 0);
1556 }
1557
1558 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1559 {
1560 struct pci_dev *dev;
1561
1562 dev = pci_get_slot(bus, devfn);
1563 if (dev) {
1564 pci_dev_put(dev);
1565 return dev;
1566 }
1567
1568 dev = pci_scan_device(bus, devfn);
1569 if (!dev)
1570 return NULL;
1571
1572 pci_device_add(dev, bus);
1573
1574 return dev;
1575 }
1576 EXPORT_SYMBOL(pci_scan_single_device);
1577
1578 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1579 {
1580 int pos;
1581 u16 cap = 0;
1582 unsigned next_fn;
1583
1584 if (pci_ari_enabled(bus)) {
1585 if (!dev)
1586 return 0;
1587 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1588 if (!pos)
1589 return 0;
1590
1591 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1592 next_fn = PCI_ARI_CAP_NFN(cap);
1593 if (next_fn <= fn)
1594 return 0; /* protect against malformed list */
1595
1596 return next_fn;
1597 }
1598
1599 /* dev may be NULL for non-contiguous multifunction devices */
1600 if (!dev || dev->multifunction)
1601 return (fn + 1) % 8;
1602
1603 return 0;
1604 }
1605
1606 static int only_one_child(struct pci_bus *bus)
1607 {
1608 struct pci_dev *parent = bus->self;
1609
1610 if (!parent || !pci_is_pcie(parent))
1611 return 0;
1612 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1613 return 1;
1614 if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM &&
1615 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1616 return 1;
1617 return 0;
1618 }
1619
1620 /**
1621 * pci_scan_slot - scan a PCI slot on a bus for devices.
1622 * @bus: PCI bus to scan
1623 * @devfn: slot number to scan (must have zero function.)
1624 *
1625 * Scan a PCI slot on the specified PCI bus for devices, adding
1626 * discovered devices to the @bus->devices list. New devices
1627 * will not have is_added set.
1628 *
1629 * Returns the number of new devices found.
1630 */
1631 int pci_scan_slot(struct pci_bus *bus, int devfn)
1632 {
1633 unsigned fn, nr = 0;
1634 struct pci_dev *dev;
1635
1636 if (only_one_child(bus) && (devfn > 0))
1637 return 0; /* Already scanned the entire slot */
1638
1639 dev = pci_scan_single_device(bus, devfn);
1640 if (!dev)
1641 return 0;
1642 if (!dev->is_added)
1643 nr++;
1644
1645 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1646 dev = pci_scan_single_device(bus, devfn + fn);
1647 if (dev) {
1648 if (!dev->is_added)
1649 nr++;
1650 dev->multifunction = 1;
1651 }
1652 }
1653
1654 /* only one slot has pcie device */
1655 if (bus->self && nr)
1656 pcie_aspm_init_link_state(bus->self);
1657
1658 return nr;
1659 }
1660 EXPORT_SYMBOL(pci_scan_slot);
1661
1662 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1663 {
1664 u8 *smpss = data;
1665
1666 if (!pci_is_pcie(dev))
1667 return 0;
1668
1669 /*
1670 * We don't have a way to change MPS settings on devices that have
1671 * drivers attached. A hot-added device might support only the minimum
1672 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1673 * where devices may be hot-added, we limit the fabric MPS to 128 so
1674 * hot-added devices will work correctly.
1675 *
1676 * However, if we hot-add a device to a slot directly below a Root
1677 * Port, it's impossible for there to be other existing devices below
1678 * the port. We don't limit the MPS in this case because we can
1679 * reconfigure MPS on both the Root Port and the hot-added device,
1680 * and there are no other devices involved.
1681 *
1682 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1683 */
1684 if (dev->is_hotplug_bridge &&
1685 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1686 *smpss = 0;
1687
1688 if (*smpss > dev->pcie_mpss)
1689 *smpss = dev->pcie_mpss;
1690
1691 return 0;
1692 }
1693
1694 static void pcie_write_mps(struct pci_dev *dev, int mps)
1695 {
1696 int rc;
1697
1698 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1699 mps = 128 << dev->pcie_mpss;
1700
1701 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1702 dev->bus->self)
1703 /* For "Performance", the assumption is made that
1704 * downstream communication will never be larger than
1705 * the MRRS. So, the MPS only needs to be configured
1706 * for the upstream communication. This being the case,
1707 * walk from the top down and set the MPS of the child
1708 * to that of the parent bus.
1709 *
1710 * Configure the device MPS with the smaller of the
1711 * device MPSS or the bridge MPS (which is assumed to be
1712 * properly configured at this point to the largest
1713 * allowable MPS based on its parent bus).
1714 */
1715 mps = min(mps, pcie_get_mps(dev->bus->self));
1716 }
1717
1718 rc = pcie_set_mps(dev, mps);
1719 if (rc)
1720 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1721 }
1722
1723 static void pcie_write_mrrs(struct pci_dev *dev)
1724 {
1725 int rc, mrrs;
1726
1727 /* In the "safe" case, do not configure the MRRS. There appear to be
1728 * issues with setting MRRS to 0 on a number of devices.
1729 */
1730 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1731 return;
1732
1733 /* For Max performance, the MRRS must be set to the largest supported
1734 * value. However, it cannot be configured larger than the MPS the
1735 * device or the bus can support. This should already be properly
1736 * configured by a prior call to pcie_write_mps.
1737 */
1738 mrrs = pcie_get_mps(dev);
1739
1740 /* MRRS is a R/W register. Invalid values can be written, but a
1741 * subsequent read will verify if the value is acceptable or not.
1742 * If the MRRS value provided is not acceptable (e.g., too large),
1743 * shrink the value until it is acceptable to the HW.
1744 */
1745 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1746 rc = pcie_set_readrq(dev, mrrs);
1747 if (!rc)
1748 break;
1749
1750 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1751 mrrs /= 2;
1752 }
1753
1754 if (mrrs < 128)
1755 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1756 }
1757
1758 static void pcie_bus_detect_mps(struct pci_dev *dev)
1759 {
1760 struct pci_dev *bridge = dev->bus->self;
1761 int mps, p_mps;
1762
1763 if (!bridge)
1764 return;
1765
1766 mps = pcie_get_mps(dev);
1767 p_mps = pcie_get_mps(bridge);
1768
1769 if (mps != p_mps)
1770 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1771 mps, pci_name(bridge), p_mps);
1772 }
1773
1774 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1775 {
1776 int mps, orig_mps;
1777
1778 if (!pci_is_pcie(dev))
1779 return 0;
1780
1781 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1782 pcie_bus_detect_mps(dev);
1783 return 0;
1784 }
1785
1786 mps = 128 << *(u8 *)data;
1787 orig_mps = pcie_get_mps(dev);
1788
1789 pcie_write_mps(dev, mps);
1790 pcie_write_mrrs(dev);
1791
1792 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1793 pcie_get_mps(dev), 128 << dev->pcie_mpss,
1794 orig_mps, pcie_get_readrq(dev));
1795
1796 return 0;
1797 }
1798
1799 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1800 * parents then children fashion. If this changes, then this code will not
1801 * work as designed.
1802 */
1803 void pcie_bus_configure_settings(struct pci_bus *bus)
1804 {
1805 u8 smpss = 0;
1806
1807 if (!bus->self)
1808 return;
1809
1810 if (!pci_is_pcie(bus->self))
1811 return;
1812
1813 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1814 * to be aware of the MPS of the destination. To work around this,
1815 * simply force the MPS of the entire system to the smallest possible.
1816 */
1817 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1818 smpss = 0;
1819
1820 if (pcie_bus_config == PCIE_BUS_SAFE) {
1821 smpss = bus->self->pcie_mpss;
1822
1823 pcie_find_smpss(bus->self, &smpss);
1824 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1825 }
1826
1827 pcie_bus_configure_set(bus->self, &smpss);
1828 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1829 }
1830 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1831
1832 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1833 {
1834 unsigned int devfn, pass, max = bus->busn_res.start;
1835 struct pci_dev *dev;
1836
1837 dev_dbg(&bus->dev, "scanning bus\n");
1838
1839 /* Go find them, Rover! */
1840 for (devfn = 0; devfn < 0x100; devfn += 8)
1841 pci_scan_slot(bus, devfn);
1842
1843 /* Reserve buses for SR-IOV capability. */
1844 max += pci_iov_bus_range(bus);
1845
1846 /*
1847 * After performing arch-dependent fixup of the bus, look behind
1848 * all PCI-to-PCI bridges on this bus.
1849 */
1850 if (!bus->is_added) {
1851 dev_dbg(&bus->dev, "fixups for bus\n");
1852 pcibios_fixup_bus(bus);
1853 bus->is_added = 1;
1854 }
1855
1856 for (pass = 0; pass < 2; pass++)
1857 list_for_each_entry(dev, &bus->devices, bus_list) {
1858 if (pci_is_bridge(dev))
1859 max = pci_scan_bridge(bus, dev, max, pass);
1860 }
1861
1862 /*
1863 * We've scanned the bus and so we know all about what's on
1864 * the other side of any bridges that may be on this bus plus
1865 * any devices.
1866 *
1867 * Return how far we've got finding sub-buses.
1868 */
1869 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1870 return max;
1871 }
1872 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1873
1874 /**
1875 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
1876 * @bridge: Host bridge to set up.
1877 *
1878 * Default empty implementation. Replace with an architecture-specific setup
1879 * routine, if necessary.
1880 */
1881 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
1882 {
1883 return 0;
1884 }
1885
1886 void __weak pcibios_add_bus(struct pci_bus *bus)
1887 {
1888 }
1889
1890 void __weak pcibios_remove_bus(struct pci_bus *bus)
1891 {
1892 }
1893
1894 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1895 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1896 {
1897 int error;
1898 struct pci_host_bridge *bridge;
1899 struct pci_bus *b, *b2;
1900 struct resource_entry *window, *n;
1901 struct resource *res;
1902 resource_size_t offset;
1903 char bus_addr[64];
1904 char *fmt;
1905
1906 b = pci_alloc_bus(NULL);
1907 if (!b)
1908 return NULL;
1909
1910 b->sysdata = sysdata;
1911 b->ops = ops;
1912 b->number = b->busn_res.start = bus;
1913 pci_bus_assign_domain_nr(b, parent);
1914 b2 = pci_find_bus(pci_domain_nr(b), bus);
1915 if (b2) {
1916 /* If we already got to this bus through a different bridge, ignore it */
1917 dev_dbg(&b2->dev, "bus already known\n");
1918 goto err_out;
1919 }
1920
1921 bridge = pci_alloc_host_bridge(b);
1922 if (!bridge)
1923 goto err_out;
1924
1925 bridge->dev.parent = parent;
1926 bridge->dev.release = pci_release_host_bridge_dev;
1927 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1928 error = pcibios_root_bridge_prepare(bridge);
1929 if (error) {
1930 kfree(bridge);
1931 goto err_out;
1932 }
1933
1934 error = device_register(&bridge->dev);
1935 if (error) {
1936 put_device(&bridge->dev);
1937 goto err_out;
1938 }
1939 b->bridge = get_device(&bridge->dev);
1940 device_enable_async_suspend(b->bridge);
1941 pci_set_bus_of_node(b);
1942
1943 if (!parent)
1944 set_dev_node(b->bridge, pcibus_to_node(b));
1945
1946 b->dev.class = &pcibus_class;
1947 b->dev.parent = b->bridge;
1948 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1949 error = device_register(&b->dev);
1950 if (error)
1951 goto class_dev_reg_err;
1952
1953 pcibios_add_bus(b);
1954
1955 /* Create legacy_io and legacy_mem files for this bus */
1956 pci_create_legacy_files(b);
1957
1958 if (parent)
1959 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
1960 else
1961 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
1962
1963 /* Add initial resources to the bus */
1964 resource_list_for_each_entry_safe(window, n, resources) {
1965 list_move_tail(&window->node, &bridge->windows);
1966 res = window->res;
1967 offset = window->offset;
1968 if (res->flags & IORESOURCE_BUS)
1969 pci_bus_insert_busn_res(b, bus, res->end);
1970 else
1971 pci_bus_add_resource(b, res, 0);
1972 if (offset) {
1973 if (resource_type(res) == IORESOURCE_IO)
1974 fmt = " (bus address [%#06llx-%#06llx])";
1975 else
1976 fmt = " (bus address [%#010llx-%#010llx])";
1977 snprintf(bus_addr, sizeof(bus_addr), fmt,
1978 (unsigned long long) (res->start - offset),
1979 (unsigned long long) (res->end - offset));
1980 } else
1981 bus_addr[0] = '\0';
1982 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
1983 }
1984
1985 down_write(&pci_bus_sem);
1986 list_add_tail(&b->node, &pci_root_buses);
1987 up_write(&pci_bus_sem);
1988
1989 return b;
1990
1991 class_dev_reg_err:
1992 put_device(&bridge->dev);
1993 device_unregister(&bridge->dev);
1994 err_out:
1995 kfree(b);
1996 return NULL;
1997 }
1998 EXPORT_SYMBOL_GPL(pci_create_root_bus);
1999
2000 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2001 {
2002 struct resource *res = &b->busn_res;
2003 struct resource *parent_res, *conflict;
2004
2005 res->start = bus;
2006 res->end = bus_max;
2007 res->flags = IORESOURCE_BUS;
2008
2009 if (!pci_is_root_bus(b))
2010 parent_res = &b->parent->busn_res;
2011 else {
2012 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2013 res->flags |= IORESOURCE_PCI_FIXED;
2014 }
2015
2016 conflict = request_resource_conflict(parent_res, res);
2017
2018 if (conflict)
2019 dev_printk(KERN_DEBUG, &b->dev,
2020 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2021 res, pci_is_root_bus(b) ? "domain " : "",
2022 parent_res, conflict->name, conflict);
2023
2024 return conflict == NULL;
2025 }
2026
2027 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2028 {
2029 struct resource *res = &b->busn_res;
2030 struct resource old_res = *res;
2031 resource_size_t size;
2032 int ret;
2033
2034 if (res->start > bus_max)
2035 return -EINVAL;
2036
2037 size = bus_max - res->start + 1;
2038 ret = adjust_resource(res, res->start, size);
2039 dev_printk(KERN_DEBUG, &b->dev,
2040 "busn_res: %pR end %s updated to %02x\n",
2041 &old_res, ret ? "can not be" : "is", bus_max);
2042
2043 if (!ret && !res->parent)
2044 pci_bus_insert_busn_res(b, res->start, res->end);
2045
2046 return ret;
2047 }
2048
2049 void pci_bus_release_busn_res(struct pci_bus *b)
2050 {
2051 struct resource *res = &b->busn_res;
2052 int ret;
2053
2054 if (!res->flags || !res->parent)
2055 return;
2056
2057 ret = release_resource(res);
2058 dev_printk(KERN_DEBUG, &b->dev,
2059 "busn_res: %pR %s released\n",
2060 res, ret ? "can not be" : "is");
2061 }
2062
2063 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2064 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2065 {
2066 struct resource_entry *window;
2067 bool found = false;
2068 struct pci_bus *b;
2069 int max;
2070
2071 resource_list_for_each_entry(window, resources)
2072 if (window->res->flags & IORESOURCE_BUS) {
2073 found = true;
2074 break;
2075 }
2076
2077 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2078 if (!b)
2079 return NULL;
2080
2081 if (!found) {
2082 dev_info(&b->dev,
2083 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2084 bus);
2085 pci_bus_insert_busn_res(b, bus, 255);
2086 }
2087
2088 max = pci_scan_child_bus(b);
2089
2090 if (!found)
2091 pci_bus_update_busn_res_end(b, max);
2092
2093 return b;
2094 }
2095 EXPORT_SYMBOL(pci_scan_root_bus);
2096
2097 /* Deprecated; use pci_scan_root_bus() instead */
2098 struct pci_bus *pci_scan_bus_parented(struct device *parent,
2099 int bus, struct pci_ops *ops, void *sysdata)
2100 {
2101 LIST_HEAD(resources);
2102 struct pci_bus *b;
2103
2104 pci_add_resource(&resources, &ioport_resource);
2105 pci_add_resource(&resources, &iomem_resource);
2106 pci_add_resource(&resources, &busn_resource);
2107 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
2108 if (b)
2109 pci_scan_child_bus(b);
2110 else
2111 pci_free_resource_list(&resources);
2112 return b;
2113 }
2114 EXPORT_SYMBOL(pci_scan_bus_parented);
2115
2116 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2117 void *sysdata)
2118 {
2119 LIST_HEAD(resources);
2120 struct pci_bus *b;
2121
2122 pci_add_resource(&resources, &ioport_resource);
2123 pci_add_resource(&resources, &iomem_resource);
2124 pci_add_resource(&resources, &busn_resource);
2125 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2126 if (b) {
2127 pci_scan_child_bus(b);
2128 } else {
2129 pci_free_resource_list(&resources);
2130 }
2131 return b;
2132 }
2133 EXPORT_SYMBOL(pci_scan_bus);
2134
2135 /**
2136 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2137 * @bridge: PCI bridge for the bus to scan
2138 *
2139 * Scan a PCI bus and child buses for new devices, add them,
2140 * and enable them, resizing bridge mmio/io resource if necessary
2141 * and possible. The caller must ensure the child devices are already
2142 * removed for resizing to occur.
2143 *
2144 * Returns the max number of subordinate bus discovered.
2145 */
2146 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2147 {
2148 unsigned int max;
2149 struct pci_bus *bus = bridge->subordinate;
2150
2151 max = pci_scan_child_bus(bus);
2152
2153 pci_assign_unassigned_bridge_resources(bridge);
2154
2155 pci_bus_add_devices(bus);
2156
2157 return max;
2158 }
2159
2160 /**
2161 * pci_rescan_bus - scan a PCI bus for devices.
2162 * @bus: PCI bus to scan
2163 *
2164 * Scan a PCI bus and child buses for new devices, adds them,
2165 * and enables them.
2166 *
2167 * Returns the max number of subordinate bus discovered.
2168 */
2169 unsigned int pci_rescan_bus(struct pci_bus *bus)
2170 {
2171 unsigned int max;
2172
2173 max = pci_scan_child_bus(bus);
2174 pci_assign_unassigned_bus_resources(bus);
2175 pci_bus_add_devices(bus);
2176
2177 return max;
2178 }
2179 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2180
2181 /*
2182 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2183 * routines should always be executed under this mutex.
2184 */
2185 static DEFINE_MUTEX(pci_rescan_remove_lock);
2186
2187 void pci_lock_rescan_remove(void)
2188 {
2189 mutex_lock(&pci_rescan_remove_lock);
2190 }
2191 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2192
2193 void pci_unlock_rescan_remove(void)
2194 {
2195 mutex_unlock(&pci_rescan_remove_lock);
2196 }
2197 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2198
2199 static int __init pci_sort_bf_cmp(const struct device *d_a,
2200 const struct device *d_b)
2201 {
2202 const struct pci_dev *a = to_pci_dev(d_a);
2203 const struct pci_dev *b = to_pci_dev(d_b);
2204
2205 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2206 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2207
2208 if (a->bus->number < b->bus->number) return -1;
2209 else if (a->bus->number > b->bus->number) return 1;
2210
2211 if (a->devfn < b->devfn) return -1;
2212 else if (a->devfn > b->devfn) return 1;
2213
2214 return 0;
2215 }
2216
2217 void __init pci_sort_breadthfirst(void)
2218 {
2219 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2220 }
Linux with added FPC-III support