arch/sh/boards/mach-migor/setup.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas System Solutions Asia Pte. Ltd - Migo-R
   4  *
   5  * Copyright (C) 2008 Magnus Damm
   6  */
   7 #include <linux/clkdev.h>
   8 #include <linux/init.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/input.h>
  12 #include <linux/input/sh_keysc.h>
  13 #include <linux/memblock.h>
  14 #include <linux/mmc/host.h>
  15 #include <linux/mtd/physmap.h>
  16 #include <linux/mfd/tmio.h>
  17 #include <linux/mtd/platnand.h>
  18 #include <linux/i2c.h>
  19 #include <linux/regulator/fixed.h>
  20 #include <linux/regulator/machine.h>
  21 #include <linux/smc91x.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/gpio.h>
  25 #include <linux/gpio/machine.h>
  26 #include <linux/videodev2.h>
  27 #include <linux/sh_intc.h>
  28 #include <video/sh_mobile_lcdc.h>
  29 #include <media/drv-intf/renesas-ceu.h>
  30 #include <media/i2c/ov772x.h>
  31 #include <media/i2c/tw9910.h>
  32 #include <asm/clock.h>
  33 #include <asm/machvec.h>
  34 #include <asm/io.h>
  35 #include <asm/suspend.h>
  36 #include <mach/migor.h>
  37 #include <cpu/sh7722.h>
  38
  39 /* Address     IRQ  Size  Bus  Description
  40  * 0x00000000       64MB  16   NOR Flash (SP29PL256N)
  41  * 0x0c000000       64MB  64   SDRAM (2xK4M563233G)
  42  * 0x10000000  IRQ0       16   Ethernet (SMC91C111)
  43  * 0x14000000  IRQ4       16   USB 2.0 Host Controller (M66596)
  44  * 0x18000000       8GB    8   NAND Flash (K9K8G08U0A)
  45  */
  46
  47 #define CEU_BUFFER_MEMORY_SIZE          (4 << 20)
  48 static phys_addr_t ceu_dma_membase;
  49
  50 static struct smc91x_platdata smc91x_info = {
  51         .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  52 };
  53
  54 static struct resource smc91x_eth_resources[] = {
  55         [0] = {
  56                 .name   = "SMC91C111" ,
  57                 .start  = 0x10000300,
  58                 .end    = 0x1000030f,
  59                 .flags  = IORESOURCE_MEM,
  60         },
  61         [1] = {
  62                 .start  = evt2irq(0x600), /* IRQ0 */
  63                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  64         },
  65 };
  66
  67 static struct platform_device smc91x_eth_device = {
  68         .name           = "smc91x",
  69         .num_resources  = ARRAY_SIZE(smc91x_eth_resources),
  70         .resource       = smc91x_eth_resources,
  71         .dev    = {
  72                 .platform_data  = &smc91x_info,
  73         },
  74 };
  75
  76 static struct sh_keysc_info sh_keysc_info = {
  77         .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
  78         .scan_timing = 3,
  79         .delay = 5,
  80         .keycodes = {
  81                 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
  82                 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
  83                 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
  84                 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
  85                 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
  86         },
  87 };
  88
  89 static struct resource sh_keysc_resources[] = {
  90         [0] = {
  91                 .start  = 0x044b0000,
  92                 .end    = 0x044b000f,
  93                 .flags  = IORESOURCE_MEM,
  94         },
  95         [1] = {
  96                 .start  = evt2irq(0xbe0),
  97                 .flags  = IORESOURCE_IRQ,
  98         },
  99 };
 100
 101 static struct platform_device sh_keysc_device = {
 102         .name           = "sh_keysc",
 103         .id             = 0, /* "keysc0" clock */
 104         .num_resources  = ARRAY_SIZE(sh_keysc_resources),
 105         .resource       = sh_keysc_resources,
 106         .dev    = {
 107                 .platform_data  = &sh_keysc_info,
 108         },
 109 };
 110
 111 static struct mtd_partition migor_nor_flash_partitions[] =
 112 {
 113         {
 114                 .name = "uboot",
 115                 .offset = 0,
 116                 .size = (1 * 1024 * 1024),
 117                 .mask_flags = MTD_WRITEABLE,    /* Read-only */
 118         },
 119         {
 120                 .name = "rootfs",
 121                 .offset = MTDPART_OFS_APPEND,
 122                 .size = (15 * 1024 * 1024),
 123         },
 124         {
 125                 .name = "other",
 126                 .offset = MTDPART_OFS_APPEND,
 127                 .size = MTDPART_SIZ_FULL,
 128         },
 129 };
 130
 131 static struct physmap_flash_data migor_nor_flash_data = {
 132         .width          = 2,
 133         .parts          = migor_nor_flash_partitions,
 134         .nr_parts       = ARRAY_SIZE(migor_nor_flash_partitions),
 135 };
 136
 137 static struct resource migor_nor_flash_resources[] = {
 138         [0] = {
 139                 .name           = "NOR Flash",
 140                 .start          = 0x00000000,
 141                 .end            = 0x03ffffff,
 142                 .flags          = IORESOURCE_MEM,
 143         }
 144 };
 145
 146 static struct platform_device migor_nor_flash_device = {
 147         .name           = "physmap-flash",
 148         .resource       = migor_nor_flash_resources,
 149         .num_resources  = ARRAY_SIZE(migor_nor_flash_resources),
 150         .dev            = {
 151                 .platform_data = &migor_nor_flash_data,
 152         },
 153 };
 154
 155 static struct mtd_partition migor_nand_flash_partitions[] = {
 156         {
 157                 .name           = "nanddata1",
 158                 .offset         = 0x0,
 159                 .size           = 512 * 1024 * 1024,
 160         },
 161         {
 162                 .name           = "nanddata2",
 163                 .offset         = MTDPART_OFS_APPEND,
 164                 .size           = 512 * 1024 * 1024,
 165         },
 166 };
 167
 168 static void migor_nand_flash_cmd_ctl(struct nand_chip *chip, int cmd,
 169                                      unsigned int ctrl)
 170 {
 171         if (cmd == NAND_CMD_NONE)
 172                 return;
 173
 174         if (ctrl & NAND_CLE)
 175                 writeb(cmd, chip->legacy.IO_ADDR_W + 0x00400000);
 176         else if (ctrl & NAND_ALE)
 177                 writeb(cmd, chip->legacy.IO_ADDR_W + 0x00800000);
 178         else
 179                 writeb(cmd, chip->legacy.IO_ADDR_W);
 180 }
 181
 182 static int migor_nand_flash_ready(struct nand_chip *chip)
 183 {
 184         return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
 185 }
 186
 187 static struct platform_nand_data migor_nand_flash_data = {
 188         .chip = {
 189                 .nr_chips = 1,
 190                 .partitions = migor_nand_flash_partitions,
 191                 .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
 192                 .chip_delay = 20,
 193         },
 194         .ctrl = {
 195                 .dev_ready = migor_nand_flash_ready,
 196                 .cmd_ctrl = migor_nand_flash_cmd_ctl,
 197         },
 198 };
 199
 200 static struct resource migor_nand_flash_resources[] = {
 201         [0] = {
 202                 .name           = "NAND Flash",
 203                 .start          = 0x18000000,
 204                 .end            = 0x18ffffff,
 205                 .flags          = IORESOURCE_MEM,
 206         },
 207 };
 208
 209 static struct platform_device migor_nand_flash_device = {
 210         .name           = "gen_nand",
 211         .resource       = migor_nand_flash_resources,
 212         .num_resources  = ARRAY_SIZE(migor_nand_flash_resources),
 213         .dev            = {
 214                 .platform_data = &migor_nand_flash_data,
 215         }
 216 };
 217
 218 static const struct fb_videomode migor_lcd_modes[] = {
 219         {
 220 #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
 221                 .name = "LB070WV1",
 222                 .xres = 800,
 223                 .yres = 480,
 224                 .left_margin = 64,
 225                 .right_margin = 16,
 226                 .hsync_len = 120,
 227                 .sync = 0,
 228 #elif defined(CONFIG_SH_MIGOR_QVGA)
 229                 .name = "PH240320T",
 230                 .xres = 320,
 231                 .yres = 240,
 232                 .left_margin = 0,
 233                 .right_margin = 16,
 234                 .hsync_len = 8,
 235                 .sync = FB_SYNC_HOR_HIGH_ACT,
 236 #endif
 237                 .upper_margin = 1,
 238                 .lower_margin = 17,
 239                 .vsync_len = 2,
 240         },
 241 };
 242
 243 static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
 244 #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
 245         .clock_source = LCDC_CLK_BUS,
 246         .ch[0] = {
 247                 .chan = LCDC_CHAN_MAINLCD,
 248                 .fourcc = V4L2_PIX_FMT_RGB565,
 249                 .interface_type = RGB16,
 250                 .clock_divider = 2,
 251                 .lcd_modes = migor_lcd_modes,
 252                 .num_modes = ARRAY_SIZE(migor_lcd_modes),
 253                 .panel_cfg = { /* 7.0 inch */
 254                         .width = 152,
 255                         .height = 91,
 256                 },
 257         }
 258 #elif defined(CONFIG_SH_MIGOR_QVGA)
 259         .clock_source = LCDC_CLK_PERIPHERAL,
 260         .ch[0] = {
 261                 .chan = LCDC_CHAN_MAINLCD,
 262                 .fourcc = V4L2_PIX_FMT_RGB565,
 263                 .interface_type = SYS16A,
 264                 .clock_divider = 10,
 265                 .lcd_modes = migor_lcd_modes,
 266                 .num_modes = ARRAY_SIZE(migor_lcd_modes),
 267                 .panel_cfg = {
 268                         .width = 49,    /* 2.4 inch */
 269                         .height = 37,
 270                         .setup_sys = migor_lcd_qvga_setup,
 271                 },
 272                 .sys_bus_cfg = {
 273                         .ldmt2r = 0x06000a09,
 274                         .ldmt3r = 0x180e3418,
 275                         /* set 1s delay to encourage fsync() */
 276                         .deferred_io_msec = 1000,
 277                 },
 278         }
 279 #endif
 280 };
 281
 282 static struct resource migor_lcdc_resources[] = {
 283         [0] = {
 284                 .name   = "LCDC",
 285                 .start  = 0xfe940000, /* P4-only space */
 286                 .end    = 0xfe942fff,
 287                 .flags  = IORESOURCE_MEM,
 288         },
 289         [1] = {
 290                 .start  = evt2irq(0x580),
 291                 .flags  = IORESOURCE_IRQ,
 292         },
 293 };
 294
 295 static struct platform_device migor_lcdc_device = {
 296         .name           = "sh_mobile_lcdc_fb",
 297         .num_resources  = ARRAY_SIZE(migor_lcdc_resources),
 298         .resource       = migor_lcdc_resources,
 299         .dev    = {
 300                 .platform_data  = &sh_mobile_lcdc_info,
 301         },
 302 };
 303
 304 static struct ceu_platform_data ceu_pdata = {
 305         .num_subdevs                    = 2,
 306         .subdevs = {
 307                 { /* [0] = ov772x */
 308                         .flags          = 0,
 309                         .bus_width      = 8,
 310                         .bus_shift      = 0,
 311                         .i2c_adapter_id = 0,
 312                         .i2c_address    = 0x21,
 313                 },
 314                 { /* [1] = tw9910 */
 315                         .flags          = 0,
 316                         .bus_width      = 8,
 317                         .bus_shift      = 0,
 318                         .i2c_adapter_id = 0,
 319                         .i2c_address    = 0x45,
 320                 },
 321         },
 322 };
 323
 324 static struct resource migor_ceu_resources[] = {
 325         [0] = {
 326                 .name   = "CEU",
 327                 .start  = 0xfe910000,
 328                 .end    = 0xfe91009f,
 329                 .flags  = IORESOURCE_MEM,
 330         },
 331         [1] = {
 332                 .start  = evt2irq(0x880),
 333                 .flags  = IORESOURCE_IRQ,
 334         },
 335 };
 336
 337 static struct platform_device migor_ceu_device = {
 338         .name           = "renesas-ceu",
 339         .id             = 0, /* ceu.0 */
 340         .num_resources  = ARRAY_SIZE(migor_ceu_resources),
 341         .resource       = migor_ceu_resources,
 342         .dev    = {
 343                 .platform_data  = &ceu_pdata,
 344         },
 345 };
 346
 347 /* Powerdown/reset gpios for CEU image sensors */
 348 static struct gpiod_lookup_table ov7725_gpios = {
 349         .dev_id         = "0-0021",
 350         .table          = {
 351                 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT0, "powerdown",
 352                             GPIO_ACTIVE_HIGH),
 353                 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "reset", GPIO_ACTIVE_LOW),
 354         },
 355 };
 356
 357 static struct gpiod_lookup_table tw9910_gpios = {
 358         .dev_id         = "0-0045",
 359         .table          = {
 360                 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT2, "pdn", GPIO_ACTIVE_LOW),
 361                 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "rstb", GPIO_ACTIVE_LOW),
 362         },
 363 };
 364
 365 /* Fixed 3.3V regulator to be used by SDHI0 */
 366 static struct regulator_consumer_supply fixed3v3_power_consumers[] =
 367 {
 368         REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
 369         REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
 370 };
 371
 372 static struct resource sdhi_cn9_resources[] = {
 373         [0] = {
 374                 .name   = "SDHI",
 375                 .start  = 0x04ce0000,
 376                 .end    = 0x04ce00ff,
 377                 .flags  = IORESOURCE_MEM,
 378         },
 379         [1] = {
 380                 .start  = evt2irq(0xe80),
 381                 .flags  = IORESOURCE_IRQ,
 382         },
 383 };
 384
 385 static struct tmio_mmc_data sh7724_sdhi_data = {
 386         .chan_priv_tx   = (void *)SHDMA_SLAVE_SDHI0_TX,
 387         .chan_priv_rx   = (void *)SHDMA_SLAVE_SDHI0_RX,
 388         .capabilities   = MMC_CAP_SDIO_IRQ,
 389 };
 390
 391 static struct platform_device sdhi_cn9_device = {
 392         .name           = "sh_mobile_sdhi",
 393         .num_resources  = ARRAY_SIZE(sdhi_cn9_resources),
 394         .resource       = sdhi_cn9_resources,
 395         .dev = {
 396                 .platform_data  = &sh7724_sdhi_data,
 397         },
 398 };
 399
 400 static struct ov772x_camera_info ov7725_info = {
 401         .flags          = 0,
 402 };
 403
 404 static struct tw9910_video_info tw9910_info = {
 405         .buswidth       = 8,
 406         .mpout          = TW9910_MPO_FIELD,
 407 };
 408
 409 static struct i2c_board_info migor_i2c_devices[] = {
 410         {
 411                 I2C_BOARD_INFO("rs5c372b", 0x32),
 412         },
 413         {
 414                 I2C_BOARD_INFO("migor_ts", 0x51),
 415                 .irq = evt2irq(0x6c0), /* IRQ6 */
 416         },
 417         {
 418                 I2C_BOARD_INFO("wm8978", 0x1a),
 419         },
 420         {
 421                 I2C_BOARD_INFO("ov772x", 0x21),
 422                 .platform_data = &ov7725_info,
 423         },
 424         {
 425                 I2C_BOARD_INFO("tw9910", 0x45),
 426                 .platform_data = &tw9910_info,
 427         },
 428 };
 429
 430 static struct platform_device *migor_devices[] __initdata = {
 431         &smc91x_eth_device,
 432         &sh_keysc_device,
 433         &migor_lcdc_device,
 434         &migor_nor_flash_device,
 435         &migor_nand_flash_device,
 436         &sdhi_cn9_device,
 437 };
 438
 439 extern char migor_sdram_enter_start;
 440 extern char migor_sdram_enter_end;
 441 extern char migor_sdram_leave_start;
 442 extern char migor_sdram_leave_end;
 443
 444 static int __init migor_devices_setup(void)
 445 {
 446         struct clk *video_clk;
 447
 448         /* register board specific self-refresh code */
 449         sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
 450                                         &migor_sdram_enter_start,
 451                                         &migor_sdram_enter_end,
 452                                         &migor_sdram_leave_start,
 453                                         &migor_sdram_leave_end);
 454
 455         regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
 456                                      ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
 457
 458         /* Let D11 LED show STATUS0 */
 459         gpio_request(GPIO_FN_STATUS0, NULL);
 460
 461         /* Lit D12 LED show PDSTATUS */
 462         gpio_request(GPIO_FN_PDSTATUS, NULL);
 463
 464         /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
 465         gpio_request(GPIO_FN_IRQ0, NULL);
 466         __raw_writel(0x00003400, BSC_CS4BCR);
 467         __raw_writel(0x00110080, BSC_CS4WCR);
 468
 469         /* KEYSC */
 470         gpio_request(GPIO_FN_KEYOUT0, NULL);
 471         gpio_request(GPIO_FN_KEYOUT1, NULL);
 472         gpio_request(GPIO_FN_KEYOUT2, NULL);
 473         gpio_request(GPIO_FN_KEYOUT3, NULL);
 474         gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
 475         gpio_request(GPIO_FN_KEYIN1, NULL);
 476         gpio_request(GPIO_FN_KEYIN2, NULL);
 477         gpio_request(GPIO_FN_KEYIN3, NULL);
 478         gpio_request(GPIO_FN_KEYIN4, NULL);
 479         gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
 480
 481         /* NAND Flash */
 482         gpio_request(GPIO_FN_CS6A_CE2B, NULL);
 483         __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
 484         gpio_request(GPIO_PTA1, NULL);
 485         gpio_direction_input(GPIO_PTA1);
 486
 487         /* SDHI */
 488         gpio_request(GPIO_FN_SDHICD, NULL);
 489         gpio_request(GPIO_FN_SDHIWP, NULL);
 490         gpio_request(GPIO_FN_SDHID3, NULL);
 491         gpio_request(GPIO_FN_SDHID2, NULL);
 492         gpio_request(GPIO_FN_SDHID1, NULL);
 493         gpio_request(GPIO_FN_SDHID0, NULL);
 494         gpio_request(GPIO_FN_SDHICMD, NULL);
 495         gpio_request(GPIO_FN_SDHICLK, NULL);
 496
 497         /* Touch Panel */
 498         gpio_request(GPIO_FN_IRQ6, NULL);
 499
 500         /* LCD Panel */
 501 #ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
 502         gpio_request(GPIO_FN_LCDD17, NULL);
 503         gpio_request(GPIO_FN_LCDD16, NULL);
 504         gpio_request(GPIO_FN_LCDD15, NULL);
 505         gpio_request(GPIO_FN_LCDD14, NULL);
 506         gpio_request(GPIO_FN_LCDD13, NULL);
 507         gpio_request(GPIO_FN_LCDD12, NULL);
 508         gpio_request(GPIO_FN_LCDD11, NULL);
 509         gpio_request(GPIO_FN_LCDD10, NULL);
 510         gpio_request(GPIO_FN_LCDD8, NULL);
 511         gpio_request(GPIO_FN_LCDD7, NULL);
 512         gpio_request(GPIO_FN_LCDD6, NULL);
 513         gpio_request(GPIO_FN_LCDD5, NULL);
 514         gpio_request(GPIO_FN_LCDD4, NULL);
 515         gpio_request(GPIO_FN_LCDD3, NULL);
 516         gpio_request(GPIO_FN_LCDD2, NULL);
 517         gpio_request(GPIO_FN_LCDD1, NULL);
 518         gpio_request(GPIO_FN_LCDRS, NULL);
 519         gpio_request(GPIO_FN_LCDCS, NULL);
 520         gpio_request(GPIO_FN_LCDRD, NULL);
 521         gpio_request(GPIO_FN_LCDWR, NULL);
 522         gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
 523         gpio_direction_output(GPIO_PTH2, 1);
 524 #endif
 525 #ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
 526         gpio_request(GPIO_FN_LCDD15, NULL);
 527         gpio_request(GPIO_FN_LCDD14, NULL);
 528         gpio_request(GPIO_FN_LCDD13, NULL);
 529         gpio_request(GPIO_FN_LCDD12, NULL);
 530         gpio_request(GPIO_FN_LCDD11, NULL);
 531         gpio_request(GPIO_FN_LCDD10, NULL);
 532         gpio_request(GPIO_FN_LCDD9, NULL);
 533         gpio_request(GPIO_FN_LCDD8, NULL);
 534         gpio_request(GPIO_FN_LCDD7, NULL);
 535         gpio_request(GPIO_FN_LCDD6, NULL);
 536         gpio_request(GPIO_FN_LCDD5, NULL);
 537         gpio_request(GPIO_FN_LCDD4, NULL);
 538         gpio_request(GPIO_FN_LCDD3, NULL);
 539         gpio_request(GPIO_FN_LCDD2, NULL);
 540         gpio_request(GPIO_FN_LCDD1, NULL);
 541         gpio_request(GPIO_FN_LCDD0, NULL);
 542         gpio_request(GPIO_FN_LCDLCLK, NULL);
 543         gpio_request(GPIO_FN_LCDDCK, NULL);
 544         gpio_request(GPIO_FN_LCDVEPWC, NULL);
 545         gpio_request(GPIO_FN_LCDVCPWC, NULL);
 546         gpio_request(GPIO_FN_LCDVSYN, NULL);
 547         gpio_request(GPIO_FN_LCDHSYN, NULL);
 548         gpio_request(GPIO_FN_LCDDISP, NULL);
 549         gpio_request(GPIO_FN_LCDDON, NULL);
 550 #endif
 551
 552         /* CEU */
 553         gpio_request(GPIO_FN_VIO_CLK2, NULL);
 554         gpio_request(GPIO_FN_VIO_VD2, NULL);
 555         gpio_request(GPIO_FN_VIO_HD2, NULL);
 556         gpio_request(GPIO_FN_VIO_FLD, NULL);
 557         gpio_request(GPIO_FN_VIO_CKO, NULL);
 558         gpio_request(GPIO_FN_VIO_D15, NULL);
 559         gpio_request(GPIO_FN_VIO_D14, NULL);
 560         gpio_request(GPIO_FN_VIO_D13, NULL);
 561         gpio_request(GPIO_FN_VIO_D12, NULL);
 562         gpio_request(GPIO_FN_VIO_D11, NULL);
 563         gpio_request(GPIO_FN_VIO_D10, NULL);
 564         gpio_request(GPIO_FN_VIO_D9, NULL);
 565         gpio_request(GPIO_FN_VIO_D8, NULL);
 566
 567         __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
 568
 569         /* SIU: Port B */
 570         gpio_request(GPIO_FN_SIUBOLR, NULL);
 571         gpio_request(GPIO_FN_SIUBOBT, NULL);
 572         gpio_request(GPIO_FN_SIUBISLD, NULL);
 573         gpio_request(GPIO_FN_SIUBOSLD, NULL);
 574         gpio_request(GPIO_FN_SIUMCKB, NULL);
 575
 576         /*
 577          * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
 578          * output. Need only SIUB, set to output for master mode (table 34.2)
 579          */
 580         __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
 581
 582          /*
 583           * Use 10 MHz VIO_CKO instead of 24 MHz to work around signal quality
 584           * issues on Panel Board V2.1.
 585           */
 586         video_clk = clk_get(NULL, "video_clk");
 587         if (!IS_ERR(video_clk)) {
 588                 clk_set_rate(video_clk, clk_round_rate(video_clk, 10000000));
 589                 clk_put(video_clk);
 590         }
 591
 592         /* Add a clock alias for ov7725 xclk source. */
 593         clk_add_alias(NULL, "0-0021", "video_clk", NULL);
 594
 595         /* Register GPIOs for video sources. */
 596         gpiod_add_lookup_table(&ov7725_gpios);
 597         gpiod_add_lookup_table(&tw9910_gpios);
 598
 599         i2c_register_board_info(0, migor_i2c_devices,
 600                                 ARRAY_SIZE(migor_i2c_devices));
 601
 602         /* Initialize CEU platform device separately to map memory first */
 603         device_initialize(&migor_ceu_device.dev);
 604         arch_setup_pdev_archdata(&migor_ceu_device);
 605         dma_declare_coherent_memory(&migor_ceu_device.dev,
 606                                     ceu_dma_membase, ceu_dma_membase,
 607                                     ceu_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1,
 608                                     DMA_MEMORY_EXCLUSIVE);
 609
 610         platform_device_add(&migor_ceu_device);
 611
 612         return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
 613 }
 614 arch_initcall(migor_devices_setup);
 615
 616 /* Return the board specific boot mode pin configuration */
 617 static int migor_mode_pins(void)
 618 {
 619         /* MD0=1, MD1=1, MD2=0: Clock Mode 3
 620          * MD3=0: 16-bit Area0 Bus Width
 621          * MD5=1: Little Endian
 622          * TSTMD=1, MD8=0: Test Mode Disabled
 623          */
 624         return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
 625 }
 626
 627 /* Reserve a portion of memory for CEU buffers */
 628 static void __init migor_mv_mem_reserve(void)
 629 {
 630         phys_addr_t phys;
 631         phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
 632
 633         phys = memblock_alloc_base(size, PAGE_SIZE, MEMBLOCK_ALLOC_ANYWHERE);
 634         memblock_free(phys, size);
 635         memblock_remove(phys, size);
 636
 637         ceu_dma_membase = phys;
 638 }
 639
 640 /*
 641  * The Machine Vector
 642  */
 643 static struct sh_machine_vector mv_migor __initmv = {
 644         .mv_name                = "Migo-R",
 645         .mv_mode_pins           = migor_mode_pins,
 646         .mv_mem_reserve         = migor_mv_mem_reserve,
 647 };