arch/sh/boards/mach-se/7724/setup.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * linux/arch/sh/boards/se/7724/setup.c
   4  *
   5  * Copyright (C) 2009 Renesas Solutions Corp.
   6  *
   7  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   8  */
   9 #include <asm/clock.h>
  10 #include <asm/heartbeat.h>
  11 #include <asm/io.h>
  12 #include <asm/suspend.h>
  13
  14 #include <cpu/sh7724.h>
  15
  16 #include <linux/delay.h>
  17 #include <linux/device.h>
  18 #include <linux/gpio.h>
  19 #include <linux/init.h>
  20 #include <linux/input.h>
  21 #include <linux/input/sh_keysc.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/memblock.h>
  24 #include <linux/mfd/tmio.h>
  25 #include <linux/mmc/host.h>
  26 #include <linux/mtd/physmap.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/regulator/fixed.h>
  29 #include <linux/regulator/machine.h>
  30 #include <linux/sh_eth.h>
  31 #include <linux/sh_intc.h>
  32 #include <linux/smc91x.h>
  33 #include <linux/usb/r8a66597.h>
  34 #include <linux/videodev2.h>
  35
  36 #include <mach-se/mach/se7724.h>
  37 #include <media/drv-intf/renesas-ceu.h>
  38
  39 #include <sound/sh_fsi.h>
  40 #include <sound/simple_card.h>
  41
  42 #include <video/sh_mobile_lcdc.h>
  43
  44 #define CEU_BUFFER_MEMORY_SIZE          (4 << 20)
  45 static phys_addr_t ceu0_dma_membase;
  46 static phys_addr_t ceu1_dma_membase;
  47
  48 /*
  49  * SWx    1234 5678
  50  * ------------------------------------
  51  * SW31 : 1001 1100    : default
  52  * SW32 : 0111 1111    : use on board flash
  53  *
  54  * SW41 : abxx xxxx  -> a = 0 : Analog  monitor
  55  *                          1 : Digital monitor
  56  *                      b = 0 : VGA
  57  *                          1 : 720p
  58  */
  59
  60 /*
  61  * about 720p
  62  *
  63  * When you use 1280 x 720 lcdc output,
  64  * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
  65  * and change SW41 to use 720p
  66  */
  67
  68 /*
  69  * about sound
  70  *
  71  * This setup.c supports FSI slave mode.
  72  * Please change J20, J21, J22 pin to 1-2 connection.
  73  */
  74
  75 /* Heartbeat */
  76 static struct resource heartbeat_resource = {
  77         .start  = PA_LED,
  78         .end    = PA_LED,
  79         .flags  = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
  80 };
  81
  82 static struct platform_device heartbeat_device = {
  83         .name           = "heartbeat",
  84         .id             = -1,
  85         .num_resources  = 1,
  86         .resource       = &heartbeat_resource,
  87 };
  88
  89 /* LAN91C111 */
  90 static struct smc91x_platdata smc91x_info = {
  91         .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  92 };
  93
  94 static struct resource smc91x_eth_resources[] = {
  95         [0] = {
  96                 .name   = "SMC91C111" ,
  97                 .start  = 0x1a300300,
  98                 .end    = 0x1a30030f,
  99                 .flags  = IORESOURCE_MEM,
 100         },
 101         [1] = {
 102                 .start  = IRQ0_SMC,
 103                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 104         },
 105 };
 106
 107 static struct platform_device smc91x_eth_device = {
 108         .name   = "smc91x",
 109         .num_resources  = ARRAY_SIZE(smc91x_eth_resources),
 110         .resource       = smc91x_eth_resources,
 111         .dev    = {
 112                 .platform_data  = &smc91x_info,
 113         },
 114 };
 115
 116 /* MTD */
 117 static struct mtd_partition nor_flash_partitions[] = {
 118         {
 119                 .name = "uboot",
 120                 .offset = 0,
 121                 .size = (1 * 1024 * 1024),
 122                 .mask_flags = MTD_WRITEABLE,    /* Read-only */
 123         }, {
 124                 .name = "kernel",
 125                 .offset = MTDPART_OFS_APPEND,
 126                 .size = (2 * 1024 * 1024),
 127         }, {
 128                 .name = "free-area",
 129                 .offset = MTDPART_OFS_APPEND,
 130                 .size = MTDPART_SIZ_FULL,
 131         },
 132 };
 133
 134 static struct physmap_flash_data nor_flash_data = {
 135         .width          = 2,
 136         .parts          = nor_flash_partitions,
 137         .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
 138 };
 139
 140 static struct resource nor_flash_resources[] = {
 141         [0] = {
 142                 .name   = "NOR Flash",
 143                 .start  = 0x00000000,
 144                 .end    = 0x01ffffff,
 145                 .flags  = IORESOURCE_MEM,
 146         }
 147 };
 148
 149 static struct platform_device nor_flash_device = {
 150         .name           = "physmap-flash",
 151         .resource       = nor_flash_resources,
 152         .num_resources  = ARRAY_SIZE(nor_flash_resources),
 153         .dev            = {
 154                 .platform_data = &nor_flash_data,
 155         },
 156 };
 157
 158 /* LCDC */
 159 static const struct fb_videomode lcdc_720p_modes[] = {
 160         {
 161                 .name           = "LB070WV1",
 162                 .sync           = 0, /* hsync and vsync are active low */
 163                 .xres           = 1280,
 164                 .yres           = 720,
 165                 .left_margin    = 220,
 166                 .right_margin   = 110,
 167                 .hsync_len      = 40,
 168                 .upper_margin   = 20,
 169                 .lower_margin   = 5,
 170                 .vsync_len      = 5,
 171         },
 172 };
 173
 174 static const struct fb_videomode lcdc_vga_modes[] = {
 175         {
 176                 .name           = "LB070WV1",
 177                 .sync           = 0, /* hsync and vsync are active low */
 178                 .xres           = 640,
 179                 .yres           = 480,
 180                 .left_margin    = 105,
 181                 .right_margin   = 50,
 182                 .hsync_len      = 96,
 183                 .upper_margin   = 33,
 184                 .lower_margin   = 10,
 185                 .vsync_len      = 2,
 186         },
 187 };
 188
 189 static struct sh_mobile_lcdc_info lcdc_info = {
 190         .clock_source = LCDC_CLK_EXTERNAL,
 191         .ch[0] = {
 192                 .chan = LCDC_CHAN_MAINLCD,
 193                 .fourcc = V4L2_PIX_FMT_RGB565,
 194                 .clock_divider = 1,
 195                 .panel_cfg = { /* 7.0 inch */
 196                         .width = 152,
 197                         .height = 91,
 198                 },
 199         }
 200 };
 201
 202 static struct resource lcdc_resources[] = {
 203         [0] = {
 204                 .name   = "LCDC",
 205                 .start  = 0xfe940000,
 206                 .end    = 0xfe942fff,
 207                 .flags  = IORESOURCE_MEM,
 208         },
 209         [1] = {
 210                 .start  = evt2irq(0xf40),
 211                 .flags  = IORESOURCE_IRQ,
 212         },
 213 };
 214
 215 static struct platform_device lcdc_device = {
 216         .name           = "sh_mobile_lcdc_fb",
 217         .num_resources  = ARRAY_SIZE(lcdc_resources),
 218         .resource       = lcdc_resources,
 219         .dev            = {
 220                 .platform_data  = &lcdc_info,
 221         },
 222 };
 223
 224 /* CEU0 */
 225 static struct ceu_platform_data ceu0_pdata = {
 226         .num_subdevs = 0,
 227 };
 228
 229 static struct resource ceu0_resources[] = {
 230         [0] = {
 231                 .name   = "CEU0",
 232                 .start  = 0xfe910000,
 233                 .end    = 0xfe91009f,
 234                 .flags  = IORESOURCE_MEM,
 235         },
 236         [1] = {
 237                 .start  = evt2irq(0x880),
 238                 .flags  = IORESOURCE_IRQ,
 239         },
 240 };
 241
 242 static struct platform_device ceu0_device = {
 243         .name           = "renesas-ceu",
 244         .id             = 0, /* "ceu.0" clock */
 245         .num_resources  = ARRAY_SIZE(ceu0_resources),
 246         .resource       = ceu0_resources,
 247         .dev    = {
 248                 .platform_data  = &ceu0_pdata,
 249         },
 250 };
 251
 252 /* CEU1 */
 253 static struct ceu_platform_data ceu1_pdata = {
 254         .num_subdevs = 0,
 255 };
 256
 257 static struct resource ceu1_resources[] = {
 258         [0] = {
 259                 .name   = "CEU1",
 260                 .start  = 0xfe914000,
 261                 .end    = 0xfe91409f,
 262                 .flags  = IORESOURCE_MEM,
 263         },
 264         [1] = {
 265                 .start  = evt2irq(0x9e0),
 266                 .flags  = IORESOURCE_IRQ,
 267         },
 268 };
 269
 270 static struct platform_device ceu1_device = {
 271         .name           = "renesas-ceu",
 272         .id             = 1, /* "ceu.1" clock */
 273         .num_resources  = ARRAY_SIZE(ceu1_resources),
 274         .resource       = ceu1_resources,
 275         .dev    = {
 276                 .platform_data  = &ceu1_pdata,
 277         },
 278 };
 279
 280 /* FSI */
 281 /* change J20, J21, J22 pin to 1-2 connection to use slave mode */
 282 static struct resource fsi_resources[] = {
 283         [0] = {
 284                 .name   = "FSI",
 285                 .start  = 0xFE3C0000,
 286                 .end    = 0xFE3C021d,
 287                 .flags  = IORESOURCE_MEM,
 288         },
 289         [1] = {
 290                 .start  = evt2irq(0xf80),
 291                 .flags  = IORESOURCE_IRQ,
 292         },
 293 };
 294
 295 static struct platform_device fsi_device = {
 296         .name           = "sh_fsi",
 297         .id             = 0,
 298         .num_resources  = ARRAY_SIZE(fsi_resources),
 299         .resource       = fsi_resources,
 300 };
 301
 302 static struct asoc_simple_card_info fsi_ak4642_info = {
 303         .name           = "AK4642",
 304         .card           = "FSIA-AK4642",
 305         .codec          = "ak4642-codec.0-0012",
 306         .platform       = "sh_fsi.0",
 307         .daifmt         = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
 308         .cpu_dai = {
 309                 .name   = "fsia-dai",
 310         },
 311         .codec_dai = {
 312                 .name   = "ak4642-hifi",
 313                 .sysclk = 11289600,
 314         },
 315 };
 316
 317 static struct platform_device fsi_ak4642_device = {
 318         .name   = "asoc-simple-card",
 319         .dev    = {
 320                 .platform_data  = &fsi_ak4642_info,
 321         },
 322 };
 323
 324 /* KEYSC in SoC (Needs SW33-2 set to ON) */
 325 static struct sh_keysc_info keysc_info = {
 326         .mode = SH_KEYSC_MODE_1,
 327         .scan_timing = 3,
 328         .delay = 50,
 329         .keycodes = {
 330                 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
 331                 KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
 332                 KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
 333                 KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
 334                 KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
 335                 KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
 336         },
 337 };
 338
 339 static struct resource keysc_resources[] = {
 340         [0] = {
 341                 .name   = "KEYSC",
 342                 .start  = 0x044b0000,
 343                 .end    = 0x044b000f,
 344                 .flags  = IORESOURCE_MEM,
 345         },
 346         [1] = {
 347                 .start  = evt2irq(0xbe0),
 348                 .flags  = IORESOURCE_IRQ,
 349         },
 350 };
 351
 352 static struct platform_device keysc_device = {
 353         .name           = "sh_keysc",
 354         .id             = 0, /* "keysc0" clock */
 355         .num_resources  = ARRAY_SIZE(keysc_resources),
 356         .resource       = keysc_resources,
 357         .dev    = {
 358                 .platform_data  = &keysc_info,
 359         },
 360 };
 361
 362 /* SH Eth */
 363 static struct resource sh_eth_resources[] = {
 364         [0] = {
 365                 .start = SH_ETH_ADDR,
 366                 .end   = SH_ETH_ADDR + 0x1FC - 1,
 367                 .flags = IORESOURCE_MEM,
 368         },
 369         [1] = {
 370                 .start = evt2irq(0xd60),
 371                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 372         },
 373 };
 374
 375 static struct sh_eth_plat_data sh_eth_plat = {
 376         .phy = 0x1f, /* SMSC LAN8187 */
 377         .phy_interface = PHY_INTERFACE_MODE_MII,
 378 };
 379
 380 static struct platform_device sh_eth_device = {
 381         .name = "sh7724-ether",
 382         .id = 0,
 383         .dev = {
 384                 .platform_data = &sh_eth_plat,
 385         },
 386         .num_resources = ARRAY_SIZE(sh_eth_resources),
 387         .resource = sh_eth_resources,
 388 };
 389
 390 static struct r8a66597_platdata sh7724_usb0_host_data = {
 391         .on_chip = 1,
 392 };
 393
 394 static struct resource sh7724_usb0_host_resources[] = {
 395         [0] = {
 396                 .start  = 0xa4d80000,
 397                 .end    = 0xa4d80124 - 1,
 398                 .flags  = IORESOURCE_MEM,
 399         },
 400         [1] = {
 401                 .start  = evt2irq(0xa20),
 402                 .end    = evt2irq(0xa20),
 403                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
 404         },
 405 };
 406
 407 static struct platform_device sh7724_usb0_host_device = {
 408         .name           = "r8a66597_hcd",
 409         .id             = 0,
 410         .dev = {
 411                 .dma_mask               = NULL,         /*  not use dma */
 412                 .coherent_dma_mask      = 0xffffffff,
 413                 .platform_data          = &sh7724_usb0_host_data,
 414         },
 415         .num_resources  = ARRAY_SIZE(sh7724_usb0_host_resources),
 416         .resource       = sh7724_usb0_host_resources,
 417 };
 418
 419 static struct r8a66597_platdata sh7724_usb1_gadget_data = {
 420         .on_chip = 1,
 421 };
 422
 423 static struct resource sh7724_usb1_gadget_resources[] = {
 424         [0] = {
 425                 .start  = 0xa4d90000,
 426                 .end    = 0xa4d90123,
 427                 .flags  = IORESOURCE_MEM,
 428         },
 429         [1] = {
 430                 .start  = evt2irq(0xa40),
 431                 .end    = evt2irq(0xa40),
 432                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
 433         },
 434 };
 435
 436 static struct platform_device sh7724_usb1_gadget_device = {
 437         .name           = "r8a66597_udc",
 438         .id             = 1, /* USB1 */
 439         .dev = {
 440                 .dma_mask               = NULL,         /*  not use dma */
 441                 .coherent_dma_mask      = 0xffffffff,
 442                 .platform_data          = &sh7724_usb1_gadget_data,
 443         },
 444         .num_resources  = ARRAY_SIZE(sh7724_usb1_gadget_resources),
 445         .resource       = sh7724_usb1_gadget_resources,
 446 };
 447
 448 /* Fixed 3.3V regulator to be used by SDHI0, SDHI1 */
 449 static struct regulator_consumer_supply fixed3v3_power_consumers[] =
 450 {
 451         REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
 452         REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
 453         REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
 454         REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
 455 };
 456
 457 static struct resource sdhi0_cn7_resources[] = {
 458         [0] = {
 459                 .name   = "SDHI0",
 460                 .start  = 0x04ce0000,
 461                 .end    = 0x04ce00ff,
 462                 .flags  = IORESOURCE_MEM,
 463         },
 464         [1] = {
 465                 .start  = evt2irq(0xe80),
 466                 .flags  = IORESOURCE_IRQ,
 467         },
 468 };
 469
 470 static struct tmio_mmc_data sh7724_sdhi0_data = {
 471         .chan_priv_tx   = (void *)SHDMA_SLAVE_SDHI0_TX,
 472         .chan_priv_rx   = (void *)SHDMA_SLAVE_SDHI0_RX,
 473         .capabilities   = MMC_CAP_SDIO_IRQ,
 474 };
 475
 476 static struct platform_device sdhi0_cn7_device = {
 477         .name           = "sh_mobile_sdhi",
 478         .id             = 0,
 479         .num_resources  = ARRAY_SIZE(sdhi0_cn7_resources),
 480         .resource       = sdhi0_cn7_resources,
 481         .dev = {
 482                 .platform_data  = &sh7724_sdhi0_data,
 483         },
 484 };
 485
 486 static struct resource sdhi1_cn8_resources[] = {
 487         [0] = {
 488                 .name   = "SDHI1",
 489                 .start  = 0x04cf0000,
 490                 .end    = 0x04cf00ff,
 491                 .flags  = IORESOURCE_MEM,
 492         },
 493         [1] = {
 494                 .start  = evt2irq(0x4e0),
 495                 .flags  = IORESOURCE_IRQ,
 496         },
 497 };
 498
 499 static struct tmio_mmc_data sh7724_sdhi1_data = {
 500         .chan_priv_tx   = (void *)SHDMA_SLAVE_SDHI1_TX,
 501         .chan_priv_rx   = (void *)SHDMA_SLAVE_SDHI1_RX,
 502         .capabilities   = MMC_CAP_SDIO_IRQ,
 503 };
 504
 505 static struct platform_device sdhi1_cn8_device = {
 506         .name           = "sh_mobile_sdhi",
 507         .id             = 1,
 508         .num_resources  = ARRAY_SIZE(sdhi1_cn8_resources),
 509         .resource       = sdhi1_cn8_resources,
 510         .dev = {
 511                 .platform_data  = &sh7724_sdhi1_data,
 512         },
 513 };
 514
 515 /* IrDA */
 516 static struct resource irda_resources[] = {
 517         [0] = {
 518                 .name   = "IrDA",
 519                 .start  = 0xA45D0000,
 520                 .end    = 0xA45D0049,
 521                 .flags  = IORESOURCE_MEM,
 522         },
 523         [1] = {
 524                 .start  = evt2irq(0x480),
 525                 .flags  = IORESOURCE_IRQ,
 526         },
 527 };
 528
 529 static struct platform_device irda_device = {
 530         .name           = "sh_sir",
 531         .num_resources  = ARRAY_SIZE(irda_resources),
 532         .resource       = irda_resources,
 533 };
 534
 535 #include <media/i2c/ak881x.h>
 536 #include <media/drv-intf/sh_vou.h>
 537
 538 static struct ak881x_pdata ak881x_pdata = {
 539         .flags = AK881X_IF_MODE_SLAVE,
 540 };
 541
 542 static struct i2c_board_info ak8813 = {
 543         /* With open J18 jumper address is 0x21 */
 544         I2C_BOARD_INFO("ak8813", 0x20),
 545         .platform_data = &ak881x_pdata,
 546 };
 547
 548 static struct sh_vou_pdata sh_vou_pdata = {
 549         .bus_fmt        = SH_VOU_BUS_8BIT,
 550         .flags          = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
 551         .board_info     = &ak8813,
 552         .i2c_adap       = 0,
 553 };
 554
 555 static struct resource sh_vou_resources[] = {
 556         [0] = {
 557                 .start  = 0xfe960000,
 558                 .end    = 0xfe962043,
 559                 .flags  = IORESOURCE_MEM,
 560         },
 561         [1] = {
 562                 .start  = evt2irq(0x8e0),
 563                 .flags  = IORESOURCE_IRQ,
 564         },
 565 };
 566
 567 static struct platform_device vou_device = {
 568         .name           = "sh-vou",
 569         .id             = -1,
 570         .num_resources  = ARRAY_SIZE(sh_vou_resources),
 571         .resource       = sh_vou_resources,
 572         .dev            = {
 573                 .platform_data  = &sh_vou_pdata,
 574         },
 575 };
 576
 577 static struct platform_device *ms7724se_ceu_devices[] __initdata = {
 578         &ceu0_device,
 579         &ceu1_device,
 580 };
 581
 582 static struct platform_device *ms7724se_devices[] __initdata = {
 583         &heartbeat_device,
 584         &smc91x_eth_device,
 585         &lcdc_device,
 586         &nor_flash_device,
 587         &keysc_device,
 588         &sh_eth_device,
 589         &sh7724_usb0_host_device,
 590         &sh7724_usb1_gadget_device,
 591         &fsi_device,
 592         &fsi_ak4642_device,
 593         &sdhi0_cn7_device,
 594         &sdhi1_cn8_device,
 595         &irda_device,
 596         &vou_device,
 597 };
 598
 599 /* I2C device */
 600 static struct i2c_board_info i2c0_devices[] = {
 601         {
 602                 I2C_BOARD_INFO("ak4642", 0x12),
 603         },
 604 };
 605
 606 #define EEPROM_OP   0xBA206000
 607 #define EEPROM_ADR  0xBA206004
 608 #define EEPROM_DATA 0xBA20600C
 609 #define EEPROM_STAT 0xBA206010
 610 #define EEPROM_STRT 0xBA206014
 611
 612 static int __init sh_eth_is_eeprom_ready(void)
 613 {
 614         int t = 10000;
 615
 616         while (t--) {
 617                 if (!__raw_readw(EEPROM_STAT))
 618                         return 1;
 619                 udelay(1);
 620         }
 621
 622         printk(KERN_ERR "ms7724se can not access to eeprom\n");
 623         return 0;
 624 }
 625
 626 static void __init sh_eth_init(void)
 627 {
 628         int i;
 629         u16 mac;
 630
 631         /* check EEPROM status */
 632         if (!sh_eth_is_eeprom_ready())
 633                 return;
 634
 635         /* read MAC addr from EEPROM */
 636         for (i = 0 ; i < 3 ; i++) {
 637                 __raw_writew(0x0, EEPROM_OP); /* read */
 638                 __raw_writew(i*2, EEPROM_ADR);
 639                 __raw_writew(0x1, EEPROM_STRT);
 640                 if (!sh_eth_is_eeprom_ready())
 641                         return;
 642
 643                 mac = __raw_readw(EEPROM_DATA);
 644                 sh_eth_plat.mac_addr[i << 1] = mac & 0xff;
 645                 sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8;
 646         }
 647 }
 648
 649 #define SW4140    0xBA201000
 650 #define FPGA_OUT  0xBA200400
 651 #define PORT_HIZA 0xA4050158
 652 #define PORT_MSELCRB 0xA4050182
 653
 654 #define SW41_A    0x0100
 655 #define SW41_B    0x0200
 656 #define SW41_C    0x0400
 657 #define SW41_D    0x0800
 658 #define SW41_E    0x1000
 659 #define SW41_F    0x2000
 660 #define SW41_G    0x4000
 661 #define SW41_H    0x8000
 662
 663 extern char ms7724se_sdram_enter_start;
 664 extern char ms7724se_sdram_enter_end;
 665 extern char ms7724se_sdram_leave_start;
 666 extern char ms7724se_sdram_leave_end;
 667
 668 static int __init arch_setup(void)
 669 {
 670         /* enable I2C device */
 671         i2c_register_board_info(0, i2c0_devices,
 672                                 ARRAY_SIZE(i2c0_devices));
 673         return 0;
 674 }
 675 arch_initcall(arch_setup);
 676
 677 static int __init devices_setup(void)
 678 {
 679         u16 sw = __raw_readw(SW4140); /* select camera, monitor */
 680         struct clk *clk;
 681         u16 fpga_out;
 682
 683         /* register board specific self-refresh code */
 684         sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
 685                                         SUSP_SH_RSTANDBY,
 686                                         &ms7724se_sdram_enter_start,
 687                                         &ms7724se_sdram_enter_end,
 688                                         &ms7724se_sdram_leave_start,
 689                                         &ms7724se_sdram_leave_end);
 690
 691         regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
 692                                      ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
 693
 694         /* Reset Release */
 695         fpga_out = __raw_readw(FPGA_OUT);
 696         /* bit4: NTSC_PDN, bit5: NTSC_RESET */
 697         fpga_out &= ~((1 << 1)  | /* LAN */
 698                       (1 << 4)  | /* AK8813 PDN */
 699                       (1 << 5)  | /* AK8813 RESET */
 700                       (1 << 6)  | /* VIDEO DAC */
 701                       (1 << 7)  | /* AK4643 */
 702                       (1 << 8)  | /* IrDA */
 703                       (1 << 12) | /* USB0 */
 704                       (1 << 14)); /* RMII */
 705         __raw_writew(fpga_out | (1 << 4), FPGA_OUT);
 706
 707         udelay(10);
 708
 709         /* AK8813 RESET */
 710         __raw_writew(fpga_out | (1 << 5), FPGA_OUT);
 711
 712         udelay(10);
 713
 714         __raw_writew(fpga_out, FPGA_OUT);
 715
 716         /* turn on USB clocks, use external clock */
 717         __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
 718
 719         /* Let LED9 show STATUS2 */
 720         gpio_request(GPIO_FN_STATUS2, NULL);
 721
 722         /* Lit LED10 show STATUS0 */
 723         gpio_request(GPIO_FN_STATUS0, NULL);
 724
 725         /* Lit LED11 show PDSTATUS */
 726         gpio_request(GPIO_FN_PDSTATUS, NULL);
 727
 728         /* enable USB0 port */
 729         __raw_writew(0x0600, 0xa40501d4);
 730
 731         /* enable USB1 port */
 732         __raw_writew(0x0600, 0xa4050192);
 733
 734         /* enable IRQ 0,1,2 */
 735         gpio_request(GPIO_FN_INTC_IRQ0, NULL);
 736         gpio_request(GPIO_FN_INTC_IRQ1, NULL);
 737         gpio_request(GPIO_FN_INTC_IRQ2, NULL);
 738
 739         /* enable SCIFA3 */
 740         gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
 741         gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
 742         gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
 743         gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
 744         gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
 745
 746         /* enable LCDC */
 747         gpio_request(GPIO_FN_LCDD23,   NULL);
 748         gpio_request(GPIO_FN_LCDD22,   NULL);
 749         gpio_request(GPIO_FN_LCDD21,   NULL);
 750         gpio_request(GPIO_FN_LCDD20,   NULL);
 751         gpio_request(GPIO_FN_LCDD19,   NULL);
 752         gpio_request(GPIO_FN_LCDD18,   NULL);
 753         gpio_request(GPIO_FN_LCDD17,   NULL);
 754         gpio_request(GPIO_FN_LCDD16,   NULL);
 755         gpio_request(GPIO_FN_LCDD15,   NULL);
 756         gpio_request(GPIO_FN_LCDD14,   NULL);
 757         gpio_request(GPIO_FN_LCDD13,   NULL);
 758         gpio_request(GPIO_FN_LCDD12,   NULL);
 759         gpio_request(GPIO_FN_LCDD11,   NULL);
 760         gpio_request(GPIO_FN_LCDD10,   NULL);
 761         gpio_request(GPIO_FN_LCDD9,    NULL);
 762         gpio_request(GPIO_FN_LCDD8,    NULL);
 763         gpio_request(GPIO_FN_LCDD7,    NULL);
 764         gpio_request(GPIO_FN_LCDD6,    NULL);
 765         gpio_request(GPIO_FN_LCDD5,    NULL);
 766         gpio_request(GPIO_FN_LCDD4,    NULL);
 767         gpio_request(GPIO_FN_LCDD3,    NULL);
 768         gpio_request(GPIO_FN_LCDD2,    NULL);
 769         gpio_request(GPIO_FN_LCDD1,    NULL);
 770         gpio_request(GPIO_FN_LCDD0,    NULL);
 771         gpio_request(GPIO_FN_LCDDISP,  NULL);
 772         gpio_request(GPIO_FN_LCDHSYN,  NULL);
 773         gpio_request(GPIO_FN_LCDDCK,   NULL);
 774         gpio_request(GPIO_FN_LCDVSYN,  NULL);
 775         gpio_request(GPIO_FN_LCDDON,   NULL);
 776         gpio_request(GPIO_FN_LCDVEPWC, NULL);
 777         gpio_request(GPIO_FN_LCDVCPWC, NULL);
 778         gpio_request(GPIO_FN_LCDRD,    NULL);
 779         gpio_request(GPIO_FN_LCDLCLK,  NULL);
 780         __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
 781
 782         /* enable CEU0 */
 783         gpio_request(GPIO_FN_VIO0_D15, NULL);
 784         gpio_request(GPIO_FN_VIO0_D14, NULL);
 785         gpio_request(GPIO_FN_VIO0_D13, NULL);
 786         gpio_request(GPIO_FN_VIO0_D12, NULL);
 787         gpio_request(GPIO_FN_VIO0_D11, NULL);
 788         gpio_request(GPIO_FN_VIO0_D10, NULL);
 789         gpio_request(GPIO_FN_VIO0_D9,  NULL);
 790         gpio_request(GPIO_FN_VIO0_D8,  NULL);
 791         gpio_request(GPIO_FN_VIO0_D7,  NULL);
 792         gpio_request(GPIO_FN_VIO0_D6,  NULL);
 793         gpio_request(GPIO_FN_VIO0_D5,  NULL);
 794         gpio_request(GPIO_FN_VIO0_D4,  NULL);
 795         gpio_request(GPIO_FN_VIO0_D3,  NULL);
 796         gpio_request(GPIO_FN_VIO0_D2,  NULL);
 797         gpio_request(GPIO_FN_VIO0_D1,  NULL);
 798         gpio_request(GPIO_FN_VIO0_D0,  NULL);
 799         gpio_request(GPIO_FN_VIO0_VD,  NULL);
 800         gpio_request(GPIO_FN_VIO0_CLK, NULL);
 801         gpio_request(GPIO_FN_VIO0_FLD, NULL);
 802         gpio_request(GPIO_FN_VIO0_HD,  NULL);
 803
 804         /* enable CEU1 */
 805         gpio_request(GPIO_FN_VIO1_D7,  NULL);
 806         gpio_request(GPIO_FN_VIO1_D6,  NULL);
 807         gpio_request(GPIO_FN_VIO1_D5,  NULL);
 808         gpio_request(GPIO_FN_VIO1_D4,  NULL);
 809         gpio_request(GPIO_FN_VIO1_D3,  NULL);
 810         gpio_request(GPIO_FN_VIO1_D2,  NULL);
 811         gpio_request(GPIO_FN_VIO1_D1,  NULL);
 812         gpio_request(GPIO_FN_VIO1_D0,  NULL);
 813         gpio_request(GPIO_FN_VIO1_FLD, NULL);
 814         gpio_request(GPIO_FN_VIO1_HD,  NULL);
 815         gpio_request(GPIO_FN_VIO1_VD,  NULL);
 816         gpio_request(GPIO_FN_VIO1_CLK, NULL);
 817
 818         /* KEYSC */
 819         gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
 820         gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
 821         gpio_request(GPIO_FN_KEYIN4,      NULL);
 822         gpio_request(GPIO_FN_KEYIN3,      NULL);
 823         gpio_request(GPIO_FN_KEYIN2,      NULL);
 824         gpio_request(GPIO_FN_KEYIN1,      NULL);
 825         gpio_request(GPIO_FN_KEYIN0,      NULL);
 826         gpio_request(GPIO_FN_KEYOUT3,     NULL);
 827         gpio_request(GPIO_FN_KEYOUT2,     NULL);
 828         gpio_request(GPIO_FN_KEYOUT1,     NULL);
 829         gpio_request(GPIO_FN_KEYOUT0,     NULL);
 830
 831         /* enable FSI */
 832         gpio_request(GPIO_FN_FSIMCKA,    NULL);
 833         gpio_request(GPIO_FN_FSIIASD,    NULL);
 834         gpio_request(GPIO_FN_FSIOASD,    NULL);
 835         gpio_request(GPIO_FN_FSIIABCK,   NULL);
 836         gpio_request(GPIO_FN_FSIIALRCK,  NULL);
 837         gpio_request(GPIO_FN_FSIOABCK,   NULL);
 838         gpio_request(GPIO_FN_FSIOALRCK,  NULL);
 839         gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
 840
 841         /* set SPU2 clock to 83.4 MHz */
 842         clk = clk_get(NULL, "spu_clk");
 843         if (!IS_ERR(clk)) {
 844                 clk_set_rate(clk, clk_round_rate(clk, 83333333));
 845                 clk_put(clk);
 846         }
 847
 848         /* change parent of FSI A */
 849         clk = clk_get(NULL, "fsia_clk");
 850         if (!IS_ERR(clk)) {
 851                 /* 48kHz dummy clock was used to make sure 1/1 divide */
 852                 clk_set_rate(&sh7724_fsimcka_clk, 48000);
 853                 clk_set_parent(clk, &sh7724_fsimcka_clk);
 854                 clk_set_rate(clk, 48000);
 855                 clk_put(clk);
 856         }
 857
 858         /* SDHI0 connected to cn7 */
 859         gpio_request(GPIO_FN_SDHI0CD, NULL);
 860         gpio_request(GPIO_FN_SDHI0WP, NULL);
 861         gpio_request(GPIO_FN_SDHI0D3, NULL);
 862         gpio_request(GPIO_FN_SDHI0D2, NULL);
 863         gpio_request(GPIO_FN_SDHI0D1, NULL);
 864         gpio_request(GPIO_FN_SDHI0D0, NULL);
 865         gpio_request(GPIO_FN_SDHI0CMD, NULL);
 866         gpio_request(GPIO_FN_SDHI0CLK, NULL);
 867
 868         /* SDHI1 connected to cn8 */
 869         gpio_request(GPIO_FN_SDHI1CD, NULL);
 870         gpio_request(GPIO_FN_SDHI1WP, NULL);
 871         gpio_request(GPIO_FN_SDHI1D3, NULL);
 872         gpio_request(GPIO_FN_SDHI1D2, NULL);
 873         gpio_request(GPIO_FN_SDHI1D1, NULL);
 874         gpio_request(GPIO_FN_SDHI1D0, NULL);
 875         gpio_request(GPIO_FN_SDHI1CMD, NULL);
 876         gpio_request(GPIO_FN_SDHI1CLK, NULL);
 877
 878         /* enable IrDA */
 879         gpio_request(GPIO_FN_IRDA_OUT, NULL);
 880         gpio_request(GPIO_FN_IRDA_IN,  NULL);
 881
 882         /*
 883          * enable SH-Eth
 884          *
 885          * please remove J33 pin from your board !!
 886          *
 887          * ms7724 board should not use GPIO_FN_LNKSTA pin
 888          * So, This time PTX5 is set to input pin
 889          */
 890         gpio_request(GPIO_FN_RMII_RXD0,    NULL);
 891         gpio_request(GPIO_FN_RMII_RXD1,    NULL);
 892         gpio_request(GPIO_FN_RMII_TXD0,    NULL);
 893         gpio_request(GPIO_FN_RMII_TXD1,    NULL);
 894         gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
 895         gpio_request(GPIO_FN_RMII_TX_EN,   NULL);
 896         gpio_request(GPIO_FN_RMII_RX_ER,   NULL);
 897         gpio_request(GPIO_FN_RMII_CRS_DV,  NULL);
 898         gpio_request(GPIO_FN_MDIO,         NULL);
 899         gpio_request(GPIO_FN_MDC,          NULL);
 900         gpio_request(GPIO_PTX5, NULL);
 901         gpio_direction_input(GPIO_PTX5);
 902         sh_eth_init();
 903
 904         if (sw & SW41_B) {
 905                 /* 720p */
 906                 lcdc_info.ch[0].lcd_modes = lcdc_720p_modes;
 907                 lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_720p_modes);
 908         } else {
 909                 /* VGA */
 910                 lcdc_info.ch[0].lcd_modes = lcdc_vga_modes;
 911                 lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_vga_modes);
 912         }
 913
 914         if (sw & SW41_A) {
 915                 /* Digital monitor */
 916                 lcdc_info.ch[0].interface_type = RGB18;
 917                 lcdc_info.ch[0].flags          = 0;
 918         } else {
 919                 /* Analog monitor */
 920                 lcdc_info.ch[0].interface_type = RGB24;
 921                 lcdc_info.ch[0].flags          = LCDC_FLAGS_DWPOL;
 922         }
 923
 924         /* VOU */
 925         gpio_request(GPIO_FN_DV_D15, NULL);
 926         gpio_request(GPIO_FN_DV_D14, NULL);
 927         gpio_request(GPIO_FN_DV_D13, NULL);
 928         gpio_request(GPIO_FN_DV_D12, NULL);
 929         gpio_request(GPIO_FN_DV_D11, NULL);
 930         gpio_request(GPIO_FN_DV_D10, NULL);
 931         gpio_request(GPIO_FN_DV_D9, NULL);
 932         gpio_request(GPIO_FN_DV_D8, NULL);
 933         gpio_request(GPIO_FN_DV_CLKI, NULL);
 934         gpio_request(GPIO_FN_DV_CLK, NULL);
 935         gpio_request(GPIO_FN_DV_VSYNC, NULL);
 936         gpio_request(GPIO_FN_DV_HSYNC, NULL);
 937
 938         /* Initialize CEU platform devices separately to map memory first */
 939         device_initialize(&ms7724se_ceu_devices[0]->dev);
 940         arch_setup_pdev_archdata(ms7724se_ceu_devices[0]);
 941         dma_declare_coherent_memory(&ms7724se_ceu_devices[0]->dev,
 942                                     ceu0_dma_membase, ceu0_dma_membase,
 943                                     ceu0_dma_membase +
 944                                     CEU_BUFFER_MEMORY_SIZE - 1,
 945                                     DMA_MEMORY_EXCLUSIVE);
 946         platform_device_add(ms7724se_ceu_devices[0]);
 947
 948         device_initialize(&ms7724se_ceu_devices[1]->dev);
 949         arch_setup_pdev_archdata(ms7724se_ceu_devices[1]);
 950         dma_declare_coherent_memory(&ms7724se_ceu_devices[1]->dev,
 951                                     ceu1_dma_membase, ceu1_dma_membase,
 952                                     ceu1_dma_membase +
 953                                     CEU_BUFFER_MEMORY_SIZE - 1,
 954                                     DMA_MEMORY_EXCLUSIVE);
 955         platform_device_add(ms7724se_ceu_devices[1]);
 956
 957         return platform_add_devices(ms7724se_devices,
 958                                     ARRAY_SIZE(ms7724se_devices));
 959 }
 960 device_initcall(devices_setup);
 961
 962 /* Reserve a portion of memory for CEU 0 and CEU 1 buffers */
 963 static void __init ms7724se_mv_mem_reserve(void)
 964 {
 965         phys_addr_t phys;
 966         phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
 967
 968         phys = memblock_alloc_base(size, PAGE_SIZE, MEMBLOCK_ALLOC_ANYWHERE);
 969         memblock_free(phys, size);
 970         memblock_remove(phys, size);
 971         ceu0_dma_membase = phys;
 972
 973         phys = memblock_alloc_base(size, PAGE_SIZE, MEMBLOCK_ALLOC_ANYWHERE);
 974         memblock_free(phys, size);
 975         memblock_remove(phys, size);
 976         ceu1_dma_membase = phys;
 977 }
 978
 979 static struct sh_machine_vector mv_ms7724se __initmv = {
 980         .mv_name        = "ms7724se",
 981         .mv_init_irq    = init_se7724_IRQ,
 982         .mv_mem_reserve = ms7724se_mv_mem_reserve,
 983 };