1 #include <linux/perf_event.h>
2 #include <linux/export.h>
3 #include <linux/types.h>
4 #include <linux/init.h>
5 #include <linux/slab.h>
6 #include <asm/apicdef.h>
8 #include "../perf_event.h"
10 static __initconst
const u64 amd_hw_cache_event_ids
11 [PERF_COUNT_HW_CACHE_MAX
]
12 [PERF_COUNT_HW_CACHE_OP_MAX
]
13 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
17 [ C(RESULT_ACCESS
) ] = 0x0040, /* Data Cache Accesses */
18 [ C(RESULT_MISS
) ] = 0x0141, /* Data Cache Misses */
21 [ C(RESULT_ACCESS
) ] = 0,
22 [ C(RESULT_MISS
) ] = 0,
24 [ C(OP_PREFETCH
) ] = {
25 [ C(RESULT_ACCESS
) ] = 0x0267, /* Data Prefetcher :attempts */
26 [ C(RESULT_MISS
) ] = 0x0167, /* Data Prefetcher :cancelled */
31 [ C(RESULT_ACCESS
) ] = 0x0080, /* Instruction cache fetches */
32 [ C(RESULT_MISS
) ] = 0x0081, /* Instruction cache misses */
35 [ C(RESULT_ACCESS
) ] = -1,
36 [ C(RESULT_MISS
) ] = -1,
38 [ C(OP_PREFETCH
) ] = {
39 [ C(RESULT_ACCESS
) ] = 0x014B, /* Prefetch Instructions :Load */
40 [ C(RESULT_MISS
) ] = 0,
45 [ C(RESULT_ACCESS
) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
46 [ C(RESULT_MISS
) ] = 0x037E, /* L2 Cache Misses : IC+DC */
49 [ C(RESULT_ACCESS
) ] = 0x017F, /* L2 Fill/Writeback */
50 [ C(RESULT_MISS
) ] = 0,
52 [ C(OP_PREFETCH
) ] = {
53 [ C(RESULT_ACCESS
) ] = 0,
54 [ C(RESULT_MISS
) ] = 0,
59 [ C(RESULT_ACCESS
) ] = 0x0040, /* Data Cache Accesses */
60 [ C(RESULT_MISS
) ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */
63 [ C(RESULT_ACCESS
) ] = 0,
64 [ C(RESULT_MISS
) ] = 0,
66 [ C(OP_PREFETCH
) ] = {
67 [ C(RESULT_ACCESS
) ] = 0,
68 [ C(RESULT_MISS
) ] = 0,
73 [ C(RESULT_ACCESS
) ] = 0x0080, /* Instruction fecthes */
74 [ C(RESULT_MISS
) ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */
77 [ C(RESULT_ACCESS
) ] = -1,
78 [ C(RESULT_MISS
) ] = -1,
80 [ C(OP_PREFETCH
) ] = {
81 [ C(RESULT_ACCESS
) ] = -1,
82 [ C(RESULT_MISS
) ] = -1,
87 [ C(RESULT_ACCESS
) ] = 0x00c2, /* Retired Branch Instr. */
88 [ C(RESULT_MISS
) ] = 0x00c3, /* Retired Mispredicted BI */
91 [ C(RESULT_ACCESS
) ] = -1,
92 [ C(RESULT_MISS
) ] = -1,
94 [ C(OP_PREFETCH
) ] = {
95 [ C(RESULT_ACCESS
) ] = -1,
96 [ C(RESULT_MISS
) ] = -1,
101 [ C(RESULT_ACCESS
) ] = 0xb8e9, /* CPU Request to Memory, l+r */
102 [ C(RESULT_MISS
) ] = 0x98e9, /* CPU Request to Memory, r */
105 [ C(RESULT_ACCESS
) ] = -1,
106 [ C(RESULT_MISS
) ] = -1,
108 [ C(OP_PREFETCH
) ] = {
109 [ C(RESULT_ACCESS
) ] = -1,
110 [ C(RESULT_MISS
) ] = -1,
116 * AMD Performance Monitor K7 and later.
118 static const u64 amd_perfmon_event_map
[PERF_COUNT_HW_MAX
] =
120 [PERF_COUNT_HW_CPU_CYCLES
] = 0x0076,
121 [PERF_COUNT_HW_INSTRUCTIONS
] = 0x00c0,
122 [PERF_COUNT_HW_CACHE_REFERENCES
] = 0x077d,
123 [PERF_COUNT_HW_CACHE_MISSES
] = 0x077e,
124 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = 0x00c2,
125 [PERF_COUNT_HW_BRANCH_MISSES
] = 0x00c3,
126 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
] = 0x00d0, /* "Decoder empty" event */
127 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND
] = 0x00d1, /* "Dispatch stalls" event */
130 static u64
amd_pmu_event_map(int hw_event
)
132 return amd_perfmon_event_map
[hw_event
];
136 * Previously calculated offsets
138 static unsigned int event_offsets
[X86_PMC_IDX_MAX
] __read_mostly
;
139 static unsigned int count_offsets
[X86_PMC_IDX_MAX
] __read_mostly
;
143 * 4 counters starting at 0xc0010000 each offset by 1
145 * CPUs with core performance counter extensions:
146 * 6 counters starting at 0xc0010200 each offset by 2
148 static inline int amd_pmu_addr_offset(int index
, bool eventsel
)
156 offset
= event_offsets
[index
];
158 offset
= count_offsets
[index
];
163 if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE
))
169 event_offsets
[index
] = offset
;
171 count_offsets
[index
] = offset
;
176 static int amd_core_hw_config(struct perf_event
*event
)
178 if (event
->attr
.exclude_host
&& event
->attr
.exclude_guest
)
180 * When HO == GO == 1 the hardware treats that as GO == HO == 0
181 * and will count in both modes. We don't want to count in that
182 * case so we emulate no-counting by setting US = OS = 0.
184 event
->hw
.config
&= ~(ARCH_PERFMON_EVENTSEL_USR
|
185 ARCH_PERFMON_EVENTSEL_OS
);
186 else if (event
->attr
.exclude_host
)
187 event
->hw
.config
|= AMD64_EVENTSEL_GUESTONLY
;
188 else if (event
->attr
.exclude_guest
)
189 event
->hw
.config
|= AMD64_EVENTSEL_HOSTONLY
;
195 * AMD64 events are detected based on their event codes.
197 static inline unsigned int amd_get_event_code(struct hw_perf_event
*hwc
)
199 return ((hwc
->config
>> 24) & 0x0f00) | (hwc
->config
& 0x00ff);
202 static inline int amd_is_nb_event(struct hw_perf_event
*hwc
)
204 return (hwc
->config
& 0xe0) == 0xe0;
207 static inline int amd_has_nb(struct cpu_hw_events
*cpuc
)
209 struct amd_nb
*nb
= cpuc
->amd_nb
;
211 return nb
&& nb
->nb_id
!= -1;
214 static int amd_pmu_hw_config(struct perf_event
*event
)
218 /* pass precise event sampling to ibs: */
219 if (event
->attr
.precise_ip
&& get_ibs_caps())
222 if (has_branch_stack(event
))
225 ret
= x86_pmu_hw_config(event
);
229 if (event
->attr
.type
== PERF_TYPE_RAW
)
230 event
->hw
.config
|= event
->attr
.config
& AMD64_RAW_EVENT_MASK
;
232 return amd_core_hw_config(event
);
235 static void __amd_put_nb_event_constraints(struct cpu_hw_events
*cpuc
,
236 struct perf_event
*event
)
238 struct amd_nb
*nb
= cpuc
->amd_nb
;
242 * need to scan whole list because event may not have
243 * been assigned during scheduling
245 * no race condition possible because event can only
246 * be removed on one CPU at a time AND PMU is disabled
249 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
250 if (cmpxchg(nb
->owners
+ i
, event
, NULL
) == event
)
256 * AMD64 NorthBridge events need special treatment because
257 * counter access needs to be synchronized across all cores
258 * of a package. Refer to BKDG section 3.12
260 * NB events are events measuring L3 cache, Hypertransport
261 * traffic. They are identified by an event code >= 0xe00.
262 * They measure events on the NorthBride which is shared
263 * by all cores on a package. NB events are counted on a
264 * shared set of counters. When a NB event is programmed
265 * in a counter, the data actually comes from a shared
266 * counter. Thus, access to those counters needs to be
269 * We implement the synchronization such that no two cores
270 * can be measuring NB events using the same counters. Thus,
271 * we maintain a per-NB allocation table. The available slot
272 * is propagated using the event_constraint structure.
274 * We provide only one choice for each NB event based on
275 * the fact that only NB events have restrictions. Consequently,
276 * if a counter is available, there is a guarantee the NB event
277 * will be assigned to it. If no slot is available, an empty
278 * constraint is returned and scheduling will eventually fail
281 * Note that all cores attached the same NB compete for the same
282 * counters to host NB events, this is why we use atomic ops. Some
283 * multi-chip CPUs may have more than one NB.
285 * Given that resources are allocated (cmpxchg), they must be
286 * eventually freed for others to use. This is accomplished by
287 * calling __amd_put_nb_event_constraints()
289 * Non NB events are not impacted by this restriction.
291 static struct event_constraint
*
292 __amd_get_nb_event_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
,
293 struct event_constraint
*c
)
295 struct hw_perf_event
*hwc
= &event
->hw
;
296 struct amd_nb
*nb
= cpuc
->amd_nb
;
297 struct perf_event
*old
;
307 * detect if already present, if so reuse
309 * cannot merge with actual allocation
310 * because of possible holes
312 * event can already be present yet not assigned (in hwc->idx)
313 * because of successive calls to x86_schedule_events() from
314 * hw_perf_group_sched_in() without hw_perf_enable()
316 for_each_set_bit(idx
, c
->idxmsk
, x86_pmu
.num_counters
) {
317 if (new == -1 || hwc
->idx
== idx
)
318 /* assign free slot, prefer hwc->idx */
319 old
= cmpxchg(nb
->owners
+ idx
, NULL
, event
);
320 else if (nb
->owners
[idx
] == event
)
321 /* event already present */
326 if (old
&& old
!= event
)
329 /* reassign to this slot */
331 cmpxchg(nb
->owners
+ new, event
, NULL
);
334 /* already present, reuse */
340 return &emptyconstraint
;
342 return &nb
->event_constraints
[new];
345 static struct amd_nb
*amd_alloc_nb(int cpu
)
350 nb
= kzalloc_node(sizeof(struct amd_nb
), GFP_KERNEL
, cpu_to_node(cpu
));
357 * initialize all possible NB constraints
359 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
360 __set_bit(i
, nb
->event_constraints
[i
].idxmsk
);
361 nb
->event_constraints
[i
].weight
= 1;
366 static int amd_pmu_cpu_prepare(int cpu
)
368 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
370 WARN_ON_ONCE(cpuc
->amd_nb
);
372 if (!x86_pmu
.amd_nb_constraints
)
375 cpuc
->amd_nb
= amd_alloc_nb(cpu
);
382 static void amd_pmu_cpu_starting(int cpu
)
384 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
385 void **onln
= &cpuc
->kfree_on_online
[X86_PERF_KFREE_SHARED
];
389 cpuc
->perf_ctr_virt_mask
= AMD64_EVENTSEL_HOSTONLY
;
391 if (!x86_pmu
.amd_nb_constraints
)
394 nb_id
= amd_get_nb_id(cpu
);
395 WARN_ON_ONCE(nb_id
== BAD_APICID
);
397 for_each_online_cpu(i
) {
398 nb
= per_cpu(cpu_hw_events
, i
).amd_nb
;
399 if (WARN_ON_ONCE(!nb
))
402 if (nb
->nb_id
== nb_id
) {
403 *onln
= cpuc
->amd_nb
;
409 cpuc
->amd_nb
->nb_id
= nb_id
;
410 cpuc
->amd_nb
->refcnt
++;
413 static void amd_pmu_cpu_dead(int cpu
)
415 struct cpu_hw_events
*cpuhw
;
417 if (!x86_pmu
.amd_nb_constraints
)
420 cpuhw
= &per_cpu(cpu_hw_events
, cpu
);
423 struct amd_nb
*nb
= cpuhw
->amd_nb
;
425 if (nb
->nb_id
== -1 || --nb
->refcnt
== 0)
428 cpuhw
->amd_nb
= NULL
;
432 static struct event_constraint
*
433 amd_get_event_constraints(struct cpu_hw_events
*cpuc
, int idx
,
434 struct perf_event
*event
)
437 * if not NB event or no NB, then no constraints
439 if (!(amd_has_nb(cpuc
) && amd_is_nb_event(&event
->hw
)))
440 return &unconstrained
;
442 return __amd_get_nb_event_constraints(cpuc
, event
, NULL
);
445 static void amd_put_event_constraints(struct cpu_hw_events
*cpuc
,
446 struct perf_event
*event
)
448 if (amd_has_nb(cpuc
) && amd_is_nb_event(&event
->hw
))
449 __amd_put_nb_event_constraints(cpuc
, event
);
452 PMU_FORMAT_ATTR(event
, "config:0-7,32-35");
453 PMU_FORMAT_ATTR(umask
, "config:8-15" );
454 PMU_FORMAT_ATTR(edge
, "config:18" );
455 PMU_FORMAT_ATTR(inv
, "config:23" );
456 PMU_FORMAT_ATTR(cmask
, "config:24-31" );
458 static struct attribute
*amd_format_attr
[] = {
459 &format_attr_event
.attr
,
460 &format_attr_umask
.attr
,
461 &format_attr_edge
.attr
,
462 &format_attr_inv
.attr
,
463 &format_attr_cmask
.attr
,
469 #define AMD_EVENT_TYPE_MASK 0x000000F0ULL
471 #define AMD_EVENT_FP 0x00000000ULL ... 0x00000010ULL
472 #define AMD_EVENT_LS 0x00000020ULL ... 0x00000030ULL
473 #define AMD_EVENT_DC 0x00000040ULL ... 0x00000050ULL
474 #define AMD_EVENT_CU 0x00000060ULL ... 0x00000070ULL
475 #define AMD_EVENT_IC_DE 0x00000080ULL ... 0x00000090ULL
476 #define AMD_EVENT_EX_LS 0x000000C0ULL
477 #define AMD_EVENT_DE 0x000000D0ULL
478 #define AMD_EVENT_NB 0x000000E0ULL ... 0x000000F0ULL
481 * AMD family 15h event code/PMC mappings:
483 * type = event_code & 0x0F0:
485 * 0x000 FP PERF_CTL[5:3]
486 * 0x010 FP PERF_CTL[5:3]
487 * 0x020 LS PERF_CTL[5:0]
488 * 0x030 LS PERF_CTL[5:0]
489 * 0x040 DC PERF_CTL[5:0]
490 * 0x050 DC PERF_CTL[5:0]
491 * 0x060 CU PERF_CTL[2:0]
492 * 0x070 CU PERF_CTL[2:0]
493 * 0x080 IC/DE PERF_CTL[2:0]
494 * 0x090 IC/DE PERF_CTL[2:0]
497 * 0x0C0 EX/LS PERF_CTL[5:0]
498 * 0x0D0 DE PERF_CTL[2:0]
499 * 0x0E0 NB NB_PERF_CTL[3:0]
500 * 0x0F0 NB NB_PERF_CTL[3:0]
504 * 0x000 FP PERF_CTL[3], PERF_CTL[5:3] (*)
505 * 0x003 FP PERF_CTL[3]
506 * 0x004 FP PERF_CTL[3], PERF_CTL[5:3] (*)
507 * 0x00B FP PERF_CTL[3]
508 * 0x00D FP PERF_CTL[3]
509 * 0x023 DE PERF_CTL[2:0]
510 * 0x02D LS PERF_CTL[3]
511 * 0x02E LS PERF_CTL[3,0]
512 * 0x031 LS PERF_CTL[2:0] (**)
513 * 0x043 CU PERF_CTL[2:0]
514 * 0x045 CU PERF_CTL[2:0]
515 * 0x046 CU PERF_CTL[2:0]
516 * 0x054 CU PERF_CTL[2:0]
517 * 0x055 CU PERF_CTL[2:0]
518 * 0x08F IC PERF_CTL[0]
519 * 0x187 DE PERF_CTL[0]
520 * 0x188 DE PERF_CTL[0]
521 * 0x0DB EX PERF_CTL[5:0]
522 * 0x0DC LS PERF_CTL[5:0]
523 * 0x0DD LS PERF_CTL[5:0]
524 * 0x0DE LS PERF_CTL[5:0]
525 * 0x0DF LS PERF_CTL[5:0]
526 * 0x1C0 EX PERF_CTL[5:3]
527 * 0x1D6 EX PERF_CTL[5:0]
528 * 0x1D8 EX PERF_CTL[5:0]
530 * (*) depending on the umask all FPU counters may be used
531 * (**) only one unitmask enabled at a time
534 static struct event_constraint amd_f15_PMC0
= EVENT_CONSTRAINT(0, 0x01, 0);
535 static struct event_constraint amd_f15_PMC20
= EVENT_CONSTRAINT(0, 0x07, 0);
536 static struct event_constraint amd_f15_PMC3
= EVENT_CONSTRAINT(0, 0x08, 0);
537 static struct event_constraint amd_f15_PMC30
= EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
538 static struct event_constraint amd_f15_PMC50
= EVENT_CONSTRAINT(0, 0x3F, 0);
539 static struct event_constraint amd_f15_PMC53
= EVENT_CONSTRAINT(0, 0x38, 0);
541 static struct event_constraint
*
542 amd_get_event_constraints_f15h(struct cpu_hw_events
*cpuc
, int idx
,
543 struct perf_event
*event
)
545 struct hw_perf_event
*hwc
= &event
->hw
;
546 unsigned int event_code
= amd_get_event_code(hwc
);
548 switch (event_code
& AMD_EVENT_TYPE_MASK
) {
550 switch (event_code
) {
552 if (!(hwc
->config
& 0x0000F000ULL
))
554 if (!(hwc
->config
& 0x00000F00ULL
))
556 return &amd_f15_PMC3
;
558 if (hweight_long(hwc
->config
& ARCH_PERFMON_EVENTSEL_UMASK
) <= 1)
560 return &amd_f15_PMC3
;
564 return &amd_f15_PMC3
;
566 return &amd_f15_PMC53
;
569 case AMD_EVENT_EX_LS
:
570 switch (event_code
) {
577 return &amd_f15_PMC20
;
579 return &amd_f15_PMC3
;
581 return &amd_f15_PMC30
;
583 if (hweight_long(hwc
->config
& ARCH_PERFMON_EVENTSEL_UMASK
) <= 1)
584 return &amd_f15_PMC20
;
585 return &emptyconstraint
;
587 return &amd_f15_PMC53
;
589 return &amd_f15_PMC50
;
592 case AMD_EVENT_IC_DE
:
594 switch (event_code
) {
598 return &amd_f15_PMC0
;
599 case 0x0DB ... 0x0DF:
602 return &amd_f15_PMC50
;
604 return &amd_f15_PMC20
;
607 /* moved to uncore.c */
608 return &emptyconstraint
;
610 return &emptyconstraint
;
614 static ssize_t
amd_event_sysfs_show(char *page
, u64 config
)
616 u64 event
= (config
& ARCH_PERFMON_EVENTSEL_EVENT
) |
617 (config
& AMD64_EVENTSEL_EVENT
) >> 24;
619 return x86_event_sysfs_show(page
, config
, event
);
622 static __initconst
const struct x86_pmu amd_pmu
= {
624 .handle_irq
= x86_pmu_handle_irq
,
625 .disable_all
= x86_pmu_disable_all
,
626 .enable_all
= x86_pmu_enable_all
,
627 .enable
= x86_pmu_enable_event
,
628 .disable
= x86_pmu_disable_event
,
629 .hw_config
= amd_pmu_hw_config
,
630 .schedule_events
= x86_schedule_events
,
631 .eventsel
= MSR_K7_EVNTSEL0
,
632 .perfctr
= MSR_K7_PERFCTR0
,
633 .addr_offset
= amd_pmu_addr_offset
,
634 .event_map
= amd_pmu_event_map
,
635 .max_events
= ARRAY_SIZE(amd_perfmon_event_map
),
636 .num_counters
= AMD64_NUM_COUNTERS
,
638 .cntval_mask
= (1ULL << 48) - 1,
640 /* use highest bit to detect overflow */
641 .max_period
= (1ULL << 47) - 1,
642 .get_event_constraints
= amd_get_event_constraints
,
643 .put_event_constraints
= amd_put_event_constraints
,
645 .format_attrs
= amd_format_attr
,
646 .events_sysfs_show
= amd_event_sysfs_show
,
648 .cpu_prepare
= amd_pmu_cpu_prepare
,
649 .cpu_starting
= amd_pmu_cpu_starting
,
650 .cpu_dead
= amd_pmu_cpu_dead
,
652 .amd_nb_constraints
= 1,
655 static int __init
amd_core_pmu_init(void)
657 if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE
))
660 switch (boot_cpu_data
.x86
) {
663 x86_pmu
.get_event_constraints
= amd_get_event_constraints_f15h
;
668 * In family 17h, there are no event constraints in the PMC hardware.
669 * We fallback to using default amd_get_event_constraints.
674 /* Using default amd_get_event_constraints. */
677 pr_err("core perfctr but no constraints; unknown hardware!\n");
682 * If core performance counter extensions exists, we must use
683 * MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also
684 * amd_pmu_addr_offset().
686 x86_pmu
.eventsel
= MSR_F15H_PERF_CTL
;
687 x86_pmu
.perfctr
= MSR_F15H_PERF_CTR
;
688 x86_pmu
.num_counters
= AMD64_NUM_COUNTERS_CORE
;
690 * AMD Core perfctr has separate MSRs for the NB events, see
691 * the amd/uncore.c driver.
693 x86_pmu
.amd_nb_constraints
= 0;
695 pr_cont("core perfctr, ");
699 __init
int amd_pmu_init(void)
703 /* Performance-monitoring supported from K7 and later: */
704 if (boot_cpu_data
.x86
< 6)
709 ret
= amd_core_pmu_init();
713 if (num_possible_cpus() == 1) {
715 * No point in allocating data structures to serialize
716 * against other CPUs, when there is only the one CPU.
718 x86_pmu
.amd_nb_constraints
= 0;
721 /* Events are common for all AMDs */
722 memcpy(hw_cache_event_ids
, amd_hw_cache_event_ids
,
723 sizeof(hw_cache_event_ids
));
728 void amd_pmu_enable_virt(void)
730 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
732 cpuc
->perf_ctr_virt_mask
= 0;
734 /* Reload all events */
735 x86_pmu_disable_all();
736 x86_pmu_enable_all(0);
738 EXPORT_SYMBOL_GPL(amd_pmu_enable_virt
);
740 void amd_pmu_disable_virt(void)
742 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
745 * We only mask out the Host-only bit so that host-only counting works
746 * when SVM is disabled. If someone sets up a guest-only counter when
747 * SVM is disabled the Guest-only bits still gets set and the counter
748 * will not count anything.
750 cpuc
->perf_ctr_virt_mask
= AMD64_EVENTSEL_HOSTONLY
;
752 /* Reload all events */
753 x86_pmu_disable_all();
754 x86_pmu_enable_all(0);
756 EXPORT_SYMBOL_GPL(amd_pmu_disable_virt
);