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KVM: x86: fix emulation of RSM and IRET instructions
[linux/fpc-iii.git] / arch / x86 / kvm / x86.c
blobe1c1003f1f93bca78a32032c54a8f5f26e0c56ce
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
37 #include <linux/fs.h>
38 #include <linux/vmalloc.h>
39 #include <linux/export.h>
40 #include <linux/moduleparam.h>
41 #include <linux/mman.h>
42 #include <linux/highmem.h>
43 #include <linux/iommu.h>
44 #include <linux/intel-iommu.h>
45 #include <linux/cpufreq.h>
46 #include <linux/user-return-notifier.h>
47 #include <linux/srcu.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <linux/uaccess.h>
51 #include <linux/hash.h>
52 #include <linux/pci.h>
53 #include <linux/timekeeper_internal.h>
54 #include <linux/pvclock_gtod.h>
55 #include <linux/kvm_irqfd.h>
56 #include <linux/irqbypass.h>
57 #include <trace/events/kvm.h>
58
59 #include <asm/debugreg.h>
60 #include <asm/msr.h>
61 #include <asm/desc.h>
62 #include <asm/mce.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67 #include <asm/irq_remapping.h>
68
69 #define CREATE_TRACE_POINTS
70 #include "trace.h"
71
72 #define MAX_IO_MSRS 256
73 #define KVM_MAX_MCE_BANKS 32
74 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
75 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
76
77 #define emul_to_vcpu(ctxt) \
78 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79
80 /* EFER defaults:
81 * - enable syscall per default because its emulated by KVM
82 * - enable LME and LMA per default on 64 bit KVM
83 */
84 #ifdef CONFIG_X86_64
85 static
86 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
87 #else
88 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
89 #endif
90
91 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
92 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
93
94 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
95 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
96
97 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
98 static void process_nmi(struct kvm_vcpu *vcpu);
99 static void enter_smm(struct kvm_vcpu *vcpu);
100 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
101
102 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
103 EXPORT_SYMBOL_GPL(kvm_x86_ops);
104
105 static bool __read_mostly ignore_msrs = 0;
106 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
107
108 unsigned int min_timer_period_us = 500;
109 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
110
111 static bool __read_mostly kvmclock_periodic_sync = true;
112 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
113
114 bool __read_mostly kvm_has_tsc_control;
115 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
116 u32 __read_mostly kvm_max_guest_tsc_khz;
117 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
118 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
119 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
120 u64 __read_mostly kvm_max_tsc_scaling_ratio;
121 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
122 u64 __read_mostly kvm_default_tsc_scaling_ratio;
123 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
124
125 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
126 static u32 __read_mostly tsc_tolerance_ppm = 250;
127 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
128
129 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
130 unsigned int __read_mostly lapic_timer_advance_ns = 0;
131 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
132
133 static bool __read_mostly vector_hashing = true;
134 module_param(vector_hashing, bool, S_IRUGO);
135
136 static bool __read_mostly backwards_tsc_observed = false;
137
138 #define KVM_NR_SHARED_MSRS 16
139
140 struct kvm_shared_msrs_global {
141 int nr;
142 u32 msrs[KVM_NR_SHARED_MSRS];
143 };
144
145 struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
152 };
153
154 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
155 static struct kvm_shared_msrs __percpu *shared_msrs;
156
157 struct kvm_stats_debugfs_item debugfs_entries[] = {
158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
168 { "halt_exits", VCPU_STAT(halt_exits) },
169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
173 { "hypercalls", VCPU_STAT(hypercalls) },
174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
181 { "irq_injections", VCPU_STAT(irq_injections) },
182 { "nmi_injections", VCPU_STAT(nmi_injections) },
183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
190 { "mmu_unsync", VM_STAT(mmu_unsync) },
191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
192 { "largepages", VM_STAT(lpages) },
193 { NULL }
194 };
195
196 u64 __read_mostly host_xcr0;
197
198 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
199
200 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
201 {
202 int i;
203 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
204 vcpu->arch.apf.gfns[i] = ~0;
205 }
206
207 static void kvm_on_user_return(struct user_return_notifier *urn)
208 {
209 unsigned slot;
210 struct kvm_shared_msrs *locals
211 = container_of(urn, struct kvm_shared_msrs, urn);
212 struct kvm_shared_msr_values *values;
213 unsigned long flags;
214
215 /*
216 * Disabling irqs at this point since the following code could be
217 * interrupted and executed through kvm_arch_hardware_disable()
218 */
219 local_irq_save(flags);
220 if (locals->registered) {
221 locals->registered = false;
222 user_return_notifier_unregister(urn);
223 }
224 local_irq_restore(flags);
225 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
226 values = &locals->values[slot];
227 if (values->host != values->curr) {
228 wrmsrl(shared_msrs_global.msrs[slot], values->host);
229 values->curr = values->host;
230 }
231 }
232 }
233
234 static void shared_msr_update(unsigned slot, u32 msr)
235 {
236 u64 value;
237 unsigned int cpu = smp_processor_id();
238 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
239
240 /* only read, and nobody should modify it at this time,
241 * so don't need lock */
242 if (slot >= shared_msrs_global.nr) {
243 printk(KERN_ERR "kvm: invalid MSR slot!");
244 return;
245 }
246 rdmsrl_safe(msr, &value);
247 smsr->values[slot].host = value;
248 smsr->values[slot].curr = value;
249 }
250
251 void kvm_define_shared_msr(unsigned slot, u32 msr)
252 {
253 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
254 shared_msrs_global.msrs[slot] = msr;
255 if (slot >= shared_msrs_global.nr)
256 shared_msrs_global.nr = slot + 1;
257 }
258 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
259
260 static void kvm_shared_msr_cpu_online(void)
261 {
262 unsigned i;
263
264 for (i = 0; i < shared_msrs_global.nr; ++i)
265 shared_msr_update(i, shared_msrs_global.msrs[i]);
266 }
267
268 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
269 {
270 unsigned int cpu = smp_processor_id();
271 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
272 int err;
273
274 if (((value ^ smsr->values[slot].curr) & mask) == 0)
275 return 0;
276 smsr->values[slot].curr = value;
277 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
278 if (err)
279 return 1;
280
281 if (!smsr->registered) {
282 smsr->urn.on_user_return = kvm_on_user_return;
283 user_return_notifier_register(&smsr->urn);
284 smsr->registered = true;
285 }
286 return 0;
287 }
288 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
289
290 static void drop_user_return_notifiers(void)
291 {
292 unsigned int cpu = smp_processor_id();
293 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
294
295 if (smsr->registered)
296 kvm_on_user_return(&smsr->urn);
297 }
298
299 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
300 {
301 return vcpu->arch.apic_base;
302 }
303 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
304
305 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
306 {
307 u64 old_state = vcpu->arch.apic_base &
308 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
309 u64 new_state = msr_info->data &
310 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
311 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
312 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
313
314 if (!msr_info->host_initiated &&
315 ((msr_info->data & reserved_bits) != 0 ||
316 new_state == X2APIC_ENABLE ||
317 (new_state == MSR_IA32_APICBASE_ENABLE &&
318 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
319 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
320 old_state == 0)))
321 return 1;
322
323 kvm_lapic_set_base(vcpu, msr_info->data);
324 return 0;
325 }
326 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
327
328 asmlinkage __visible void kvm_spurious_fault(void)
329 {
330 /* Fault while not rebooting. We want the trace. */
331 BUG();
332 }
333 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
334
335 #define EXCPT_BENIGN 0
336 #define EXCPT_CONTRIBUTORY 1
337 #define EXCPT_PF 2
338
339 static int exception_class(int vector)
340 {
341 switch (vector) {
342 case PF_VECTOR:
343 return EXCPT_PF;
344 case DE_VECTOR:
345 case TS_VECTOR:
346 case NP_VECTOR:
347 case SS_VECTOR:
348 case GP_VECTOR:
349 return EXCPT_CONTRIBUTORY;
350 default:
351 break;
352 }
353 return EXCPT_BENIGN;
354 }
355
356 #define EXCPT_FAULT 0
357 #define EXCPT_TRAP 1
358 #define EXCPT_ABORT 2
359 #define EXCPT_INTERRUPT 3
360
361 static int exception_type(int vector)
362 {
363 unsigned int mask;
364
365 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
366 return EXCPT_INTERRUPT;
367
368 mask = 1 << vector;
369
370 /* #DB is trap, as instruction watchpoints are handled elsewhere */
371 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
372 return EXCPT_TRAP;
373
374 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
375 return EXCPT_ABORT;
376
377 /* Reserved exceptions will result in fault */
378 return EXCPT_FAULT;
379 }
380
381 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
382 unsigned nr, bool has_error, u32 error_code,
383 bool reinject)
384 {
385 u32 prev_nr;
386 int class1, class2;
387
388 kvm_make_request(KVM_REQ_EVENT, vcpu);
389
390 if (!vcpu->arch.exception.pending) {
391 queue:
392 if (has_error && !is_protmode(vcpu))
393 has_error = false;
394 vcpu->arch.exception.pending = true;
395 vcpu->arch.exception.has_error_code = has_error;
396 vcpu->arch.exception.nr = nr;
397 vcpu->arch.exception.error_code = error_code;
398 vcpu->arch.exception.reinject = reinject;
399 return;
400 }
401
402 /* to check exception */
403 prev_nr = vcpu->arch.exception.nr;
404 if (prev_nr == DF_VECTOR) {
405 /* triple fault -> shutdown */
406 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
407 return;
408 }
409 class1 = exception_class(prev_nr);
410 class2 = exception_class(nr);
411 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
412 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
413 /* generate double fault per SDM Table 5-5 */
414 vcpu->arch.exception.pending = true;
415 vcpu->arch.exception.has_error_code = true;
416 vcpu->arch.exception.nr = DF_VECTOR;
417 vcpu->arch.exception.error_code = 0;
418 } else
419 /* replace previous exception with a new one in a hope
420 that instruction re-execution will regenerate lost
421 exception */
422 goto queue;
423 }
424
425 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
426 {
427 kvm_multiple_exception(vcpu, nr, false, 0, false);
428 }
429 EXPORT_SYMBOL_GPL(kvm_queue_exception);
430
431 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
432 {
433 kvm_multiple_exception(vcpu, nr, false, 0, true);
434 }
435 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
436
437 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
438 {
439 if (err)
440 kvm_inject_gp(vcpu, 0);
441 else
442 kvm_x86_ops->skip_emulated_instruction(vcpu);
443 }
444 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
445
446 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
447 {
448 ++vcpu->stat.pf_guest;
449 vcpu->arch.cr2 = fault->address;
450 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
451 }
452 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
453
454 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
455 {
456 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
457 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
458 else
459 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
460
461 return fault->nested_page_fault;
462 }
463
464 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
465 {
466 atomic_inc(&vcpu->arch.nmi_queued);
467 kvm_make_request(KVM_REQ_NMI, vcpu);
468 }
469 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
470
471 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
472 {
473 kvm_multiple_exception(vcpu, nr, true, error_code, false);
474 }
475 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
476
477 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
478 {
479 kvm_multiple_exception(vcpu, nr, true, error_code, true);
480 }
481 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
482
483 /*
484 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
485 * a #GP and return false.
486 */
487 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
488 {
489 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
490 return true;
491 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
492 return false;
493 }
494 EXPORT_SYMBOL_GPL(kvm_require_cpl);
495
496 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
497 {
498 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
499 return true;
500
501 kvm_queue_exception(vcpu, UD_VECTOR);
502 return false;
503 }
504 EXPORT_SYMBOL_GPL(kvm_require_dr);
505
506 /*
507 * This function will be used to read from the physical memory of the currently
508 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
509 * can read from guest physical or from the guest's guest physical memory.
510 */
511 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
512 gfn_t ngfn, void *data, int offset, int len,
513 u32 access)
514 {
515 struct x86_exception exception;
516 gfn_t real_gfn;
517 gpa_t ngpa;
518
519 ngpa = gfn_to_gpa(ngfn);
520 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
521 if (real_gfn == UNMAPPED_GVA)
522 return -EFAULT;
523
524 real_gfn = gpa_to_gfn(real_gfn);
525
526 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
527 }
528 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
529
530 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
531 void *data, int offset, int len, u32 access)
532 {
533 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
534 data, offset, len, access);
535 }
536
537 /*
538 * Load the pae pdptrs. Return true is they are all valid.
539 */
540 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
541 {
542 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
543 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
544 int i;
545 int ret;
546 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
547
548 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
549 offset * sizeof(u64), sizeof(pdpte),
550 PFERR_USER_MASK|PFERR_WRITE_MASK);
551 if (ret < 0) {
552 ret = 0;
553 goto out;
554 }
555 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
556 if ((pdpte[i] & PT_PRESENT_MASK) &&
557 (pdpte[i] &
558 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
559 ret = 0;
560 goto out;
561 }
562 }
563 ret = 1;
564
565 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
566 __set_bit(VCPU_EXREG_PDPTR,
567 (unsigned long *)&vcpu->arch.regs_avail);
568 __set_bit(VCPU_EXREG_PDPTR,
569 (unsigned long *)&vcpu->arch.regs_dirty);
570 out:
571
572 return ret;
573 }
574 EXPORT_SYMBOL_GPL(load_pdptrs);
575
576 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
577 {
578 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
579 bool changed = true;
580 int offset;
581 gfn_t gfn;
582 int r;
583
584 if (is_long_mode(vcpu) || !is_pae(vcpu))
585 return false;
586
587 if (!test_bit(VCPU_EXREG_PDPTR,
588 (unsigned long *)&vcpu->arch.regs_avail))
589 return true;
590
591 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
592 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
593 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
594 PFERR_USER_MASK | PFERR_WRITE_MASK);
595 if (r < 0)
596 goto out;
597 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
598 out:
599
600 return changed;
601 }
602
603 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
604 {
605 unsigned long old_cr0 = kvm_read_cr0(vcpu);
606 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
607
608 cr0 |= X86_CR0_ET;
609
610 #ifdef CONFIG_X86_64
611 if (cr0 & 0xffffffff00000000UL)
612 return 1;
613 #endif
614
615 cr0 &= ~CR0_RESERVED_BITS;
616
617 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
618 return 1;
619
620 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
621 return 1;
622
623 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
624 #ifdef CONFIG_X86_64
625 if ((vcpu->arch.efer & EFER_LME)) {
626 int cs_db, cs_l;
627
628 if (!is_pae(vcpu))
629 return 1;
630 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
631 if (cs_l)
632 return 1;
633 } else
634 #endif
635 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
636 kvm_read_cr3(vcpu)))
637 return 1;
638 }
639
640 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
641 return 1;
642
643 kvm_x86_ops->set_cr0(vcpu, cr0);
644
645 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
646 kvm_clear_async_pf_completion_queue(vcpu);
647 kvm_async_pf_hash_reset(vcpu);
648 }
649
650 if ((cr0 ^ old_cr0) & update_bits)
651 kvm_mmu_reset_context(vcpu);
652
653 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
654 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
655 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
656 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
657
658 return 0;
659 }
660 EXPORT_SYMBOL_GPL(kvm_set_cr0);
661
662 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
663 {
664 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
665 }
666 EXPORT_SYMBOL_GPL(kvm_lmsw);
667
668 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
669 {
670 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
671 !vcpu->guest_xcr0_loaded) {
672 /* kvm_set_xcr() also depends on this */
673 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
674 vcpu->guest_xcr0_loaded = 1;
675 }
676 }
677
678 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
679 {
680 if (vcpu->guest_xcr0_loaded) {
681 if (vcpu->arch.xcr0 != host_xcr0)
682 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
683 vcpu->guest_xcr0_loaded = 0;
684 }
685 }
686
687 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
688 {
689 u64 xcr0 = xcr;
690 u64 old_xcr0 = vcpu->arch.xcr0;
691 u64 valid_bits;
692
693 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
694 if (index != XCR_XFEATURE_ENABLED_MASK)
695 return 1;
696 if (!(xcr0 & XFEATURE_MASK_FP))
697 return 1;
698 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
699 return 1;
700
701 /*
702 * Do not allow the guest to set bits that we do not support
703 * saving. However, xcr0 bit 0 is always set, even if the
704 * emulated CPU does not support XSAVE (see fx_init).
705 */
706 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
707 if (xcr0 & ~valid_bits)
708 return 1;
709
710 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
711 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
712 return 1;
713
714 if (xcr0 & XFEATURE_MASK_AVX512) {
715 if (!(xcr0 & XFEATURE_MASK_YMM))
716 return 1;
717 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
718 return 1;
719 }
720 vcpu->arch.xcr0 = xcr0;
721
722 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
723 kvm_update_cpuid(vcpu);
724 return 0;
725 }
726
727 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
728 {
729 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
730 __kvm_set_xcr(vcpu, index, xcr)) {
731 kvm_inject_gp(vcpu, 0);
732 return 1;
733 }
734 return 0;
735 }
736 EXPORT_SYMBOL_GPL(kvm_set_xcr);
737
738 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
739 {
740 unsigned long old_cr4 = kvm_read_cr4(vcpu);
741 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
742 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
743
744 if (cr4 & CR4_RESERVED_BITS)
745 return 1;
746
747 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
748 return 1;
749
750 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
751 return 1;
752
753 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
754 return 1;
755
756 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
757 return 1;
758
759 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
760 return 1;
761
762 if (is_long_mode(vcpu)) {
763 if (!(cr4 & X86_CR4_PAE))
764 return 1;
765 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
766 && ((cr4 ^ old_cr4) & pdptr_bits)
767 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
768 kvm_read_cr3(vcpu)))
769 return 1;
770
771 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
772 if (!guest_cpuid_has_pcid(vcpu))
773 return 1;
774
775 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
776 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
777 return 1;
778 }
779
780 if (kvm_x86_ops->set_cr4(vcpu, cr4))
781 return 1;
782
783 if (((cr4 ^ old_cr4) & pdptr_bits) ||
784 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
785 kvm_mmu_reset_context(vcpu);
786
787 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
788 kvm_update_cpuid(vcpu);
789
790 return 0;
791 }
792 EXPORT_SYMBOL_GPL(kvm_set_cr4);
793
794 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
795 {
796 #ifdef CONFIG_X86_64
797 cr3 &= ~CR3_PCID_INVD;
798 #endif
799
800 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
801 kvm_mmu_sync_roots(vcpu);
802 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
803 return 0;
804 }
805
806 if (is_long_mode(vcpu)) {
807 if (cr3 & CR3_L_MODE_RESERVED_BITS)
808 return 1;
809 } else if (is_pae(vcpu) && is_paging(vcpu) &&
810 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
811 return 1;
812
813 vcpu->arch.cr3 = cr3;
814 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
815 kvm_mmu_new_cr3(vcpu);
816 return 0;
817 }
818 EXPORT_SYMBOL_GPL(kvm_set_cr3);
819
820 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
821 {
822 if (cr8 & CR8_RESERVED_BITS)
823 return 1;
824 if (lapic_in_kernel(vcpu))
825 kvm_lapic_set_tpr(vcpu, cr8);
826 else
827 vcpu->arch.cr8 = cr8;
828 return 0;
829 }
830 EXPORT_SYMBOL_GPL(kvm_set_cr8);
831
832 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
833 {
834 if (lapic_in_kernel(vcpu))
835 return kvm_lapic_get_cr8(vcpu);
836 else
837 return vcpu->arch.cr8;
838 }
839 EXPORT_SYMBOL_GPL(kvm_get_cr8);
840
841 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
842 {
843 int i;
844
845 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
846 for (i = 0; i < KVM_NR_DB_REGS; i++)
847 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
848 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
849 }
850 }
851
852 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
853 {
854 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
855 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
856 }
857
858 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
859 {
860 unsigned long dr7;
861
862 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
863 dr7 = vcpu->arch.guest_debug_dr7;
864 else
865 dr7 = vcpu->arch.dr7;
866 kvm_x86_ops->set_dr7(vcpu, dr7);
867 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
868 if (dr7 & DR7_BP_EN_MASK)
869 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
870 }
871
872 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
873 {
874 u64 fixed = DR6_FIXED_1;
875
876 if (!guest_cpuid_has_rtm(vcpu))
877 fixed |= DR6_RTM;
878 return fixed;
879 }
880
881 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
882 {
883 switch (dr) {
884 case 0 ... 3:
885 vcpu->arch.db[dr] = val;
886 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
887 vcpu->arch.eff_db[dr] = val;
888 break;
889 case 4:
890 /* fall through */
891 case 6:
892 if (val & 0xffffffff00000000ULL)
893 return -1; /* #GP */
894 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
895 kvm_update_dr6(vcpu);
896 break;
897 case 5:
898 /* fall through */
899 default: /* 7 */
900 if (val & 0xffffffff00000000ULL)
901 return -1; /* #GP */
902 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
903 kvm_update_dr7(vcpu);
904 break;
905 }
906
907 return 0;
908 }
909
910 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
911 {
912 if (__kvm_set_dr(vcpu, dr, val)) {
913 kvm_inject_gp(vcpu, 0);
914 return 1;
915 }
916 return 0;
917 }
918 EXPORT_SYMBOL_GPL(kvm_set_dr);
919
920 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
921 {
922 switch (dr) {
923 case 0 ... 3:
924 *val = vcpu->arch.db[dr];
925 break;
926 case 4:
927 /* fall through */
928 case 6:
929 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
930 *val = vcpu->arch.dr6;
931 else
932 *val = kvm_x86_ops->get_dr6(vcpu);
933 break;
934 case 5:
935 /* fall through */
936 default: /* 7 */
937 *val = vcpu->arch.dr7;
938 break;
939 }
940 return 0;
941 }
942 EXPORT_SYMBOL_GPL(kvm_get_dr);
943
944 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
945 {
946 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
947 u64 data;
948 int err;
949
950 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
951 if (err)
952 return err;
953 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
954 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
955 return err;
956 }
957 EXPORT_SYMBOL_GPL(kvm_rdpmc);
958
959 /*
960 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
961 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
962 *
963 * This list is modified at module load time to reflect the
964 * capabilities of the host cpu. This capabilities test skips MSRs that are
965 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
966 * may depend on host virtualization features rather than host cpu features.
967 */
968
969 static u32 msrs_to_save[] = {
970 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
971 MSR_STAR,
972 #ifdef CONFIG_X86_64
973 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
974 #endif
975 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
976 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
977 };
978
979 static unsigned num_msrs_to_save;
980
981 static u32 emulated_msrs[] = {
982 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
983 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
984 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
985 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
986 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
987 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
988 HV_X64_MSR_RESET,
989 HV_X64_MSR_VP_INDEX,
990 HV_X64_MSR_VP_RUNTIME,
991 HV_X64_MSR_SCONTROL,
992 HV_X64_MSR_STIMER0_CONFIG,
993 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
994 MSR_KVM_PV_EOI_EN,
995
996 MSR_IA32_TSC_ADJUST,
997 MSR_IA32_TSCDEADLINE,
998 MSR_IA32_MISC_ENABLE,
999 MSR_IA32_MCG_STATUS,
1000 MSR_IA32_MCG_CTL,
1001 MSR_IA32_MCG_EXT_CTL,
1002 MSR_IA32_SMBASE,
1003 };
1004
1005 static unsigned num_emulated_msrs;
1006
1007 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1008 {
1009 if (efer & efer_reserved_bits)
1010 return false;
1011
1012 if (efer & EFER_FFXSR) {
1013 struct kvm_cpuid_entry2 *feat;
1014
1015 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1016 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
1017 return false;
1018 }
1019
1020 if (efer & EFER_SVME) {
1021 struct kvm_cpuid_entry2 *feat;
1022
1023 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1024 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1025 return false;
1026 }
1027
1028 return true;
1029 }
1030 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1031
1032 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1033 {
1034 u64 old_efer = vcpu->arch.efer;
1035
1036 if (!kvm_valid_efer(vcpu, efer))
1037 return 1;
1038
1039 if (is_paging(vcpu)
1040 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1041 return 1;
1042
1043 efer &= ~EFER_LMA;
1044 efer |= vcpu->arch.efer & EFER_LMA;
1045
1046 kvm_x86_ops->set_efer(vcpu, efer);
1047
1048 /* Update reserved bits */
1049 if ((efer ^ old_efer) & EFER_NX)
1050 kvm_mmu_reset_context(vcpu);
1051
1052 return 0;
1053 }
1054
1055 void kvm_enable_efer_bits(u64 mask)
1056 {
1057 efer_reserved_bits &= ~mask;
1058 }
1059 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1060
1061 /*
1062 * Writes msr value into into the appropriate "register".
1063 * Returns 0 on success, non-0 otherwise.
1064 * Assumes vcpu_load() was already called.
1065 */
1066 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1067 {
1068 switch (msr->index) {
1069 case MSR_FS_BASE:
1070 case MSR_GS_BASE:
1071 case MSR_KERNEL_GS_BASE:
1072 case MSR_CSTAR:
1073 case MSR_LSTAR:
1074 if (is_noncanonical_address(msr->data))
1075 return 1;
1076 break;
1077 case MSR_IA32_SYSENTER_EIP:
1078 case MSR_IA32_SYSENTER_ESP:
1079 /*
1080 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1081 * non-canonical address is written on Intel but not on
1082 * AMD (which ignores the top 32-bits, because it does
1083 * not implement 64-bit SYSENTER).
1084 *
1085 * 64-bit code should hence be able to write a non-canonical
1086 * value on AMD. Making the address canonical ensures that
1087 * vmentry does not fail on Intel after writing a non-canonical
1088 * value, and that something deterministic happens if the guest
1089 * invokes 64-bit SYSENTER.
1090 */
1091 msr->data = get_canonical(msr->data);
1092 }
1093 return kvm_x86_ops->set_msr(vcpu, msr);
1094 }
1095 EXPORT_SYMBOL_GPL(kvm_set_msr);
1096
1097 /*
1098 * Adapt set_msr() to msr_io()'s calling convention
1099 */
1100 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1101 {
1102 struct msr_data msr;
1103 int r;
1104
1105 msr.index = index;
1106 msr.host_initiated = true;
1107 r = kvm_get_msr(vcpu, &msr);
1108 if (r)
1109 return r;
1110
1111 *data = msr.data;
1112 return 0;
1113 }
1114
1115 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1116 {
1117 struct msr_data msr;
1118
1119 msr.data = *data;
1120 msr.index = index;
1121 msr.host_initiated = true;
1122 return kvm_set_msr(vcpu, &msr);
1123 }
1124
1125 #ifdef CONFIG_X86_64
1126 struct pvclock_gtod_data {
1127 seqcount_t seq;
1128
1129 struct { /* extract of a clocksource struct */
1130 int vclock_mode;
1131 cycle_t cycle_last;
1132 cycle_t mask;
1133 u32 mult;
1134 u32 shift;
1135 } clock;
1136
1137 u64 boot_ns;
1138 u64 nsec_base;
1139 };
1140
1141 static struct pvclock_gtod_data pvclock_gtod_data;
1142
1143 static void update_pvclock_gtod(struct timekeeper *tk)
1144 {
1145 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1146 u64 boot_ns;
1147
1148 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1149
1150 write_seqcount_begin(&vdata->seq);
1151
1152 /* copy pvclock gtod data */
1153 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1154 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1155 vdata->clock.mask = tk->tkr_mono.mask;
1156 vdata->clock.mult = tk->tkr_mono.mult;
1157 vdata->clock.shift = tk->tkr_mono.shift;
1158
1159 vdata->boot_ns = boot_ns;
1160 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1161
1162 write_seqcount_end(&vdata->seq);
1163 }
1164 #endif
1165
1166 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1167 {
1168 /*
1169 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1170 * vcpu_enter_guest. This function is only called from
1171 * the physical CPU that is running vcpu.
1172 */
1173 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1174 }
1175
1176 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1177 {
1178 int version;
1179 int r;
1180 struct pvclock_wall_clock wc;
1181 struct timespec64 boot;
1182
1183 if (!wall_clock)
1184 return;
1185
1186 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1187 if (r)
1188 return;
1189
1190 if (version & 1)
1191 ++version; /* first time write, random junk */
1192
1193 ++version;
1194
1195 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1196 return;
1197
1198 /*
1199 * The guest calculates current wall clock time by adding
1200 * system time (updated by kvm_guest_time_update below) to the
1201 * wall clock specified here. guest system time equals host
1202 * system time for us, thus we must fill in host boot time here.
1203 */
1204 getboottime64(&boot);
1205
1206 if (kvm->arch.kvmclock_offset) {
1207 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1208 boot = timespec64_sub(boot, ts);
1209 }
1210 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1211 wc.nsec = boot.tv_nsec;
1212 wc.version = version;
1213
1214 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1215
1216 version++;
1217 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1218 }
1219
1220 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1221 {
1222 do_shl32_div32(dividend, divisor);
1223 return dividend;
1224 }
1225
1226 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1227 s8 *pshift, u32 *pmultiplier)
1228 {
1229 uint64_t scaled64;
1230 int32_t shift = 0;
1231 uint64_t tps64;
1232 uint32_t tps32;
1233
1234 tps64 = base_hz;
1235 scaled64 = scaled_hz;
1236 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1237 tps64 >>= 1;
1238 shift--;
1239 }
1240
1241 tps32 = (uint32_t)tps64;
1242 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1243 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1244 scaled64 >>= 1;
1245 else
1246 tps32 <<= 1;
1247 shift++;
1248 }
1249
1250 *pshift = shift;
1251 *pmultiplier = div_frac(scaled64, tps32);
1252
1253 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1254 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1255 }
1256
1257 #ifdef CONFIG_X86_64
1258 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1259 #endif
1260
1261 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1262 static unsigned long max_tsc_khz;
1263
1264 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1265 {
1266 u64 v = (u64)khz * (1000000 + ppm);
1267 do_div(v, 1000000);
1268 return v;
1269 }
1270
1271 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1272 {
1273 u64 ratio;
1274
1275 /* Guest TSC same frequency as host TSC? */
1276 if (!scale) {
1277 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1278 return 0;
1279 }
1280
1281 /* TSC scaling supported? */
1282 if (!kvm_has_tsc_control) {
1283 if (user_tsc_khz > tsc_khz) {
1284 vcpu->arch.tsc_catchup = 1;
1285 vcpu->arch.tsc_always_catchup = 1;
1286 return 0;
1287 } else {
1288 WARN(1, "user requested TSC rate below hardware speed\n");
1289 return -1;
1290 }
1291 }
1292
1293 /* TSC scaling required - calculate ratio */
1294 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1295 user_tsc_khz, tsc_khz);
1296
1297 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1298 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1299 user_tsc_khz);
1300 return -1;
1301 }
1302
1303 vcpu->arch.tsc_scaling_ratio = ratio;
1304 return 0;
1305 }
1306
1307 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1308 {
1309 u32 thresh_lo, thresh_hi;
1310 int use_scaling = 0;
1311
1312 /* tsc_khz can be zero if TSC calibration fails */
1313 if (user_tsc_khz == 0) {
1314 /* set tsc_scaling_ratio to a safe value */
1315 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1316 return -1;
1317 }
1318
1319 /* Compute a scale to convert nanoseconds in TSC cycles */
1320 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1321 &vcpu->arch.virtual_tsc_shift,
1322 &vcpu->arch.virtual_tsc_mult);
1323 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1324
1325 /*
1326 * Compute the variation in TSC rate which is acceptable
1327 * within the range of tolerance and decide if the
1328 * rate being applied is within that bounds of the hardware
1329 * rate. If so, no scaling or compensation need be done.
1330 */
1331 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1332 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1333 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1334 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1335 use_scaling = 1;
1336 }
1337 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1338 }
1339
1340 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1341 {
1342 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1343 vcpu->arch.virtual_tsc_mult,
1344 vcpu->arch.virtual_tsc_shift);
1345 tsc += vcpu->arch.this_tsc_write;
1346 return tsc;
1347 }
1348
1349 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1350 {
1351 #ifdef CONFIG_X86_64
1352 bool vcpus_matched;
1353 struct kvm_arch *ka = &vcpu->kvm->arch;
1354 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1355
1356 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1357 atomic_read(&vcpu->kvm->online_vcpus));
1358
1359 /*
1360 * Once the masterclock is enabled, always perform request in
1361 * order to update it.
1362 *
1363 * In order to enable masterclock, the host clocksource must be TSC
1364 * and the vcpus need to have matched TSCs. When that happens,
1365 * perform request to enable masterclock.
1366 */
1367 if (ka->use_master_clock ||
1368 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1369 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1370
1371 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1372 atomic_read(&vcpu->kvm->online_vcpus),
1373 ka->use_master_clock, gtod->clock.vclock_mode);
1374 #endif
1375 }
1376
1377 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1378 {
1379 u64 curr_offset = vcpu->arch.tsc_offset;
1380 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1381 }
1382
1383 /*
1384 * Multiply tsc by a fixed point number represented by ratio.
1385 *
1386 * The most significant 64-N bits (mult) of ratio represent the
1387 * integral part of the fixed point number; the remaining N bits
1388 * (frac) represent the fractional part, ie. ratio represents a fixed
1389 * point number (mult + frac * 2^(-N)).
1390 *
1391 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1392 */
1393 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1394 {
1395 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1396 }
1397
1398 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1399 {
1400 u64 _tsc = tsc;
1401 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1402
1403 if (ratio != kvm_default_tsc_scaling_ratio)
1404 _tsc = __scale_tsc(ratio, tsc);
1405
1406 return _tsc;
1407 }
1408 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1409
1410 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1411 {
1412 u64 tsc;
1413
1414 tsc = kvm_scale_tsc(vcpu, rdtsc());
1415
1416 return target_tsc - tsc;
1417 }
1418
1419 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1420 {
1421 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1422 }
1423 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1424
1425 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1426 {
1427 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1428 vcpu->arch.tsc_offset = offset;
1429 }
1430
1431 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1432 {
1433 struct kvm *kvm = vcpu->kvm;
1434 u64 offset, ns, elapsed;
1435 unsigned long flags;
1436 s64 usdiff;
1437 bool matched;
1438 bool already_matched;
1439 u64 data = msr->data;
1440
1441 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1442 offset = kvm_compute_tsc_offset(vcpu, data);
1443 ns = ktime_get_boot_ns();
1444 elapsed = ns - kvm->arch.last_tsc_nsec;
1445
1446 if (vcpu->arch.virtual_tsc_khz) {
1447 int faulted = 0;
1448
1449 /* n.b - signed multiplication and division required */
1450 usdiff = data - kvm->arch.last_tsc_write;
1451 #ifdef CONFIG_X86_64
1452 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1453 #else
1454 /* do_div() only does unsigned */
1455 asm("1: idivl %[divisor]\n"
1456 "2: xor %%edx, %%edx\n"
1457 " movl $0, %[faulted]\n"
1458 "3:\n"
1459 ".section .fixup,\"ax\"\n"
1460 "4: movl $1, %[faulted]\n"
1461 " jmp 3b\n"
1462 ".previous\n"
1463
1464 _ASM_EXTABLE(1b, 4b)
1465
1466 : "=A"(usdiff), [faulted] "=r" (faulted)
1467 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1468
1469 #endif
1470 do_div(elapsed, 1000);
1471 usdiff -= elapsed;
1472 if (usdiff < 0)
1473 usdiff = -usdiff;
1474
1475 /* idivl overflow => difference is larger than USEC_PER_SEC */
1476 if (faulted)
1477 usdiff = USEC_PER_SEC;
1478 } else
1479 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1480
1481 /*
1482 * Special case: TSC write with a small delta (1 second) of virtual
1483 * cycle time against real time is interpreted as an attempt to
1484 * synchronize the CPU.
1485 *
1486 * For a reliable TSC, we can match TSC offsets, and for an unstable
1487 * TSC, we add elapsed time in this computation. We could let the
1488 * compensation code attempt to catch up if we fall behind, but
1489 * it's better to try to match offsets from the beginning.
1490 */
1491 if (usdiff < USEC_PER_SEC &&
1492 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1493 if (!check_tsc_unstable()) {
1494 offset = kvm->arch.cur_tsc_offset;
1495 pr_debug("kvm: matched tsc offset for %llu\n", data);
1496 } else {
1497 u64 delta = nsec_to_cycles(vcpu, elapsed);
1498 data += delta;
1499 offset = kvm_compute_tsc_offset(vcpu, data);
1500 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1501 }
1502 matched = true;
1503 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1504 } else {
1505 /*
1506 * We split periods of matched TSC writes into generations.
1507 * For each generation, we track the original measured
1508 * nanosecond time, offset, and write, so if TSCs are in
1509 * sync, we can match exact offset, and if not, we can match
1510 * exact software computation in compute_guest_tsc()
1511 *
1512 * These values are tracked in kvm->arch.cur_xxx variables.
1513 */
1514 kvm->arch.cur_tsc_generation++;
1515 kvm->arch.cur_tsc_nsec = ns;
1516 kvm->arch.cur_tsc_write = data;
1517 kvm->arch.cur_tsc_offset = offset;
1518 matched = false;
1519 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1520 kvm->arch.cur_tsc_generation, data);
1521 }
1522
1523 /*
1524 * We also track th most recent recorded KHZ, write and time to
1525 * allow the matching interval to be extended at each write.
1526 */
1527 kvm->arch.last_tsc_nsec = ns;
1528 kvm->arch.last_tsc_write = data;
1529 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1530
1531 vcpu->arch.last_guest_tsc = data;
1532
1533 /* Keep track of which generation this VCPU has synchronized to */
1534 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1535 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1536 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1537
1538 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1539 update_ia32_tsc_adjust_msr(vcpu, offset);
1540 kvm_vcpu_write_tsc_offset(vcpu, offset);
1541 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1542
1543 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1544 if (!matched) {
1545 kvm->arch.nr_vcpus_matched_tsc = 0;
1546 } else if (!already_matched) {
1547 kvm->arch.nr_vcpus_matched_tsc++;
1548 }
1549
1550 kvm_track_tsc_matching(vcpu);
1551 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1552 }
1553
1554 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1555
1556 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1557 s64 adjustment)
1558 {
1559 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1560 }
1561
1562 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1563 {
1564 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1565 WARN_ON(adjustment < 0);
1566 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1567 adjust_tsc_offset_guest(vcpu, adjustment);
1568 }
1569
1570 #ifdef CONFIG_X86_64
1571
1572 static cycle_t read_tsc(void)
1573 {
1574 cycle_t ret = (cycle_t)rdtsc_ordered();
1575 u64 last = pvclock_gtod_data.clock.cycle_last;
1576
1577 if (likely(ret >= last))
1578 return ret;
1579
1580 /*
1581 * GCC likes to generate cmov here, but this branch is extremely
1582 * predictable (it's just a function of time and the likely is
1583 * very likely) and there's a data dependence, so force GCC
1584 * to generate a branch instead. I don't barrier() because
1585 * we don't actually need a barrier, and if this function
1586 * ever gets inlined it will generate worse code.
1587 */
1588 asm volatile ("");
1589 return last;
1590 }
1591
1592 static inline u64 vgettsc(cycle_t *cycle_now)
1593 {
1594 long v;
1595 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1596
1597 *cycle_now = read_tsc();
1598
1599 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1600 return v * gtod->clock.mult;
1601 }
1602
1603 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1604 {
1605 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1606 unsigned long seq;
1607 int mode;
1608 u64 ns;
1609
1610 do {
1611 seq = read_seqcount_begin(&gtod->seq);
1612 mode = gtod->clock.vclock_mode;
1613 ns = gtod->nsec_base;
1614 ns += vgettsc(cycle_now);
1615 ns >>= gtod->clock.shift;
1616 ns += gtod->boot_ns;
1617 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1618 *t = ns;
1619
1620 return mode;
1621 }
1622
1623 /* returns true if host is using tsc clocksource */
1624 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1625 {
1626 /* checked again under seqlock below */
1627 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1628 return false;
1629
1630 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1631 }
1632 #endif
1633
1634 /*
1635 *
1636 * Assuming a stable TSC across physical CPUS, and a stable TSC
1637 * across virtual CPUs, the following condition is possible.
1638 * Each numbered line represents an event visible to both
1639 * CPUs at the next numbered event.
1640 *
1641 * "timespecX" represents host monotonic time. "tscX" represents
1642 * RDTSC value.
1643 *
1644 * VCPU0 on CPU0 | VCPU1 on CPU1
1645 *
1646 * 1. read timespec0,tsc0
1647 * 2. | timespec1 = timespec0 + N
1648 * | tsc1 = tsc0 + M
1649 * 3. transition to guest | transition to guest
1650 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1651 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1652 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1653 *
1654 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1655 *
1656 * - ret0 < ret1
1657 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1658 * ...
1659 * - 0 < N - M => M < N
1660 *
1661 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1662 * always the case (the difference between two distinct xtime instances
1663 * might be smaller then the difference between corresponding TSC reads,
1664 * when updating guest vcpus pvclock areas).
1665 *
1666 * To avoid that problem, do not allow visibility of distinct
1667 * system_timestamp/tsc_timestamp values simultaneously: use a master
1668 * copy of host monotonic time values. Update that master copy
1669 * in lockstep.
1670 *
1671 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1672 *
1673 */
1674
1675 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1676 {
1677 #ifdef CONFIG_X86_64
1678 struct kvm_arch *ka = &kvm->arch;
1679 int vclock_mode;
1680 bool host_tsc_clocksource, vcpus_matched;
1681
1682 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1683 atomic_read(&kvm->online_vcpus));
1684
1685 /*
1686 * If the host uses TSC clock, then passthrough TSC as stable
1687 * to the guest.
1688 */
1689 host_tsc_clocksource = kvm_get_time_and_clockread(
1690 &ka->master_kernel_ns,
1691 &ka->master_cycle_now);
1692
1693 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1694 && !backwards_tsc_observed
1695 && !ka->boot_vcpu_runs_old_kvmclock;
1696
1697 if (ka->use_master_clock)
1698 atomic_set(&kvm_guest_has_master_clock, 1);
1699
1700 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1701 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1702 vcpus_matched);
1703 #endif
1704 }
1705
1706 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1707 {
1708 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1709 }
1710
1711 static void kvm_gen_update_masterclock(struct kvm *kvm)
1712 {
1713 #ifdef CONFIG_X86_64
1714 int i;
1715 struct kvm_vcpu *vcpu;
1716 struct kvm_arch *ka = &kvm->arch;
1717
1718 spin_lock(&ka->pvclock_gtod_sync_lock);
1719 kvm_make_mclock_inprogress_request(kvm);
1720 /* no guest entries from this point */
1721 pvclock_update_vm_gtod_copy(kvm);
1722
1723 kvm_for_each_vcpu(i, vcpu, kvm)
1724 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1725
1726 /* guest entries allowed */
1727 kvm_for_each_vcpu(i, vcpu, kvm)
1728 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1729
1730 spin_unlock(&ka->pvclock_gtod_sync_lock);
1731 #endif
1732 }
1733
1734 static u64 __get_kvmclock_ns(struct kvm *kvm)
1735 {
1736 struct kvm_arch *ka = &kvm->arch;
1737 struct pvclock_vcpu_time_info hv_clock;
1738 u64 ret;
1739
1740 spin_lock(&ka->pvclock_gtod_sync_lock);
1741 if (!ka->use_master_clock) {
1742 spin_unlock(&ka->pvclock_gtod_sync_lock);
1743 return ktime_get_boot_ns() + ka->kvmclock_offset;
1744 }
1745
1746 hv_clock.tsc_timestamp = ka->master_cycle_now;
1747 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1748 spin_unlock(&ka->pvclock_gtod_sync_lock);
1749
1750 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1751 get_cpu();
1752
1753 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1754 &hv_clock.tsc_shift,
1755 &hv_clock.tsc_to_system_mul);
1756 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1757
1758 put_cpu();
1759
1760 return ret;
1761 }
1762
1763 u64 get_kvmclock_ns(struct kvm *kvm)
1764 {
1765 unsigned long flags;
1766 s64 ns;
1767
1768 local_irq_save(flags);
1769 ns = __get_kvmclock_ns(kvm);
1770 local_irq_restore(flags);
1771
1772 return ns;
1773 }
1774
1775 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1776 {
1777 struct kvm_vcpu_arch *vcpu = &v->arch;
1778 struct pvclock_vcpu_time_info guest_hv_clock;
1779
1780 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1781 &guest_hv_clock, sizeof(guest_hv_clock))))
1782 return;
1783
1784 /* This VCPU is paused, but it's legal for a guest to read another
1785 * VCPU's kvmclock, so we really have to follow the specification where
1786 * it says that version is odd if data is being modified, and even after
1787 * it is consistent.
1788 *
1789 * Version field updates must be kept separate. This is because
1790 * kvm_write_guest_cached might use a "rep movs" instruction, and
1791 * writes within a string instruction are weakly ordered. So there
1792 * are three writes overall.
1793 *
1794 * As a small optimization, only write the version field in the first
1795 * and third write. The vcpu->pv_time cache is still valid, because the
1796 * version field is the first in the struct.
1797 */
1798 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1799
1800 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1801 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1802 &vcpu->hv_clock,
1803 sizeof(vcpu->hv_clock.version));
1804
1805 smp_wmb();
1806
1807 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1808 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1809
1810 if (vcpu->pvclock_set_guest_stopped_request) {
1811 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1812 vcpu->pvclock_set_guest_stopped_request = false;
1813 }
1814
1815 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1816
1817 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1818 &vcpu->hv_clock,
1819 sizeof(vcpu->hv_clock));
1820
1821 smp_wmb();
1822
1823 vcpu->hv_clock.version++;
1824 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1825 &vcpu->hv_clock,
1826 sizeof(vcpu->hv_clock.version));
1827 }
1828
1829 static int kvm_guest_time_update(struct kvm_vcpu *v)
1830 {
1831 unsigned long flags, tgt_tsc_khz;
1832 struct kvm_vcpu_arch *vcpu = &v->arch;
1833 struct kvm_arch *ka = &v->kvm->arch;
1834 s64 kernel_ns;
1835 u64 tsc_timestamp, host_tsc;
1836 u8 pvclock_flags;
1837 bool use_master_clock;
1838
1839 kernel_ns = 0;
1840 host_tsc = 0;
1841
1842 /*
1843 * If the host uses TSC clock, then passthrough TSC as stable
1844 * to the guest.
1845 */
1846 spin_lock(&ka->pvclock_gtod_sync_lock);
1847 use_master_clock = ka->use_master_clock;
1848 if (use_master_clock) {
1849 host_tsc = ka->master_cycle_now;
1850 kernel_ns = ka->master_kernel_ns;
1851 }
1852 spin_unlock(&ka->pvclock_gtod_sync_lock);
1853
1854 /* Keep irq disabled to prevent changes to the clock */
1855 local_irq_save(flags);
1856 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1857 if (unlikely(tgt_tsc_khz == 0)) {
1858 local_irq_restore(flags);
1859 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1860 return 1;
1861 }
1862 if (!use_master_clock) {
1863 host_tsc = rdtsc();
1864 kernel_ns = ktime_get_boot_ns();
1865 }
1866
1867 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1868
1869 /*
1870 * We may have to catch up the TSC to match elapsed wall clock
1871 * time for two reasons, even if kvmclock is used.
1872 * 1) CPU could have been running below the maximum TSC rate
1873 * 2) Broken TSC compensation resets the base at each VCPU
1874 * entry to avoid unknown leaps of TSC even when running
1875 * again on the same CPU. This may cause apparent elapsed
1876 * time to disappear, and the guest to stand still or run
1877 * very slowly.
1878 */
1879 if (vcpu->tsc_catchup) {
1880 u64 tsc = compute_guest_tsc(v, kernel_ns);
1881 if (tsc > tsc_timestamp) {
1882 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1883 tsc_timestamp = tsc;
1884 }
1885 }
1886
1887 local_irq_restore(flags);
1888
1889 /* With all the info we got, fill in the values */
1890
1891 if (kvm_has_tsc_control)
1892 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1893
1894 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1895 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1896 &vcpu->hv_clock.tsc_shift,
1897 &vcpu->hv_clock.tsc_to_system_mul);
1898 vcpu->hw_tsc_khz = tgt_tsc_khz;
1899 }
1900
1901 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1902 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1903 vcpu->last_guest_tsc = tsc_timestamp;
1904
1905 /* If the host uses TSC clocksource, then it is stable */
1906 pvclock_flags = 0;
1907 if (use_master_clock)
1908 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1909
1910 vcpu->hv_clock.flags = pvclock_flags;
1911
1912 if (vcpu->pv_time_enabled)
1913 kvm_setup_pvclock_page(v);
1914 if (v == kvm_get_vcpu(v->kvm, 0))
1915 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
1916 return 0;
1917 }
1918
1919 /*
1920 * kvmclock updates which are isolated to a given vcpu, such as
1921 * vcpu->cpu migration, should not allow system_timestamp from
1922 * the rest of the vcpus to remain static. Otherwise ntp frequency
1923 * correction applies to one vcpu's system_timestamp but not
1924 * the others.
1925 *
1926 * So in those cases, request a kvmclock update for all vcpus.
1927 * We need to rate-limit these requests though, as they can
1928 * considerably slow guests that have a large number of vcpus.
1929 * The time for a remote vcpu to update its kvmclock is bound
1930 * by the delay we use to rate-limit the updates.
1931 */
1932
1933 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1934
1935 static void kvmclock_update_fn(struct work_struct *work)
1936 {
1937 int i;
1938 struct delayed_work *dwork = to_delayed_work(work);
1939 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1940 kvmclock_update_work);
1941 struct kvm *kvm = container_of(ka, struct kvm, arch);
1942 struct kvm_vcpu *vcpu;
1943
1944 kvm_for_each_vcpu(i, vcpu, kvm) {
1945 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1946 kvm_vcpu_kick(vcpu);
1947 }
1948 }
1949
1950 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1951 {
1952 struct kvm *kvm = v->kvm;
1953
1954 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1955 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1956 KVMCLOCK_UPDATE_DELAY);
1957 }
1958
1959 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1960
1961 static void kvmclock_sync_fn(struct work_struct *work)
1962 {
1963 struct delayed_work *dwork = to_delayed_work(work);
1964 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1965 kvmclock_sync_work);
1966 struct kvm *kvm = container_of(ka, struct kvm, arch);
1967
1968 if (!kvmclock_periodic_sync)
1969 return;
1970
1971 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1972 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1973 KVMCLOCK_SYNC_PERIOD);
1974 }
1975
1976 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1977 {
1978 u64 mcg_cap = vcpu->arch.mcg_cap;
1979 unsigned bank_num = mcg_cap & 0xff;
1980
1981 switch (msr) {
1982 case MSR_IA32_MCG_STATUS:
1983 vcpu->arch.mcg_status = data;
1984 break;
1985 case MSR_IA32_MCG_CTL:
1986 if (!(mcg_cap & MCG_CTL_P))
1987 return 1;
1988 if (data != 0 && data != ~(u64)0)
1989 return -1;
1990 vcpu->arch.mcg_ctl = data;
1991 break;
1992 default:
1993 if (msr >= MSR_IA32_MC0_CTL &&
1994 msr < MSR_IA32_MCx_CTL(bank_num)) {
1995 u32 offset = msr - MSR_IA32_MC0_CTL;
1996 /* only 0 or all 1s can be written to IA32_MCi_CTL
1997 * some Linux kernels though clear bit 10 in bank 4 to
1998 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1999 * this to avoid an uncatched #GP in the guest
2000 */
2001 if ((offset & 0x3) == 0 &&
2002 data != 0 && (data | (1 << 10)) != ~(u64)0)
2003 return -1;
2004 vcpu->arch.mce_banks[offset] = data;
2005 break;
2006 }
2007 return 1;
2008 }
2009 return 0;
2010 }
2011
2012 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2013 {
2014 struct kvm *kvm = vcpu->kvm;
2015 int lm = is_long_mode(vcpu);
2016 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2017 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2018 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2019 : kvm->arch.xen_hvm_config.blob_size_32;
2020 u32 page_num = data & ~PAGE_MASK;
2021 u64 page_addr = data & PAGE_MASK;
2022 u8 *page;
2023 int r;
2024
2025 r = -E2BIG;
2026 if (page_num >= blob_size)
2027 goto out;
2028 r = -ENOMEM;
2029 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2030 if (IS_ERR(page)) {
2031 r = PTR_ERR(page);
2032 goto out;
2033 }
2034 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2035 goto out_free;
2036 r = 0;
2037 out_free:
2038 kfree(page);
2039 out:
2040 return r;
2041 }
2042
2043 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2044 {
2045 gpa_t gpa = data & ~0x3f;
2046
2047 /* Bits 2:5 are reserved, Should be zero */
2048 if (data & 0x3c)
2049 return 1;
2050
2051 vcpu->arch.apf.msr_val = data;
2052
2053 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2054 kvm_clear_async_pf_completion_queue(vcpu);
2055 kvm_async_pf_hash_reset(vcpu);
2056 return 0;
2057 }
2058
2059 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2060 sizeof(u32)))
2061 return 1;
2062
2063 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2064 kvm_async_pf_wakeup_all(vcpu);
2065 return 0;
2066 }
2067
2068 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2069 {
2070 vcpu->arch.pv_time_enabled = false;
2071 }
2072
2073 static void record_steal_time(struct kvm_vcpu *vcpu)
2074 {
2075 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2076 return;
2077
2078 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2079 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2080 return;
2081
2082 if (vcpu->arch.st.steal.version & 1)
2083 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2084
2085 vcpu->arch.st.steal.version += 1;
2086
2087 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2088 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2089
2090 smp_wmb();
2091
2092 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2093 vcpu->arch.st.last_steal;
2094 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2095
2096 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2097 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2098
2099 smp_wmb();
2100
2101 vcpu->arch.st.steal.version += 1;
2102
2103 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2104 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2105 }
2106
2107 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2108 {
2109 bool pr = false;
2110 u32 msr = msr_info->index;
2111 u64 data = msr_info->data;
2112
2113 switch (msr) {
2114 case MSR_AMD64_NB_CFG:
2115 case MSR_IA32_UCODE_REV:
2116 case MSR_IA32_UCODE_WRITE:
2117 case MSR_VM_HSAVE_PA:
2118 case MSR_AMD64_PATCH_LOADER:
2119 case MSR_AMD64_BU_CFG2:
2120 break;
2121
2122 case MSR_EFER:
2123 return set_efer(vcpu, data);
2124 case MSR_K7_HWCR:
2125 data &= ~(u64)0x40; /* ignore flush filter disable */
2126 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2127 data &= ~(u64)0x8; /* ignore TLB cache disable */
2128 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2129 if (data != 0) {
2130 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2131 data);
2132 return 1;
2133 }
2134 break;
2135 case MSR_FAM10H_MMIO_CONF_BASE:
2136 if (data != 0) {
2137 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2138 "0x%llx\n", data);
2139 return 1;
2140 }
2141 break;
2142 case MSR_IA32_DEBUGCTLMSR:
2143 if (!data) {
2144 /* We support the non-activated case already */
2145 break;
2146 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2147 /* Values other than LBR and BTF are vendor-specific,
2148 thus reserved and should throw a #GP */
2149 return 1;
2150 }
2151 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2152 __func__, data);
2153 break;
2154 case 0x200 ... 0x2ff:
2155 return kvm_mtrr_set_msr(vcpu, msr, data);
2156 case MSR_IA32_APICBASE:
2157 return kvm_set_apic_base(vcpu, msr_info);
2158 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2159 return kvm_x2apic_msr_write(vcpu, msr, data);
2160 case MSR_IA32_TSCDEADLINE:
2161 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2162 break;
2163 case MSR_IA32_TSC_ADJUST:
2164 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2165 if (!msr_info->host_initiated) {
2166 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2167 adjust_tsc_offset_guest(vcpu, adj);
2168 }
2169 vcpu->arch.ia32_tsc_adjust_msr = data;
2170 }
2171 break;
2172 case MSR_IA32_MISC_ENABLE:
2173 vcpu->arch.ia32_misc_enable_msr = data;
2174 break;
2175 case MSR_IA32_SMBASE:
2176 if (!msr_info->host_initiated)
2177 return 1;
2178 vcpu->arch.smbase = data;
2179 break;
2180 case MSR_KVM_WALL_CLOCK_NEW:
2181 case MSR_KVM_WALL_CLOCK:
2182 vcpu->kvm->arch.wall_clock = data;
2183 kvm_write_wall_clock(vcpu->kvm, data);
2184 break;
2185 case MSR_KVM_SYSTEM_TIME_NEW:
2186 case MSR_KVM_SYSTEM_TIME: {
2187 u64 gpa_offset;
2188 struct kvm_arch *ka = &vcpu->kvm->arch;
2189
2190 kvmclock_reset(vcpu);
2191
2192 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2193 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2194
2195 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2196 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2197 &vcpu->requests);
2198
2199 ka->boot_vcpu_runs_old_kvmclock = tmp;
2200 }
2201
2202 vcpu->arch.time = data;
2203 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2204
2205 /* we verify if the enable bit is set... */
2206 if (!(data & 1))
2207 break;
2208
2209 gpa_offset = data & ~(PAGE_MASK | 1);
2210
2211 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2212 &vcpu->arch.pv_time, data & ~1ULL,
2213 sizeof(struct pvclock_vcpu_time_info)))
2214 vcpu->arch.pv_time_enabled = false;
2215 else
2216 vcpu->arch.pv_time_enabled = true;
2217
2218 break;
2219 }
2220 case MSR_KVM_ASYNC_PF_EN:
2221 if (kvm_pv_enable_async_pf(vcpu, data))
2222 return 1;
2223 break;
2224 case MSR_KVM_STEAL_TIME:
2225
2226 if (unlikely(!sched_info_on()))
2227 return 1;
2228
2229 if (data & KVM_STEAL_RESERVED_MASK)
2230 return 1;
2231
2232 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2233 data & KVM_STEAL_VALID_BITS,
2234 sizeof(struct kvm_steal_time)))
2235 return 1;
2236
2237 vcpu->arch.st.msr_val = data;
2238
2239 if (!(data & KVM_MSR_ENABLED))
2240 break;
2241
2242 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2243
2244 break;
2245 case MSR_KVM_PV_EOI_EN:
2246 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2247 return 1;
2248 break;
2249
2250 case MSR_IA32_MCG_CTL:
2251 case MSR_IA32_MCG_STATUS:
2252 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2253 return set_msr_mce(vcpu, msr, data);
2254
2255 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2256 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2257 pr = true; /* fall through */
2258 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2259 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2260 if (kvm_pmu_is_valid_msr(vcpu, msr))
2261 return kvm_pmu_set_msr(vcpu, msr_info);
2262
2263 if (pr || data != 0)
2264 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2265 "0x%x data 0x%llx\n", msr, data);
2266 break;
2267 case MSR_K7_CLK_CTL:
2268 /*
2269 * Ignore all writes to this no longer documented MSR.
2270 * Writes are only relevant for old K7 processors,
2271 * all pre-dating SVM, but a recommended workaround from
2272 * AMD for these chips. It is possible to specify the
2273 * affected processor models on the command line, hence
2274 * the need to ignore the workaround.
2275 */
2276 break;
2277 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2278 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2279 case HV_X64_MSR_CRASH_CTL:
2280 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2281 return kvm_hv_set_msr_common(vcpu, msr, data,
2282 msr_info->host_initiated);
2283 case MSR_IA32_BBL_CR_CTL3:
2284 /* Drop writes to this legacy MSR -- see rdmsr
2285 * counterpart for further detail.
2286 */
2287 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
2288 break;
2289 case MSR_AMD64_OSVW_ID_LENGTH:
2290 if (!guest_cpuid_has_osvw(vcpu))
2291 return 1;
2292 vcpu->arch.osvw.length = data;
2293 break;
2294 case MSR_AMD64_OSVW_STATUS:
2295 if (!guest_cpuid_has_osvw(vcpu))
2296 return 1;
2297 vcpu->arch.osvw.status = data;
2298 break;
2299 default:
2300 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2301 return xen_hvm_config(vcpu, data);
2302 if (kvm_pmu_is_valid_msr(vcpu, msr))
2303 return kvm_pmu_set_msr(vcpu, msr_info);
2304 if (!ignore_msrs) {
2305 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2306 msr, data);
2307 return 1;
2308 } else {
2309 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2310 msr, data);
2311 break;
2312 }
2313 }
2314 return 0;
2315 }
2316 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2317
2318
2319 /*
2320 * Reads an msr value (of 'msr_index') into 'pdata'.
2321 * Returns 0 on success, non-0 otherwise.
2322 * Assumes vcpu_load() was already called.
2323 */
2324 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2325 {
2326 return kvm_x86_ops->get_msr(vcpu, msr);
2327 }
2328 EXPORT_SYMBOL_GPL(kvm_get_msr);
2329
2330 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2331 {
2332 u64 data;
2333 u64 mcg_cap = vcpu->arch.mcg_cap;
2334 unsigned bank_num = mcg_cap & 0xff;
2335
2336 switch (msr) {
2337 case MSR_IA32_P5_MC_ADDR:
2338 case MSR_IA32_P5_MC_TYPE:
2339 data = 0;
2340 break;
2341 case MSR_IA32_MCG_CAP:
2342 data = vcpu->arch.mcg_cap;
2343 break;
2344 case MSR_IA32_MCG_CTL:
2345 if (!(mcg_cap & MCG_CTL_P))
2346 return 1;
2347 data = vcpu->arch.mcg_ctl;
2348 break;
2349 case MSR_IA32_MCG_STATUS:
2350 data = vcpu->arch.mcg_status;
2351 break;
2352 default:
2353 if (msr >= MSR_IA32_MC0_CTL &&
2354 msr < MSR_IA32_MCx_CTL(bank_num)) {
2355 u32 offset = msr - MSR_IA32_MC0_CTL;
2356 data = vcpu->arch.mce_banks[offset];
2357 break;
2358 }
2359 return 1;
2360 }
2361 *pdata = data;
2362 return 0;
2363 }
2364
2365 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2366 {
2367 switch (msr_info->index) {
2368 case MSR_IA32_PLATFORM_ID:
2369 case MSR_IA32_EBL_CR_POWERON:
2370 case MSR_IA32_DEBUGCTLMSR:
2371 case MSR_IA32_LASTBRANCHFROMIP:
2372 case MSR_IA32_LASTBRANCHTOIP:
2373 case MSR_IA32_LASTINTFROMIP:
2374 case MSR_IA32_LASTINTTOIP:
2375 case MSR_K8_SYSCFG:
2376 case MSR_K8_TSEG_ADDR:
2377 case MSR_K8_TSEG_MASK:
2378 case MSR_K7_HWCR:
2379 case MSR_VM_HSAVE_PA:
2380 case MSR_K8_INT_PENDING_MSG:
2381 case MSR_AMD64_NB_CFG:
2382 case MSR_FAM10H_MMIO_CONF_BASE:
2383 case MSR_AMD64_BU_CFG2:
2384 case MSR_IA32_PERF_CTL:
2385 msr_info->data = 0;
2386 break;
2387 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2388 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2389 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2390 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2391 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2392 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2393 msr_info->data = 0;
2394 break;
2395 case MSR_IA32_UCODE_REV:
2396 msr_info->data = 0x100000000ULL;
2397 break;
2398 case MSR_MTRRcap:
2399 case 0x200 ... 0x2ff:
2400 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2401 case 0xcd: /* fsb frequency */
2402 msr_info->data = 3;
2403 break;
2404 /*
2405 * MSR_EBC_FREQUENCY_ID
2406 * Conservative value valid for even the basic CPU models.
2407 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2408 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2409 * and 266MHz for model 3, or 4. Set Core Clock
2410 * Frequency to System Bus Frequency Ratio to 1 (bits
2411 * 31:24) even though these are only valid for CPU
2412 * models > 2, however guests may end up dividing or
2413 * multiplying by zero otherwise.
2414 */
2415 case MSR_EBC_FREQUENCY_ID:
2416 msr_info->data = 1 << 24;
2417 break;
2418 case MSR_IA32_APICBASE:
2419 msr_info->data = kvm_get_apic_base(vcpu);
2420 break;
2421 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2422 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2423 break;
2424 case MSR_IA32_TSCDEADLINE:
2425 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2426 break;
2427 case MSR_IA32_TSC_ADJUST:
2428 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2429 break;
2430 case MSR_IA32_MISC_ENABLE:
2431 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2432 break;
2433 case MSR_IA32_SMBASE:
2434 if (!msr_info->host_initiated)
2435 return 1;
2436 msr_info->data = vcpu->arch.smbase;
2437 break;
2438 case MSR_IA32_PERF_STATUS:
2439 /* TSC increment by tick */
2440 msr_info->data = 1000ULL;
2441 /* CPU multiplier */
2442 msr_info->data |= (((uint64_t)4ULL) << 40);
2443 break;
2444 case MSR_EFER:
2445 msr_info->data = vcpu->arch.efer;
2446 break;
2447 case MSR_KVM_WALL_CLOCK:
2448 case MSR_KVM_WALL_CLOCK_NEW:
2449 msr_info->data = vcpu->kvm->arch.wall_clock;
2450 break;
2451 case MSR_KVM_SYSTEM_TIME:
2452 case MSR_KVM_SYSTEM_TIME_NEW:
2453 msr_info->data = vcpu->arch.time;
2454 break;
2455 case MSR_KVM_ASYNC_PF_EN:
2456 msr_info->data = vcpu->arch.apf.msr_val;
2457 break;
2458 case MSR_KVM_STEAL_TIME:
2459 msr_info->data = vcpu->arch.st.msr_val;
2460 break;
2461 case MSR_KVM_PV_EOI_EN:
2462 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2463 break;
2464 case MSR_IA32_P5_MC_ADDR:
2465 case MSR_IA32_P5_MC_TYPE:
2466 case MSR_IA32_MCG_CAP:
2467 case MSR_IA32_MCG_CTL:
2468 case MSR_IA32_MCG_STATUS:
2469 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2470 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2471 case MSR_K7_CLK_CTL:
2472 /*
2473 * Provide expected ramp-up count for K7. All other
2474 * are set to zero, indicating minimum divisors for
2475 * every field.
2476 *
2477 * This prevents guest kernels on AMD host with CPU
2478 * type 6, model 8 and higher from exploding due to
2479 * the rdmsr failing.
2480 */
2481 msr_info->data = 0x20000000;
2482 break;
2483 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2484 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2485 case HV_X64_MSR_CRASH_CTL:
2486 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2487 return kvm_hv_get_msr_common(vcpu,
2488 msr_info->index, &msr_info->data);
2489 break;
2490 case MSR_IA32_BBL_CR_CTL3:
2491 /* This legacy MSR exists but isn't fully documented in current
2492 * silicon. It is however accessed by winxp in very narrow
2493 * scenarios where it sets bit #19, itself documented as
2494 * a "reserved" bit. Best effort attempt to source coherent
2495 * read data here should the balance of the register be
2496 * interpreted by the guest:
2497 *
2498 * L2 cache control register 3: 64GB range, 256KB size,
2499 * enabled, latency 0x1, configured
2500 */
2501 msr_info->data = 0xbe702111;
2502 break;
2503 case MSR_AMD64_OSVW_ID_LENGTH:
2504 if (!guest_cpuid_has_osvw(vcpu))
2505 return 1;
2506 msr_info->data = vcpu->arch.osvw.length;
2507 break;
2508 case MSR_AMD64_OSVW_STATUS:
2509 if (!guest_cpuid_has_osvw(vcpu))
2510 return 1;
2511 msr_info->data = vcpu->arch.osvw.status;
2512 break;
2513 default:
2514 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2515 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2516 if (!ignore_msrs) {
2517 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2518 return 1;
2519 } else {
2520 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2521 msr_info->data = 0;
2522 }
2523 break;
2524 }
2525 return 0;
2526 }
2527 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2528
2529 /*
2530 * Read or write a bunch of msrs. All parameters are kernel addresses.
2531 *
2532 * @return number of msrs set successfully.
2533 */
2534 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2535 struct kvm_msr_entry *entries,
2536 int (*do_msr)(struct kvm_vcpu *vcpu,
2537 unsigned index, u64 *data))
2538 {
2539 int i, idx;
2540
2541 idx = srcu_read_lock(&vcpu->kvm->srcu);
2542 for (i = 0; i < msrs->nmsrs; ++i)
2543 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2544 break;
2545 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2546
2547 return i;
2548 }
2549
2550 /*
2551 * Read or write a bunch of msrs. Parameters are user addresses.
2552 *
2553 * @return number of msrs set successfully.
2554 */
2555 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2556 int (*do_msr)(struct kvm_vcpu *vcpu,
2557 unsigned index, u64 *data),
2558 int writeback)
2559 {
2560 struct kvm_msrs msrs;
2561 struct kvm_msr_entry *entries;
2562 int r, n;
2563 unsigned size;
2564
2565 r = -EFAULT;
2566 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2567 goto out;
2568
2569 r = -E2BIG;
2570 if (msrs.nmsrs >= MAX_IO_MSRS)
2571 goto out;
2572
2573 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2574 entries = memdup_user(user_msrs->entries, size);
2575 if (IS_ERR(entries)) {
2576 r = PTR_ERR(entries);
2577 goto out;
2578 }
2579
2580 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2581 if (r < 0)
2582 goto out_free;
2583
2584 r = -EFAULT;
2585 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2586 goto out_free;
2587
2588 r = n;
2589
2590 out_free:
2591 kfree(entries);
2592 out:
2593 return r;
2594 }
2595
2596 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2597 {
2598 int r;
2599
2600 switch (ext) {
2601 case KVM_CAP_IRQCHIP:
2602 case KVM_CAP_HLT:
2603 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2604 case KVM_CAP_SET_TSS_ADDR:
2605 case KVM_CAP_EXT_CPUID:
2606 case KVM_CAP_EXT_EMUL_CPUID:
2607 case KVM_CAP_CLOCKSOURCE:
2608 case KVM_CAP_PIT:
2609 case KVM_CAP_NOP_IO_DELAY:
2610 case KVM_CAP_MP_STATE:
2611 case KVM_CAP_SYNC_MMU:
2612 case KVM_CAP_USER_NMI:
2613 case KVM_CAP_REINJECT_CONTROL:
2614 case KVM_CAP_IRQ_INJECT_STATUS:
2615 case KVM_CAP_IOEVENTFD:
2616 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2617 case KVM_CAP_PIT2:
2618 case KVM_CAP_PIT_STATE2:
2619 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2620 case KVM_CAP_XEN_HVM:
2621 case KVM_CAP_VCPU_EVENTS:
2622 case KVM_CAP_HYPERV:
2623 case KVM_CAP_HYPERV_VAPIC:
2624 case KVM_CAP_HYPERV_SPIN:
2625 case KVM_CAP_HYPERV_SYNIC:
2626 case KVM_CAP_PCI_SEGMENT:
2627 case KVM_CAP_DEBUGREGS:
2628 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2629 case KVM_CAP_XSAVE:
2630 case KVM_CAP_ASYNC_PF:
2631 case KVM_CAP_GET_TSC_KHZ:
2632 case KVM_CAP_KVMCLOCK_CTRL:
2633 case KVM_CAP_READONLY_MEM:
2634 case KVM_CAP_HYPERV_TIME:
2635 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2636 case KVM_CAP_TSC_DEADLINE_TIMER:
2637 case KVM_CAP_ENABLE_CAP_VM:
2638 case KVM_CAP_DISABLE_QUIRKS:
2639 case KVM_CAP_SET_BOOT_CPU_ID:
2640 case KVM_CAP_SPLIT_IRQCHIP:
2641 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2642 case KVM_CAP_ASSIGN_DEV_IRQ:
2643 case KVM_CAP_PCI_2_3:
2644 #endif
2645 r = 1;
2646 break;
2647 case KVM_CAP_ADJUST_CLOCK:
2648 r = KVM_CLOCK_TSC_STABLE;
2649 break;
2650 case KVM_CAP_X86_SMM:
2651 /* SMBASE is usually relocated above 1M on modern chipsets,
2652 * and SMM handlers might indeed rely on 4G segment limits,
2653 * so do not report SMM to be available if real mode is
2654 * emulated via vm86 mode. Still, do not go to great lengths
2655 * to avoid userspace's usage of the feature, because it is a
2656 * fringe case that is not enabled except via specific settings
2657 * of the module parameters.
2658 */
2659 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2660 break;
2661 case KVM_CAP_COALESCED_MMIO:
2662 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2663 break;
2664 case KVM_CAP_VAPIC:
2665 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2666 break;
2667 case KVM_CAP_NR_VCPUS:
2668 r = KVM_SOFT_MAX_VCPUS;
2669 break;
2670 case KVM_CAP_MAX_VCPUS:
2671 r = KVM_MAX_VCPUS;
2672 break;
2673 case KVM_CAP_NR_MEMSLOTS:
2674 r = KVM_USER_MEM_SLOTS;
2675 break;
2676 case KVM_CAP_PV_MMU: /* obsolete */
2677 r = 0;
2678 break;
2679 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2680 case KVM_CAP_IOMMU:
2681 r = iommu_present(&pci_bus_type);
2682 break;
2683 #endif
2684 case KVM_CAP_MCE:
2685 r = KVM_MAX_MCE_BANKS;
2686 break;
2687 case KVM_CAP_XCRS:
2688 r = boot_cpu_has(X86_FEATURE_XSAVE);
2689 break;
2690 case KVM_CAP_TSC_CONTROL:
2691 r = kvm_has_tsc_control;
2692 break;
2693 case KVM_CAP_X2APIC_API:
2694 r = KVM_X2APIC_API_VALID_FLAGS;
2695 break;
2696 default:
2697 r = 0;
2698 break;
2699 }
2700 return r;
2701
2702 }
2703
2704 long kvm_arch_dev_ioctl(struct file *filp,
2705 unsigned int ioctl, unsigned long arg)
2706 {
2707 void __user *argp = (void __user *)arg;
2708 long r;
2709
2710 switch (ioctl) {
2711 case KVM_GET_MSR_INDEX_LIST: {
2712 struct kvm_msr_list __user *user_msr_list = argp;
2713 struct kvm_msr_list msr_list;
2714 unsigned n;
2715
2716 r = -EFAULT;
2717 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2718 goto out;
2719 n = msr_list.nmsrs;
2720 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2721 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2722 goto out;
2723 r = -E2BIG;
2724 if (n < msr_list.nmsrs)
2725 goto out;
2726 r = -EFAULT;
2727 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2728 num_msrs_to_save * sizeof(u32)))
2729 goto out;
2730 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2731 &emulated_msrs,
2732 num_emulated_msrs * sizeof(u32)))
2733 goto out;
2734 r = 0;
2735 break;
2736 }
2737 case KVM_GET_SUPPORTED_CPUID:
2738 case KVM_GET_EMULATED_CPUID: {
2739 struct kvm_cpuid2 __user *cpuid_arg = argp;
2740 struct kvm_cpuid2 cpuid;
2741
2742 r = -EFAULT;
2743 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2744 goto out;
2745
2746 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2747 ioctl);
2748 if (r)
2749 goto out;
2750
2751 r = -EFAULT;
2752 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2753 goto out;
2754 r = 0;
2755 break;
2756 }
2757 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2758 r = -EFAULT;
2759 if (copy_to_user(argp, &kvm_mce_cap_supported,
2760 sizeof(kvm_mce_cap_supported)))
2761 goto out;
2762 r = 0;
2763 break;
2764 }
2765 default:
2766 r = -EINVAL;
2767 }
2768 out:
2769 return r;
2770 }
2771
2772 static void wbinvd_ipi(void *garbage)
2773 {
2774 wbinvd();
2775 }
2776
2777 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2778 {
2779 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2780 }
2781
2782 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2783 {
2784 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2785 }
2786
2787 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2788 {
2789 /* Address WBINVD may be executed by guest */
2790 if (need_emulate_wbinvd(vcpu)) {
2791 if (kvm_x86_ops->has_wbinvd_exit())
2792 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2793 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2794 smp_call_function_single(vcpu->cpu,
2795 wbinvd_ipi, NULL, 1);
2796 }
2797
2798 kvm_x86_ops->vcpu_load(vcpu, cpu);
2799
2800 /* Apply any externally detected TSC adjustments (due to suspend) */
2801 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2802 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2803 vcpu->arch.tsc_offset_adjustment = 0;
2804 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2805 }
2806
2807 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2808 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2809 rdtsc() - vcpu->arch.last_host_tsc;
2810 if (tsc_delta < 0)
2811 mark_tsc_unstable("KVM discovered backwards TSC");
2812
2813 if (check_tsc_unstable()) {
2814 u64 offset = kvm_compute_tsc_offset(vcpu,
2815 vcpu->arch.last_guest_tsc);
2816 kvm_vcpu_write_tsc_offset(vcpu, offset);
2817 vcpu->arch.tsc_catchup = 1;
2818 }
2819 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2820 kvm_x86_ops->set_hv_timer(vcpu,
2821 kvm_get_lapic_tscdeadline_msr(vcpu)))
2822 kvm_lapic_switch_to_sw_timer(vcpu);
2823 /*
2824 * On a host with synchronized TSC, there is no need to update
2825 * kvmclock on vcpu->cpu migration
2826 */
2827 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2828 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2829 if (vcpu->cpu != cpu)
2830 kvm_migrate_timers(vcpu);
2831 vcpu->cpu = cpu;
2832 }
2833
2834 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2835 }
2836
2837 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2838 {
2839 kvm_x86_ops->vcpu_put(vcpu);
2840 kvm_put_guest_fpu(vcpu);
2841 vcpu->arch.last_host_tsc = rdtsc();
2842 }
2843
2844 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2845 struct kvm_lapic_state *s)
2846 {
2847 if (vcpu->arch.apicv_active)
2848 kvm_x86_ops->sync_pir_to_irr(vcpu);
2849
2850 return kvm_apic_get_state(vcpu, s);
2851 }
2852
2853 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2854 struct kvm_lapic_state *s)
2855 {
2856 int r;
2857
2858 r = kvm_apic_set_state(vcpu, s);
2859 if (r)
2860 return r;
2861 update_cr8_intercept(vcpu);
2862
2863 return 0;
2864 }
2865
2866 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2867 {
2868 return (!lapic_in_kernel(vcpu) ||
2869 kvm_apic_accept_pic_intr(vcpu));
2870 }
2871
2872 /*
2873 * if userspace requested an interrupt window, check that the
2874 * interrupt window is open.
2875 *
2876 * No need to exit to userspace if we already have an interrupt queued.
2877 */
2878 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2879 {
2880 return kvm_arch_interrupt_allowed(vcpu) &&
2881 !kvm_cpu_has_interrupt(vcpu) &&
2882 !kvm_event_needs_reinjection(vcpu) &&
2883 kvm_cpu_accept_dm_intr(vcpu);
2884 }
2885
2886 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2887 struct kvm_interrupt *irq)
2888 {
2889 if (irq->irq >= KVM_NR_INTERRUPTS)
2890 return -EINVAL;
2891
2892 if (!irqchip_in_kernel(vcpu->kvm)) {
2893 kvm_queue_interrupt(vcpu, irq->irq, false);
2894 kvm_make_request(KVM_REQ_EVENT, vcpu);
2895 return 0;
2896 }
2897
2898 /*
2899 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2900 * fail for in-kernel 8259.
2901 */
2902 if (pic_in_kernel(vcpu->kvm))
2903 return -ENXIO;
2904
2905 if (vcpu->arch.pending_external_vector != -1)
2906 return -EEXIST;
2907
2908 vcpu->arch.pending_external_vector = irq->irq;
2909 kvm_make_request(KVM_REQ_EVENT, vcpu);
2910 return 0;
2911 }
2912
2913 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2914 {
2915 kvm_inject_nmi(vcpu);
2916
2917 return 0;
2918 }
2919
2920 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2921 {
2922 kvm_make_request(KVM_REQ_SMI, vcpu);
2923
2924 return 0;
2925 }
2926
2927 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2928 struct kvm_tpr_access_ctl *tac)
2929 {
2930 if (tac->flags)
2931 return -EINVAL;
2932 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2933 return 0;
2934 }
2935
2936 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2937 u64 mcg_cap)
2938 {
2939 int r;
2940 unsigned bank_num = mcg_cap & 0xff, bank;
2941
2942 r = -EINVAL;
2943 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2944 goto out;
2945 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
2946 goto out;
2947 r = 0;
2948 vcpu->arch.mcg_cap = mcg_cap;
2949 /* Init IA32_MCG_CTL to all 1s */
2950 if (mcg_cap & MCG_CTL_P)
2951 vcpu->arch.mcg_ctl = ~(u64)0;
2952 /* Init IA32_MCi_CTL to all 1s */
2953 for (bank = 0; bank < bank_num; bank++)
2954 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2955
2956 if (kvm_x86_ops->setup_mce)
2957 kvm_x86_ops->setup_mce(vcpu);
2958 out:
2959 return r;
2960 }
2961
2962 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2963 struct kvm_x86_mce *mce)
2964 {
2965 u64 mcg_cap = vcpu->arch.mcg_cap;
2966 unsigned bank_num = mcg_cap & 0xff;
2967 u64 *banks = vcpu->arch.mce_banks;
2968
2969 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2970 return -EINVAL;
2971 /*
2972 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2973 * reporting is disabled
2974 */
2975 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2976 vcpu->arch.mcg_ctl != ~(u64)0)
2977 return 0;
2978 banks += 4 * mce->bank;
2979 /*
2980 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2981 * reporting is disabled for the bank
2982 */
2983 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2984 return 0;
2985 if (mce->status & MCI_STATUS_UC) {
2986 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2987 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2988 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2989 return 0;
2990 }
2991 if (banks[1] & MCI_STATUS_VAL)
2992 mce->status |= MCI_STATUS_OVER;
2993 banks[2] = mce->addr;
2994 banks[3] = mce->misc;
2995 vcpu->arch.mcg_status = mce->mcg_status;
2996 banks[1] = mce->status;
2997 kvm_queue_exception(vcpu, MC_VECTOR);
2998 } else if (!(banks[1] & MCI_STATUS_VAL)
2999 || !(banks[1] & MCI_STATUS_UC)) {
3000 if (banks[1] & MCI_STATUS_VAL)
3001 mce->status |= MCI_STATUS_OVER;
3002 banks[2] = mce->addr;
3003 banks[3] = mce->misc;
3004 banks[1] = mce->status;
3005 } else
3006 banks[1] |= MCI_STATUS_OVER;
3007 return 0;
3008 }
3009
3010 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3011 struct kvm_vcpu_events *events)
3012 {
3013 process_nmi(vcpu);
3014 events->exception.injected =
3015 vcpu->arch.exception.pending &&
3016 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3017 events->exception.nr = vcpu->arch.exception.nr;
3018 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3019 events->exception.pad = 0;
3020 events->exception.error_code = vcpu->arch.exception.error_code;
3021
3022 events->interrupt.injected =
3023 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3024 events->interrupt.nr = vcpu->arch.interrupt.nr;
3025 events->interrupt.soft = 0;
3026 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3027
3028 events->nmi.injected = vcpu->arch.nmi_injected;
3029 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3030 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3031 events->nmi.pad = 0;
3032
3033 events->sipi_vector = 0; /* never valid when reporting to user space */
3034
3035 events->smi.smm = is_smm(vcpu);
3036 events->smi.pending = vcpu->arch.smi_pending;
3037 events->smi.smm_inside_nmi =
3038 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3039 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3040
3041 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3042 | KVM_VCPUEVENT_VALID_SHADOW
3043 | KVM_VCPUEVENT_VALID_SMM);
3044 memset(&events->reserved, 0, sizeof(events->reserved));
3045 }
3046
3047 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3048
3049 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3050 struct kvm_vcpu_events *events)
3051 {
3052 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3053 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3054 | KVM_VCPUEVENT_VALID_SHADOW
3055 | KVM_VCPUEVENT_VALID_SMM))
3056 return -EINVAL;
3057
3058 if (events->exception.injected &&
3059 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3060 return -EINVAL;
3061
3062 /* INITs are latched while in SMM */
3063 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3064 (events->smi.smm || events->smi.pending) &&
3065 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3066 return -EINVAL;
3067
3068 process_nmi(vcpu);
3069 vcpu->arch.exception.pending = events->exception.injected;
3070 vcpu->arch.exception.nr = events->exception.nr;
3071 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3072 vcpu->arch.exception.error_code = events->exception.error_code;
3073
3074 vcpu->arch.interrupt.pending = events->interrupt.injected;
3075 vcpu->arch.interrupt.nr = events->interrupt.nr;
3076 vcpu->arch.interrupt.soft = events->interrupt.soft;
3077 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3078 kvm_x86_ops->set_interrupt_shadow(vcpu,
3079 events->interrupt.shadow);
3080
3081 vcpu->arch.nmi_injected = events->nmi.injected;
3082 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3083 vcpu->arch.nmi_pending = events->nmi.pending;
3084 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3085
3086 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3087 lapic_in_kernel(vcpu))
3088 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3089
3090 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3091 u32 hflags = vcpu->arch.hflags;
3092 if (events->smi.smm)
3093 hflags |= HF_SMM_MASK;
3094 else
3095 hflags &= ~HF_SMM_MASK;
3096 kvm_set_hflags(vcpu, hflags);
3097
3098 vcpu->arch.smi_pending = events->smi.pending;
3099 if (events->smi.smm_inside_nmi)
3100 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3101 else
3102 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3103 if (lapic_in_kernel(vcpu)) {
3104 if (events->smi.latched_init)
3105 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3106 else
3107 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3108 }
3109 }
3110
3111 kvm_make_request(KVM_REQ_EVENT, vcpu);
3112
3113 return 0;
3114 }
3115
3116 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3117 struct kvm_debugregs *dbgregs)
3118 {
3119 unsigned long val;
3120
3121 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3122 kvm_get_dr(vcpu, 6, &val);
3123 dbgregs->dr6 = val;
3124 dbgregs->dr7 = vcpu->arch.dr7;
3125 dbgregs->flags = 0;
3126 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3127 }
3128
3129 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3130 struct kvm_debugregs *dbgregs)
3131 {
3132 if (dbgregs->flags)
3133 return -EINVAL;
3134
3135 if (dbgregs->dr6 & ~0xffffffffull)
3136 return -EINVAL;
3137 if (dbgregs->dr7 & ~0xffffffffull)
3138 return -EINVAL;
3139
3140 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3141 kvm_update_dr0123(vcpu);
3142 vcpu->arch.dr6 = dbgregs->dr6;
3143 kvm_update_dr6(vcpu);
3144 vcpu->arch.dr7 = dbgregs->dr7;
3145 kvm_update_dr7(vcpu);
3146
3147 return 0;
3148 }
3149
3150 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3151
3152 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3153 {
3154 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3155 u64 xstate_bv = xsave->header.xfeatures;
3156 u64 valid;
3157
3158 /*
3159 * Copy legacy XSAVE area, to avoid complications with CPUID
3160 * leaves 0 and 1 in the loop below.
3161 */
3162 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3163
3164 /* Set XSTATE_BV */
3165 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3166 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3167
3168 /*
3169 * Copy each region from the possibly compacted offset to the
3170 * non-compacted offset.
3171 */
3172 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3173 while (valid) {
3174 u64 feature = valid & -valid;
3175 int index = fls64(feature) - 1;
3176 void *src = get_xsave_addr(xsave, feature);
3177
3178 if (src) {
3179 u32 size, offset, ecx, edx;
3180 cpuid_count(XSTATE_CPUID, index,
3181 &size, &offset, &ecx, &edx);
3182 memcpy(dest + offset, src, size);
3183 }
3184
3185 valid -= feature;
3186 }
3187 }
3188
3189 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3190 {
3191 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3192 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3193 u64 valid;
3194
3195 /*
3196 * Copy legacy XSAVE area, to avoid complications with CPUID
3197 * leaves 0 and 1 in the loop below.
3198 */
3199 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3200
3201 /* Set XSTATE_BV and possibly XCOMP_BV. */
3202 xsave->header.xfeatures = xstate_bv;
3203 if (boot_cpu_has(X86_FEATURE_XSAVES))
3204 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3205
3206 /*
3207 * Copy each region from the non-compacted offset to the
3208 * possibly compacted offset.
3209 */
3210 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3211 while (valid) {
3212 u64 feature = valid & -valid;
3213 int index = fls64(feature) - 1;
3214 void *dest = get_xsave_addr(xsave, feature);
3215
3216 if (dest) {
3217 u32 size, offset, ecx, edx;
3218 cpuid_count(XSTATE_CPUID, index,
3219 &size, &offset, &ecx, &edx);
3220 memcpy(dest, src + offset, size);
3221 }
3222
3223 valid -= feature;
3224 }
3225 }
3226
3227 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3228 struct kvm_xsave *guest_xsave)
3229 {
3230 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3231 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3232 fill_xsave((u8 *) guest_xsave->region, vcpu);
3233 } else {
3234 memcpy(guest_xsave->region,
3235 &vcpu->arch.guest_fpu.state.fxsave,
3236 sizeof(struct fxregs_state));
3237 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3238 XFEATURE_MASK_FPSSE;
3239 }
3240 }
3241
3242 #define XSAVE_MXCSR_OFFSET 24
3243
3244 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3245 struct kvm_xsave *guest_xsave)
3246 {
3247 u64 xstate_bv =
3248 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3249 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3250
3251 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3252 /*
3253 * Here we allow setting states that are not present in
3254 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3255 * with old userspace.
3256 */
3257 if (xstate_bv & ~kvm_supported_xcr0() ||
3258 mxcsr & ~mxcsr_feature_mask)
3259 return -EINVAL;
3260 load_xsave(vcpu, (u8 *)guest_xsave->region);
3261 } else {
3262 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3263 mxcsr & ~mxcsr_feature_mask)
3264 return -EINVAL;
3265 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3266 guest_xsave->region, sizeof(struct fxregs_state));
3267 }
3268 return 0;
3269 }
3270
3271 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3272 struct kvm_xcrs *guest_xcrs)
3273 {
3274 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3275 guest_xcrs->nr_xcrs = 0;
3276 return;
3277 }
3278
3279 guest_xcrs->nr_xcrs = 1;
3280 guest_xcrs->flags = 0;
3281 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3282 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3283 }
3284
3285 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3286 struct kvm_xcrs *guest_xcrs)
3287 {
3288 int i, r = 0;
3289
3290 if (!boot_cpu_has(X86_FEATURE_XSAVE))
3291 return -EINVAL;
3292
3293 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3294 return -EINVAL;
3295
3296 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3297 /* Only support XCR0 currently */
3298 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3299 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3300 guest_xcrs->xcrs[i].value);
3301 break;
3302 }
3303 if (r)
3304 r = -EINVAL;
3305 return r;
3306 }
3307
3308 /*
3309 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3310 * stopped by the hypervisor. This function will be called from the host only.
3311 * EINVAL is returned when the host attempts to set the flag for a guest that
3312 * does not support pv clocks.
3313 */
3314 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3315 {
3316 if (!vcpu->arch.pv_time_enabled)
3317 return -EINVAL;
3318 vcpu->arch.pvclock_set_guest_stopped_request = true;
3319 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3320 return 0;
3321 }
3322
3323 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3324 struct kvm_enable_cap *cap)
3325 {
3326 if (cap->flags)
3327 return -EINVAL;
3328
3329 switch (cap->cap) {
3330 case KVM_CAP_HYPERV_SYNIC:
3331 if (!irqchip_in_kernel(vcpu->kvm))
3332 return -EINVAL;
3333 return kvm_hv_activate_synic(vcpu);
3334 default:
3335 return -EINVAL;
3336 }
3337 }
3338
3339 long kvm_arch_vcpu_ioctl(struct file *filp,
3340 unsigned int ioctl, unsigned long arg)
3341 {
3342 struct kvm_vcpu *vcpu = filp->private_data;
3343 void __user *argp = (void __user *)arg;
3344 int r;
3345 union {
3346 struct kvm_lapic_state *lapic;
3347 struct kvm_xsave *xsave;
3348 struct kvm_xcrs *xcrs;
3349 void *buffer;
3350 } u;
3351
3352 u.buffer = NULL;
3353 switch (ioctl) {
3354 case KVM_GET_LAPIC: {
3355 r = -EINVAL;
3356 if (!lapic_in_kernel(vcpu))
3357 goto out;
3358 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3359
3360 r = -ENOMEM;
3361 if (!u.lapic)
3362 goto out;
3363 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3364 if (r)
3365 goto out;
3366 r = -EFAULT;
3367 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3368 goto out;
3369 r = 0;
3370 break;
3371 }
3372 case KVM_SET_LAPIC: {
3373 r = -EINVAL;
3374 if (!lapic_in_kernel(vcpu))
3375 goto out;
3376 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3377 if (IS_ERR(u.lapic))
3378 return PTR_ERR(u.lapic);
3379
3380 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3381 break;
3382 }
3383 case KVM_INTERRUPT: {
3384 struct kvm_interrupt irq;
3385
3386 r = -EFAULT;
3387 if (copy_from_user(&irq, argp, sizeof irq))
3388 goto out;
3389 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3390 break;
3391 }
3392 case KVM_NMI: {
3393 r = kvm_vcpu_ioctl_nmi(vcpu);
3394 break;
3395 }
3396 case KVM_SMI: {
3397 r = kvm_vcpu_ioctl_smi(vcpu);
3398 break;
3399 }
3400 case KVM_SET_CPUID: {
3401 struct kvm_cpuid __user *cpuid_arg = argp;
3402 struct kvm_cpuid cpuid;
3403
3404 r = -EFAULT;
3405 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3406 goto out;
3407 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3408 break;
3409 }
3410 case KVM_SET_CPUID2: {
3411 struct kvm_cpuid2 __user *cpuid_arg = argp;
3412 struct kvm_cpuid2 cpuid;
3413
3414 r = -EFAULT;
3415 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3416 goto out;
3417 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3418 cpuid_arg->entries);
3419 break;
3420 }
3421 case KVM_GET_CPUID2: {
3422 struct kvm_cpuid2 __user *cpuid_arg = argp;
3423 struct kvm_cpuid2 cpuid;
3424
3425 r = -EFAULT;
3426 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3427 goto out;
3428 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3429 cpuid_arg->entries);
3430 if (r)
3431 goto out;
3432 r = -EFAULT;
3433 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3434 goto out;
3435 r = 0;
3436 break;
3437 }
3438 case KVM_GET_MSRS:
3439 r = msr_io(vcpu, argp, do_get_msr, 1);
3440 break;
3441 case KVM_SET_MSRS:
3442 r = msr_io(vcpu, argp, do_set_msr, 0);
3443 break;
3444 case KVM_TPR_ACCESS_REPORTING: {
3445 struct kvm_tpr_access_ctl tac;
3446
3447 r = -EFAULT;
3448 if (copy_from_user(&tac, argp, sizeof tac))
3449 goto out;
3450 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3451 if (r)
3452 goto out;
3453 r = -EFAULT;
3454 if (copy_to_user(argp, &tac, sizeof tac))
3455 goto out;
3456 r = 0;
3457 break;
3458 };
3459 case KVM_SET_VAPIC_ADDR: {
3460 struct kvm_vapic_addr va;
3461 int idx;
3462
3463 r = -EINVAL;
3464 if (!lapic_in_kernel(vcpu))
3465 goto out;
3466 r = -EFAULT;
3467 if (copy_from_user(&va, argp, sizeof va))
3468 goto out;
3469 idx = srcu_read_lock(&vcpu->kvm->srcu);
3470 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3471 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3472 break;
3473 }
3474 case KVM_X86_SETUP_MCE: {
3475 u64 mcg_cap;
3476
3477 r = -EFAULT;
3478 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3479 goto out;
3480 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3481 break;
3482 }
3483 case KVM_X86_SET_MCE: {
3484 struct kvm_x86_mce mce;
3485
3486 r = -EFAULT;
3487 if (copy_from_user(&mce, argp, sizeof mce))
3488 goto out;
3489 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3490 break;
3491 }
3492 case KVM_GET_VCPU_EVENTS: {
3493 struct kvm_vcpu_events events;
3494
3495 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3496
3497 r = -EFAULT;
3498 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3499 break;
3500 r = 0;
3501 break;
3502 }
3503 case KVM_SET_VCPU_EVENTS: {
3504 struct kvm_vcpu_events events;
3505
3506 r = -EFAULT;
3507 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3508 break;
3509
3510 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3511 break;
3512 }
3513 case KVM_GET_DEBUGREGS: {
3514 struct kvm_debugregs dbgregs;
3515
3516 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3517
3518 r = -EFAULT;
3519 if (copy_to_user(argp, &dbgregs,
3520 sizeof(struct kvm_debugregs)))
3521 break;
3522 r = 0;
3523 break;
3524 }
3525 case KVM_SET_DEBUGREGS: {
3526 struct kvm_debugregs dbgregs;
3527
3528 r = -EFAULT;
3529 if (copy_from_user(&dbgregs, argp,
3530 sizeof(struct kvm_debugregs)))
3531 break;
3532
3533 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3534 break;
3535 }
3536 case KVM_GET_XSAVE: {
3537 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3538 r = -ENOMEM;
3539 if (!u.xsave)
3540 break;
3541
3542 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3543
3544 r = -EFAULT;
3545 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3546 break;
3547 r = 0;
3548 break;
3549 }
3550 case KVM_SET_XSAVE: {
3551 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3552 if (IS_ERR(u.xsave))
3553 return PTR_ERR(u.xsave);
3554
3555 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3556 break;
3557 }
3558 case KVM_GET_XCRS: {
3559 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3560 r = -ENOMEM;
3561 if (!u.xcrs)
3562 break;
3563
3564 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3565
3566 r = -EFAULT;
3567 if (copy_to_user(argp, u.xcrs,
3568 sizeof(struct kvm_xcrs)))
3569 break;
3570 r = 0;
3571 break;
3572 }
3573 case KVM_SET_XCRS: {
3574 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3575 if (IS_ERR(u.xcrs))
3576 return PTR_ERR(u.xcrs);
3577
3578 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3579 break;
3580 }
3581 case KVM_SET_TSC_KHZ: {
3582 u32 user_tsc_khz;
3583
3584 r = -EINVAL;
3585 user_tsc_khz = (u32)arg;
3586
3587 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3588 goto out;
3589
3590 if (user_tsc_khz == 0)
3591 user_tsc_khz = tsc_khz;
3592
3593 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3594 r = 0;
3595
3596 goto out;
3597 }
3598 case KVM_GET_TSC_KHZ: {
3599 r = vcpu->arch.virtual_tsc_khz;
3600 goto out;
3601 }
3602 case KVM_KVMCLOCK_CTRL: {
3603 r = kvm_set_guest_paused(vcpu);
3604 goto out;
3605 }
3606 case KVM_ENABLE_CAP: {
3607 struct kvm_enable_cap cap;
3608
3609 r = -EFAULT;
3610 if (copy_from_user(&cap, argp, sizeof(cap)))
3611 goto out;
3612 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3613 break;
3614 }
3615 default:
3616 r = -EINVAL;
3617 }
3618 out:
3619 kfree(u.buffer);
3620 return r;
3621 }
3622
3623 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3624 {
3625 return VM_FAULT_SIGBUS;
3626 }
3627
3628 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3629 {
3630 int ret;
3631
3632 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3633 return -EINVAL;
3634 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3635 return ret;
3636 }
3637
3638 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3639 u64 ident_addr)
3640 {
3641 kvm->arch.ept_identity_map_addr = ident_addr;
3642 return 0;
3643 }
3644
3645 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3646 u32 kvm_nr_mmu_pages)
3647 {
3648 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3649 return -EINVAL;
3650
3651 mutex_lock(&kvm->slots_lock);
3652
3653 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3654 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3655
3656 mutex_unlock(&kvm->slots_lock);
3657 return 0;
3658 }
3659
3660 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3661 {
3662 return kvm->arch.n_max_mmu_pages;
3663 }
3664
3665 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3666 {
3667 int r;
3668
3669 r = 0;
3670 switch (chip->chip_id) {
3671 case KVM_IRQCHIP_PIC_MASTER:
3672 memcpy(&chip->chip.pic,
3673 &pic_irqchip(kvm)->pics[0],
3674 sizeof(struct kvm_pic_state));
3675 break;
3676 case KVM_IRQCHIP_PIC_SLAVE:
3677 memcpy(&chip->chip.pic,
3678 &pic_irqchip(kvm)->pics[1],
3679 sizeof(struct kvm_pic_state));
3680 break;
3681 case KVM_IRQCHIP_IOAPIC:
3682 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3683 break;
3684 default:
3685 r = -EINVAL;
3686 break;
3687 }
3688 return r;
3689 }
3690
3691 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3692 {
3693 int r;
3694
3695 r = 0;
3696 switch (chip->chip_id) {
3697 case KVM_IRQCHIP_PIC_MASTER:
3698 spin_lock(&pic_irqchip(kvm)->lock);
3699 memcpy(&pic_irqchip(kvm)->pics[0],
3700 &chip->chip.pic,
3701 sizeof(struct kvm_pic_state));
3702 spin_unlock(&pic_irqchip(kvm)->lock);
3703 break;
3704 case KVM_IRQCHIP_PIC_SLAVE:
3705 spin_lock(&pic_irqchip(kvm)->lock);
3706 memcpy(&pic_irqchip(kvm)->pics[1],
3707 &chip->chip.pic,
3708 sizeof(struct kvm_pic_state));
3709 spin_unlock(&pic_irqchip(kvm)->lock);
3710 break;
3711 case KVM_IRQCHIP_IOAPIC:
3712 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3713 break;
3714 default:
3715 r = -EINVAL;
3716 break;
3717 }
3718 kvm_pic_update_irq(pic_irqchip(kvm));
3719 return r;
3720 }
3721
3722 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3723 {
3724 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3725
3726 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3727
3728 mutex_lock(&kps->lock);
3729 memcpy(ps, &kps->channels, sizeof(*ps));
3730 mutex_unlock(&kps->lock);
3731 return 0;
3732 }
3733
3734 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3735 {
3736 int i;
3737 struct kvm_pit *pit = kvm->arch.vpit;
3738
3739 mutex_lock(&pit->pit_state.lock);
3740 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3741 for (i = 0; i < 3; i++)
3742 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3743 mutex_unlock(&pit->pit_state.lock);
3744 return 0;
3745 }
3746
3747 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3748 {
3749 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3750 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3751 sizeof(ps->channels));
3752 ps->flags = kvm->arch.vpit->pit_state.flags;
3753 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3754 memset(&ps->reserved, 0, sizeof(ps->reserved));
3755 return 0;
3756 }
3757
3758 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3759 {
3760 int start = 0;
3761 int i;
3762 u32 prev_legacy, cur_legacy;
3763 struct kvm_pit *pit = kvm->arch.vpit;
3764
3765 mutex_lock(&pit->pit_state.lock);
3766 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3767 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3768 if (!prev_legacy && cur_legacy)
3769 start = 1;
3770 memcpy(&pit->pit_state.channels, &ps->channels,
3771 sizeof(pit->pit_state.channels));
3772 pit->pit_state.flags = ps->flags;
3773 for (i = 0; i < 3; i++)
3774 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3775 start && i == 0);
3776 mutex_unlock(&pit->pit_state.lock);
3777 return 0;
3778 }
3779
3780 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3781 struct kvm_reinject_control *control)
3782 {
3783 struct kvm_pit *pit = kvm->arch.vpit;
3784
3785 if (!pit)
3786 return -ENXIO;
3787
3788 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3789 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3790 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3791 */
3792 mutex_lock(&pit->pit_state.lock);
3793 kvm_pit_set_reinject(pit, control->pit_reinject);
3794 mutex_unlock(&pit->pit_state.lock);
3795
3796 return 0;
3797 }
3798
3799 /**
3800 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3801 * @kvm: kvm instance
3802 * @log: slot id and address to which we copy the log
3803 *
3804 * Steps 1-4 below provide general overview of dirty page logging. See
3805 * kvm_get_dirty_log_protect() function description for additional details.
3806 *
3807 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3808 * always flush the TLB (step 4) even if previous step failed and the dirty
3809 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3810 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3811 * writes will be marked dirty for next log read.
3812 *
3813 * 1. Take a snapshot of the bit and clear it if needed.
3814 * 2. Write protect the corresponding page.
3815 * 3. Copy the snapshot to the userspace.
3816 * 4. Flush TLB's if needed.
3817 */
3818 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3819 {
3820 bool is_dirty = false;
3821 int r;
3822
3823 mutex_lock(&kvm->slots_lock);
3824
3825 /*
3826 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3827 */
3828 if (kvm_x86_ops->flush_log_dirty)
3829 kvm_x86_ops->flush_log_dirty(kvm);
3830
3831 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3832
3833 /*
3834 * All the TLBs can be flushed out of mmu lock, see the comments in
3835 * kvm_mmu_slot_remove_write_access().
3836 */
3837 lockdep_assert_held(&kvm->slots_lock);
3838 if (is_dirty)
3839 kvm_flush_remote_tlbs(kvm);
3840
3841 mutex_unlock(&kvm->slots_lock);
3842 return r;
3843 }
3844
3845 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3846 bool line_status)
3847 {
3848 if (!irqchip_in_kernel(kvm))
3849 return -ENXIO;
3850
3851 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3852 irq_event->irq, irq_event->level,
3853 line_status);
3854 return 0;
3855 }
3856
3857 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3858 struct kvm_enable_cap *cap)
3859 {
3860 int r;
3861
3862 if (cap->flags)
3863 return -EINVAL;
3864
3865 switch (cap->cap) {
3866 case KVM_CAP_DISABLE_QUIRKS:
3867 kvm->arch.disabled_quirks = cap->args[0];
3868 r = 0;
3869 break;
3870 case KVM_CAP_SPLIT_IRQCHIP: {
3871 mutex_lock(&kvm->lock);
3872 r = -EINVAL;
3873 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3874 goto split_irqchip_unlock;
3875 r = -EEXIST;
3876 if (irqchip_in_kernel(kvm))
3877 goto split_irqchip_unlock;
3878 if (kvm->created_vcpus)
3879 goto split_irqchip_unlock;
3880 r = kvm_setup_empty_irq_routing(kvm);
3881 if (r)
3882 goto split_irqchip_unlock;
3883 /* Pairs with irqchip_in_kernel. */
3884 smp_wmb();
3885 kvm->arch.irqchip_split = true;
3886 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3887 r = 0;
3888 split_irqchip_unlock:
3889 mutex_unlock(&kvm->lock);
3890 break;
3891 }
3892 case KVM_CAP_X2APIC_API:
3893 r = -EINVAL;
3894 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3895 break;
3896
3897 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3898 kvm->arch.x2apic_format = true;
3899 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3900 kvm->arch.x2apic_broadcast_quirk_disabled = true;
3901
3902 r = 0;
3903 break;
3904 default:
3905 r = -EINVAL;
3906 break;
3907 }
3908 return r;
3909 }
3910
3911 long kvm_arch_vm_ioctl(struct file *filp,
3912 unsigned int ioctl, unsigned long arg)
3913 {
3914 struct kvm *kvm = filp->private_data;
3915 void __user *argp = (void __user *)arg;
3916 int r = -ENOTTY;
3917 /*
3918 * This union makes it completely explicit to gcc-3.x
3919 * that these two variables' stack usage should be
3920 * combined, not added together.
3921 */
3922 union {
3923 struct kvm_pit_state ps;
3924 struct kvm_pit_state2 ps2;
3925 struct kvm_pit_config pit_config;
3926 } u;
3927
3928 switch (ioctl) {
3929 case KVM_SET_TSS_ADDR:
3930 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3931 break;
3932 case KVM_SET_IDENTITY_MAP_ADDR: {
3933 u64 ident_addr;
3934
3935 r = -EFAULT;
3936 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3937 goto out;
3938 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3939 break;
3940 }
3941 case KVM_SET_NR_MMU_PAGES:
3942 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3943 break;
3944 case KVM_GET_NR_MMU_PAGES:
3945 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3946 break;
3947 case KVM_CREATE_IRQCHIP: {
3948 struct kvm_pic *vpic;
3949
3950 mutex_lock(&kvm->lock);
3951 r = -EEXIST;
3952 if (kvm->arch.vpic)
3953 goto create_irqchip_unlock;
3954 r = -EINVAL;
3955 if (kvm->created_vcpus)
3956 goto create_irqchip_unlock;
3957 r = -ENOMEM;
3958 vpic = kvm_create_pic(kvm);
3959 if (vpic) {
3960 r = kvm_ioapic_init(kvm);
3961 if (r) {
3962 mutex_lock(&kvm->slots_lock);
3963 kvm_destroy_pic(vpic);
3964 mutex_unlock(&kvm->slots_lock);
3965 goto create_irqchip_unlock;
3966 }
3967 } else
3968 goto create_irqchip_unlock;
3969 r = kvm_setup_default_irq_routing(kvm);
3970 if (r) {
3971 mutex_lock(&kvm->slots_lock);
3972 mutex_lock(&kvm->irq_lock);
3973 kvm_ioapic_destroy(kvm);
3974 kvm_destroy_pic(vpic);
3975 mutex_unlock(&kvm->irq_lock);
3976 mutex_unlock(&kvm->slots_lock);
3977 goto create_irqchip_unlock;
3978 }
3979 /* Write kvm->irq_routing before kvm->arch.vpic. */
3980 smp_wmb();
3981 kvm->arch.vpic = vpic;
3982 create_irqchip_unlock:
3983 mutex_unlock(&kvm->lock);
3984 break;
3985 }
3986 case KVM_CREATE_PIT:
3987 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3988 goto create_pit;
3989 case KVM_CREATE_PIT2:
3990 r = -EFAULT;
3991 if (copy_from_user(&u.pit_config, argp,
3992 sizeof(struct kvm_pit_config)))
3993 goto out;
3994 create_pit:
3995 mutex_lock(&kvm->lock);
3996 r = -EEXIST;
3997 if (kvm->arch.vpit)
3998 goto create_pit_unlock;
3999 r = -ENOMEM;
4000 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4001 if (kvm->arch.vpit)
4002 r = 0;
4003 create_pit_unlock:
4004 mutex_unlock(&kvm->lock);
4005 break;
4006 case KVM_GET_IRQCHIP: {
4007 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4008 struct kvm_irqchip *chip;
4009
4010 chip = memdup_user(argp, sizeof(*chip));
4011 if (IS_ERR(chip)) {
4012 r = PTR_ERR(chip);
4013 goto out;
4014 }
4015
4016 r = -ENXIO;
4017 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
4018 goto get_irqchip_out;
4019 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4020 if (r)
4021 goto get_irqchip_out;
4022 r = -EFAULT;
4023 if (copy_to_user(argp, chip, sizeof *chip))
4024 goto get_irqchip_out;
4025 r = 0;
4026 get_irqchip_out:
4027 kfree(chip);
4028 break;
4029 }
4030 case KVM_SET_IRQCHIP: {
4031 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4032 struct kvm_irqchip *chip;
4033
4034 chip = memdup_user(argp, sizeof(*chip));
4035 if (IS_ERR(chip)) {
4036 r = PTR_ERR(chip);
4037 goto out;
4038 }
4039
4040 r = -ENXIO;
4041 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
4042 goto set_irqchip_out;
4043 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4044 if (r)
4045 goto set_irqchip_out;
4046 r = 0;
4047 set_irqchip_out:
4048 kfree(chip);
4049 break;
4050 }
4051 case KVM_GET_PIT: {
4052 r = -EFAULT;
4053 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4054 goto out;
4055 r = -ENXIO;
4056 if (!kvm->arch.vpit)
4057 goto out;
4058 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4059 if (r)
4060 goto out;
4061 r = -EFAULT;
4062 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4063 goto out;
4064 r = 0;
4065 break;
4066 }
4067 case KVM_SET_PIT: {
4068 r = -EFAULT;
4069 if (copy_from_user(&u.ps, argp, sizeof u.ps))
4070 goto out;
4071 r = -ENXIO;
4072 if (!kvm->arch.vpit)
4073 goto out;
4074 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4075 break;
4076 }
4077 case KVM_GET_PIT2: {
4078 r = -ENXIO;
4079 if (!kvm->arch.vpit)
4080 goto out;
4081 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4082 if (r)
4083 goto out;
4084 r = -EFAULT;
4085 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4086 goto out;
4087 r = 0;
4088 break;
4089 }
4090 case KVM_SET_PIT2: {
4091 r = -EFAULT;
4092 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4093 goto out;
4094 r = -ENXIO;
4095 if (!kvm->arch.vpit)
4096 goto out;
4097 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4098 break;
4099 }
4100 case KVM_REINJECT_CONTROL: {
4101 struct kvm_reinject_control control;
4102 r = -EFAULT;
4103 if (copy_from_user(&control, argp, sizeof(control)))
4104 goto out;
4105 r = kvm_vm_ioctl_reinject(kvm, &control);
4106 break;
4107 }
4108 case KVM_SET_BOOT_CPU_ID:
4109 r = 0;
4110 mutex_lock(&kvm->lock);
4111 if (kvm->created_vcpus)
4112 r = -EBUSY;
4113 else
4114 kvm->arch.bsp_vcpu_id = arg;
4115 mutex_unlock(&kvm->lock);
4116 break;
4117 case KVM_XEN_HVM_CONFIG: {
4118 r = -EFAULT;
4119 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4120 sizeof(struct kvm_xen_hvm_config)))
4121 goto out;
4122 r = -EINVAL;
4123 if (kvm->arch.xen_hvm_config.flags)
4124 goto out;
4125 r = 0;
4126 break;
4127 }
4128 case KVM_SET_CLOCK: {
4129 struct kvm_clock_data user_ns;
4130 u64 now_ns;
4131
4132 r = -EFAULT;
4133 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4134 goto out;
4135
4136 r = -EINVAL;
4137 if (user_ns.flags)
4138 goto out;
4139
4140 r = 0;
4141 local_irq_disable();
4142 now_ns = __get_kvmclock_ns(kvm);
4143 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4144 local_irq_enable();
4145 kvm_gen_update_masterclock(kvm);
4146 break;
4147 }
4148 case KVM_GET_CLOCK: {
4149 struct kvm_clock_data user_ns;
4150 u64 now_ns;
4151
4152 local_irq_disable();
4153 now_ns = __get_kvmclock_ns(kvm);
4154 user_ns.clock = now_ns;
4155 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4156 local_irq_enable();
4157 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4158
4159 r = -EFAULT;
4160 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4161 goto out;
4162 r = 0;
4163 break;
4164 }
4165 case KVM_ENABLE_CAP: {
4166 struct kvm_enable_cap cap;
4167
4168 r = -EFAULT;
4169 if (copy_from_user(&cap, argp, sizeof(cap)))
4170 goto out;
4171 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4172 break;
4173 }
4174 default:
4175 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4176 }
4177 out:
4178 return r;
4179 }
4180
4181 static void kvm_init_msr_list(void)
4182 {
4183 u32 dummy[2];
4184 unsigned i, j;
4185
4186 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4187 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4188 continue;
4189
4190 /*
4191 * Even MSRs that are valid in the host may not be exposed
4192 * to the guests in some cases.
4193 */
4194 switch (msrs_to_save[i]) {
4195 case MSR_IA32_BNDCFGS:
4196 if (!kvm_x86_ops->mpx_supported())
4197 continue;
4198 break;
4199 case MSR_TSC_AUX:
4200 if (!kvm_x86_ops->rdtscp_supported())
4201 continue;
4202 break;
4203 default:
4204 break;
4205 }
4206
4207 if (j < i)
4208 msrs_to_save[j] = msrs_to_save[i];
4209 j++;
4210 }
4211 num_msrs_to_save = j;
4212
4213 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4214 switch (emulated_msrs[i]) {
4215 case MSR_IA32_SMBASE:
4216 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4217 continue;
4218 break;
4219 default:
4220 break;
4221 }
4222
4223 if (j < i)
4224 emulated_msrs[j] = emulated_msrs[i];
4225 j++;
4226 }
4227 num_emulated_msrs = j;
4228 }
4229
4230 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4231 const void *v)
4232 {
4233 int handled = 0;
4234 int n;
4235
4236 do {
4237 n = min(len, 8);
4238 if (!(lapic_in_kernel(vcpu) &&
4239 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4240 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4241 break;
4242 handled += n;
4243 addr += n;
4244 len -= n;
4245 v += n;
4246 } while (len);
4247
4248 return handled;
4249 }
4250
4251 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4252 {
4253 int handled = 0;
4254 int n;
4255
4256 do {
4257 n = min(len, 8);
4258 if (!(lapic_in_kernel(vcpu) &&
4259 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4260 addr, n, v))
4261 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4262 break;
4263 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4264 handled += n;
4265 addr += n;
4266 len -= n;
4267 v += n;
4268 } while (len);
4269
4270 return handled;
4271 }
4272
4273 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4274 struct kvm_segment *var, int seg)
4275 {
4276 kvm_x86_ops->set_segment(vcpu, var, seg);
4277 }
4278
4279 void kvm_get_segment(struct kvm_vcpu *vcpu,
4280 struct kvm_segment *var, int seg)
4281 {
4282 kvm_x86_ops->get_segment(vcpu, var, seg);
4283 }
4284
4285 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4286 struct x86_exception *exception)
4287 {
4288 gpa_t t_gpa;
4289
4290 BUG_ON(!mmu_is_nested(vcpu));
4291
4292 /* NPT walks are always user-walks */
4293 access |= PFERR_USER_MASK;
4294 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4295
4296 return t_gpa;
4297 }
4298
4299 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4300 struct x86_exception *exception)
4301 {
4302 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4303 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4304 }
4305
4306 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4307 struct x86_exception *exception)
4308 {
4309 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4310 access |= PFERR_FETCH_MASK;
4311 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4312 }
4313
4314 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4315 struct x86_exception *exception)
4316 {
4317 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4318 access |= PFERR_WRITE_MASK;
4319 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4320 }
4321
4322 /* uses this to access any guest's mapped memory without checking CPL */
4323 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4324 struct x86_exception *exception)
4325 {
4326 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4327 }
4328
4329 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4330 struct kvm_vcpu *vcpu, u32 access,
4331 struct x86_exception *exception)
4332 {
4333 void *data = val;
4334 int r = X86EMUL_CONTINUE;
4335
4336 while (bytes) {
4337 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4338 exception);
4339 unsigned offset = addr & (PAGE_SIZE-1);
4340 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4341 int ret;
4342
4343 if (gpa == UNMAPPED_GVA)
4344 return X86EMUL_PROPAGATE_FAULT;
4345 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4346 offset, toread);
4347 if (ret < 0) {
4348 r = X86EMUL_IO_NEEDED;
4349 goto out;
4350 }
4351
4352 bytes -= toread;
4353 data += toread;
4354 addr += toread;
4355 }
4356 out:
4357 return r;
4358 }
4359
4360 /* used for instruction fetching */
4361 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4362 gva_t addr, void *val, unsigned int bytes,
4363 struct x86_exception *exception)
4364 {
4365 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4366 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4367 unsigned offset;
4368 int ret;
4369
4370 /* Inline kvm_read_guest_virt_helper for speed. */
4371 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4372 exception);
4373 if (unlikely(gpa == UNMAPPED_GVA))
4374 return X86EMUL_PROPAGATE_FAULT;
4375
4376 offset = addr & (PAGE_SIZE-1);
4377 if (WARN_ON(offset + bytes > PAGE_SIZE))
4378 bytes = (unsigned)PAGE_SIZE - offset;
4379 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4380 offset, bytes);
4381 if (unlikely(ret < 0))
4382 return X86EMUL_IO_NEEDED;
4383
4384 return X86EMUL_CONTINUE;
4385 }
4386
4387 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4388 gva_t addr, void *val, unsigned int bytes,
4389 struct x86_exception *exception)
4390 {
4391 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4392 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4393
4394 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4395 exception);
4396 }
4397 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4398
4399 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4400 gva_t addr, void *val, unsigned int bytes,
4401 struct x86_exception *exception)
4402 {
4403 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4404 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4405 }
4406
4407 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4408 unsigned long addr, void *val, unsigned int bytes)
4409 {
4410 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4411 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4412
4413 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4414 }
4415
4416 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4417 gva_t addr, void *val,
4418 unsigned int bytes,
4419 struct x86_exception *exception)
4420 {
4421 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4422 void *data = val;
4423 int r = X86EMUL_CONTINUE;
4424
4425 while (bytes) {
4426 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4427 PFERR_WRITE_MASK,
4428 exception);
4429 unsigned offset = addr & (PAGE_SIZE-1);
4430 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4431 int ret;
4432
4433 if (gpa == UNMAPPED_GVA)
4434 return X86EMUL_PROPAGATE_FAULT;
4435 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4436 if (ret < 0) {
4437 r = X86EMUL_IO_NEEDED;
4438 goto out;
4439 }
4440
4441 bytes -= towrite;
4442 data += towrite;
4443 addr += towrite;
4444 }
4445 out:
4446 return r;
4447 }
4448 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4449
4450 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4451 gpa_t *gpa, struct x86_exception *exception,
4452 bool write)
4453 {
4454 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4455 | (write ? PFERR_WRITE_MASK : 0);
4456
4457 /*
4458 * currently PKRU is only applied to ept enabled guest so
4459 * there is no pkey in EPT page table for L1 guest or EPT
4460 * shadow page table for L2 guest.
4461 */
4462 if (vcpu_match_mmio_gva(vcpu, gva)
4463 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4464 vcpu->arch.access, 0, access)) {
4465 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4466 (gva & (PAGE_SIZE - 1));
4467 trace_vcpu_match_mmio(gva, *gpa, write, false);
4468 return 1;
4469 }
4470
4471 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4472
4473 if (*gpa == UNMAPPED_GVA)
4474 return -1;
4475
4476 /* For APIC access vmexit */
4477 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4478 return 1;
4479
4480 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4481 trace_vcpu_match_mmio(gva, *gpa, write, true);
4482 return 1;
4483 }
4484
4485 return 0;
4486 }
4487
4488 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4489 const void *val, int bytes)
4490 {
4491 int ret;
4492
4493 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4494 if (ret < 0)
4495 return 0;
4496 kvm_page_track_write(vcpu, gpa, val, bytes);
4497 return 1;
4498 }
4499
4500 struct read_write_emulator_ops {
4501 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4502 int bytes);
4503 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4504 void *val, int bytes);
4505 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4506 int bytes, void *val);
4507 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4508 void *val, int bytes);
4509 bool write;
4510 };
4511
4512 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4513 {
4514 if (vcpu->mmio_read_completed) {
4515 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4516 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4517 vcpu->mmio_read_completed = 0;
4518 return 1;
4519 }
4520
4521 return 0;
4522 }
4523
4524 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4525 void *val, int bytes)
4526 {
4527 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4528 }
4529
4530 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4531 void *val, int bytes)
4532 {
4533 return emulator_write_phys(vcpu, gpa, val, bytes);
4534 }
4535
4536 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4537 {
4538 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4539 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4540 }
4541
4542 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4543 void *val, int bytes)
4544 {
4545 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4546 return X86EMUL_IO_NEEDED;
4547 }
4548
4549 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4550 void *val, int bytes)
4551 {
4552 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4553
4554 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4555 return X86EMUL_CONTINUE;
4556 }
4557
4558 static const struct read_write_emulator_ops read_emultor = {
4559 .read_write_prepare = read_prepare,
4560 .read_write_emulate = read_emulate,
4561 .read_write_mmio = vcpu_mmio_read,
4562 .read_write_exit_mmio = read_exit_mmio,
4563 };
4564
4565 static const struct read_write_emulator_ops write_emultor = {
4566 .read_write_emulate = write_emulate,
4567 .read_write_mmio = write_mmio,
4568 .read_write_exit_mmio = write_exit_mmio,
4569 .write = true,
4570 };
4571
4572 static int emulator_read_write_onepage(unsigned long addr, void *val,
4573 unsigned int bytes,
4574 struct x86_exception *exception,
4575 struct kvm_vcpu *vcpu,
4576 const struct read_write_emulator_ops *ops)
4577 {
4578 gpa_t gpa;
4579 int handled, ret;
4580 bool write = ops->write;
4581 struct kvm_mmio_fragment *frag;
4582
4583 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4584
4585 if (ret < 0)
4586 return X86EMUL_PROPAGATE_FAULT;
4587
4588 /* For APIC access vmexit */
4589 if (ret)
4590 goto mmio;
4591
4592 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4593 return X86EMUL_CONTINUE;
4594
4595 mmio:
4596 /*
4597 * Is this MMIO handled locally?
4598 */
4599 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4600 if (handled == bytes)
4601 return X86EMUL_CONTINUE;
4602
4603 gpa += handled;
4604 bytes -= handled;
4605 val += handled;
4606
4607 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4608 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4609 frag->gpa = gpa;
4610 frag->data = val;
4611 frag->len = bytes;
4612 return X86EMUL_CONTINUE;
4613 }
4614
4615 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4616 unsigned long addr,
4617 void *val, unsigned int bytes,
4618 struct x86_exception *exception,
4619 const struct read_write_emulator_ops *ops)
4620 {
4621 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4622 gpa_t gpa;
4623 int rc;
4624
4625 if (ops->read_write_prepare &&
4626 ops->read_write_prepare(vcpu, val, bytes))
4627 return X86EMUL_CONTINUE;
4628
4629 vcpu->mmio_nr_fragments = 0;
4630
4631 /* Crossing a page boundary? */
4632 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4633 int now;
4634
4635 now = -addr & ~PAGE_MASK;
4636 rc = emulator_read_write_onepage(addr, val, now, exception,
4637 vcpu, ops);
4638
4639 if (rc != X86EMUL_CONTINUE)
4640 return rc;
4641 addr += now;
4642 if (ctxt->mode != X86EMUL_MODE_PROT64)
4643 addr = (u32)addr;
4644 val += now;
4645 bytes -= now;
4646 }
4647
4648 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4649 vcpu, ops);
4650 if (rc != X86EMUL_CONTINUE)
4651 return rc;
4652
4653 if (!vcpu->mmio_nr_fragments)
4654 return rc;
4655
4656 gpa = vcpu->mmio_fragments[0].gpa;
4657
4658 vcpu->mmio_needed = 1;
4659 vcpu->mmio_cur_fragment = 0;
4660
4661 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4662 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4663 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4664 vcpu->run->mmio.phys_addr = gpa;
4665
4666 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4667 }
4668
4669 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4670 unsigned long addr,
4671 void *val,
4672 unsigned int bytes,
4673 struct x86_exception *exception)
4674 {
4675 return emulator_read_write(ctxt, addr, val, bytes,
4676 exception, &read_emultor);
4677 }
4678
4679 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4680 unsigned long addr,
4681 const void *val,
4682 unsigned int bytes,
4683 struct x86_exception *exception)
4684 {
4685 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4686 exception, &write_emultor);
4687 }
4688
4689 #define CMPXCHG_TYPE(t, ptr, old, new) \
4690 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4691
4692 #ifdef CONFIG_X86_64
4693 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4694 #else
4695 # define CMPXCHG64(ptr, old, new) \
4696 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4697 #endif
4698
4699 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4700 unsigned long addr,
4701 const void *old,
4702 const void *new,
4703 unsigned int bytes,
4704 struct x86_exception *exception)
4705 {
4706 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4707 gpa_t gpa;
4708 struct page *page;
4709 char *kaddr;
4710 bool exchanged;
4711
4712 /* guests cmpxchg8b have to be emulated atomically */
4713 if (bytes > 8 || (bytes & (bytes - 1)))
4714 goto emul_write;
4715
4716 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4717
4718 if (gpa == UNMAPPED_GVA ||
4719 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4720 goto emul_write;
4721
4722 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4723 goto emul_write;
4724
4725 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4726 if (is_error_page(page))
4727 goto emul_write;
4728
4729 kaddr = kmap_atomic(page);
4730 kaddr += offset_in_page(gpa);
4731 switch (bytes) {
4732 case 1:
4733 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4734 break;
4735 case 2:
4736 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4737 break;
4738 case 4:
4739 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4740 break;
4741 case 8:
4742 exchanged = CMPXCHG64(kaddr, old, new);
4743 break;
4744 default:
4745 BUG();
4746 }
4747 kunmap_atomic(kaddr);
4748 kvm_release_page_dirty(page);
4749
4750 if (!exchanged)
4751 return X86EMUL_CMPXCHG_FAILED;
4752
4753 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4754 kvm_page_track_write(vcpu, gpa, new, bytes);
4755
4756 return X86EMUL_CONTINUE;
4757
4758 emul_write:
4759 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4760
4761 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4762 }
4763
4764 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4765 {
4766 int r = 0, i;
4767
4768 for (i = 0; i < vcpu->arch.pio.count; i++) {
4769 if (vcpu->arch.pio.in)
4770 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4771 vcpu->arch.pio.size, pd);
4772 else
4773 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4774 vcpu->arch.pio.port, vcpu->arch.pio.size,
4775 pd);
4776 if (r)
4777 break;
4778 pd += vcpu->arch.pio.size;
4779 }
4780 return r;
4781 }
4782
4783 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4784 unsigned short port, void *val,
4785 unsigned int count, bool in)
4786 {
4787 vcpu->arch.pio.port = port;
4788 vcpu->arch.pio.in = in;
4789 vcpu->arch.pio.count = count;
4790 vcpu->arch.pio.size = size;
4791
4792 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4793 vcpu->arch.pio.count = 0;
4794 return 1;
4795 }
4796
4797 vcpu->run->exit_reason = KVM_EXIT_IO;
4798 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4799 vcpu->run->io.size = size;
4800 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4801 vcpu->run->io.count = count;
4802 vcpu->run->io.port = port;
4803
4804 return 0;
4805 }
4806
4807 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4808 int size, unsigned short port, void *val,
4809 unsigned int count)
4810 {
4811 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4812 int ret;
4813
4814 if (vcpu->arch.pio.count)
4815 goto data_avail;
4816
4817 memset(vcpu->arch.pio_data, 0, size * count);
4818
4819 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4820 if (ret) {
4821 data_avail:
4822 memcpy(val, vcpu->arch.pio_data, size * count);
4823 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4824 vcpu->arch.pio.count = 0;
4825 return 1;
4826 }
4827
4828 return 0;
4829 }
4830
4831 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4832 int size, unsigned short port,
4833 const void *val, unsigned int count)
4834 {
4835 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4836
4837 memcpy(vcpu->arch.pio_data, val, size * count);
4838 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4839 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4840 }
4841
4842 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4843 {
4844 return kvm_x86_ops->get_segment_base(vcpu, seg);
4845 }
4846
4847 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4848 {
4849 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4850 }
4851
4852 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4853 {
4854 if (!need_emulate_wbinvd(vcpu))
4855 return X86EMUL_CONTINUE;
4856
4857 if (kvm_x86_ops->has_wbinvd_exit()) {
4858 int cpu = get_cpu();
4859
4860 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4861 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4862 wbinvd_ipi, NULL, 1);
4863 put_cpu();
4864 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4865 } else
4866 wbinvd();
4867 return X86EMUL_CONTINUE;
4868 }
4869
4870 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4871 {
4872 kvm_x86_ops->skip_emulated_instruction(vcpu);
4873 return kvm_emulate_wbinvd_noskip(vcpu);
4874 }
4875 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4876
4877
4878
4879 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4880 {
4881 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4882 }
4883
4884 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4885 unsigned long *dest)
4886 {
4887 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4888 }
4889
4890 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4891 unsigned long value)
4892 {
4893
4894 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4895 }
4896
4897 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4898 {
4899 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4900 }
4901
4902 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4903 {
4904 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4905 unsigned long value;
4906
4907 switch (cr) {
4908 case 0:
4909 value = kvm_read_cr0(vcpu);
4910 break;
4911 case 2:
4912 value = vcpu->arch.cr2;
4913 break;
4914 case 3:
4915 value = kvm_read_cr3(vcpu);
4916 break;
4917 case 4:
4918 value = kvm_read_cr4(vcpu);
4919 break;
4920 case 8:
4921 value = kvm_get_cr8(vcpu);
4922 break;
4923 default:
4924 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4925 return 0;
4926 }
4927
4928 return value;
4929 }
4930
4931 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4932 {
4933 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4934 int res = 0;
4935
4936 switch (cr) {
4937 case 0:
4938 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4939 break;
4940 case 2:
4941 vcpu->arch.cr2 = val;
4942 break;
4943 case 3:
4944 res = kvm_set_cr3(vcpu, val);
4945 break;
4946 case 4:
4947 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4948 break;
4949 case 8:
4950 res = kvm_set_cr8(vcpu, val);
4951 break;
4952 default:
4953 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4954 res = -1;
4955 }
4956
4957 return res;
4958 }
4959
4960 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4961 {
4962 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4963 }
4964
4965 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4966 {
4967 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4968 }
4969
4970 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4971 {
4972 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4973 }
4974
4975 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4976 {
4977 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4978 }
4979
4980 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4981 {
4982 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4983 }
4984
4985 static unsigned long emulator_get_cached_segment_base(
4986 struct x86_emulate_ctxt *ctxt, int seg)
4987 {
4988 return get_segment_base(emul_to_vcpu(ctxt), seg);
4989 }
4990
4991 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4992 struct desc_struct *desc, u32 *base3,
4993 int seg)
4994 {
4995 struct kvm_segment var;
4996
4997 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4998 *selector = var.selector;
4999
5000 if (var.unusable) {
5001 memset(desc, 0, sizeof(*desc));
5002 return false;
5003 }
5004
5005 if (var.g)
5006 var.limit >>= 12;
5007 set_desc_limit(desc, var.limit);
5008 set_desc_base(desc, (unsigned long)var.base);
5009 #ifdef CONFIG_X86_64
5010 if (base3)
5011 *base3 = var.base >> 32;
5012 #endif
5013 desc->type = var.type;
5014 desc->s = var.s;
5015 desc->dpl = var.dpl;
5016 desc->p = var.present;
5017 desc->avl = var.avl;
5018 desc->l = var.l;
5019 desc->d = var.db;
5020 desc->g = var.g;
5021
5022 return true;
5023 }
5024
5025 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5026 struct desc_struct *desc, u32 base3,
5027 int seg)
5028 {
5029 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5030 struct kvm_segment var;
5031
5032 var.selector = selector;
5033 var.base = get_desc_base(desc);
5034 #ifdef CONFIG_X86_64
5035 var.base |= ((u64)base3) << 32;
5036 #endif
5037 var.limit = get_desc_limit(desc);
5038 if (desc->g)
5039 var.limit = (var.limit << 12) | 0xfff;
5040 var.type = desc->type;
5041 var.dpl = desc->dpl;
5042 var.db = desc->d;
5043 var.s = desc->s;
5044 var.l = desc->l;
5045 var.g = desc->g;
5046 var.avl = desc->avl;
5047 var.present = desc->p;
5048 var.unusable = !var.present;
5049 var.padding = 0;
5050
5051 kvm_set_segment(vcpu, &var, seg);
5052 return;
5053 }
5054
5055 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5056 u32 msr_index, u64 *pdata)
5057 {
5058 struct msr_data msr;
5059 int r;
5060
5061 msr.index = msr_index;
5062 msr.host_initiated = false;
5063 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5064 if (r)
5065 return r;
5066
5067 *pdata = msr.data;
5068 return 0;
5069 }
5070
5071 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5072 u32 msr_index, u64 data)
5073 {
5074 struct msr_data msr;
5075
5076 msr.data = data;
5077 msr.index = msr_index;
5078 msr.host_initiated = false;
5079 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5080 }
5081
5082 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5083 {
5084 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5085
5086 return vcpu->arch.smbase;
5087 }
5088
5089 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5090 {
5091 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5092
5093 vcpu->arch.smbase = smbase;
5094 }
5095
5096 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5097 u32 pmc)
5098 {
5099 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5100 }
5101
5102 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5103 u32 pmc, u64 *pdata)
5104 {
5105 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5106 }
5107
5108 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5109 {
5110 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5111 }
5112
5113 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5114 {
5115 preempt_disable();
5116 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5117 /*
5118 * CR0.TS may reference the host fpu state, not the guest fpu state,
5119 * so it may be clear at this point.
5120 */
5121 clts();
5122 }
5123
5124 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5125 {
5126 preempt_enable();
5127 }
5128
5129 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5130 struct x86_instruction_info *info,
5131 enum x86_intercept_stage stage)
5132 {
5133 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5134 }
5135
5136 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5137 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5138 {
5139 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5140 }
5141
5142 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5143 {
5144 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5145 }
5146
5147 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5148 {
5149 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5150 }
5151
5152 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5153 {
5154 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5155 }
5156
5157 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5158 {
5159 return emul_to_vcpu(ctxt)->arch.hflags;
5160 }
5161
5162 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5163 {
5164 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5165 }
5166
5167 static const struct x86_emulate_ops emulate_ops = {
5168 .read_gpr = emulator_read_gpr,
5169 .write_gpr = emulator_write_gpr,
5170 .read_std = kvm_read_guest_virt_system,
5171 .write_std = kvm_write_guest_virt_system,
5172 .read_phys = kvm_read_guest_phys_system,
5173 .fetch = kvm_fetch_guest_virt,
5174 .read_emulated = emulator_read_emulated,
5175 .write_emulated = emulator_write_emulated,
5176 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5177 .invlpg = emulator_invlpg,
5178 .pio_in_emulated = emulator_pio_in_emulated,
5179 .pio_out_emulated = emulator_pio_out_emulated,
5180 .get_segment = emulator_get_segment,
5181 .set_segment = emulator_set_segment,
5182 .get_cached_segment_base = emulator_get_cached_segment_base,
5183 .get_gdt = emulator_get_gdt,
5184 .get_idt = emulator_get_idt,
5185 .set_gdt = emulator_set_gdt,
5186 .set_idt = emulator_set_idt,
5187 .get_cr = emulator_get_cr,
5188 .set_cr = emulator_set_cr,
5189 .cpl = emulator_get_cpl,
5190 .get_dr = emulator_get_dr,
5191 .set_dr = emulator_set_dr,
5192 .get_smbase = emulator_get_smbase,
5193 .set_smbase = emulator_set_smbase,
5194 .set_msr = emulator_set_msr,
5195 .get_msr = emulator_get_msr,
5196 .check_pmc = emulator_check_pmc,
5197 .read_pmc = emulator_read_pmc,
5198 .halt = emulator_halt,
5199 .wbinvd = emulator_wbinvd,
5200 .fix_hypercall = emulator_fix_hypercall,
5201 .get_fpu = emulator_get_fpu,
5202 .put_fpu = emulator_put_fpu,
5203 .intercept = emulator_intercept,
5204 .get_cpuid = emulator_get_cpuid,
5205 .set_nmi_mask = emulator_set_nmi_mask,
5206 .get_hflags = emulator_get_hflags,
5207 .set_hflags = emulator_set_hflags,
5208 };
5209
5210 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5211 {
5212 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5213 /*
5214 * an sti; sti; sequence only disable interrupts for the first
5215 * instruction. So, if the last instruction, be it emulated or
5216 * not, left the system with the INT_STI flag enabled, it
5217 * means that the last instruction is an sti. We should not
5218 * leave the flag on in this case. The same goes for mov ss
5219 */
5220 if (int_shadow & mask)
5221 mask = 0;
5222 if (unlikely(int_shadow || mask)) {
5223 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5224 if (!mask)
5225 kvm_make_request(KVM_REQ_EVENT, vcpu);
5226 }
5227 }
5228
5229 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5230 {
5231 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5232 if (ctxt->exception.vector == PF_VECTOR)
5233 return kvm_propagate_fault(vcpu, &ctxt->exception);
5234
5235 if (ctxt->exception.error_code_valid)
5236 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5237 ctxt->exception.error_code);
5238 else
5239 kvm_queue_exception(vcpu, ctxt->exception.vector);
5240 return false;
5241 }
5242
5243 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5244 {
5245 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5246 int cs_db, cs_l;
5247
5248 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5249
5250 ctxt->eflags = kvm_get_rflags(vcpu);
5251 ctxt->eip = kvm_rip_read(vcpu);
5252 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5253 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5254 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5255 cs_db ? X86EMUL_MODE_PROT32 :
5256 X86EMUL_MODE_PROT16;
5257 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5258 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5259 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5260
5261 init_decode_cache(ctxt);
5262 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5263 }
5264
5265 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5266 {
5267 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5268 int ret;
5269
5270 init_emulate_ctxt(vcpu);
5271
5272 ctxt->op_bytes = 2;
5273 ctxt->ad_bytes = 2;
5274 ctxt->_eip = ctxt->eip + inc_eip;
5275 ret = emulate_int_real(ctxt, irq);
5276
5277 if (ret != X86EMUL_CONTINUE)
5278 return EMULATE_FAIL;
5279
5280 ctxt->eip = ctxt->_eip;
5281 kvm_rip_write(vcpu, ctxt->eip);
5282 kvm_set_rflags(vcpu, ctxt->eflags);
5283
5284 if (irq == NMI_VECTOR)
5285 vcpu->arch.nmi_pending = 0;
5286 else
5287 vcpu->arch.interrupt.pending = false;
5288
5289 return EMULATE_DONE;
5290 }
5291 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5292
5293 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5294 {
5295 int r = EMULATE_DONE;
5296
5297 ++vcpu->stat.insn_emulation_fail;
5298 trace_kvm_emulate_insn_failed(vcpu);
5299 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5300 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5301 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5302 vcpu->run->internal.ndata = 0;
5303 r = EMULATE_FAIL;
5304 }
5305 kvm_queue_exception(vcpu, UD_VECTOR);
5306
5307 return r;
5308 }
5309
5310 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5311 bool write_fault_to_shadow_pgtable,
5312 int emulation_type)
5313 {
5314 gpa_t gpa = cr2;
5315 kvm_pfn_t pfn;
5316
5317 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5318 return false;
5319
5320 if (!vcpu->arch.mmu.direct_map) {
5321 /*
5322 * Write permission should be allowed since only
5323 * write access need to be emulated.
5324 */
5325 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5326
5327 /*
5328 * If the mapping is invalid in guest, let cpu retry
5329 * it to generate fault.
5330 */
5331 if (gpa == UNMAPPED_GVA)
5332 return true;
5333 }
5334
5335 /*
5336 * Do not retry the unhandleable instruction if it faults on the
5337 * readonly host memory, otherwise it will goto a infinite loop:
5338 * retry instruction -> write #PF -> emulation fail -> retry
5339 * instruction -> ...
5340 */
5341 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5342
5343 /*
5344 * If the instruction failed on the error pfn, it can not be fixed,
5345 * report the error to userspace.
5346 */
5347 if (is_error_noslot_pfn(pfn))
5348 return false;
5349
5350 kvm_release_pfn_clean(pfn);
5351
5352 /* The instructions are well-emulated on direct mmu. */
5353 if (vcpu->arch.mmu.direct_map) {
5354 unsigned int indirect_shadow_pages;
5355
5356 spin_lock(&vcpu->kvm->mmu_lock);
5357 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5358 spin_unlock(&vcpu->kvm->mmu_lock);
5359
5360 if (indirect_shadow_pages)
5361 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5362
5363 return true;
5364 }
5365
5366 /*
5367 * if emulation was due to access to shadowed page table
5368 * and it failed try to unshadow page and re-enter the
5369 * guest to let CPU execute the instruction.
5370 */
5371 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5372
5373 /*
5374 * If the access faults on its page table, it can not
5375 * be fixed by unprotecting shadow page and it should
5376 * be reported to userspace.
5377 */
5378 return !write_fault_to_shadow_pgtable;
5379 }
5380
5381 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5382 unsigned long cr2, int emulation_type)
5383 {
5384 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5385 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5386
5387 last_retry_eip = vcpu->arch.last_retry_eip;
5388 last_retry_addr = vcpu->arch.last_retry_addr;
5389
5390 /*
5391 * If the emulation is caused by #PF and it is non-page_table
5392 * writing instruction, it means the VM-EXIT is caused by shadow
5393 * page protected, we can zap the shadow page and retry this
5394 * instruction directly.
5395 *
5396 * Note: if the guest uses a non-page-table modifying instruction
5397 * on the PDE that points to the instruction, then we will unmap
5398 * the instruction and go to an infinite loop. So, we cache the
5399 * last retried eip and the last fault address, if we meet the eip
5400 * and the address again, we can break out of the potential infinite
5401 * loop.
5402 */
5403 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5404
5405 if (!(emulation_type & EMULTYPE_RETRY))
5406 return false;
5407
5408 if (x86_page_table_writing_insn(ctxt))
5409 return false;
5410
5411 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5412 return false;
5413
5414 vcpu->arch.last_retry_eip = ctxt->eip;
5415 vcpu->arch.last_retry_addr = cr2;
5416
5417 if (!vcpu->arch.mmu.direct_map)
5418 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5419
5420 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5421
5422 return true;
5423 }
5424
5425 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5426 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5427
5428 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5429 {
5430 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5431 /* This is a good place to trace that we are exiting SMM. */
5432 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5433
5434 /* Process a latched INIT or SMI, if any. */
5435 kvm_make_request(KVM_REQ_EVENT, vcpu);
5436 }
5437
5438 kvm_mmu_reset_context(vcpu);
5439 }
5440
5441 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5442 {
5443 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5444
5445 vcpu->arch.hflags = emul_flags;
5446
5447 if (changed & HF_SMM_MASK)
5448 kvm_smm_changed(vcpu);
5449 }
5450
5451 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5452 unsigned long *db)
5453 {
5454 u32 dr6 = 0;
5455 int i;
5456 u32 enable, rwlen;
5457
5458 enable = dr7;
5459 rwlen = dr7 >> 16;
5460 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5461 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5462 dr6 |= (1 << i);
5463 return dr6;
5464 }
5465
5466 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5467 {
5468 struct kvm_run *kvm_run = vcpu->run;
5469
5470 /*
5471 * rflags is the old, "raw" value of the flags. The new value has
5472 * not been saved yet.
5473 *
5474 * This is correct even for TF set by the guest, because "the
5475 * processor will not generate this exception after the instruction
5476 * that sets the TF flag".
5477 */
5478 if (unlikely(rflags & X86_EFLAGS_TF)) {
5479 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5480 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5481 DR6_RTM;
5482 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5483 kvm_run->debug.arch.exception = DB_VECTOR;
5484 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5485 *r = EMULATE_USER_EXIT;
5486 } else {
5487 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5488 /*
5489 * "Certain debug exceptions may clear bit 0-3. The
5490 * remaining contents of the DR6 register are never
5491 * cleared by the processor".
5492 */
5493 vcpu->arch.dr6 &= ~15;
5494 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5495 kvm_queue_exception(vcpu, DB_VECTOR);
5496 }
5497 }
5498 }
5499
5500 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5501 {
5502 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5503 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5504 struct kvm_run *kvm_run = vcpu->run;
5505 unsigned long eip = kvm_get_linear_rip(vcpu);
5506 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5507 vcpu->arch.guest_debug_dr7,
5508 vcpu->arch.eff_db);
5509
5510 if (dr6 != 0) {
5511 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5512 kvm_run->debug.arch.pc = eip;
5513 kvm_run->debug.arch.exception = DB_VECTOR;
5514 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5515 *r = EMULATE_USER_EXIT;
5516 return true;
5517 }
5518 }
5519
5520 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5521 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5522 unsigned long eip = kvm_get_linear_rip(vcpu);
5523 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5524 vcpu->arch.dr7,
5525 vcpu->arch.db);
5526
5527 if (dr6 != 0) {
5528 vcpu->arch.dr6 &= ~15;
5529 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5530 kvm_queue_exception(vcpu, DB_VECTOR);
5531 *r = EMULATE_DONE;
5532 return true;
5533 }
5534 }
5535
5536 return false;
5537 }
5538
5539 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5540 unsigned long cr2,
5541 int emulation_type,
5542 void *insn,
5543 int insn_len)
5544 {
5545 int r;
5546 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5547 bool writeback = true;
5548 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5549
5550 /*
5551 * Clear write_fault_to_shadow_pgtable here to ensure it is
5552 * never reused.
5553 */
5554 vcpu->arch.write_fault_to_shadow_pgtable = false;
5555 kvm_clear_exception_queue(vcpu);
5556
5557 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5558 init_emulate_ctxt(vcpu);
5559
5560 /*
5561 * We will reenter on the same instruction since
5562 * we do not set complete_userspace_io. This does not
5563 * handle watchpoints yet, those would be handled in
5564 * the emulate_ops.
5565 */
5566 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5567 return r;
5568
5569 ctxt->interruptibility = 0;
5570 ctxt->have_exception = false;
5571 ctxt->exception.vector = -1;
5572 ctxt->perm_ok = false;
5573
5574 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5575
5576 r = x86_decode_insn(ctxt, insn, insn_len);
5577
5578 trace_kvm_emulate_insn_start(vcpu);
5579 ++vcpu->stat.insn_emulation;
5580 if (r != EMULATION_OK) {
5581 if (emulation_type & EMULTYPE_TRAP_UD)
5582 return EMULATE_FAIL;
5583 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5584 emulation_type))
5585 return EMULATE_DONE;
5586 if (emulation_type & EMULTYPE_SKIP)
5587 return EMULATE_FAIL;
5588 return handle_emulation_failure(vcpu);
5589 }
5590 }
5591
5592 if (emulation_type & EMULTYPE_SKIP) {
5593 kvm_rip_write(vcpu, ctxt->_eip);
5594 if (ctxt->eflags & X86_EFLAGS_RF)
5595 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5596 return EMULATE_DONE;
5597 }
5598
5599 if (retry_instruction(ctxt, cr2, emulation_type))
5600 return EMULATE_DONE;
5601
5602 /* this is needed for vmware backdoor interface to work since it
5603 changes registers values during IO operation */
5604 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5605 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5606 emulator_invalidate_register_cache(ctxt);
5607 }
5608
5609 restart:
5610 r = x86_emulate_insn(ctxt);
5611
5612 if (r == EMULATION_INTERCEPTED)
5613 return EMULATE_DONE;
5614
5615 if (r == EMULATION_FAILED) {
5616 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5617 emulation_type))
5618 return EMULATE_DONE;
5619
5620 return handle_emulation_failure(vcpu);
5621 }
5622
5623 if (ctxt->have_exception) {
5624 r = EMULATE_DONE;
5625 if (inject_emulated_exception(vcpu))
5626 return r;
5627 } else if (vcpu->arch.pio.count) {
5628 if (!vcpu->arch.pio.in) {
5629 /* FIXME: return into emulator if single-stepping. */
5630 vcpu->arch.pio.count = 0;
5631 } else {
5632 writeback = false;
5633 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5634 }
5635 r = EMULATE_USER_EXIT;
5636 } else if (vcpu->mmio_needed) {
5637 if (!vcpu->mmio_is_write)
5638 writeback = false;
5639 r = EMULATE_USER_EXIT;
5640 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5641 } else if (r == EMULATION_RESTART)
5642 goto restart;
5643 else
5644 r = EMULATE_DONE;
5645
5646 if (writeback) {
5647 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5648 toggle_interruptibility(vcpu, ctxt->interruptibility);
5649 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5650 kvm_rip_write(vcpu, ctxt->eip);
5651 if (r == EMULATE_DONE)
5652 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5653 if (!ctxt->have_exception ||
5654 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5655 __kvm_set_rflags(vcpu, ctxt->eflags);
5656
5657 /*
5658 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5659 * do nothing, and it will be requested again as soon as
5660 * the shadow expires. But we still need to check here,
5661 * because POPF has no interrupt shadow.
5662 */
5663 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5664 kvm_make_request(KVM_REQ_EVENT, vcpu);
5665 } else
5666 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5667
5668 return r;
5669 }
5670 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5671
5672 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5673 {
5674 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5675 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5676 size, port, &val, 1);
5677 /* do not return to emulator after return from userspace */
5678 vcpu->arch.pio.count = 0;
5679 return ret;
5680 }
5681 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5682
5683 static int kvmclock_cpu_down_prep(unsigned int cpu)
5684 {
5685 __this_cpu_write(cpu_tsc_khz, 0);
5686 return 0;
5687 }
5688
5689 static void tsc_khz_changed(void *data)
5690 {
5691 struct cpufreq_freqs *freq = data;
5692 unsigned long khz = 0;
5693
5694 if (data)
5695 khz = freq->new;
5696 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5697 khz = cpufreq_quick_get(raw_smp_processor_id());
5698 if (!khz)
5699 khz = tsc_khz;
5700 __this_cpu_write(cpu_tsc_khz, khz);
5701 }
5702
5703 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5704 void *data)
5705 {
5706 struct cpufreq_freqs *freq = data;
5707 struct kvm *kvm;
5708 struct kvm_vcpu *vcpu;
5709 int i, send_ipi = 0;
5710
5711 /*
5712 * We allow guests to temporarily run on slowing clocks,
5713 * provided we notify them after, or to run on accelerating
5714 * clocks, provided we notify them before. Thus time never
5715 * goes backwards.
5716 *
5717 * However, we have a problem. We can't atomically update
5718 * the frequency of a given CPU from this function; it is
5719 * merely a notifier, which can be called from any CPU.
5720 * Changing the TSC frequency at arbitrary points in time
5721 * requires a recomputation of local variables related to
5722 * the TSC for each VCPU. We must flag these local variables
5723 * to be updated and be sure the update takes place with the
5724 * new frequency before any guests proceed.
5725 *
5726 * Unfortunately, the combination of hotplug CPU and frequency
5727 * change creates an intractable locking scenario; the order
5728 * of when these callouts happen is undefined with respect to
5729 * CPU hotplug, and they can race with each other. As such,
5730 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5731 * undefined; you can actually have a CPU frequency change take
5732 * place in between the computation of X and the setting of the
5733 * variable. To protect against this problem, all updates of
5734 * the per_cpu tsc_khz variable are done in an interrupt
5735 * protected IPI, and all callers wishing to update the value
5736 * must wait for a synchronous IPI to complete (which is trivial
5737 * if the caller is on the CPU already). This establishes the
5738 * necessary total order on variable updates.
5739 *
5740 * Note that because a guest time update may take place
5741 * anytime after the setting of the VCPU's request bit, the
5742 * correct TSC value must be set before the request. However,
5743 * to ensure the update actually makes it to any guest which
5744 * starts running in hardware virtualization between the set
5745 * and the acquisition of the spinlock, we must also ping the
5746 * CPU after setting the request bit.
5747 *
5748 */
5749
5750 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5751 return 0;
5752 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5753 return 0;
5754
5755 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5756
5757 spin_lock(&kvm_lock);
5758 list_for_each_entry(kvm, &vm_list, vm_list) {
5759 kvm_for_each_vcpu(i, vcpu, kvm) {
5760 if (vcpu->cpu != freq->cpu)
5761 continue;
5762 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5763 if (vcpu->cpu != smp_processor_id())
5764 send_ipi = 1;
5765 }
5766 }
5767 spin_unlock(&kvm_lock);
5768
5769 if (freq->old < freq->new && send_ipi) {
5770 /*
5771 * We upscale the frequency. Must make the guest
5772 * doesn't see old kvmclock values while running with
5773 * the new frequency, otherwise we risk the guest sees
5774 * time go backwards.
5775 *
5776 * In case we update the frequency for another cpu
5777 * (which might be in guest context) send an interrupt
5778 * to kick the cpu out of guest context. Next time
5779 * guest context is entered kvmclock will be updated,
5780 * so the guest will not see stale values.
5781 */
5782 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5783 }
5784 return 0;
5785 }
5786
5787 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5788 .notifier_call = kvmclock_cpufreq_notifier
5789 };
5790
5791 static int kvmclock_cpu_online(unsigned int cpu)
5792 {
5793 tsc_khz_changed(NULL);
5794 return 0;
5795 }
5796
5797 static void kvm_timer_init(void)
5798 {
5799 max_tsc_khz = tsc_khz;
5800
5801 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5802 #ifdef CONFIG_CPU_FREQ
5803 struct cpufreq_policy policy;
5804 int cpu;
5805
5806 memset(&policy, 0, sizeof(policy));
5807 cpu = get_cpu();
5808 cpufreq_get_policy(&policy, cpu);
5809 if (policy.cpuinfo.max_freq)
5810 max_tsc_khz = policy.cpuinfo.max_freq;
5811 put_cpu();
5812 #endif
5813 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5814 CPUFREQ_TRANSITION_NOTIFIER);
5815 }
5816 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5817
5818 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "AP_X86_KVM_CLK_ONLINE",
5819 kvmclock_cpu_online, kvmclock_cpu_down_prep);
5820 }
5821
5822 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5823
5824 int kvm_is_in_guest(void)
5825 {
5826 return __this_cpu_read(current_vcpu) != NULL;
5827 }
5828
5829 static int kvm_is_user_mode(void)
5830 {
5831 int user_mode = 3;
5832
5833 if (__this_cpu_read(current_vcpu))
5834 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5835
5836 return user_mode != 0;
5837 }
5838
5839 static unsigned long kvm_get_guest_ip(void)
5840 {
5841 unsigned long ip = 0;
5842
5843 if (__this_cpu_read(current_vcpu))
5844 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5845
5846 return ip;
5847 }
5848
5849 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5850 .is_in_guest = kvm_is_in_guest,
5851 .is_user_mode = kvm_is_user_mode,
5852 .get_guest_ip = kvm_get_guest_ip,
5853 };
5854
5855 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5856 {
5857 __this_cpu_write(current_vcpu, vcpu);
5858 }
5859 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5860
5861 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5862 {
5863 __this_cpu_write(current_vcpu, NULL);
5864 }
5865 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5866
5867 static void kvm_set_mmio_spte_mask(void)
5868 {
5869 u64 mask;
5870 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5871
5872 /*
5873 * Set the reserved bits and the present bit of an paging-structure
5874 * entry to generate page fault with PFER.RSV = 1.
5875 */
5876 /* Mask the reserved physical address bits. */
5877 mask = rsvd_bits(maxphyaddr, 51);
5878
5879 /* Bit 62 is always reserved for 32bit host. */
5880 mask |= 0x3ull << 62;
5881
5882 /* Set the present bit. */
5883 mask |= 1ull;
5884
5885 #ifdef CONFIG_X86_64
5886 /*
5887 * If reserved bit is not supported, clear the present bit to disable
5888 * mmio page fault.
5889 */
5890 if (maxphyaddr == 52)
5891 mask &= ~1ull;
5892 #endif
5893
5894 kvm_mmu_set_mmio_spte_mask(mask);
5895 }
5896
5897 #ifdef CONFIG_X86_64
5898 static void pvclock_gtod_update_fn(struct work_struct *work)
5899 {
5900 struct kvm *kvm;
5901
5902 struct kvm_vcpu *vcpu;
5903 int i;
5904
5905 spin_lock(&kvm_lock);
5906 list_for_each_entry(kvm, &vm_list, vm_list)
5907 kvm_for_each_vcpu(i, vcpu, kvm)
5908 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5909 atomic_set(&kvm_guest_has_master_clock, 0);
5910 spin_unlock(&kvm_lock);
5911 }
5912
5913 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5914
5915 /*
5916 * Notification about pvclock gtod data update.
5917 */
5918 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5919 void *priv)
5920 {
5921 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5922 struct timekeeper *tk = priv;
5923
5924 update_pvclock_gtod(tk);
5925
5926 /* disable master clock if host does not trust, or does not
5927 * use, TSC clocksource
5928 */
5929 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5930 atomic_read(&kvm_guest_has_master_clock) != 0)
5931 queue_work(system_long_wq, &pvclock_gtod_work);
5932
5933 return 0;
5934 }
5935
5936 static struct notifier_block pvclock_gtod_notifier = {
5937 .notifier_call = pvclock_gtod_notify,
5938 };
5939 #endif
5940
5941 int kvm_arch_init(void *opaque)
5942 {
5943 int r;
5944 struct kvm_x86_ops *ops = opaque;
5945
5946 if (kvm_x86_ops) {
5947 printk(KERN_ERR "kvm: already loaded the other module\n");
5948 r = -EEXIST;
5949 goto out;
5950 }
5951
5952 if (!ops->cpu_has_kvm_support()) {
5953 printk(KERN_ERR "kvm: no hardware support\n");
5954 r = -EOPNOTSUPP;
5955 goto out;
5956 }
5957 if (ops->disabled_by_bios()) {
5958 printk(KERN_ERR "kvm: disabled by bios\n");
5959 r = -EOPNOTSUPP;
5960 goto out;
5961 }
5962
5963 r = -ENOMEM;
5964 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5965 if (!shared_msrs) {
5966 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5967 goto out;
5968 }
5969
5970 r = kvm_mmu_module_init();
5971 if (r)
5972 goto out_free_percpu;
5973
5974 kvm_set_mmio_spte_mask();
5975
5976 kvm_x86_ops = ops;
5977
5978 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5979 PT_DIRTY_MASK, PT64_NX_MASK, 0,
5980 PT_PRESENT_MASK);
5981 kvm_timer_init();
5982
5983 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5984
5985 if (boot_cpu_has(X86_FEATURE_XSAVE))
5986 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5987
5988 kvm_lapic_init();
5989 #ifdef CONFIG_X86_64
5990 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5991 #endif
5992
5993 return 0;
5994
5995 out_free_percpu:
5996 free_percpu(shared_msrs);
5997 out:
5998 return r;
5999 }
6000
6001 void kvm_arch_exit(void)
6002 {
6003 kvm_lapic_exit();
6004 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6005
6006 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6007 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6008 CPUFREQ_TRANSITION_NOTIFIER);
6009 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6010 #ifdef CONFIG_X86_64
6011 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6012 #endif
6013 kvm_x86_ops = NULL;
6014 kvm_mmu_module_exit();
6015 free_percpu(shared_msrs);
6016 }
6017
6018 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6019 {
6020 ++vcpu->stat.halt_exits;
6021 if (lapic_in_kernel(vcpu)) {
6022 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6023 return 1;
6024 } else {
6025 vcpu->run->exit_reason = KVM_EXIT_HLT;
6026 return 0;
6027 }
6028 }
6029 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6030
6031 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6032 {
6033 kvm_x86_ops->skip_emulated_instruction(vcpu);
6034 return kvm_vcpu_halt(vcpu);
6035 }
6036 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6037
6038 /*
6039 * kvm_pv_kick_cpu_op: Kick a vcpu.
6040 *
6041 * @apicid - apicid of vcpu to be kicked.
6042 */
6043 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6044 {
6045 struct kvm_lapic_irq lapic_irq;
6046
6047 lapic_irq.shorthand = 0;
6048 lapic_irq.dest_mode = 0;
6049 lapic_irq.dest_id = apicid;
6050 lapic_irq.msi_redir_hint = false;
6051
6052 lapic_irq.delivery_mode = APIC_DM_REMRD;
6053 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6054 }
6055
6056 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6057 {
6058 vcpu->arch.apicv_active = false;
6059 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6060 }
6061
6062 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6063 {
6064 unsigned long nr, a0, a1, a2, a3, ret;
6065 int op_64_bit, r = 1;
6066
6067 kvm_x86_ops->skip_emulated_instruction(vcpu);
6068
6069 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6070 return kvm_hv_hypercall(vcpu);
6071
6072 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6073 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6074 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6075 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6076 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
6077
6078 trace_kvm_hypercall(nr, a0, a1, a2, a3);
6079
6080 op_64_bit = is_64_bit_mode(vcpu);
6081 if (!op_64_bit) {
6082 nr &= 0xFFFFFFFF;
6083 a0 &= 0xFFFFFFFF;
6084 a1 &= 0xFFFFFFFF;
6085 a2 &= 0xFFFFFFFF;
6086 a3 &= 0xFFFFFFFF;
6087 }
6088
6089 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6090 ret = -KVM_EPERM;
6091 goto out;
6092 }
6093
6094 switch (nr) {
6095 case KVM_HC_VAPIC_POLL_IRQ:
6096 ret = 0;
6097 break;
6098 case KVM_HC_KICK_CPU:
6099 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6100 ret = 0;
6101 break;
6102 default:
6103 ret = -KVM_ENOSYS;
6104 break;
6105 }
6106 out:
6107 if (!op_64_bit)
6108 ret = (u32)ret;
6109 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6110 ++vcpu->stat.hypercalls;
6111 return r;
6112 }
6113 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6114
6115 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6116 {
6117 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6118 char instruction[3];
6119 unsigned long rip = kvm_rip_read(vcpu);
6120
6121 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6122
6123 return emulator_write_emulated(ctxt, rip, instruction, 3,
6124 &ctxt->exception);
6125 }
6126
6127 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6128 {
6129 return vcpu->run->request_interrupt_window &&
6130 likely(!pic_in_kernel(vcpu->kvm));
6131 }
6132
6133 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6134 {
6135 struct kvm_run *kvm_run = vcpu->run;
6136
6137 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6138 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6139 kvm_run->cr8 = kvm_get_cr8(vcpu);
6140 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6141 kvm_run->ready_for_interrupt_injection =
6142 pic_in_kernel(vcpu->kvm) ||
6143 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6144 }
6145
6146 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6147 {
6148 int max_irr, tpr;
6149
6150 if (!kvm_x86_ops->update_cr8_intercept)
6151 return;
6152
6153 if (!lapic_in_kernel(vcpu))
6154 return;
6155
6156 if (vcpu->arch.apicv_active)
6157 return;
6158
6159 if (!vcpu->arch.apic->vapic_addr)
6160 max_irr = kvm_lapic_find_highest_irr(vcpu);
6161 else
6162 max_irr = -1;
6163
6164 if (max_irr != -1)
6165 max_irr >>= 4;
6166
6167 tpr = kvm_lapic_get_cr8(vcpu);
6168
6169 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6170 }
6171
6172 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6173 {
6174 int r;
6175
6176 /* try to reinject previous events if any */
6177 if (vcpu->arch.exception.pending) {
6178 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6179 vcpu->arch.exception.has_error_code,
6180 vcpu->arch.exception.error_code);
6181
6182 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6183 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6184 X86_EFLAGS_RF);
6185
6186 if (vcpu->arch.exception.nr == DB_VECTOR &&
6187 (vcpu->arch.dr7 & DR7_GD)) {
6188 vcpu->arch.dr7 &= ~DR7_GD;
6189 kvm_update_dr7(vcpu);
6190 }
6191
6192 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6193 vcpu->arch.exception.has_error_code,
6194 vcpu->arch.exception.error_code,
6195 vcpu->arch.exception.reinject);
6196 return 0;
6197 }
6198
6199 if (vcpu->arch.nmi_injected) {
6200 kvm_x86_ops->set_nmi(vcpu);
6201 return 0;
6202 }
6203
6204 if (vcpu->arch.interrupt.pending) {
6205 kvm_x86_ops->set_irq(vcpu);
6206 return 0;
6207 }
6208
6209 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6210 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6211 if (r != 0)
6212 return r;
6213 }
6214
6215 /* try to inject new event if pending */
6216 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6217 vcpu->arch.smi_pending = false;
6218 enter_smm(vcpu);
6219 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6220 --vcpu->arch.nmi_pending;
6221 vcpu->arch.nmi_injected = true;
6222 kvm_x86_ops->set_nmi(vcpu);
6223 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6224 /*
6225 * Because interrupts can be injected asynchronously, we are
6226 * calling check_nested_events again here to avoid a race condition.
6227 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6228 * proposal and current concerns. Perhaps we should be setting
6229 * KVM_REQ_EVENT only on certain events and not unconditionally?
6230 */
6231 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6232 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6233 if (r != 0)
6234 return r;
6235 }
6236 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6237 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6238 false);
6239 kvm_x86_ops->set_irq(vcpu);
6240 }
6241 }
6242
6243 return 0;
6244 }
6245
6246 static void process_nmi(struct kvm_vcpu *vcpu)
6247 {
6248 unsigned limit = 2;
6249
6250 /*
6251 * x86 is limited to one NMI running, and one NMI pending after it.
6252 * If an NMI is already in progress, limit further NMIs to just one.
6253 * Otherwise, allow two (and we'll inject the first one immediately).
6254 */
6255 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6256 limit = 1;
6257
6258 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6259 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6260 kvm_make_request(KVM_REQ_EVENT, vcpu);
6261 }
6262
6263 #define put_smstate(type, buf, offset, val) \
6264 *(type *)((buf) + (offset) - 0x7e00) = val
6265
6266 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
6267 {
6268 u32 flags = 0;
6269 flags |= seg->g << 23;
6270 flags |= seg->db << 22;
6271 flags |= seg->l << 21;
6272 flags |= seg->avl << 20;
6273 flags |= seg->present << 15;
6274 flags |= seg->dpl << 13;
6275 flags |= seg->s << 12;
6276 flags |= seg->type << 8;
6277 return flags;
6278 }
6279
6280 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6281 {
6282 struct kvm_segment seg;
6283 int offset;
6284
6285 kvm_get_segment(vcpu, &seg, n);
6286 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6287
6288 if (n < 3)
6289 offset = 0x7f84 + n * 12;
6290 else
6291 offset = 0x7f2c + (n - 3) * 12;
6292
6293 put_smstate(u32, buf, offset + 8, seg.base);
6294 put_smstate(u32, buf, offset + 4, seg.limit);
6295 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
6296 }
6297
6298 #ifdef CONFIG_X86_64
6299 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6300 {
6301 struct kvm_segment seg;
6302 int offset;
6303 u16 flags;
6304
6305 kvm_get_segment(vcpu, &seg, n);
6306 offset = 0x7e00 + n * 16;
6307
6308 flags = enter_smm_get_segment_flags(&seg) >> 8;
6309 put_smstate(u16, buf, offset, seg.selector);
6310 put_smstate(u16, buf, offset + 2, flags);
6311 put_smstate(u32, buf, offset + 4, seg.limit);
6312 put_smstate(u64, buf, offset + 8, seg.base);
6313 }
6314 #endif
6315
6316 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6317 {
6318 struct desc_ptr dt;
6319 struct kvm_segment seg;
6320 unsigned long val;
6321 int i;
6322
6323 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6324 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6325 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6326 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6327
6328 for (i = 0; i < 8; i++)
6329 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6330
6331 kvm_get_dr(vcpu, 6, &val);
6332 put_smstate(u32, buf, 0x7fcc, (u32)val);
6333 kvm_get_dr(vcpu, 7, &val);
6334 put_smstate(u32, buf, 0x7fc8, (u32)val);
6335
6336 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6337 put_smstate(u32, buf, 0x7fc4, seg.selector);
6338 put_smstate(u32, buf, 0x7f64, seg.base);
6339 put_smstate(u32, buf, 0x7f60, seg.limit);
6340 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
6341
6342 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6343 put_smstate(u32, buf, 0x7fc0, seg.selector);
6344 put_smstate(u32, buf, 0x7f80, seg.base);
6345 put_smstate(u32, buf, 0x7f7c, seg.limit);
6346 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
6347
6348 kvm_x86_ops->get_gdt(vcpu, &dt);
6349 put_smstate(u32, buf, 0x7f74, dt.address);
6350 put_smstate(u32, buf, 0x7f70, dt.size);
6351
6352 kvm_x86_ops->get_idt(vcpu, &dt);
6353 put_smstate(u32, buf, 0x7f58, dt.address);
6354 put_smstate(u32, buf, 0x7f54, dt.size);
6355
6356 for (i = 0; i < 6; i++)
6357 enter_smm_save_seg_32(vcpu, buf, i);
6358
6359 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6360
6361 /* revision id */
6362 put_smstate(u32, buf, 0x7efc, 0x00020000);
6363 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6364 }
6365
6366 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6367 {
6368 #ifdef CONFIG_X86_64
6369 struct desc_ptr dt;
6370 struct kvm_segment seg;
6371 unsigned long val;
6372 int i;
6373
6374 for (i = 0; i < 16; i++)
6375 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6376
6377 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6378 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6379
6380 kvm_get_dr(vcpu, 6, &val);
6381 put_smstate(u64, buf, 0x7f68, val);
6382 kvm_get_dr(vcpu, 7, &val);
6383 put_smstate(u64, buf, 0x7f60, val);
6384
6385 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6386 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6387 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6388
6389 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6390
6391 /* revision id */
6392 put_smstate(u32, buf, 0x7efc, 0x00020064);
6393
6394 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6395
6396 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6397 put_smstate(u16, buf, 0x7e90, seg.selector);
6398 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
6399 put_smstate(u32, buf, 0x7e94, seg.limit);
6400 put_smstate(u64, buf, 0x7e98, seg.base);
6401
6402 kvm_x86_ops->get_idt(vcpu, &dt);
6403 put_smstate(u32, buf, 0x7e84, dt.size);
6404 put_smstate(u64, buf, 0x7e88, dt.address);
6405
6406 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6407 put_smstate(u16, buf, 0x7e70, seg.selector);
6408 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
6409 put_smstate(u32, buf, 0x7e74, seg.limit);
6410 put_smstate(u64, buf, 0x7e78, seg.base);
6411
6412 kvm_x86_ops->get_gdt(vcpu, &dt);
6413 put_smstate(u32, buf, 0x7e64, dt.size);
6414 put_smstate(u64, buf, 0x7e68, dt.address);
6415
6416 for (i = 0; i < 6; i++)
6417 enter_smm_save_seg_64(vcpu, buf, i);
6418 #else
6419 WARN_ON_ONCE(1);
6420 #endif
6421 }
6422
6423 static void enter_smm(struct kvm_vcpu *vcpu)
6424 {
6425 struct kvm_segment cs, ds;
6426 struct desc_ptr dt;
6427 char buf[512];
6428 u32 cr0;
6429
6430 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6431 vcpu->arch.hflags |= HF_SMM_MASK;
6432 memset(buf, 0, 512);
6433 if (guest_cpuid_has_longmode(vcpu))
6434 enter_smm_save_state_64(vcpu, buf);
6435 else
6436 enter_smm_save_state_32(vcpu, buf);
6437
6438 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6439
6440 if (kvm_x86_ops->get_nmi_mask(vcpu))
6441 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6442 else
6443 kvm_x86_ops->set_nmi_mask(vcpu, true);
6444
6445 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6446 kvm_rip_write(vcpu, 0x8000);
6447
6448 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6449 kvm_x86_ops->set_cr0(vcpu, cr0);
6450 vcpu->arch.cr0 = cr0;
6451
6452 kvm_x86_ops->set_cr4(vcpu, 0);
6453
6454 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6455 dt.address = dt.size = 0;
6456 kvm_x86_ops->set_idt(vcpu, &dt);
6457
6458 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6459
6460 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6461 cs.base = vcpu->arch.smbase;
6462
6463 ds.selector = 0;
6464 ds.base = 0;
6465
6466 cs.limit = ds.limit = 0xffffffff;
6467 cs.type = ds.type = 0x3;
6468 cs.dpl = ds.dpl = 0;
6469 cs.db = ds.db = 0;
6470 cs.s = ds.s = 1;
6471 cs.l = ds.l = 0;
6472 cs.g = ds.g = 1;
6473 cs.avl = ds.avl = 0;
6474 cs.present = ds.present = 1;
6475 cs.unusable = ds.unusable = 0;
6476 cs.padding = ds.padding = 0;
6477
6478 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6479 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6480 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6481 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6482 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6483 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6484
6485 if (guest_cpuid_has_longmode(vcpu))
6486 kvm_x86_ops->set_efer(vcpu, 0);
6487
6488 kvm_update_cpuid(vcpu);
6489 kvm_mmu_reset_context(vcpu);
6490 }
6491
6492 static void process_smi(struct kvm_vcpu *vcpu)
6493 {
6494 vcpu->arch.smi_pending = true;
6495 kvm_make_request(KVM_REQ_EVENT, vcpu);
6496 }
6497
6498 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6499 {
6500 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6501 }
6502
6503 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6504 {
6505 u64 eoi_exit_bitmap[4];
6506
6507 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6508 return;
6509
6510 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6511
6512 if (irqchip_split(vcpu->kvm))
6513 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6514 else {
6515 if (vcpu->arch.apicv_active)
6516 kvm_x86_ops->sync_pir_to_irr(vcpu);
6517 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6518 }
6519 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6520 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6521 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6522 }
6523
6524 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6525 {
6526 ++vcpu->stat.tlb_flush;
6527 kvm_x86_ops->tlb_flush(vcpu);
6528 }
6529
6530 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6531 {
6532 struct page *page = NULL;
6533
6534 if (!lapic_in_kernel(vcpu))
6535 return;
6536
6537 if (!kvm_x86_ops->set_apic_access_page_addr)
6538 return;
6539
6540 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6541 if (is_error_page(page))
6542 return;
6543 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6544
6545 /*
6546 * Do not pin apic access page in memory, the MMU notifier
6547 * will call us again if it is migrated or swapped out.
6548 */
6549 put_page(page);
6550 }
6551 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6552
6553 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6554 unsigned long address)
6555 {
6556 /*
6557 * The physical address of apic access page is stored in the VMCS.
6558 * Update it when it becomes invalid.
6559 */
6560 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6561 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6562 }
6563
6564 /*
6565 * Returns 1 to let vcpu_run() continue the guest execution loop without
6566 * exiting to the userspace. Otherwise, the value will be returned to the
6567 * userspace.
6568 */
6569 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6570 {
6571 int r;
6572 bool req_int_win =
6573 dm_request_for_irq_injection(vcpu) &&
6574 kvm_cpu_accept_dm_intr(vcpu);
6575
6576 bool req_immediate_exit = false;
6577
6578 if (vcpu->requests) {
6579 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6580 kvm_mmu_unload(vcpu);
6581 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6582 __kvm_migrate_timers(vcpu);
6583 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6584 kvm_gen_update_masterclock(vcpu->kvm);
6585 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6586 kvm_gen_kvmclock_update(vcpu);
6587 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6588 r = kvm_guest_time_update(vcpu);
6589 if (unlikely(r))
6590 goto out;
6591 }
6592 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6593 kvm_mmu_sync_roots(vcpu);
6594 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6595 kvm_vcpu_flush_tlb(vcpu);
6596 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6597 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6598 r = 0;
6599 goto out;
6600 }
6601 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6602 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6603 r = 0;
6604 goto out;
6605 }
6606 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6607 vcpu->fpu_active = 0;
6608 kvm_x86_ops->fpu_deactivate(vcpu);
6609 }
6610 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6611 /* Page is swapped out. Do synthetic halt */
6612 vcpu->arch.apf.halted = true;
6613 r = 1;
6614 goto out;
6615 }
6616 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6617 record_steal_time(vcpu);
6618 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6619 process_smi(vcpu);
6620 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6621 process_nmi(vcpu);
6622 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6623 kvm_pmu_handle_event(vcpu);
6624 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6625 kvm_pmu_deliver_pmi(vcpu);
6626 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6627 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6628 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6629 vcpu->arch.ioapic_handled_vectors)) {
6630 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6631 vcpu->run->eoi.vector =
6632 vcpu->arch.pending_ioapic_eoi;
6633 r = 0;
6634 goto out;
6635 }
6636 }
6637 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6638 vcpu_scan_ioapic(vcpu);
6639 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6640 kvm_vcpu_reload_apic_access_page(vcpu);
6641 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6642 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6643 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6644 r = 0;
6645 goto out;
6646 }
6647 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6648 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6649 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6650 r = 0;
6651 goto out;
6652 }
6653 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6654 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6655 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6656 r = 0;
6657 goto out;
6658 }
6659
6660 /*
6661 * KVM_REQ_HV_STIMER has to be processed after
6662 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6663 * depend on the guest clock being up-to-date
6664 */
6665 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6666 kvm_hv_process_stimers(vcpu);
6667 }
6668
6669 /*
6670 * KVM_REQ_EVENT is not set when posted interrupts are set by
6671 * VT-d hardware, so we have to update RVI unconditionally.
6672 */
6673 if (kvm_lapic_enabled(vcpu)) {
6674 /*
6675 * Update architecture specific hints for APIC
6676 * virtual interrupt delivery.
6677 */
6678 if (vcpu->arch.apicv_active)
6679 kvm_x86_ops->hwapic_irr_update(vcpu,
6680 kvm_lapic_find_highest_irr(vcpu));
6681 }
6682
6683 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6684 kvm_apic_accept_events(vcpu);
6685 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6686 r = 1;
6687 goto out;
6688 }
6689
6690 if (inject_pending_event(vcpu, req_int_win) != 0)
6691 req_immediate_exit = true;
6692 else {
6693 /* Enable NMI/IRQ window open exits if needed.
6694 *
6695 * SMIs have two cases: 1) they can be nested, and
6696 * then there is nothing to do here because RSM will
6697 * cause a vmexit anyway; 2) or the SMI can be pending
6698 * because inject_pending_event has completed the
6699 * injection of an IRQ or NMI from the previous vmexit,
6700 * and then we request an immediate exit to inject the SMI.
6701 */
6702 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6703 req_immediate_exit = true;
6704 if (vcpu->arch.nmi_pending)
6705 kvm_x86_ops->enable_nmi_window(vcpu);
6706 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6707 kvm_x86_ops->enable_irq_window(vcpu);
6708 }
6709
6710 if (kvm_lapic_enabled(vcpu)) {
6711 update_cr8_intercept(vcpu);
6712 kvm_lapic_sync_to_vapic(vcpu);
6713 }
6714 }
6715
6716 r = kvm_mmu_reload(vcpu);
6717 if (unlikely(r)) {
6718 goto cancel_injection;
6719 }
6720
6721 preempt_disable();
6722
6723 kvm_x86_ops->prepare_guest_switch(vcpu);
6724 if (vcpu->fpu_active)
6725 kvm_load_guest_fpu(vcpu);
6726 vcpu->mode = IN_GUEST_MODE;
6727
6728 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6729
6730 /*
6731 * We should set ->mode before check ->requests,
6732 * Please see the comment in kvm_make_all_cpus_request.
6733 * This also orders the write to mode from any reads
6734 * to the page tables done while the VCPU is running.
6735 * Please see the comment in kvm_flush_remote_tlbs.
6736 */
6737 smp_mb__after_srcu_read_unlock();
6738
6739 local_irq_disable();
6740
6741 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6742 || need_resched() || signal_pending(current)) {
6743 vcpu->mode = OUTSIDE_GUEST_MODE;
6744 smp_wmb();
6745 local_irq_enable();
6746 preempt_enable();
6747 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6748 r = 1;
6749 goto cancel_injection;
6750 }
6751
6752 kvm_load_guest_xcr0(vcpu);
6753
6754 if (req_immediate_exit) {
6755 kvm_make_request(KVM_REQ_EVENT, vcpu);
6756 smp_send_reschedule(vcpu->cpu);
6757 }
6758
6759 trace_kvm_entry(vcpu->vcpu_id);
6760 wait_lapic_expire(vcpu);
6761 guest_enter_irqoff();
6762
6763 if (unlikely(vcpu->arch.switch_db_regs)) {
6764 set_debugreg(0, 7);
6765 set_debugreg(vcpu->arch.eff_db[0], 0);
6766 set_debugreg(vcpu->arch.eff_db[1], 1);
6767 set_debugreg(vcpu->arch.eff_db[2], 2);
6768 set_debugreg(vcpu->arch.eff_db[3], 3);
6769 set_debugreg(vcpu->arch.dr6, 6);
6770 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6771 }
6772
6773 kvm_x86_ops->run(vcpu);
6774
6775 /*
6776 * Do this here before restoring debug registers on the host. And
6777 * since we do this before handling the vmexit, a DR access vmexit
6778 * can (a) read the correct value of the debug registers, (b) set
6779 * KVM_DEBUGREG_WONT_EXIT again.
6780 */
6781 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6782 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6783 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6784 kvm_update_dr0123(vcpu);
6785 kvm_update_dr6(vcpu);
6786 kvm_update_dr7(vcpu);
6787 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6788 }
6789
6790 /*
6791 * If the guest has used debug registers, at least dr7
6792 * will be disabled while returning to the host.
6793 * If we don't have active breakpoints in the host, we don't
6794 * care about the messed up debug address registers. But if
6795 * we have some of them active, restore the old state.
6796 */
6797 if (hw_breakpoint_active())
6798 hw_breakpoint_restore();
6799
6800 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6801
6802 vcpu->mode = OUTSIDE_GUEST_MODE;
6803 smp_wmb();
6804
6805 kvm_put_guest_xcr0(vcpu);
6806
6807 kvm_x86_ops->handle_external_intr(vcpu);
6808
6809 ++vcpu->stat.exits;
6810
6811 guest_exit_irqoff();
6812
6813 local_irq_enable();
6814 preempt_enable();
6815
6816 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6817
6818 /*
6819 * Profile KVM exit RIPs:
6820 */
6821 if (unlikely(prof_on == KVM_PROFILING)) {
6822 unsigned long rip = kvm_rip_read(vcpu);
6823 profile_hit(KVM_PROFILING, (void *)rip);
6824 }
6825
6826 if (unlikely(vcpu->arch.tsc_always_catchup))
6827 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6828
6829 if (vcpu->arch.apic_attention)
6830 kvm_lapic_sync_from_vapic(vcpu);
6831
6832 r = kvm_x86_ops->handle_exit(vcpu);
6833 return r;
6834
6835 cancel_injection:
6836 kvm_x86_ops->cancel_injection(vcpu);
6837 if (unlikely(vcpu->arch.apic_attention))
6838 kvm_lapic_sync_from_vapic(vcpu);
6839 out:
6840 return r;
6841 }
6842
6843 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6844 {
6845 if (!kvm_arch_vcpu_runnable(vcpu) &&
6846 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6847 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6848 kvm_vcpu_block(vcpu);
6849 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6850
6851 if (kvm_x86_ops->post_block)
6852 kvm_x86_ops->post_block(vcpu);
6853
6854 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6855 return 1;
6856 }
6857
6858 kvm_apic_accept_events(vcpu);
6859 switch(vcpu->arch.mp_state) {
6860 case KVM_MP_STATE_HALTED:
6861 vcpu->arch.pv.pv_unhalted = false;
6862 vcpu->arch.mp_state =
6863 KVM_MP_STATE_RUNNABLE;
6864 case KVM_MP_STATE_RUNNABLE:
6865 vcpu->arch.apf.halted = false;
6866 break;
6867 case KVM_MP_STATE_INIT_RECEIVED:
6868 break;
6869 default:
6870 return -EINTR;
6871 break;
6872 }
6873 return 1;
6874 }
6875
6876 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6877 {
6878 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6879 !vcpu->arch.apf.halted);
6880 }
6881
6882 static int vcpu_run(struct kvm_vcpu *vcpu)
6883 {
6884 int r;
6885 struct kvm *kvm = vcpu->kvm;
6886
6887 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6888
6889 for (;;) {
6890 if (kvm_vcpu_running(vcpu)) {
6891 r = vcpu_enter_guest(vcpu);
6892 } else {
6893 r = vcpu_block(kvm, vcpu);
6894 }
6895
6896 if (r <= 0)
6897 break;
6898
6899 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6900 if (kvm_cpu_has_pending_timer(vcpu))
6901 kvm_inject_pending_timer_irqs(vcpu);
6902
6903 if (dm_request_for_irq_injection(vcpu) &&
6904 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
6905 r = 0;
6906 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6907 ++vcpu->stat.request_irq_exits;
6908 break;
6909 }
6910
6911 kvm_check_async_pf_completion(vcpu);
6912
6913 if (signal_pending(current)) {
6914 r = -EINTR;
6915 vcpu->run->exit_reason = KVM_EXIT_INTR;
6916 ++vcpu->stat.signal_exits;
6917 break;
6918 }
6919 if (need_resched()) {
6920 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6921 cond_resched();
6922 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6923 }
6924 }
6925
6926 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6927
6928 return r;
6929 }
6930
6931 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6932 {
6933 int r;
6934 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6935 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6936 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6937 if (r != EMULATE_DONE)
6938 return 0;
6939 return 1;
6940 }
6941
6942 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6943 {
6944 BUG_ON(!vcpu->arch.pio.count);
6945
6946 return complete_emulated_io(vcpu);
6947 }
6948
6949 /*
6950 * Implements the following, as a state machine:
6951 *
6952 * read:
6953 * for each fragment
6954 * for each mmio piece in the fragment
6955 * write gpa, len
6956 * exit
6957 * copy data
6958 * execute insn
6959 *
6960 * write:
6961 * for each fragment
6962 * for each mmio piece in the fragment
6963 * write gpa, len
6964 * copy data
6965 * exit
6966 */
6967 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6968 {
6969 struct kvm_run *run = vcpu->run;
6970 struct kvm_mmio_fragment *frag;
6971 unsigned len;
6972
6973 BUG_ON(!vcpu->mmio_needed);
6974
6975 /* Complete previous fragment */
6976 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6977 len = min(8u, frag->len);
6978 if (!vcpu->mmio_is_write)
6979 memcpy(frag->data, run->mmio.data, len);
6980
6981 if (frag->len <= 8) {
6982 /* Switch to the next fragment. */
6983 frag++;
6984 vcpu->mmio_cur_fragment++;
6985 } else {
6986 /* Go forward to the next mmio piece. */
6987 frag->data += len;
6988 frag->gpa += len;
6989 frag->len -= len;
6990 }
6991
6992 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6993 vcpu->mmio_needed = 0;
6994
6995 /* FIXME: return into emulator if single-stepping. */
6996 if (vcpu->mmio_is_write)
6997 return 1;
6998 vcpu->mmio_read_completed = 1;
6999 return complete_emulated_io(vcpu);
7000 }
7001
7002 run->exit_reason = KVM_EXIT_MMIO;
7003 run->mmio.phys_addr = frag->gpa;
7004 if (vcpu->mmio_is_write)
7005 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7006 run->mmio.len = min(8u, frag->len);
7007 run->mmio.is_write = vcpu->mmio_is_write;
7008 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7009 return 0;
7010 }
7011
7012
7013 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7014 {
7015 struct fpu *fpu = &current->thread.fpu;
7016 int r;
7017 sigset_t sigsaved;
7018
7019 fpu__activate_curr(fpu);
7020
7021 if (vcpu->sigset_active)
7022 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7023
7024 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
7025 kvm_vcpu_block(vcpu);
7026 kvm_apic_accept_events(vcpu);
7027 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
7028 r = -EAGAIN;
7029 goto out;
7030 }
7031
7032 /* re-sync apic's tpr */
7033 if (!lapic_in_kernel(vcpu)) {
7034 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7035 r = -EINVAL;
7036 goto out;
7037 }
7038 }
7039
7040 if (unlikely(vcpu->arch.complete_userspace_io)) {
7041 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7042 vcpu->arch.complete_userspace_io = NULL;
7043 r = cui(vcpu);
7044 if (r <= 0)
7045 goto out;
7046 } else
7047 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
7048
7049 r = vcpu_run(vcpu);
7050
7051 out:
7052 post_kvm_run_save(vcpu);
7053 if (vcpu->sigset_active)
7054 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7055
7056 return r;
7057 }
7058
7059 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7060 {
7061 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7062 /*
7063 * We are here if userspace calls get_regs() in the middle of
7064 * instruction emulation. Registers state needs to be copied
7065 * back from emulation context to vcpu. Userspace shouldn't do
7066 * that usually, but some bad designed PV devices (vmware
7067 * backdoor interface) need this to work
7068 */
7069 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7070 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7071 }
7072 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7073 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7074 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7075 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7076 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7077 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7078 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7079 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
7080 #ifdef CONFIG_X86_64
7081 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7082 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7083 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7084 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7085 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7086 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7087 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7088 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
7089 #endif
7090
7091 regs->rip = kvm_rip_read(vcpu);
7092 regs->rflags = kvm_get_rflags(vcpu);
7093
7094 return 0;
7095 }
7096
7097 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7098 {
7099 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7100 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7101
7102 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7103 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7104 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7105 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7106 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7107 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7108 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7109 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
7110 #ifdef CONFIG_X86_64
7111 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7112 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7113 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7114 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7115 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7116 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7117 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7118 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
7119 #endif
7120
7121 kvm_rip_write(vcpu, regs->rip);
7122 kvm_set_rflags(vcpu, regs->rflags);
7123
7124 vcpu->arch.exception.pending = false;
7125
7126 kvm_make_request(KVM_REQ_EVENT, vcpu);
7127
7128 return 0;
7129 }
7130
7131 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7132 {
7133 struct kvm_segment cs;
7134
7135 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7136 *db = cs.db;
7137 *l = cs.l;
7138 }
7139 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7140
7141 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7142 struct kvm_sregs *sregs)
7143 {
7144 struct desc_ptr dt;
7145
7146 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7147 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7148 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7149 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7150 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7151 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7152
7153 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7154 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7155
7156 kvm_x86_ops->get_idt(vcpu, &dt);
7157 sregs->idt.limit = dt.size;
7158 sregs->idt.base = dt.address;
7159 kvm_x86_ops->get_gdt(vcpu, &dt);
7160 sregs->gdt.limit = dt.size;
7161 sregs->gdt.base = dt.address;
7162
7163 sregs->cr0 = kvm_read_cr0(vcpu);
7164 sregs->cr2 = vcpu->arch.cr2;
7165 sregs->cr3 = kvm_read_cr3(vcpu);
7166 sregs->cr4 = kvm_read_cr4(vcpu);
7167 sregs->cr8 = kvm_get_cr8(vcpu);
7168 sregs->efer = vcpu->arch.efer;
7169 sregs->apic_base = kvm_get_apic_base(vcpu);
7170
7171 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7172
7173 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7174 set_bit(vcpu->arch.interrupt.nr,
7175 (unsigned long *)sregs->interrupt_bitmap);
7176
7177 return 0;
7178 }
7179
7180 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7181 struct kvm_mp_state *mp_state)
7182 {
7183 kvm_apic_accept_events(vcpu);
7184 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7185 vcpu->arch.pv.pv_unhalted)
7186 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7187 else
7188 mp_state->mp_state = vcpu->arch.mp_state;
7189
7190 return 0;
7191 }
7192
7193 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7194 struct kvm_mp_state *mp_state)
7195 {
7196 if (!lapic_in_kernel(vcpu) &&
7197 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7198 return -EINVAL;
7199
7200 /* INITs are latched while in SMM */
7201 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7202 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7203 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7204 return -EINVAL;
7205
7206 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7207 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7208 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7209 } else
7210 vcpu->arch.mp_state = mp_state->mp_state;
7211 kvm_make_request(KVM_REQ_EVENT, vcpu);
7212 return 0;
7213 }
7214
7215 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7216 int reason, bool has_error_code, u32 error_code)
7217 {
7218 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7219 int ret;
7220
7221 init_emulate_ctxt(vcpu);
7222
7223 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7224 has_error_code, error_code);
7225
7226 if (ret)
7227 return EMULATE_FAIL;
7228
7229 kvm_rip_write(vcpu, ctxt->eip);
7230 kvm_set_rflags(vcpu, ctxt->eflags);
7231 kvm_make_request(KVM_REQ_EVENT, vcpu);
7232 return EMULATE_DONE;
7233 }
7234 EXPORT_SYMBOL_GPL(kvm_task_switch);
7235
7236 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7237 struct kvm_sregs *sregs)
7238 {
7239 struct msr_data apic_base_msr;
7240 int mmu_reset_needed = 0;
7241 int pending_vec, max_bits, idx;
7242 struct desc_ptr dt;
7243
7244 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7245 return -EINVAL;
7246
7247 dt.size = sregs->idt.limit;
7248 dt.address = sregs->idt.base;
7249 kvm_x86_ops->set_idt(vcpu, &dt);
7250 dt.size = sregs->gdt.limit;
7251 dt.address = sregs->gdt.base;
7252 kvm_x86_ops->set_gdt(vcpu, &dt);
7253
7254 vcpu->arch.cr2 = sregs->cr2;
7255 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7256 vcpu->arch.cr3 = sregs->cr3;
7257 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7258
7259 kvm_set_cr8(vcpu, sregs->cr8);
7260
7261 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7262 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7263 apic_base_msr.data = sregs->apic_base;
7264 apic_base_msr.host_initiated = true;
7265 kvm_set_apic_base(vcpu, &apic_base_msr);
7266
7267 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7268 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7269 vcpu->arch.cr0 = sregs->cr0;
7270
7271 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7272 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7273 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7274 kvm_update_cpuid(vcpu);
7275
7276 idx = srcu_read_lock(&vcpu->kvm->srcu);
7277 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7278 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7279 mmu_reset_needed = 1;
7280 }
7281 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7282
7283 if (mmu_reset_needed)
7284 kvm_mmu_reset_context(vcpu);
7285
7286 max_bits = KVM_NR_INTERRUPTS;
7287 pending_vec = find_first_bit(
7288 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7289 if (pending_vec < max_bits) {
7290 kvm_queue_interrupt(vcpu, pending_vec, false);
7291 pr_debug("Set back pending irq %d\n", pending_vec);
7292 }
7293
7294 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7295 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7296 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7297 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7298 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7299 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7300
7301 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7302 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7303
7304 update_cr8_intercept(vcpu);
7305
7306 /* Older userspace won't unhalt the vcpu on reset. */
7307 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7308 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7309 !is_protmode(vcpu))
7310 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7311
7312 kvm_make_request(KVM_REQ_EVENT, vcpu);
7313
7314 return 0;
7315 }
7316
7317 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7318 struct kvm_guest_debug *dbg)
7319 {
7320 unsigned long rflags;
7321 int i, r;
7322
7323 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7324 r = -EBUSY;
7325 if (vcpu->arch.exception.pending)
7326 goto out;
7327 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7328 kvm_queue_exception(vcpu, DB_VECTOR);
7329 else
7330 kvm_queue_exception(vcpu, BP_VECTOR);
7331 }
7332
7333 /*
7334 * Read rflags as long as potentially injected trace flags are still
7335 * filtered out.
7336 */
7337 rflags = kvm_get_rflags(vcpu);
7338
7339 vcpu->guest_debug = dbg->control;
7340 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7341 vcpu->guest_debug = 0;
7342
7343 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7344 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7345 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7346 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7347 } else {
7348 for (i = 0; i < KVM_NR_DB_REGS; i++)
7349 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7350 }
7351 kvm_update_dr7(vcpu);
7352
7353 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7354 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7355 get_segment_base(vcpu, VCPU_SREG_CS);
7356
7357 /*
7358 * Trigger an rflags update that will inject or remove the trace
7359 * flags.
7360 */
7361 kvm_set_rflags(vcpu, rflags);
7362
7363 kvm_x86_ops->update_bp_intercept(vcpu);
7364
7365 r = 0;
7366
7367 out:
7368
7369 return r;
7370 }
7371
7372 /*
7373 * Translate a guest virtual address to a guest physical address.
7374 */
7375 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7376 struct kvm_translation *tr)
7377 {
7378 unsigned long vaddr = tr->linear_address;
7379 gpa_t gpa;
7380 int idx;
7381
7382 idx = srcu_read_lock(&vcpu->kvm->srcu);
7383 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7384 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7385 tr->physical_address = gpa;
7386 tr->valid = gpa != UNMAPPED_GVA;
7387 tr->writeable = 1;
7388 tr->usermode = 0;
7389
7390 return 0;
7391 }
7392
7393 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7394 {
7395 struct fxregs_state *fxsave =
7396 &vcpu->arch.guest_fpu.state.fxsave;
7397
7398 memcpy(fpu->fpr, fxsave->st_space, 128);
7399 fpu->fcw = fxsave->cwd;
7400 fpu->fsw = fxsave->swd;
7401 fpu->ftwx = fxsave->twd;
7402 fpu->last_opcode = fxsave->fop;
7403 fpu->last_ip = fxsave->rip;
7404 fpu->last_dp = fxsave->rdp;
7405 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7406
7407 return 0;
7408 }
7409
7410 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7411 {
7412 struct fxregs_state *fxsave =
7413 &vcpu->arch.guest_fpu.state.fxsave;
7414
7415 memcpy(fxsave->st_space, fpu->fpr, 128);
7416 fxsave->cwd = fpu->fcw;
7417 fxsave->swd = fpu->fsw;
7418 fxsave->twd = fpu->ftwx;
7419 fxsave->fop = fpu->last_opcode;
7420 fxsave->rip = fpu->last_ip;
7421 fxsave->rdp = fpu->last_dp;
7422 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7423
7424 return 0;
7425 }
7426
7427 static void fx_init(struct kvm_vcpu *vcpu)
7428 {
7429 fpstate_init(&vcpu->arch.guest_fpu.state);
7430 if (boot_cpu_has(X86_FEATURE_XSAVES))
7431 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7432 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7433
7434 /*
7435 * Ensure guest xcr0 is valid for loading
7436 */
7437 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7438
7439 vcpu->arch.cr0 |= X86_CR0_ET;
7440 }
7441
7442 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7443 {
7444 if (vcpu->guest_fpu_loaded)
7445 return;
7446
7447 /*
7448 * Restore all possible states in the guest,
7449 * and assume host would use all available bits.
7450 * Guest xcr0 would be loaded later.
7451 */
7452 vcpu->guest_fpu_loaded = 1;
7453 __kernel_fpu_begin();
7454 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7455 trace_kvm_fpu(1);
7456 }
7457
7458 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7459 {
7460 if (!vcpu->guest_fpu_loaded) {
7461 vcpu->fpu_counter = 0;
7462 return;
7463 }
7464
7465 vcpu->guest_fpu_loaded = 0;
7466 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7467 __kernel_fpu_end();
7468 ++vcpu->stat.fpu_reload;
7469 /*
7470 * If using eager FPU mode, or if the guest is a frequent user
7471 * of the FPU, just leave the FPU active for next time.
7472 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7473 * the FPU in bursts will revert to loading it on demand.
7474 */
7475 if (!use_eager_fpu()) {
7476 if (++vcpu->fpu_counter < 5)
7477 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7478 }
7479 trace_kvm_fpu(0);
7480 }
7481
7482 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7483 {
7484 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7485
7486 kvmclock_reset(vcpu);
7487
7488 kvm_x86_ops->vcpu_free(vcpu);
7489 free_cpumask_var(wbinvd_dirty_mask);
7490 }
7491
7492 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7493 unsigned int id)
7494 {
7495 struct kvm_vcpu *vcpu;
7496
7497 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7498 printk_once(KERN_WARNING
7499 "kvm: SMP vm created on host with unstable TSC; "
7500 "guest TSC will not be reliable\n");
7501
7502 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7503
7504 return vcpu;
7505 }
7506
7507 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7508 {
7509 int r;
7510
7511 kvm_vcpu_mtrr_init(vcpu);
7512 r = vcpu_load(vcpu);
7513 if (r)
7514 return r;
7515 kvm_vcpu_reset(vcpu, false);
7516 kvm_mmu_setup(vcpu);
7517 vcpu_put(vcpu);
7518 return r;
7519 }
7520
7521 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7522 {
7523 struct msr_data msr;
7524 struct kvm *kvm = vcpu->kvm;
7525
7526 if (vcpu_load(vcpu))
7527 return;
7528 msr.data = 0x0;
7529 msr.index = MSR_IA32_TSC;
7530 msr.host_initiated = true;
7531 kvm_write_tsc(vcpu, &msr);
7532 vcpu_put(vcpu);
7533
7534 if (!kvmclock_periodic_sync)
7535 return;
7536
7537 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7538 KVMCLOCK_SYNC_PERIOD);
7539 }
7540
7541 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7542 {
7543 int r;
7544 vcpu->arch.apf.msr_val = 0;
7545
7546 r = vcpu_load(vcpu);
7547 BUG_ON(r);
7548 kvm_mmu_unload(vcpu);
7549 vcpu_put(vcpu);
7550
7551 kvm_x86_ops->vcpu_free(vcpu);
7552 }
7553
7554 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7555 {
7556 vcpu->arch.hflags = 0;
7557
7558 vcpu->arch.smi_pending = 0;
7559 atomic_set(&vcpu->arch.nmi_queued, 0);
7560 vcpu->arch.nmi_pending = 0;
7561 vcpu->arch.nmi_injected = false;
7562 kvm_clear_interrupt_queue(vcpu);
7563 kvm_clear_exception_queue(vcpu);
7564
7565 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7566 kvm_update_dr0123(vcpu);
7567 vcpu->arch.dr6 = DR6_INIT;
7568 kvm_update_dr6(vcpu);
7569 vcpu->arch.dr7 = DR7_FIXED_1;
7570 kvm_update_dr7(vcpu);
7571
7572 vcpu->arch.cr2 = 0;
7573
7574 kvm_make_request(KVM_REQ_EVENT, vcpu);
7575 vcpu->arch.apf.msr_val = 0;
7576 vcpu->arch.st.msr_val = 0;
7577
7578 kvmclock_reset(vcpu);
7579
7580 kvm_clear_async_pf_completion_queue(vcpu);
7581 kvm_async_pf_hash_reset(vcpu);
7582 vcpu->arch.apf.halted = false;
7583
7584 if (!init_event) {
7585 kvm_pmu_reset(vcpu);
7586 vcpu->arch.smbase = 0x30000;
7587 }
7588
7589 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7590 vcpu->arch.regs_avail = ~0;
7591 vcpu->arch.regs_dirty = ~0;
7592
7593 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7594 }
7595
7596 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7597 {
7598 struct kvm_segment cs;
7599
7600 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7601 cs.selector = vector << 8;
7602 cs.base = vector << 12;
7603 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7604 kvm_rip_write(vcpu, 0);
7605 }
7606
7607 int kvm_arch_hardware_enable(void)
7608 {
7609 struct kvm *kvm;
7610 struct kvm_vcpu *vcpu;
7611 int i;
7612 int ret;
7613 u64 local_tsc;
7614 u64 max_tsc = 0;
7615 bool stable, backwards_tsc = false;
7616
7617 kvm_shared_msr_cpu_online();
7618 ret = kvm_x86_ops->hardware_enable();
7619 if (ret != 0)
7620 return ret;
7621
7622 local_tsc = rdtsc();
7623 stable = !check_tsc_unstable();
7624 list_for_each_entry(kvm, &vm_list, vm_list) {
7625 kvm_for_each_vcpu(i, vcpu, kvm) {
7626 if (!stable && vcpu->cpu == smp_processor_id())
7627 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7628 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7629 backwards_tsc = true;
7630 if (vcpu->arch.last_host_tsc > max_tsc)
7631 max_tsc = vcpu->arch.last_host_tsc;
7632 }
7633 }
7634 }
7635
7636 /*
7637 * Sometimes, even reliable TSCs go backwards. This happens on
7638 * platforms that reset TSC during suspend or hibernate actions, but
7639 * maintain synchronization. We must compensate. Fortunately, we can
7640 * detect that condition here, which happens early in CPU bringup,
7641 * before any KVM threads can be running. Unfortunately, we can't
7642 * bring the TSCs fully up to date with real time, as we aren't yet far
7643 * enough into CPU bringup that we know how much real time has actually
7644 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
7645 * variables that haven't been updated yet.
7646 *
7647 * So we simply find the maximum observed TSC above, then record the
7648 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7649 * the adjustment will be applied. Note that we accumulate
7650 * adjustments, in case multiple suspend cycles happen before some VCPU
7651 * gets a chance to run again. In the event that no KVM threads get a
7652 * chance to run, we will miss the entire elapsed period, as we'll have
7653 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7654 * loose cycle time. This isn't too big a deal, since the loss will be
7655 * uniform across all VCPUs (not to mention the scenario is extremely
7656 * unlikely). It is possible that a second hibernate recovery happens
7657 * much faster than a first, causing the observed TSC here to be
7658 * smaller; this would require additional padding adjustment, which is
7659 * why we set last_host_tsc to the local tsc observed here.
7660 *
7661 * N.B. - this code below runs only on platforms with reliable TSC,
7662 * as that is the only way backwards_tsc is set above. Also note
7663 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7664 * have the same delta_cyc adjustment applied if backwards_tsc
7665 * is detected. Note further, this adjustment is only done once,
7666 * as we reset last_host_tsc on all VCPUs to stop this from being
7667 * called multiple times (one for each physical CPU bringup).
7668 *
7669 * Platforms with unreliable TSCs don't have to deal with this, they
7670 * will be compensated by the logic in vcpu_load, which sets the TSC to
7671 * catchup mode. This will catchup all VCPUs to real time, but cannot
7672 * guarantee that they stay in perfect synchronization.
7673 */
7674 if (backwards_tsc) {
7675 u64 delta_cyc = max_tsc - local_tsc;
7676 backwards_tsc_observed = true;
7677 list_for_each_entry(kvm, &vm_list, vm_list) {
7678 kvm_for_each_vcpu(i, vcpu, kvm) {
7679 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7680 vcpu->arch.last_host_tsc = local_tsc;
7681 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7682 }
7683
7684 /*
7685 * We have to disable TSC offset matching.. if you were
7686 * booting a VM while issuing an S4 host suspend....
7687 * you may have some problem. Solving this issue is
7688 * left as an exercise to the reader.
7689 */
7690 kvm->arch.last_tsc_nsec = 0;
7691 kvm->arch.last_tsc_write = 0;
7692 }
7693
7694 }
7695 return 0;
7696 }
7697
7698 void kvm_arch_hardware_disable(void)
7699 {
7700 kvm_x86_ops->hardware_disable();
7701 drop_user_return_notifiers();
7702 }
7703
7704 int kvm_arch_hardware_setup(void)
7705 {
7706 int r;
7707
7708 r = kvm_x86_ops->hardware_setup();
7709 if (r != 0)
7710 return r;
7711
7712 if (kvm_has_tsc_control) {
7713 /*
7714 * Make sure the user can only configure tsc_khz values that
7715 * fit into a signed integer.
7716 * A min value is not calculated needed because it will always
7717 * be 1 on all machines.
7718 */
7719 u64 max = min(0x7fffffffULL,
7720 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7721 kvm_max_guest_tsc_khz = max;
7722
7723 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7724 }
7725
7726 kvm_init_msr_list();
7727 return 0;
7728 }
7729
7730 void kvm_arch_hardware_unsetup(void)
7731 {
7732 kvm_x86_ops->hardware_unsetup();
7733 }
7734
7735 void kvm_arch_check_processor_compat(void *rtn)
7736 {
7737 kvm_x86_ops->check_processor_compatibility(rtn);
7738 }
7739
7740 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7741 {
7742 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7743 }
7744 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7745
7746 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7747 {
7748 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7749 }
7750
7751 struct static_key kvm_no_apic_vcpu __read_mostly;
7752 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7753
7754 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7755 {
7756 struct page *page;
7757 struct kvm *kvm;
7758 int r;
7759
7760 BUG_ON(vcpu->kvm == NULL);
7761 kvm = vcpu->kvm;
7762
7763 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7764 vcpu->arch.pv.pv_unhalted = false;
7765 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7766 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7767 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7768 else
7769 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7770
7771 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7772 if (!page) {
7773 r = -ENOMEM;
7774 goto fail;
7775 }
7776 vcpu->arch.pio_data = page_address(page);
7777
7778 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7779
7780 r = kvm_mmu_create(vcpu);
7781 if (r < 0)
7782 goto fail_free_pio_data;
7783
7784 if (irqchip_in_kernel(kvm)) {
7785 r = kvm_create_lapic(vcpu);
7786 if (r < 0)
7787 goto fail_mmu_destroy;
7788 } else
7789 static_key_slow_inc(&kvm_no_apic_vcpu);
7790
7791 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7792 GFP_KERNEL);
7793 if (!vcpu->arch.mce_banks) {
7794 r = -ENOMEM;
7795 goto fail_free_lapic;
7796 }
7797 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7798
7799 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7800 r = -ENOMEM;
7801 goto fail_free_mce_banks;
7802 }
7803
7804 fx_init(vcpu);
7805
7806 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7807 vcpu->arch.pv_time_enabled = false;
7808
7809 vcpu->arch.guest_supported_xcr0 = 0;
7810 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7811
7812 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7813
7814 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7815
7816 kvm_async_pf_hash_reset(vcpu);
7817 kvm_pmu_init(vcpu);
7818
7819 vcpu->arch.pending_external_vector = -1;
7820
7821 kvm_hv_vcpu_init(vcpu);
7822
7823 return 0;
7824
7825 fail_free_mce_banks:
7826 kfree(vcpu->arch.mce_banks);
7827 fail_free_lapic:
7828 kvm_free_lapic(vcpu);
7829 fail_mmu_destroy:
7830 kvm_mmu_destroy(vcpu);
7831 fail_free_pio_data:
7832 free_page((unsigned long)vcpu->arch.pio_data);
7833 fail:
7834 return r;
7835 }
7836
7837 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7838 {
7839 int idx;
7840
7841 kvm_hv_vcpu_uninit(vcpu);
7842 kvm_pmu_destroy(vcpu);
7843 kfree(vcpu->arch.mce_banks);
7844 kvm_free_lapic(vcpu);
7845 idx = srcu_read_lock(&vcpu->kvm->srcu);
7846 kvm_mmu_destroy(vcpu);
7847 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7848 free_page((unsigned long)vcpu->arch.pio_data);
7849 if (!lapic_in_kernel(vcpu))
7850 static_key_slow_dec(&kvm_no_apic_vcpu);
7851 }
7852
7853 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7854 {
7855 kvm_x86_ops->sched_in(vcpu, cpu);
7856 }
7857
7858 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7859 {
7860 if (type)
7861 return -EINVAL;
7862
7863 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7864 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7865 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7866 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7867 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7868
7869 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7870 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7871 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7872 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7873 &kvm->arch.irq_sources_bitmap);
7874
7875 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7876 mutex_init(&kvm->arch.apic_map_lock);
7877 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7878
7879 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
7880 pvclock_update_vm_gtod_copy(kvm);
7881
7882 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7883 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7884
7885 kvm_page_track_init(kvm);
7886 kvm_mmu_init_vm(kvm);
7887
7888 if (kvm_x86_ops->vm_init)
7889 return kvm_x86_ops->vm_init(kvm);
7890
7891 return 0;
7892 }
7893
7894 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7895 {
7896 int r;
7897 r = vcpu_load(vcpu);
7898 BUG_ON(r);
7899 kvm_mmu_unload(vcpu);
7900 vcpu_put(vcpu);
7901 }
7902
7903 static void kvm_free_vcpus(struct kvm *kvm)
7904 {
7905 unsigned int i;
7906 struct kvm_vcpu *vcpu;
7907
7908 /*
7909 * Unpin any mmu pages first.
7910 */
7911 kvm_for_each_vcpu(i, vcpu, kvm) {
7912 kvm_clear_async_pf_completion_queue(vcpu);
7913 kvm_unload_vcpu_mmu(vcpu);
7914 }
7915 kvm_for_each_vcpu(i, vcpu, kvm)
7916 kvm_arch_vcpu_free(vcpu);
7917
7918 mutex_lock(&kvm->lock);
7919 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7920 kvm->vcpus[i] = NULL;
7921
7922 atomic_set(&kvm->online_vcpus, 0);
7923 mutex_unlock(&kvm->lock);
7924 }
7925
7926 void kvm_arch_sync_events(struct kvm *kvm)
7927 {
7928 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7929 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7930 kvm_free_all_assigned_devices(kvm);
7931 kvm_free_pit(kvm);
7932 }
7933
7934 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7935 {
7936 int i, r;
7937 unsigned long hva;
7938 struct kvm_memslots *slots = kvm_memslots(kvm);
7939 struct kvm_memory_slot *slot, old;
7940
7941 /* Called with kvm->slots_lock held. */
7942 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7943 return -EINVAL;
7944
7945 slot = id_to_memslot(slots, id);
7946 if (size) {
7947 if (slot->npages)
7948 return -EEXIST;
7949
7950 /*
7951 * MAP_SHARED to prevent internal slot pages from being moved
7952 * by fork()/COW.
7953 */
7954 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7955 MAP_SHARED | MAP_ANONYMOUS, 0);
7956 if (IS_ERR((void *)hva))
7957 return PTR_ERR((void *)hva);
7958 } else {
7959 if (!slot->npages)
7960 return 0;
7961
7962 hva = 0;
7963 }
7964
7965 old = *slot;
7966 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7967 struct kvm_userspace_memory_region m;
7968
7969 m.slot = id | (i << 16);
7970 m.flags = 0;
7971 m.guest_phys_addr = gpa;
7972 m.userspace_addr = hva;
7973 m.memory_size = size;
7974 r = __kvm_set_memory_region(kvm, &m);
7975 if (r < 0)
7976 return r;
7977 }
7978
7979 if (!size) {
7980 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7981 WARN_ON(r < 0);
7982 }
7983
7984 return 0;
7985 }
7986 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7987
7988 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7989 {
7990 int r;
7991
7992 mutex_lock(&kvm->slots_lock);
7993 r = __x86_set_memory_region(kvm, id, gpa, size);
7994 mutex_unlock(&kvm->slots_lock);
7995
7996 return r;
7997 }
7998 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7999
8000 void kvm_arch_destroy_vm(struct kvm *kvm)
8001 {
8002 if (current->mm == kvm->mm) {
8003 /*
8004 * Free memory regions allocated on behalf of userspace,
8005 * unless the the memory map has changed due to process exit
8006 * or fd copying.
8007 */
8008 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8009 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8010 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
8011 }
8012 if (kvm_x86_ops->vm_destroy)
8013 kvm_x86_ops->vm_destroy(kvm);
8014 kvm_iommu_unmap_guest(kvm);
8015 kfree(kvm->arch.vpic);
8016 kfree(kvm->arch.vioapic);
8017 kvm_free_vcpus(kvm);
8018 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
8019 kvm_mmu_uninit_vm(kvm);
8020 kvm_page_track_cleanup(kvm);
8021 }
8022
8023 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
8024 struct kvm_memory_slot *dont)
8025 {
8026 int i;
8027
8028 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8029 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
8030 kvfree(free->arch.rmap[i]);
8031 free->arch.rmap[i] = NULL;
8032 }
8033 if (i == 0)
8034 continue;
8035
8036 if (!dont || free->arch.lpage_info[i - 1] !=
8037 dont->arch.lpage_info[i - 1]) {
8038 kvfree(free->arch.lpage_info[i - 1]);
8039 free->arch.lpage_info[i - 1] = NULL;
8040 }
8041 }
8042
8043 kvm_page_track_free_memslot(free, dont);
8044 }
8045
8046 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8047 unsigned long npages)
8048 {
8049 int i;
8050
8051 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8052 struct kvm_lpage_info *linfo;
8053 unsigned long ugfn;
8054 int lpages;
8055 int level = i + 1;
8056
8057 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8058 slot->base_gfn, level) + 1;
8059
8060 slot->arch.rmap[i] =
8061 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
8062 if (!slot->arch.rmap[i])
8063 goto out_free;
8064 if (i == 0)
8065 continue;
8066
8067 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
8068 if (!linfo)
8069 goto out_free;
8070
8071 slot->arch.lpage_info[i - 1] = linfo;
8072
8073 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
8074 linfo[0].disallow_lpage = 1;
8075 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
8076 linfo[lpages - 1].disallow_lpage = 1;
8077 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8078 /*
8079 * If the gfn and userspace address are not aligned wrt each
8080 * other, or if explicitly asked to, disable large page
8081 * support for this slot
8082 */
8083 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8084 !kvm_largepages_enabled()) {
8085 unsigned long j;
8086
8087 for (j = 0; j < lpages; ++j)
8088 linfo[j].disallow_lpage = 1;
8089 }
8090 }
8091
8092 if (kvm_page_track_create_memslot(slot, npages))
8093 goto out_free;
8094
8095 return 0;
8096
8097 out_free:
8098 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8099 kvfree(slot->arch.rmap[i]);
8100 slot->arch.rmap[i] = NULL;
8101 if (i == 0)
8102 continue;
8103
8104 kvfree(slot->arch.lpage_info[i - 1]);
8105 slot->arch.lpage_info[i - 1] = NULL;
8106 }
8107 return -ENOMEM;
8108 }
8109
8110 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
8111 {
8112 /*
8113 * memslots->generation has been incremented.
8114 * mmio generation may have reached its maximum value.
8115 */
8116 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
8117 }
8118
8119 int kvm_arch_prepare_memory_region(struct kvm *kvm,
8120 struct kvm_memory_slot *memslot,
8121 const struct kvm_userspace_memory_region *mem,
8122 enum kvm_mr_change change)
8123 {
8124 return 0;
8125 }
8126
8127 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8128 struct kvm_memory_slot *new)
8129 {
8130 /* Still write protect RO slot */
8131 if (new->flags & KVM_MEM_READONLY) {
8132 kvm_mmu_slot_remove_write_access(kvm, new);
8133 return;
8134 }
8135
8136 /*
8137 * Call kvm_x86_ops dirty logging hooks when they are valid.
8138 *
8139 * kvm_x86_ops->slot_disable_log_dirty is called when:
8140 *
8141 * - KVM_MR_CREATE with dirty logging is disabled
8142 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8143 *
8144 * The reason is, in case of PML, we need to set D-bit for any slots
8145 * with dirty logging disabled in order to eliminate unnecessary GPA
8146 * logging in PML buffer (and potential PML buffer full VMEXT). This
8147 * guarantees leaving PML enabled during guest's lifetime won't have
8148 * any additonal overhead from PML when guest is running with dirty
8149 * logging disabled for memory slots.
8150 *
8151 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8152 * to dirty logging mode.
8153 *
8154 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8155 *
8156 * In case of write protect:
8157 *
8158 * Write protect all pages for dirty logging.
8159 *
8160 * All the sptes including the large sptes which point to this
8161 * slot are set to readonly. We can not create any new large
8162 * spte on this slot until the end of the logging.
8163 *
8164 * See the comments in fast_page_fault().
8165 */
8166 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8167 if (kvm_x86_ops->slot_enable_log_dirty)
8168 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8169 else
8170 kvm_mmu_slot_remove_write_access(kvm, new);
8171 } else {
8172 if (kvm_x86_ops->slot_disable_log_dirty)
8173 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8174 }
8175 }
8176
8177 void kvm_arch_commit_memory_region(struct kvm *kvm,
8178 const struct kvm_userspace_memory_region *mem,
8179 const struct kvm_memory_slot *old,
8180 const struct kvm_memory_slot *new,
8181 enum kvm_mr_change change)
8182 {
8183 int nr_mmu_pages = 0;
8184
8185 if (!kvm->arch.n_requested_mmu_pages)
8186 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8187
8188 if (nr_mmu_pages)
8189 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8190
8191 /*
8192 * Dirty logging tracks sptes in 4k granularity, meaning that large
8193 * sptes have to be split. If live migration is successful, the guest
8194 * in the source machine will be destroyed and large sptes will be
8195 * created in the destination. However, if the guest continues to run
8196 * in the source machine (for example if live migration fails), small
8197 * sptes will remain around and cause bad performance.
8198 *
8199 * Scan sptes if dirty logging has been stopped, dropping those
8200 * which can be collapsed into a single large-page spte. Later
8201 * page faults will create the large-page sptes.
8202 */
8203 if ((change != KVM_MR_DELETE) &&
8204 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8205 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8206 kvm_mmu_zap_collapsible_sptes(kvm, new);
8207
8208 /*
8209 * Set up write protection and/or dirty logging for the new slot.
8210 *
8211 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8212 * been zapped so no dirty logging staff is needed for old slot. For
8213 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8214 * new and it's also covered when dealing with the new slot.
8215 *
8216 * FIXME: const-ify all uses of struct kvm_memory_slot.
8217 */
8218 if (change != KVM_MR_DELETE)
8219 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8220 }
8221
8222 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8223 {
8224 kvm_mmu_invalidate_zap_all_pages(kvm);
8225 }
8226
8227 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8228 struct kvm_memory_slot *slot)
8229 {
8230 kvm_mmu_invalidate_zap_all_pages(kvm);
8231 }
8232
8233 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8234 {
8235 if (!list_empty_careful(&vcpu->async_pf.done))
8236 return true;
8237
8238 if (kvm_apic_has_events(vcpu))
8239 return true;
8240
8241 if (vcpu->arch.pv.pv_unhalted)
8242 return true;
8243
8244 if (atomic_read(&vcpu->arch.nmi_queued))
8245 return true;
8246
8247 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8248 return true;
8249
8250 if (kvm_arch_interrupt_allowed(vcpu) &&
8251 kvm_cpu_has_interrupt(vcpu))
8252 return true;
8253
8254 if (kvm_hv_has_stimer_pending(vcpu))
8255 return true;
8256
8257 return false;
8258 }
8259
8260 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8261 {
8262 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8263 kvm_x86_ops->check_nested_events(vcpu, false);
8264
8265 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8266 }
8267
8268 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8269 {
8270 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8271 }
8272
8273 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8274 {
8275 return kvm_x86_ops->interrupt_allowed(vcpu);
8276 }
8277
8278 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8279 {
8280 if (is_64_bit_mode(vcpu))
8281 return kvm_rip_read(vcpu);
8282 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8283 kvm_rip_read(vcpu));
8284 }
8285 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8286
8287 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8288 {
8289 return kvm_get_linear_rip(vcpu) == linear_rip;
8290 }
8291 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8292
8293 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8294 {
8295 unsigned long rflags;
8296
8297 rflags = kvm_x86_ops->get_rflags(vcpu);
8298 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8299 rflags &= ~X86_EFLAGS_TF;
8300 return rflags;
8301 }
8302 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8303
8304 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8305 {
8306 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8307 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8308 rflags |= X86_EFLAGS_TF;
8309 kvm_x86_ops->set_rflags(vcpu, rflags);
8310 }
8311
8312 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8313 {
8314 __kvm_set_rflags(vcpu, rflags);
8315 kvm_make_request(KVM_REQ_EVENT, vcpu);
8316 }
8317 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8318
8319 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8320 {
8321 int r;
8322
8323 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8324 work->wakeup_all)
8325 return;
8326
8327 r = kvm_mmu_reload(vcpu);
8328 if (unlikely(r))
8329 return;
8330
8331 if (!vcpu->arch.mmu.direct_map &&
8332 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8333 return;
8334
8335 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8336 }
8337
8338 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8339 {
8340 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8341 }
8342
8343 static inline u32 kvm_async_pf_next_probe(u32 key)
8344 {
8345 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8346 }
8347
8348 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8349 {
8350 u32 key = kvm_async_pf_hash_fn(gfn);
8351
8352 while (vcpu->arch.apf.gfns[key] != ~0)
8353 key = kvm_async_pf_next_probe(key);
8354
8355 vcpu->arch.apf.gfns[key] = gfn;
8356 }
8357
8358 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8359 {
8360 int i;
8361 u32 key = kvm_async_pf_hash_fn(gfn);
8362
8363 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8364 (vcpu->arch.apf.gfns[key] != gfn &&
8365 vcpu->arch.apf.gfns[key] != ~0); i++)
8366 key = kvm_async_pf_next_probe(key);
8367
8368 return key;
8369 }
8370
8371 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8372 {
8373 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8374 }
8375
8376 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8377 {
8378 u32 i, j, k;
8379
8380 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8381 while (true) {
8382 vcpu->arch.apf.gfns[i] = ~0;
8383 do {
8384 j = kvm_async_pf_next_probe(j);
8385 if (vcpu->arch.apf.gfns[j] == ~0)
8386 return;
8387 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8388 /*
8389 * k lies cyclically in ]i,j]
8390 * | i.k.j |
8391 * |....j i.k.| or |.k..j i...|
8392 */
8393 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8394 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8395 i = j;
8396 }
8397 }
8398
8399 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8400 {
8401
8402 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8403 sizeof(val));
8404 }
8405
8406 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8407 struct kvm_async_pf *work)
8408 {
8409 struct x86_exception fault;
8410
8411 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8412 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8413
8414 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8415 (vcpu->arch.apf.send_user_only &&
8416 kvm_x86_ops->get_cpl(vcpu) == 0))
8417 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8418 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8419 fault.vector = PF_VECTOR;
8420 fault.error_code_valid = true;
8421 fault.error_code = 0;
8422 fault.nested_page_fault = false;
8423 fault.address = work->arch.token;
8424 kvm_inject_page_fault(vcpu, &fault);
8425 }
8426 }
8427
8428 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8429 struct kvm_async_pf *work)
8430 {
8431 struct x86_exception fault;
8432
8433 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8434 if (work->wakeup_all)
8435 work->arch.token = ~0; /* broadcast wakeup */
8436 else
8437 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8438
8439 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8440 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8441 fault.vector = PF_VECTOR;
8442 fault.error_code_valid = true;
8443 fault.error_code = 0;
8444 fault.nested_page_fault = false;
8445 fault.address = work->arch.token;
8446 kvm_inject_page_fault(vcpu, &fault);
8447 }
8448 vcpu->arch.apf.halted = false;
8449 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8450 }
8451
8452 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8453 {
8454 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8455 return true;
8456 else
8457 return kvm_can_do_async_pf(vcpu);
8458 }
8459
8460 void kvm_arch_start_assignment(struct kvm *kvm)
8461 {
8462 atomic_inc(&kvm->arch.assigned_device_count);
8463 }
8464 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8465
8466 void kvm_arch_end_assignment(struct kvm *kvm)
8467 {
8468 atomic_dec(&kvm->arch.assigned_device_count);
8469 }
8470 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8471
8472 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8473 {
8474 return atomic_read(&kvm->arch.assigned_device_count);
8475 }
8476 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8477
8478 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8479 {
8480 atomic_inc(&kvm->arch.noncoherent_dma_count);
8481 }
8482 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8483
8484 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8485 {
8486 atomic_dec(&kvm->arch.noncoherent_dma_count);
8487 }
8488 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8489
8490 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8491 {
8492 return atomic_read(&kvm->arch.noncoherent_dma_count);
8493 }
8494 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8495
8496 bool kvm_arch_has_irq_bypass(void)
8497 {
8498 return kvm_x86_ops->update_pi_irte != NULL;
8499 }
8500
8501 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8502 struct irq_bypass_producer *prod)
8503 {
8504 struct kvm_kernel_irqfd *irqfd =
8505 container_of(cons, struct kvm_kernel_irqfd, consumer);
8506
8507 irqfd->producer = prod;
8508
8509 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8510 prod->irq, irqfd->gsi, 1);
8511 }
8512
8513 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8514 struct irq_bypass_producer *prod)
8515 {
8516 int ret;
8517 struct kvm_kernel_irqfd *irqfd =
8518 container_of(cons, struct kvm_kernel_irqfd, consumer);
8519
8520 WARN_ON(irqfd->producer != prod);
8521 irqfd->producer = NULL;
8522
8523 /*
8524 * When producer of consumer is unregistered, we change back to
8525 * remapped mode, so we can re-use the current implementation
8526 * when the irq is masked/disabled or the consumer side (KVM
8527 * int this case doesn't want to receive the interrupts.
8528 */
8529 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8530 if (ret)
8531 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8532 " fails: %d\n", irqfd->consumer.token, ret);
8533 }
8534
8535 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8536 uint32_t guest_irq, bool set)
8537 {
8538 if (!kvm_x86_ops->update_pi_irte)
8539 return -EINVAL;
8540
8541 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8542 }
8543
8544 bool kvm_vector_hashing_enabled(void)
8545 {
8546 return vector_hashing;
8547 }
8548 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8549
8550 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8551 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8552 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8553 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8554 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8555 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8556 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8557 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8558 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8559 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8560 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8561 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8562 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8563 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8564 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8565 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8566 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
8567 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8568 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux with added FPC-III support