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Merge branch 'misc' into devel
[linux/fpc-iii.git] / arch / arm / mach-omap2 / gpmc.c
blob1b7b3e7d02f74f6fd606244baa2c2d366968109e
1 /*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15 #undef DEBUG
16
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/ioport.h>
22 #include <linux/spinlock.h>
23 #include <linux/io.h>
24 #include <linux/module.h>
25
26 #include <asm/mach-types.h>
27 #include <plat/gpmc.h>
28
29 #include <plat/sdrc.h>
30
31 /* GPMC register offsets */
32 #define GPMC_REVISION 0x00
33 #define GPMC_SYSCONFIG 0x10
34 #define GPMC_SYSSTATUS 0x14
35 #define GPMC_IRQSTATUS 0x18
36 #define GPMC_IRQENABLE 0x1c
37 #define GPMC_TIMEOUT_CONTROL 0x40
38 #define GPMC_ERR_ADDRESS 0x44
39 #define GPMC_ERR_TYPE 0x48
40 #define GPMC_CONFIG 0x50
41 #define GPMC_STATUS 0x54
42 #define GPMC_PREFETCH_CONFIG1 0x1e0
43 #define GPMC_PREFETCH_CONFIG2 0x1e4
44 #define GPMC_PREFETCH_CONTROL 0x1ec
45 #define GPMC_PREFETCH_STATUS 0x1f0
46 #define GPMC_ECC_CONFIG 0x1f4
47 #define GPMC_ECC_CONTROL 0x1f8
48 #define GPMC_ECC_SIZE_CONFIG 0x1fc
49 #define GPMC_ECC1_RESULT 0x200
50
51 #define GPMC_CS0_OFFSET 0x60
52 #define GPMC_CS_SIZE 0x30
53
54 #define GPMC_MEM_START 0x00000000
55 #define GPMC_MEM_END 0x3FFFFFFF
56 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
57
58 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
59 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
60
61 #define PREFETCH_FIFOTHRESHOLD (0x40 << 8)
62 #define CS_NUM_SHIFT 24
63 #define ENABLE_PREFETCH (0x1 << 7)
64 #define DMA_MPU_MODE 2
65
66 /* Structure to save gpmc cs context */
67 struct gpmc_cs_config {
68 u32 config1;
69 u32 config2;
70 u32 config3;
71 u32 config4;
72 u32 config5;
73 u32 config6;
74 u32 config7;
75 int is_valid;
76 };
77
78 /*
79 * Structure to save/restore gpmc context
80 * to support core off on OMAP3
81 */
82 struct omap3_gpmc_regs {
83 u32 sysconfig;
84 u32 irqenable;
85 u32 timeout_ctrl;
86 u32 config;
87 u32 prefetch_config1;
88 u32 prefetch_config2;
89 u32 prefetch_control;
90 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
91 };
92
93 static struct resource gpmc_mem_root;
94 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
95 static DEFINE_SPINLOCK(gpmc_mem_lock);
96 static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
97 static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */
98
99 static void __iomem *gpmc_base;
100
101 static struct clk *gpmc_l3_clk;
102
103 static void gpmc_write_reg(int idx, u32 val)
104 {
105 __raw_writel(val, gpmc_base + idx);
106 }
107
108 static u32 gpmc_read_reg(int idx)
109 {
110 return __raw_readl(gpmc_base + idx);
111 }
112
113 static void gpmc_cs_write_byte(int cs, int idx, u8 val)
114 {
115 void __iomem *reg_addr;
116
117 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
118 __raw_writeb(val, reg_addr);
119 }
120
121 static u8 gpmc_cs_read_byte(int cs, int idx)
122 {
123 void __iomem *reg_addr;
124
125 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
126 return __raw_readb(reg_addr);
127 }
128
129 void gpmc_cs_write_reg(int cs, int idx, u32 val)
130 {
131 void __iomem *reg_addr;
132
133 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
134 __raw_writel(val, reg_addr);
135 }
136
137 u32 gpmc_cs_read_reg(int cs, int idx)
138 {
139 void __iomem *reg_addr;
140
141 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
142 return __raw_readl(reg_addr);
143 }
144
145 /* TODO: Add support for gpmc_fck to clock framework and use it */
146 unsigned long gpmc_get_fclk_period(void)
147 {
148 unsigned long rate = clk_get_rate(gpmc_l3_clk);
149
150 if (rate == 0) {
151 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
152 return 0;
153 }
154
155 rate /= 1000;
156 rate = 1000000000 / rate; /* In picoseconds */
157
158 return rate;
159 }
160
161 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
162 {
163 unsigned long tick_ps;
164
165 /* Calculate in picosecs to yield more exact results */
166 tick_ps = gpmc_get_fclk_period();
167
168 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
169 }
170
171 unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
172 {
173 unsigned long tick_ps;
174
175 /* Calculate in picosecs to yield more exact results */
176 tick_ps = gpmc_get_fclk_period();
177
178 return (time_ps + tick_ps - 1) / tick_ps;
179 }
180
181 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
182 {
183 return ticks * gpmc_get_fclk_period() / 1000;
184 }
185
186 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
187 {
188 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
189
190 return ticks * gpmc_get_fclk_period() / 1000;
191 }
192
193 #ifdef DEBUG
194 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
195 int time, const char *name)
196 #else
197 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
198 int time)
199 #endif
200 {
201 u32 l;
202 int ticks, mask, nr_bits;
203
204 if (time == 0)
205 ticks = 0;
206 else
207 ticks = gpmc_ns_to_ticks(time);
208 nr_bits = end_bit - st_bit + 1;
209 if (ticks >= 1 << nr_bits) {
210 #ifdef DEBUG
211 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
212 cs, name, time, ticks, 1 << nr_bits);
213 #endif
214 return -1;
215 }
216
217 mask = (1 << nr_bits) - 1;
218 l = gpmc_cs_read_reg(cs, reg);
219 #ifdef DEBUG
220 printk(KERN_INFO
221 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
222 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
223 (l >> st_bit) & mask, time);
224 #endif
225 l &= ~(mask << st_bit);
226 l |= ticks << st_bit;
227 gpmc_cs_write_reg(cs, reg, l);
228
229 return 0;
230 }
231
232 #ifdef DEBUG
233 #define GPMC_SET_ONE(reg, st, end, field) \
234 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
235 t->field, #field) < 0) \
236 return -1
237 #else
238 #define GPMC_SET_ONE(reg, st, end, field) \
239 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
240 return -1
241 #endif
242
243 int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
244 {
245 int div;
246 u32 l;
247
248 l = sync_clk + (gpmc_get_fclk_period() - 1);
249 div = l / gpmc_get_fclk_period();
250 if (div > 4)
251 return -1;
252 if (div <= 0)
253 div = 1;
254
255 return div;
256 }
257
258 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
259 {
260 int div;
261 u32 l;
262
263 div = gpmc_cs_calc_divider(cs, t->sync_clk);
264 if (div < 0)
265 return -1;
266
267 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
268 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
269 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
270
271 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
272 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
273 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
274
275 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
276 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
277 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
278 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
279
280 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
281 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
282 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
283
284 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
285
286 if (cpu_is_omap34xx()) {
287 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
288 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
289 }
290
291 /* caller is expected to have initialized CONFIG1 to cover
292 * at least sync vs async
293 */
294 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
295 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
296 #ifdef DEBUG
297 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
298 cs, (div * gpmc_get_fclk_period()) / 1000, div);
299 #endif
300 l &= ~0x03;
301 l |= (div - 1);
302 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
303 }
304
305 return 0;
306 }
307
308 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
309 {
310 u32 l;
311 u32 mask;
312
313 mask = (1 << GPMC_SECTION_SHIFT) - size;
314 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
315 l &= ~0x3f;
316 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
317 l &= ~(0x0f << 8);
318 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
319 l |= GPMC_CONFIG7_CSVALID;
320 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
321 }
322
323 static void gpmc_cs_disable_mem(int cs)
324 {
325 u32 l;
326
327 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
328 l &= ~GPMC_CONFIG7_CSVALID;
329 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
330 }
331
332 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
333 {
334 u32 l;
335 u32 mask;
336
337 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
338 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
339 mask = (l >> 8) & 0x0f;
340 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
341 }
342
343 static int gpmc_cs_mem_enabled(int cs)
344 {
345 u32 l;
346
347 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
348 return l & GPMC_CONFIG7_CSVALID;
349 }
350
351 int gpmc_cs_set_reserved(int cs, int reserved)
352 {
353 if (cs > GPMC_CS_NUM)
354 return -ENODEV;
355
356 gpmc_cs_map &= ~(1 << cs);
357 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
358
359 return 0;
360 }
361
362 int gpmc_cs_reserved(int cs)
363 {
364 if (cs > GPMC_CS_NUM)
365 return -ENODEV;
366
367 return gpmc_cs_map & (1 << cs);
368 }
369
370 static unsigned long gpmc_mem_align(unsigned long size)
371 {
372 int order;
373
374 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
375 order = GPMC_CHUNK_SHIFT - 1;
376 do {
377 size >>= 1;
378 order++;
379 } while (size);
380 size = 1 << order;
381 return size;
382 }
383
384 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
385 {
386 struct resource *res = &gpmc_cs_mem[cs];
387 int r;
388
389 size = gpmc_mem_align(size);
390 spin_lock(&gpmc_mem_lock);
391 res->start = base;
392 res->end = base + size - 1;
393 r = request_resource(&gpmc_mem_root, res);
394 spin_unlock(&gpmc_mem_lock);
395
396 return r;
397 }
398
399 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
400 {
401 struct resource *res = &gpmc_cs_mem[cs];
402 int r = -1;
403
404 if (cs > GPMC_CS_NUM)
405 return -ENODEV;
406
407 size = gpmc_mem_align(size);
408 if (size > (1 << GPMC_SECTION_SHIFT))
409 return -ENOMEM;
410
411 spin_lock(&gpmc_mem_lock);
412 if (gpmc_cs_reserved(cs)) {
413 r = -EBUSY;
414 goto out;
415 }
416 if (gpmc_cs_mem_enabled(cs))
417 r = adjust_resource(res, res->start & ~(size - 1), size);
418 if (r < 0)
419 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
420 size, NULL, NULL);
421 if (r < 0)
422 goto out;
423
424 gpmc_cs_enable_mem(cs, res->start, resource_size(res));
425 *base = res->start;
426 gpmc_cs_set_reserved(cs, 1);
427 out:
428 spin_unlock(&gpmc_mem_lock);
429 return r;
430 }
431 EXPORT_SYMBOL(gpmc_cs_request);
432
433 void gpmc_cs_free(int cs)
434 {
435 spin_lock(&gpmc_mem_lock);
436 if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
437 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
438 BUG();
439 spin_unlock(&gpmc_mem_lock);
440 return;
441 }
442 gpmc_cs_disable_mem(cs);
443 release_resource(&gpmc_cs_mem[cs]);
444 gpmc_cs_set_reserved(cs, 0);
445 spin_unlock(&gpmc_mem_lock);
446 }
447 EXPORT_SYMBOL(gpmc_cs_free);
448
449 /**
450 * gpmc_read_status - read access request to get the different gpmc status
451 * @cmd: command type
452 * @return status
453 */
454 int gpmc_read_status(int cmd)
455 {
456 int status = -EINVAL;
457 u32 regval = 0;
458
459 switch (cmd) {
460 case GPMC_GET_IRQ_STATUS:
461 status = gpmc_read_reg(GPMC_IRQSTATUS);
462 break;
463
464 case GPMC_PREFETCH_FIFO_CNT:
465 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
466 status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
467 break;
468
469 case GPMC_PREFETCH_COUNT:
470 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
471 status = GPMC_PREFETCH_STATUS_COUNT(regval);
472 break;
473
474 case GPMC_STATUS_BUFFER:
475 regval = gpmc_read_reg(GPMC_STATUS);
476 /* 1 : buffer is available to write */
477 status = regval & GPMC_STATUS_BUFF_EMPTY;
478 break;
479
480 default:
481 printk(KERN_ERR "gpmc_read_status: Not supported\n");
482 }
483 return status;
484 }
485 EXPORT_SYMBOL(gpmc_read_status);
486
487 /**
488 * gpmc_cs_configure - write request to configure gpmc
489 * @cs: chip select number
490 * @cmd: command type
491 * @wval: value to write
492 * @return status of the operation
493 */
494 int gpmc_cs_configure(int cs, int cmd, int wval)
495 {
496 int err = 0;
497 u32 regval = 0;
498
499 switch (cmd) {
500 case GPMC_SET_IRQ_STATUS:
501 gpmc_write_reg(GPMC_IRQSTATUS, wval);
502 break;
503
504 case GPMC_CONFIG_WP:
505 regval = gpmc_read_reg(GPMC_CONFIG);
506 if (wval)
507 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
508 else
509 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
510 gpmc_write_reg(GPMC_CONFIG, regval);
511 break;
512
513 case GPMC_CONFIG_RDY_BSY:
514 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
515 if (wval)
516 regval |= WR_RD_PIN_MONITORING;
517 else
518 regval &= ~WR_RD_PIN_MONITORING;
519 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
520 break;
521
522 case GPMC_CONFIG_DEV_SIZE:
523 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
524 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
525 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
526 break;
527
528 case GPMC_CONFIG_DEV_TYPE:
529 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
530 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
531 if (wval == GPMC_DEVICETYPE_NOR)
532 regval |= GPMC_CONFIG1_MUXADDDATA;
533 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
534 break;
535
536 default:
537 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
538 err = -EINVAL;
539 }
540
541 return err;
542 }
543 EXPORT_SYMBOL(gpmc_cs_configure);
544
545 /**
546 * gpmc_nand_read - nand specific read access request
547 * @cs: chip select number
548 * @cmd: command type
549 */
550 int gpmc_nand_read(int cs, int cmd)
551 {
552 int rval = -EINVAL;
553
554 switch (cmd) {
555 case GPMC_NAND_DATA:
556 rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
557 break;
558
559 default:
560 printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
561 }
562 return rval;
563 }
564 EXPORT_SYMBOL(gpmc_nand_read);
565
566 /**
567 * gpmc_nand_write - nand specific write request
568 * @cs: chip select number
569 * @cmd: command type
570 * @wval: value to write
571 */
572 int gpmc_nand_write(int cs, int cmd, int wval)
573 {
574 int err = 0;
575
576 switch (cmd) {
577 case GPMC_NAND_COMMAND:
578 gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
579 break;
580
581 case GPMC_NAND_ADDRESS:
582 gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
583 break;
584
585 case GPMC_NAND_DATA:
586 gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
587
588 default:
589 printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
590 err = -EINVAL;
591 }
592 return err;
593 }
594 EXPORT_SYMBOL(gpmc_nand_write);
595
596
597
598 /**
599 * gpmc_prefetch_enable - configures and starts prefetch transfer
600 * @cs: cs (chip select) number
601 * @dma_mode: dma mode enable (1) or disable (0)
602 * @u32_count: number of bytes to be transferred
603 * @is_write: prefetch read(0) or write post(1) mode
604 */
605 int gpmc_prefetch_enable(int cs, int dma_mode,
606 unsigned int u32_count, int is_write)
607 {
608
609 if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
610 /* Set the amount of bytes to be prefetched */
611 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
612
613 /* Set dma/mpu mode, the prefetch read / post write and
614 * enable the engine. Set which cs is has requested for.
615 */
616 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
617 PREFETCH_FIFOTHRESHOLD |
618 ENABLE_PREFETCH |
619 (dma_mode << DMA_MPU_MODE) |
620 (0x1 & is_write)));
621
622 /* Start the prefetch engine */
623 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
624 } else {
625 return -EBUSY;
626 }
627
628 return 0;
629 }
630 EXPORT_SYMBOL(gpmc_prefetch_enable);
631
632 /**
633 * gpmc_prefetch_reset - disables and stops the prefetch engine
634 */
635 int gpmc_prefetch_reset(int cs)
636 {
637 u32 config1;
638
639 /* check if the same module/cs is trying to reset */
640 config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
641 if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
642 return -EINVAL;
643
644 /* Stop the PFPW engine */
645 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
646
647 /* Reset/disable the PFPW engine */
648 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
649
650 return 0;
651 }
652 EXPORT_SYMBOL(gpmc_prefetch_reset);
653
654 static void __init gpmc_mem_init(void)
655 {
656 int cs;
657 unsigned long boot_rom_space = 0;
658
659 /* never allocate the first page, to facilitate bug detection;
660 * even if we didn't boot from ROM.
661 */
662 boot_rom_space = BOOT_ROM_SPACE;
663 /* In apollon the CS0 is mapped as 0x0000 0000 */
664 if (machine_is_omap_apollon())
665 boot_rom_space = 0;
666 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
667 gpmc_mem_root.end = GPMC_MEM_END;
668
669 /* Reserve all regions that has been set up by bootloader */
670 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
671 u32 base, size;
672
673 if (!gpmc_cs_mem_enabled(cs))
674 continue;
675 gpmc_cs_get_memconf(cs, &base, &size);
676 if (gpmc_cs_insert_mem(cs, base, size) < 0)
677 BUG();
678 }
679 }
680
681 void __init gpmc_init(void)
682 {
683 u32 l;
684 char *ck = NULL;
685
686 if (cpu_is_omap24xx()) {
687 ck = "core_l3_ck";
688 if (cpu_is_omap2420())
689 l = OMAP2420_GPMC_BASE;
690 else
691 l = OMAP34XX_GPMC_BASE;
692 } else if (cpu_is_omap34xx()) {
693 ck = "gpmc_fck";
694 l = OMAP34XX_GPMC_BASE;
695 } else if (cpu_is_omap44xx()) {
696 ck = "gpmc_ck";
697 l = OMAP44XX_GPMC_BASE;
698 }
699
700 if (WARN_ON(!ck))
701 return;
702
703 gpmc_l3_clk = clk_get(NULL, ck);
704 if (IS_ERR(gpmc_l3_clk)) {
705 printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
706 BUG();
707 }
708
709 gpmc_base = ioremap(l, SZ_4K);
710 if (!gpmc_base) {
711 clk_put(gpmc_l3_clk);
712 printk(KERN_ERR "Could not get GPMC register memory\n");
713 BUG();
714 }
715
716 clk_enable(gpmc_l3_clk);
717
718 l = gpmc_read_reg(GPMC_REVISION);
719 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
720 /* Set smart idle mode and automatic L3 clock gating */
721 l = gpmc_read_reg(GPMC_SYSCONFIG);
722 l &= 0x03 << 3;
723 l |= (0x02 << 3) | (1 << 0);
724 gpmc_write_reg(GPMC_SYSCONFIG, l);
725 gpmc_mem_init();
726 }
727
728 #ifdef CONFIG_ARCH_OMAP3
729 static struct omap3_gpmc_regs gpmc_context;
730
731 void omap3_gpmc_save_context(void)
732 {
733 int i;
734
735 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
736 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
737 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
738 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
739 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
740 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
741 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
742 for (i = 0; i < GPMC_CS_NUM; i++) {
743 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
744 if (gpmc_context.cs_context[i].is_valid) {
745 gpmc_context.cs_context[i].config1 =
746 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
747 gpmc_context.cs_context[i].config2 =
748 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
749 gpmc_context.cs_context[i].config3 =
750 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
751 gpmc_context.cs_context[i].config4 =
752 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
753 gpmc_context.cs_context[i].config5 =
754 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
755 gpmc_context.cs_context[i].config6 =
756 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
757 gpmc_context.cs_context[i].config7 =
758 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
759 }
760 }
761 }
762
763 void omap3_gpmc_restore_context(void)
764 {
765 int i;
766
767 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
768 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
769 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
770 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
771 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
772 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
773 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
774 for (i = 0; i < GPMC_CS_NUM; i++) {
775 if (gpmc_context.cs_context[i].is_valid) {
776 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
777 gpmc_context.cs_context[i].config1);
778 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
779 gpmc_context.cs_context[i].config2);
780 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
781 gpmc_context.cs_context[i].config3);
782 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
783 gpmc_context.cs_context[i].config4);
784 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
785 gpmc_context.cs_context[i].config5);
786 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
787 gpmc_context.cs_context[i].config6);
788 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
789 gpmc_context.cs_context[i].config7);
790 }
791 }
792 }
793 #endif /* CONFIG_ARCH_OMAP3 */
794
795 /**
796 * gpmc_enable_hwecc - enable hardware ecc functionality
797 * @cs: chip select number
798 * @mode: read/write mode
799 * @dev_width: device bus width(1 for x16, 0 for x8)
800 * @ecc_size: bytes for which ECC will be generated
801 */
802 int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
803 {
804 unsigned int val;
805
806 /* check if ecc module is in used */
807 if (gpmc_ecc_used != -EINVAL)
808 return -EINVAL;
809
810 gpmc_ecc_used = cs;
811
812 /* clear ecc and enable bits */
813 val = ((0x00000001<<8) | 0x00000001);
814 gpmc_write_reg(GPMC_ECC_CONTROL, val);
815
816 /* program ecc and result sizes */
817 val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
818 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
819
820 switch (mode) {
821 case GPMC_ECC_READ:
822 gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
823 break;
824 case GPMC_ECC_READSYN:
825 gpmc_write_reg(GPMC_ECC_CONTROL, 0x100);
826 break;
827 case GPMC_ECC_WRITE:
828 gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
829 break;
830 default:
831 printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
832 break;
833 }
834
835 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
836 val = (dev_width << 7) | (cs << 1) | (0x1);
837 gpmc_write_reg(GPMC_ECC_CONFIG, val);
838 return 0;
839 }
840
841 /**
842 * gpmc_calculate_ecc - generate non-inverted ecc bytes
843 * @cs: chip select number
844 * @dat: data pointer over which ecc is computed
845 * @ecc_code: ecc code buffer
846 *
847 * Using non-inverted ECC is considered ugly since writing a blank
848 * page (padding) will clear the ECC bytes. This is not a problem as long
849 * no one is trying to write data on the seemingly unused page. Reading
850 * an erased page will produce an ECC mismatch between generated and read
851 * ECC bytes that has to be dealt with separately.
852 */
853 int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
854 {
855 unsigned int val = 0x0;
856
857 if (gpmc_ecc_used != cs)
858 return -EINVAL;
859
860 /* read ecc result */
861 val = gpmc_read_reg(GPMC_ECC1_RESULT);
862 *ecc_code++ = val; /* P128e, ..., P1e */
863 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
864 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
865 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
866
867 gpmc_ecc_used = -EINVAL;
868 return 0;
869 }
Linux with added FPC-III support