arch/arm/mach-omap2/omap-smp.c

   1 /*
   2  * OMAP4 SMP source file. It contains platform specific fucntions
   3  * needed for the linux smp kernel.
   4  *
   5  * Copyright (C) 2009 Texas Instruments, Inc.
   6  *
   7  * Author:
   8  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  *
  10  * Platform file needed for the OMAP4 SMP. This file is based on arm
  11  * realview smp platform.
  12  * * Copyright (c) 2002 ARM Limited.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #include <linux/init.h>
  19 #include <linux/device.h>
  20 #include <linux/smp.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/cacheflush.h>
  24 #include <asm/smp_scu.h>
  25 #include <mach/hardware.h>
  26 #include <mach/omap4-common.h>
  27
  28 /* SCU base address */
  29 static void __iomem *scu_base;
  30
  31 static DEFINE_SPINLOCK(boot_lock);
  32
  33 void __cpuinit platform_secondary_init(unsigned int cpu)
  34 {
  35         /*
  36          * If any interrupts are already enabled for the primary
  37          * core (e.g. timer irq), then they will not have been enabled
  38          * for us: do so
  39          */
  40         gic_secondary_init(0);
  41
  42         /*
  43          * Synchronise with the boot thread.
  44          */
  45         spin_lock(&boot_lock);
  46         spin_unlock(&boot_lock);
  47 }
  48
  49 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  50 {
  51         /*
  52          * Set synchronisation state between this boot processor
  53          * and the secondary one
  54          */
  55         spin_lock(&boot_lock);
  56
  57         /*
  58          * Update the AuxCoreBoot0 with boot state for secondary core.
  59          * omap_secondary_startup() routine will hold the secondary core till
  60          * the AuxCoreBoot1 register is updated with cpu state
  61          * A barrier is added to ensure that write buffer is drained
  62          */
  63         omap_modify_auxcoreboot0(0x200, 0xfffffdff);
  64         flush_cache_all();
  65         smp_wmb();
  66         smp_cross_call(cpumask_of(cpu), 1);
  67
  68         /*
  69          * Now the secondary core is starting up let it run its
  70          * calibrations, then wait for it to finish
  71          */
  72         spin_unlock(&boot_lock);
  73
  74         return 0;
  75 }
  76
  77 static void __init wakeup_secondary(void)
  78 {
  79         /*
  80          * Write the address of secondary startup routine into the
  81          * AuxCoreBoot1 where ROM code will jump and start executing
  82          * on secondary core once out of WFE
  83          * A barrier is added to ensure that write buffer is drained
  84          */
  85         omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
  86         smp_wmb();
  87
  88         /*
  89          * Send a 'sev' to wake the secondary core from WFE.
  90          * Drain the outstanding writes to memory
  91          */
  92         dsb_sev();
  93         mb();
  94 }
  95
  96 /*
  97  * Initialise the CPU possible map early - this describes the CPUs
  98  * which may be present or become present in the system.
  99  */
 100 void __init smp_init_cpus(void)
 101 {
 102         unsigned int i, ncores;
 103
 104         /* Never released */
 105         scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
 106         BUG_ON(!scu_base);
 107
 108         ncores = scu_get_core_count(scu_base);
 109
 110         /* sanity check */
 111         if (ncores > NR_CPUS) {
 112                 printk(KERN_WARNING
 113                        "OMAP4: no. of cores (%d) greater than configured "
 114                        "maximum of %d - clipping\n",
 115                        ncores, NR_CPUS);
 116                 ncores = NR_CPUS;
 117         }
 118
 119         for (i = 0; i < ncores; i++)
 120                 set_cpu_possible(i, true);
 121 }
 122
 123 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 124 {
 125         int i;
 126
 127         /*
 128          * Initialise the present map, which describes the set of CPUs
 129          * actually populated at the present time.
 130          */
 131         for (i = 0; i < max_cpus; i++)
 132                 set_cpu_present(i, true);
 133
 134         /*
 135          * Initialise the SCU and wake up the secondary core using
 136          * wakeup_secondary().
 137          */
 138         scu_enable(scu_base);
 139         wakeup_secondary();
 140 }