arch/arm/mach-omap2/timer-gp.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer-gp.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38
  39 #include <asm/mach/time.h>
  40 #include <plat/dmtimer.h>
  41 #include <asm/localtimer.h>
  42 #include <asm/sched_clock.h>
  43
  44 #include "timer-gp.h"
  45
  46 #include <plat/common.h>
  47
  48 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
  49 #define MAX_GPTIMER_ID          12
  50
  51 static struct omap_dm_timer *gptimer;
  52 static struct clock_event_device clockevent_gpt;
  53 static u8 __initdata gptimer_id = 1;
  54 static u8 __initdata inited;
  55 struct omap_dm_timer *gptimer_wakeup;
  56
  57 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  58 {
  59         struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
  60         struct clock_event_device *evt = &clockevent_gpt;
  61
  62         omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
  63
  64         evt->event_handler(evt);
  65         return IRQ_HANDLED;
  66 }
  67
  68 static struct irqaction omap2_gp_timer_irq = {
  69         .name           = "gp timer",
  70         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  71         .handler        = omap2_gp_timer_interrupt,
  72 };
  73
  74 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  75                                          struct clock_event_device *evt)
  76 {
  77         omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
  78
  79         return 0;
  80 }
  81
  82 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
  83                                     struct clock_event_device *evt)
  84 {
  85         u32 period;
  86
  87         omap_dm_timer_stop(gptimer);
  88
  89         switch (mode) {
  90         case CLOCK_EVT_MODE_PERIODIC:
  91                 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
  92                 period -= 1;
  93                 omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
  94                 break;
  95         case CLOCK_EVT_MODE_ONESHOT:
  96                 break;
  97         case CLOCK_EVT_MODE_UNUSED:
  98         case CLOCK_EVT_MODE_SHUTDOWN:
  99         case CLOCK_EVT_MODE_RESUME:
 100                 break;
 101         }
 102 }
 103
 104 static struct clock_event_device clockevent_gpt = {
 105         .name           = "gp timer",
 106         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 107         .shift          = 32,
 108         .set_next_event = omap2_gp_timer_set_next_event,
 109         .set_mode       = omap2_gp_timer_set_mode,
 110 };
 111
 112 /**
 113  * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
 114  * @id: GPTIMER to use (1..MAX_GPTIMER_ID)
 115  *
 116  * Define the GPTIMER that the system should use for the tick timer.
 117  * Meant to be called from board-*.c files in the event that GPTIMER1, the
 118  * default, is unsuitable.  Returns -EINVAL on error or 0 on success.
 119  */
 120 int __init omap2_gp_clockevent_set_gptimer(u8 id)
 121 {
 122         if (id < 1 || id > MAX_GPTIMER_ID)
 123                 return -EINVAL;
 124
 125         BUG_ON(inited);
 126
 127         gptimer_id = id;
 128
 129         return 0;
 130 }
 131
 132 static void __init omap2_gp_clockevent_init(void)
 133 {
 134         u32 tick_rate;
 135         int src;
 136
 137         inited = 1;
 138
 139         gptimer = omap_dm_timer_request_specific(gptimer_id);
 140         BUG_ON(gptimer == NULL);
 141         gptimer_wakeup = gptimer;
 142
 143 #if defined(CONFIG_OMAP_32K_TIMER)
 144         src = OMAP_TIMER_SRC_32_KHZ;
 145 #else
 146         src = OMAP_TIMER_SRC_SYS_CLK;
 147         WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
 148              "secure 32KiHz clock source\n");
 149 #endif
 150
 151         if (gptimer_id != 12)
 152                 WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
 153                      "timer-gp: omap_dm_timer_set_source() failed\n");
 154
 155         tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
 156
 157         pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
 158                 gptimer_id, tick_rate);
 159
 160         omap2_gp_timer_irq.dev_id = (void *)gptimer;
 161         setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
 162         omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
 163
 164         clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
 165                                      clockevent_gpt.shift);
 166         clockevent_gpt.max_delta_ns =
 167                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
 168         clockevent_gpt.min_delta_ns =
 169                 clockevent_delta2ns(3, &clockevent_gpt);
 170                 /* Timer internal resynch latency. */
 171
 172         clockevent_gpt.cpumask = cpumask_of(0);
 173         clockevents_register_device(&clockevent_gpt);
 174 }
 175
 176 /* Clocksource code */
 177
 178 #ifdef CONFIG_OMAP_32K_TIMER
 179 /*
 180  * When 32k-timer is enabled, don't use GPTimer for clocksource
 181  * instead, just leave default clocksource which uses the 32k
 182  * sync counter.  See clocksource setup in plat-omap/counter_32k.c
 183  */
 184
 185 static void __init omap2_gp_clocksource_init(void)
 186 {
 187         omap_init_clocksource_32k();
 188 }
 189
 190 #else
 191 /*
 192  * clocksource
 193  */
 194 static DEFINE_CLOCK_DATA(cd);
 195 static struct omap_dm_timer *gpt_clocksource;
 196 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 197 {
 198         return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
 199 }
 200
 201 static struct clocksource clocksource_gpt = {
 202         .name           = "gp timer",
 203         .rating         = 300,
 204         .read           = clocksource_read_cycles,
 205         .mask           = CLOCKSOURCE_MASK(32),
 206         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 207 };
 208
 209 static void notrace dmtimer_update_sched_clock(void)
 210 {
 211         u32 cyc;
 212
 213         cyc = omap_dm_timer_read_counter(gpt_clocksource);
 214
 215         update_sched_clock(&cd, cyc, (u32)~0);
 216 }
 217
 218 /* Setup free-running counter for clocksource */
 219 static void __init omap2_gp_clocksource_init(void)
 220 {
 221         static struct omap_dm_timer *gpt;
 222         u32 tick_rate;
 223         static char err1[] __initdata = KERN_ERR
 224                 "%s: failed to request dm-timer\n";
 225         static char err2[] __initdata = KERN_ERR
 226                 "%s: can't register clocksource!\n";
 227
 228         gpt = omap_dm_timer_request();
 229         if (!gpt)
 230                 printk(err1, clocksource_gpt.name);
 231         gpt_clocksource = gpt;
 232
 233         omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
 234         tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
 235
 236         omap_dm_timer_set_load_start(gpt, 1, 0);
 237
 238         init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
 239
 240         if (clocksource_register_hz(&clocksource_gpt, tick_rate))
 241                 printk(err2, clocksource_gpt.name);
 242 }
 243 #endif
 244
 245 static void __init omap2_gp_timer_init(void)
 246 {
 247 #ifdef CONFIG_LOCAL_TIMERS
 248         if (cpu_is_omap44xx()) {
 249                 twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
 250                 BUG_ON(!twd_base);
 251         }
 252 #endif
 253         omap_dm_timer_init();
 254
 255         omap2_gp_clockevent_init();
 256         omap2_gp_clocksource_init();
 257 }
 258
 259 struct sys_timer omap_timer = {
 260         .init   = omap2_gp_timer_init,
 261 };