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Merge branch 'misc' into devel
[linux/fpc-iii.git] / arch / arm / plat-omap / gpio.c
blob971d186369423c7eacb03e580a74714ad35e6f26
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/pm_runtime.h>
26
27 #include <mach/hardware.h>
28 #include <asm/irq.h>
29 #include <mach/irqs.h>
30 #include <mach/gpio.h>
31 #include <asm/mach/irq.h>
32
33 /*
34 * OMAP1510 GPIO registers
35 */
36 #define OMAP1510_GPIO_DATA_INPUT 0x00
37 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
38 #define OMAP1510_GPIO_DIR_CONTROL 0x08
39 #define OMAP1510_GPIO_INT_CONTROL 0x0c
40 #define OMAP1510_GPIO_INT_MASK 0x10
41 #define OMAP1510_GPIO_INT_STATUS 0x14
42 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43
44 #define OMAP1510_IH_GPIO_BASE 64
45
46 /*
47 * OMAP1610 specific GPIO registers
48 */
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
66
67 /*
68 * OMAP7XX specific GPIO registers
69 */
70 #define OMAP7XX_GPIO_DATA_INPUT 0x00
71 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
72 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
73 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
74 #define OMAP7XX_GPIO_INT_MASK 0x10
75 #define OMAP7XX_GPIO_INT_STATUS 0x14
76
77 /*
78 * omap2+ specific GPIO registers
79 */
80 #define OMAP24XX_GPIO_REVISION 0x0000
81 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
82 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
83 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
84 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
85 #define OMAP24XX_GPIO_WAKE_EN 0x0020
86 #define OMAP24XX_GPIO_CTRL 0x0030
87 #define OMAP24XX_GPIO_OE 0x0034
88 #define OMAP24XX_GPIO_DATAIN 0x0038
89 #define OMAP24XX_GPIO_DATAOUT 0x003c
90 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
91 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
92 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
93 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
94 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
95 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
96 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
97 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
98 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
99 #define OMAP24XX_GPIO_SETWKUENA 0x0084
100 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
101 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
102
103 #define OMAP4_GPIO_REVISION 0x0000
104 #define OMAP4_GPIO_EOI 0x0020
105 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
106 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
107 #define OMAP4_GPIO_IRQSTATUS0 0x002c
108 #define OMAP4_GPIO_IRQSTATUS1 0x0030
109 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
110 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
111 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
112 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
113 #define OMAP4_GPIO_IRQWAKEN0 0x0044
114 #define OMAP4_GPIO_IRQWAKEN1 0x0048
115 #define OMAP4_GPIO_IRQENABLE1 0x011c
116 #define OMAP4_GPIO_WAKE_EN 0x0120
117 #define OMAP4_GPIO_IRQSTATUS2 0x0128
118 #define OMAP4_GPIO_IRQENABLE2 0x012c
119 #define OMAP4_GPIO_CTRL 0x0130
120 #define OMAP4_GPIO_OE 0x0134
121 #define OMAP4_GPIO_DATAIN 0x0138
122 #define OMAP4_GPIO_DATAOUT 0x013c
123 #define OMAP4_GPIO_LEVELDETECT0 0x0140
124 #define OMAP4_GPIO_LEVELDETECT1 0x0144
125 #define OMAP4_GPIO_RISINGDETECT 0x0148
126 #define OMAP4_GPIO_FALLINGDETECT 0x014c
127 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
128 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
129 #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
130 #define OMAP4_GPIO_SETIRQENABLE1 0x0164
131 #define OMAP4_GPIO_CLEARWKUENA 0x0180
132 #define OMAP4_GPIO_SETWKUENA 0x0184
133 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
134 #define OMAP4_GPIO_SETDATAOUT 0x0194
135
136 struct gpio_bank {
137 unsigned long pbase;
138 void __iomem *base;
139 u16 irq;
140 u16 virtual_irq_start;
141 int method;
142 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
143 u32 suspend_wakeup;
144 u32 saved_wakeup;
145 #endif
146 u32 non_wakeup_gpios;
147 u32 enabled_non_wakeup_gpios;
148
149 u32 saved_datain;
150 u32 saved_fallingdetect;
151 u32 saved_risingdetect;
152 u32 level_mask;
153 u32 toggle_mask;
154 spinlock_t lock;
155 struct gpio_chip chip;
156 struct clk *dbck;
157 u32 mod_usage;
158 u32 dbck_enable_mask;
159 struct device *dev;
160 bool dbck_flag;
161 int stride;
162 };
163
164 #ifdef CONFIG_ARCH_OMAP3
165 struct omap3_gpio_regs {
166 u32 irqenable1;
167 u32 irqenable2;
168 u32 wake_en;
169 u32 ctrl;
170 u32 oe;
171 u32 leveldetect0;
172 u32 leveldetect1;
173 u32 risingdetect;
174 u32 fallingdetect;
175 u32 dataout;
176 };
177
178 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
179 #endif
180
181 /*
182 * TODO: Cleanup gpio_bank usage as it is having information
183 * related to all instances of the device
184 */
185 static struct gpio_bank *gpio_bank;
186
187 static int bank_width;
188
189 /* TODO: Analyze removing gpio_bank_count usage from driver code */
190 int gpio_bank_count;
191
192 static inline struct gpio_bank *get_gpio_bank(int gpio)
193 {
194 if (cpu_is_omap15xx()) {
195 if (OMAP_GPIO_IS_MPUIO(gpio))
196 return &gpio_bank[0];
197 return &gpio_bank[1];
198 }
199 if (cpu_is_omap16xx()) {
200 if (OMAP_GPIO_IS_MPUIO(gpio))
201 return &gpio_bank[0];
202 return &gpio_bank[1 + (gpio >> 4)];
203 }
204 if (cpu_is_omap7xx()) {
205 if (OMAP_GPIO_IS_MPUIO(gpio))
206 return &gpio_bank[0];
207 return &gpio_bank[1 + (gpio >> 5)];
208 }
209 if (cpu_is_omap24xx())
210 return &gpio_bank[gpio >> 5];
211 if (cpu_is_omap34xx() || cpu_is_omap44xx())
212 return &gpio_bank[gpio >> 5];
213 BUG();
214 return NULL;
215 }
216
217 static inline int get_gpio_index(int gpio)
218 {
219 if (cpu_is_omap7xx())
220 return gpio & 0x1f;
221 if (cpu_is_omap24xx())
222 return gpio & 0x1f;
223 if (cpu_is_omap34xx() || cpu_is_omap44xx())
224 return gpio & 0x1f;
225 return gpio & 0x0f;
226 }
227
228 static inline int gpio_valid(int gpio)
229 {
230 if (gpio < 0)
231 return -1;
232 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
233 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
234 return -1;
235 return 0;
236 }
237 if (cpu_is_omap15xx() && gpio < 16)
238 return 0;
239 if ((cpu_is_omap16xx()) && gpio < 64)
240 return 0;
241 if (cpu_is_omap7xx() && gpio < 192)
242 return 0;
243 if (cpu_is_omap2420() && gpio < 128)
244 return 0;
245 if (cpu_is_omap2430() && gpio < 160)
246 return 0;
247 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
248 return 0;
249 return -1;
250 }
251
252 static int check_gpio(int gpio)
253 {
254 if (unlikely(gpio_valid(gpio) < 0)) {
255 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
256 dump_stack();
257 return -1;
258 }
259 return 0;
260 }
261
262 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
263 {
264 void __iomem *reg = bank->base;
265 u32 l;
266
267 switch (bank->method) {
268 #ifdef CONFIG_ARCH_OMAP1
269 case METHOD_MPUIO:
270 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
271 break;
272 #endif
273 #ifdef CONFIG_ARCH_OMAP15XX
274 case METHOD_GPIO_1510:
275 reg += OMAP1510_GPIO_DIR_CONTROL;
276 break;
277 #endif
278 #ifdef CONFIG_ARCH_OMAP16XX
279 case METHOD_GPIO_1610:
280 reg += OMAP1610_GPIO_DIRECTION;
281 break;
282 #endif
283 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
284 case METHOD_GPIO_7XX:
285 reg += OMAP7XX_GPIO_DIR_CONTROL;
286 break;
287 #endif
288 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
289 case METHOD_GPIO_24XX:
290 reg += OMAP24XX_GPIO_OE;
291 break;
292 #endif
293 #if defined(CONFIG_ARCH_OMAP4)
294 case METHOD_GPIO_44XX:
295 reg += OMAP4_GPIO_OE;
296 break;
297 #endif
298 default:
299 WARN_ON(1);
300 return;
301 }
302 l = __raw_readl(reg);
303 if (is_input)
304 l |= 1 << gpio;
305 else
306 l &= ~(1 << gpio);
307 __raw_writel(l, reg);
308 }
309
310 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
311 {
312 void __iomem *reg = bank->base;
313 u32 l = 0;
314
315 switch (bank->method) {
316 #ifdef CONFIG_ARCH_OMAP1
317 case METHOD_MPUIO:
318 reg += OMAP_MPUIO_OUTPUT / bank->stride;
319 l = __raw_readl(reg);
320 if (enable)
321 l |= 1 << gpio;
322 else
323 l &= ~(1 << gpio);
324 break;
325 #endif
326 #ifdef CONFIG_ARCH_OMAP15XX
327 case METHOD_GPIO_1510:
328 reg += OMAP1510_GPIO_DATA_OUTPUT;
329 l = __raw_readl(reg);
330 if (enable)
331 l |= 1 << gpio;
332 else
333 l &= ~(1 << gpio);
334 break;
335 #endif
336 #ifdef CONFIG_ARCH_OMAP16XX
337 case METHOD_GPIO_1610:
338 if (enable)
339 reg += OMAP1610_GPIO_SET_DATAOUT;
340 else
341 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
342 l = 1 << gpio;
343 break;
344 #endif
345 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
346 case METHOD_GPIO_7XX:
347 reg += OMAP7XX_GPIO_DATA_OUTPUT;
348 l = __raw_readl(reg);
349 if (enable)
350 l |= 1 << gpio;
351 else
352 l &= ~(1 << gpio);
353 break;
354 #endif
355 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
356 case METHOD_GPIO_24XX:
357 if (enable)
358 reg += OMAP24XX_GPIO_SETDATAOUT;
359 else
360 reg += OMAP24XX_GPIO_CLEARDATAOUT;
361 l = 1 << gpio;
362 break;
363 #endif
364 #ifdef CONFIG_ARCH_OMAP4
365 case METHOD_GPIO_44XX:
366 if (enable)
367 reg += OMAP4_GPIO_SETDATAOUT;
368 else
369 reg += OMAP4_GPIO_CLEARDATAOUT;
370 l = 1 << gpio;
371 break;
372 #endif
373 default:
374 WARN_ON(1);
375 return;
376 }
377 __raw_writel(l, reg);
378 }
379
380 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
381 {
382 void __iomem *reg;
383
384 if (check_gpio(gpio) < 0)
385 return -EINVAL;
386 reg = bank->base;
387 switch (bank->method) {
388 #ifdef CONFIG_ARCH_OMAP1
389 case METHOD_MPUIO:
390 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
391 break;
392 #endif
393 #ifdef CONFIG_ARCH_OMAP15XX
394 case METHOD_GPIO_1510:
395 reg += OMAP1510_GPIO_DATA_INPUT;
396 break;
397 #endif
398 #ifdef CONFIG_ARCH_OMAP16XX
399 case METHOD_GPIO_1610:
400 reg += OMAP1610_GPIO_DATAIN;
401 break;
402 #endif
403 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
404 case METHOD_GPIO_7XX:
405 reg += OMAP7XX_GPIO_DATA_INPUT;
406 break;
407 #endif
408 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
409 case METHOD_GPIO_24XX:
410 reg += OMAP24XX_GPIO_DATAIN;
411 break;
412 #endif
413 #ifdef CONFIG_ARCH_OMAP4
414 case METHOD_GPIO_44XX:
415 reg += OMAP4_GPIO_DATAIN;
416 break;
417 #endif
418 default:
419 return -EINVAL;
420 }
421 return (__raw_readl(reg)
422 & (1 << get_gpio_index(gpio))) != 0;
423 }
424
425 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
426 {
427 void __iomem *reg;
428
429 if (check_gpio(gpio) < 0)
430 return -EINVAL;
431 reg = bank->base;
432
433 switch (bank->method) {
434 #ifdef CONFIG_ARCH_OMAP1
435 case METHOD_MPUIO:
436 reg += OMAP_MPUIO_OUTPUT / bank->stride;
437 break;
438 #endif
439 #ifdef CONFIG_ARCH_OMAP15XX
440 case METHOD_GPIO_1510:
441 reg += OMAP1510_GPIO_DATA_OUTPUT;
442 break;
443 #endif
444 #ifdef CONFIG_ARCH_OMAP16XX
445 case METHOD_GPIO_1610:
446 reg += OMAP1610_GPIO_DATAOUT;
447 break;
448 #endif
449 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
450 case METHOD_GPIO_7XX:
451 reg += OMAP7XX_GPIO_DATA_OUTPUT;
452 break;
453 #endif
454 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
455 case METHOD_GPIO_24XX:
456 reg += OMAP24XX_GPIO_DATAOUT;
457 break;
458 #endif
459 #ifdef CONFIG_ARCH_OMAP4
460 case METHOD_GPIO_44XX:
461 reg += OMAP4_GPIO_DATAOUT;
462 break;
463 #endif
464 default:
465 return -EINVAL;
466 }
467
468 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
469 }
470
471 #define MOD_REG_BIT(reg, bit_mask, set) \
472 do { \
473 int l = __raw_readl(base + reg); \
474 if (set) l |= bit_mask; \
475 else l &= ~bit_mask; \
476 __raw_writel(l, base + reg); \
477 } while(0)
478
479 /**
480 * _set_gpio_debounce - low level gpio debounce time
481 * @bank: the gpio bank we're acting upon
482 * @gpio: the gpio number on this @gpio
483 * @debounce: debounce time to use
484 *
485 * OMAP's debounce time is in 31us steps so we need
486 * to convert and round up to the closest unit.
487 */
488 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
489 unsigned debounce)
490 {
491 void __iomem *reg = bank->base;
492 u32 val;
493 u32 l;
494
495 if (!bank->dbck_flag)
496 return;
497
498 if (debounce < 32)
499 debounce = 0x01;
500 else if (debounce > 7936)
501 debounce = 0xff;
502 else
503 debounce = (debounce / 0x1f) - 1;
504
505 l = 1 << get_gpio_index(gpio);
506
507 if (bank->method == METHOD_GPIO_44XX)
508 reg += OMAP4_GPIO_DEBOUNCINGTIME;
509 else
510 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
511
512 __raw_writel(debounce, reg);
513
514 reg = bank->base;
515 if (bank->method == METHOD_GPIO_44XX)
516 reg += OMAP4_GPIO_DEBOUNCENABLE;
517 else
518 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
519
520 val = __raw_readl(reg);
521
522 if (debounce) {
523 val |= l;
524 clk_enable(bank->dbck);
525 } else {
526 val &= ~l;
527 clk_disable(bank->dbck);
528 }
529 bank->dbck_enable_mask = val;
530
531 __raw_writel(val, reg);
532 }
533
534 #ifdef CONFIG_ARCH_OMAP2PLUS
535 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
536 int trigger)
537 {
538 void __iomem *base = bank->base;
539 u32 gpio_bit = 1 << gpio;
540 u32 val;
541
542 if (cpu_is_omap44xx()) {
543 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
544 trigger & IRQ_TYPE_LEVEL_LOW);
545 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
546 trigger & IRQ_TYPE_LEVEL_HIGH);
547 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
548 trigger & IRQ_TYPE_EDGE_RISING);
549 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
550 trigger & IRQ_TYPE_EDGE_FALLING);
551 } else {
552 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
553 trigger & IRQ_TYPE_LEVEL_LOW);
554 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
555 trigger & IRQ_TYPE_LEVEL_HIGH);
556 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
557 trigger & IRQ_TYPE_EDGE_RISING);
558 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
559 trigger & IRQ_TYPE_EDGE_FALLING);
560 }
561 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
562 if (cpu_is_omap44xx()) {
563 if (trigger != 0)
564 __raw_writel(1 << gpio, bank->base+
565 OMAP4_GPIO_IRQWAKEN0);
566 else {
567 val = __raw_readl(bank->base +
568 OMAP4_GPIO_IRQWAKEN0);
569 __raw_writel(val & (~(1 << gpio)), bank->base +
570 OMAP4_GPIO_IRQWAKEN0);
571 }
572 } else {
573 /*
574 * GPIO wakeup request can only be generated on edge
575 * transitions
576 */
577 if (trigger & IRQ_TYPE_EDGE_BOTH)
578 __raw_writel(1 << gpio, bank->base
579 + OMAP24XX_GPIO_SETWKUENA);
580 else
581 __raw_writel(1 << gpio, bank->base
582 + OMAP24XX_GPIO_CLEARWKUENA);
583 }
584 }
585 /* This part needs to be executed always for OMAP34xx */
586 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
587 /*
588 * Log the edge gpio and manually trigger the IRQ
589 * after resume if the input level changes
590 * to avoid irq lost during PER RET/OFF mode
591 * Applies for omap2 non-wakeup gpio and all omap3 gpios
592 */
593 if (trigger & IRQ_TYPE_EDGE_BOTH)
594 bank->enabled_non_wakeup_gpios |= gpio_bit;
595 else
596 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
597 }
598
599 if (cpu_is_omap44xx()) {
600 bank->level_mask =
601 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
602 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
603 } else {
604 bank->level_mask =
605 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
606 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
607 }
608 }
609 #endif
610
611 #ifdef CONFIG_ARCH_OMAP1
612 /*
613 * This only applies to chips that can't do both rising and falling edge
614 * detection at once. For all other chips, this function is a noop.
615 */
616 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
617 {
618 void __iomem *reg = bank->base;
619 u32 l = 0;
620
621 switch (bank->method) {
622 case METHOD_MPUIO:
623 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
624 break;
625 #ifdef CONFIG_ARCH_OMAP15XX
626 case METHOD_GPIO_1510:
627 reg += OMAP1510_GPIO_INT_CONTROL;
628 break;
629 #endif
630 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
631 case METHOD_GPIO_7XX:
632 reg += OMAP7XX_GPIO_INT_CONTROL;
633 break;
634 #endif
635 default:
636 return;
637 }
638
639 l = __raw_readl(reg);
640 if ((l >> gpio) & 1)
641 l &= ~(1 << gpio);
642 else
643 l |= 1 << gpio;
644
645 __raw_writel(l, reg);
646 }
647 #endif
648
649 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
650 {
651 void __iomem *reg = bank->base;
652 u32 l = 0;
653
654 switch (bank->method) {
655 #ifdef CONFIG_ARCH_OMAP1
656 case METHOD_MPUIO:
657 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
658 l = __raw_readl(reg);
659 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
660 bank->toggle_mask |= 1 << gpio;
661 if (trigger & IRQ_TYPE_EDGE_RISING)
662 l |= 1 << gpio;
663 else if (trigger & IRQ_TYPE_EDGE_FALLING)
664 l &= ~(1 << gpio);
665 else
666 goto bad;
667 break;
668 #endif
669 #ifdef CONFIG_ARCH_OMAP15XX
670 case METHOD_GPIO_1510:
671 reg += OMAP1510_GPIO_INT_CONTROL;
672 l = __raw_readl(reg);
673 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
674 bank->toggle_mask |= 1 << gpio;
675 if (trigger & IRQ_TYPE_EDGE_RISING)
676 l |= 1 << gpio;
677 else if (trigger & IRQ_TYPE_EDGE_FALLING)
678 l &= ~(1 << gpio);
679 else
680 goto bad;
681 break;
682 #endif
683 #ifdef CONFIG_ARCH_OMAP16XX
684 case METHOD_GPIO_1610:
685 if (gpio & 0x08)
686 reg += OMAP1610_GPIO_EDGE_CTRL2;
687 else
688 reg += OMAP1610_GPIO_EDGE_CTRL1;
689 gpio &= 0x07;
690 l = __raw_readl(reg);
691 l &= ~(3 << (gpio << 1));
692 if (trigger & IRQ_TYPE_EDGE_RISING)
693 l |= 2 << (gpio << 1);
694 if (trigger & IRQ_TYPE_EDGE_FALLING)
695 l |= 1 << (gpio << 1);
696 if (trigger)
697 /* Enable wake-up during idle for dynamic tick */
698 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
699 else
700 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
701 break;
702 #endif
703 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
704 case METHOD_GPIO_7XX:
705 reg += OMAP7XX_GPIO_INT_CONTROL;
706 l = __raw_readl(reg);
707 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
708 bank->toggle_mask |= 1 << gpio;
709 if (trigger & IRQ_TYPE_EDGE_RISING)
710 l |= 1 << gpio;
711 else if (trigger & IRQ_TYPE_EDGE_FALLING)
712 l &= ~(1 << gpio);
713 else
714 goto bad;
715 break;
716 #endif
717 #ifdef CONFIG_ARCH_OMAP2PLUS
718 case METHOD_GPIO_24XX:
719 case METHOD_GPIO_44XX:
720 set_24xx_gpio_triggering(bank, gpio, trigger);
721 return 0;
722 #endif
723 default:
724 goto bad;
725 }
726 __raw_writel(l, reg);
727 return 0;
728 bad:
729 return -EINVAL;
730 }
731
732 static int gpio_irq_type(struct irq_data *d, unsigned type)
733 {
734 struct gpio_bank *bank;
735 unsigned gpio;
736 int retval;
737 unsigned long flags;
738
739 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
740 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
741 else
742 gpio = d->irq - IH_GPIO_BASE;
743
744 if (check_gpio(gpio) < 0)
745 return -EINVAL;
746
747 if (type & ~IRQ_TYPE_SENSE_MASK)
748 return -EINVAL;
749
750 /* OMAP1 allows only only edge triggering */
751 if (!cpu_class_is_omap2()
752 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
753 return -EINVAL;
754
755 bank = irq_data_get_irq_chip_data(d);
756 spin_lock_irqsave(&bank->lock, flags);
757 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
758 if (retval == 0) {
759 struct irq_desc *desc = irq_to_desc(d->irq);
760
761 desc->status &= ~IRQ_TYPE_SENSE_MASK;
762 desc->status |= type;
763 }
764 spin_unlock_irqrestore(&bank->lock, flags);
765
766 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
767 __set_irq_handler_unlocked(d->irq, handle_level_irq);
768 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
769 __set_irq_handler_unlocked(d->irq, handle_edge_irq);
770
771 return retval;
772 }
773
774 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
775 {
776 void __iomem *reg = bank->base;
777
778 switch (bank->method) {
779 #ifdef CONFIG_ARCH_OMAP1
780 case METHOD_MPUIO:
781 /* MPUIO irqstatus is reset by reading the status register,
782 * so do nothing here */
783 return;
784 #endif
785 #ifdef CONFIG_ARCH_OMAP15XX
786 case METHOD_GPIO_1510:
787 reg += OMAP1510_GPIO_INT_STATUS;
788 break;
789 #endif
790 #ifdef CONFIG_ARCH_OMAP16XX
791 case METHOD_GPIO_1610:
792 reg += OMAP1610_GPIO_IRQSTATUS1;
793 break;
794 #endif
795 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
796 case METHOD_GPIO_7XX:
797 reg += OMAP7XX_GPIO_INT_STATUS;
798 break;
799 #endif
800 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
801 case METHOD_GPIO_24XX:
802 reg += OMAP24XX_GPIO_IRQSTATUS1;
803 break;
804 #endif
805 #if defined(CONFIG_ARCH_OMAP4)
806 case METHOD_GPIO_44XX:
807 reg += OMAP4_GPIO_IRQSTATUS0;
808 break;
809 #endif
810 default:
811 WARN_ON(1);
812 return;
813 }
814 __raw_writel(gpio_mask, reg);
815
816 /* Workaround for clearing DSP GPIO interrupts to allow retention */
817 if (cpu_is_omap24xx() || cpu_is_omap34xx())
818 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
819 else if (cpu_is_omap44xx())
820 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
821
822 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
823 __raw_writel(gpio_mask, reg);
824
825 /* Flush posted write for the irq status to avoid spurious interrupts */
826 __raw_readl(reg);
827 }
828 }
829
830 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
831 {
832 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
833 }
834
835 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
836 {
837 void __iomem *reg = bank->base;
838 int inv = 0;
839 u32 l;
840 u32 mask;
841
842 switch (bank->method) {
843 #ifdef CONFIG_ARCH_OMAP1
844 case METHOD_MPUIO:
845 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
846 mask = 0xffff;
847 inv = 1;
848 break;
849 #endif
850 #ifdef CONFIG_ARCH_OMAP15XX
851 case METHOD_GPIO_1510:
852 reg += OMAP1510_GPIO_INT_MASK;
853 mask = 0xffff;
854 inv = 1;
855 break;
856 #endif
857 #ifdef CONFIG_ARCH_OMAP16XX
858 case METHOD_GPIO_1610:
859 reg += OMAP1610_GPIO_IRQENABLE1;
860 mask = 0xffff;
861 break;
862 #endif
863 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
864 case METHOD_GPIO_7XX:
865 reg += OMAP7XX_GPIO_INT_MASK;
866 mask = 0xffffffff;
867 inv = 1;
868 break;
869 #endif
870 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
871 case METHOD_GPIO_24XX:
872 reg += OMAP24XX_GPIO_IRQENABLE1;
873 mask = 0xffffffff;
874 break;
875 #endif
876 #if defined(CONFIG_ARCH_OMAP4)
877 case METHOD_GPIO_44XX:
878 reg += OMAP4_GPIO_IRQSTATUSSET0;
879 mask = 0xffffffff;
880 break;
881 #endif
882 default:
883 WARN_ON(1);
884 return 0;
885 }
886
887 l = __raw_readl(reg);
888 if (inv)
889 l = ~l;
890 l &= mask;
891 return l;
892 }
893
894 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
895 {
896 void __iomem *reg = bank->base;
897 u32 l;
898
899 switch (bank->method) {
900 #ifdef CONFIG_ARCH_OMAP1
901 case METHOD_MPUIO:
902 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
903 l = __raw_readl(reg);
904 if (enable)
905 l &= ~(gpio_mask);
906 else
907 l |= gpio_mask;
908 break;
909 #endif
910 #ifdef CONFIG_ARCH_OMAP15XX
911 case METHOD_GPIO_1510:
912 reg += OMAP1510_GPIO_INT_MASK;
913 l = __raw_readl(reg);
914 if (enable)
915 l &= ~(gpio_mask);
916 else
917 l |= gpio_mask;
918 break;
919 #endif
920 #ifdef CONFIG_ARCH_OMAP16XX
921 case METHOD_GPIO_1610:
922 if (enable)
923 reg += OMAP1610_GPIO_SET_IRQENABLE1;
924 else
925 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
926 l = gpio_mask;
927 break;
928 #endif
929 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
930 case METHOD_GPIO_7XX:
931 reg += OMAP7XX_GPIO_INT_MASK;
932 l = __raw_readl(reg);
933 if (enable)
934 l &= ~(gpio_mask);
935 else
936 l |= gpio_mask;
937 break;
938 #endif
939 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
940 case METHOD_GPIO_24XX:
941 if (enable)
942 reg += OMAP24XX_GPIO_SETIRQENABLE1;
943 else
944 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
945 l = gpio_mask;
946 break;
947 #endif
948 #ifdef CONFIG_ARCH_OMAP4
949 case METHOD_GPIO_44XX:
950 if (enable)
951 reg += OMAP4_GPIO_IRQSTATUSSET0;
952 else
953 reg += OMAP4_GPIO_IRQSTATUSCLR0;
954 l = gpio_mask;
955 break;
956 #endif
957 default:
958 WARN_ON(1);
959 return;
960 }
961 __raw_writel(l, reg);
962 }
963
964 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
965 {
966 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
967 }
968
969 /*
970 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
971 * 1510 does not seem to have a wake-up register. If JTAG is connected
972 * to the target, system will wake up always on GPIO events. While
973 * system is running all registered GPIO interrupts need to have wake-up
974 * enabled. When system is suspended, only selected GPIO interrupts need
975 * to have wake-up enabled.
976 */
977 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
978 {
979 unsigned long uninitialized_var(flags);
980
981 switch (bank->method) {
982 #ifdef CONFIG_ARCH_OMAP16XX
983 case METHOD_MPUIO:
984 case METHOD_GPIO_1610:
985 spin_lock_irqsave(&bank->lock, flags);
986 if (enable)
987 bank->suspend_wakeup |= (1 << gpio);
988 else
989 bank->suspend_wakeup &= ~(1 << gpio);
990 spin_unlock_irqrestore(&bank->lock, flags);
991 return 0;
992 #endif
993 #ifdef CONFIG_ARCH_OMAP2PLUS
994 case METHOD_GPIO_24XX:
995 case METHOD_GPIO_44XX:
996 if (bank->non_wakeup_gpios & (1 << gpio)) {
997 printk(KERN_ERR "Unable to modify wakeup on "
998 "non-wakeup GPIO%d\n",
999 (bank - gpio_bank) * 32 + gpio);
1000 return -EINVAL;
1001 }
1002 spin_lock_irqsave(&bank->lock, flags);
1003 if (enable)
1004 bank->suspend_wakeup |= (1 << gpio);
1005 else
1006 bank->suspend_wakeup &= ~(1 << gpio);
1007 spin_unlock_irqrestore(&bank->lock, flags);
1008 return 0;
1009 #endif
1010 default:
1011 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1012 bank->method);
1013 return -EINVAL;
1014 }
1015 }
1016
1017 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1018 {
1019 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1020 _set_gpio_irqenable(bank, gpio, 0);
1021 _clear_gpio_irqstatus(bank, gpio);
1022 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1023 }
1024
1025 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1026 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
1027 {
1028 unsigned int gpio = d->irq - IH_GPIO_BASE;
1029 struct gpio_bank *bank;
1030 int retval;
1031
1032 if (check_gpio(gpio) < 0)
1033 return -ENODEV;
1034 bank = irq_data_get_irq_chip_data(d);
1035 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1036
1037 return retval;
1038 }
1039
1040 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1041 {
1042 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1043 unsigned long flags;
1044
1045 spin_lock_irqsave(&bank->lock, flags);
1046
1047 /* Set trigger to none. You need to enable the desired trigger with
1048 * request_irq() or set_irq_type().
1049 */
1050 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1051
1052 #ifdef CONFIG_ARCH_OMAP15XX
1053 if (bank->method == METHOD_GPIO_1510) {
1054 void __iomem *reg;
1055
1056 /* Claim the pin for MPU */
1057 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1058 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1059 }
1060 #endif
1061 if (!cpu_class_is_omap1()) {
1062 if (!bank->mod_usage) {
1063 void __iomem *reg = bank->base;
1064 u32 ctrl;
1065
1066 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1067 reg += OMAP24XX_GPIO_CTRL;
1068 else if (cpu_is_omap44xx())
1069 reg += OMAP4_GPIO_CTRL;
1070 ctrl = __raw_readl(reg);
1071 /* Module is enabled, clocks are not gated */
1072 ctrl &= 0xFFFFFFFE;
1073 __raw_writel(ctrl, reg);
1074 }
1075 bank->mod_usage |= 1 << offset;
1076 }
1077 spin_unlock_irqrestore(&bank->lock, flags);
1078
1079 return 0;
1080 }
1081
1082 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1083 {
1084 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1085 unsigned long flags;
1086
1087 spin_lock_irqsave(&bank->lock, flags);
1088 #ifdef CONFIG_ARCH_OMAP16XX
1089 if (bank->method == METHOD_GPIO_1610) {
1090 /* Disable wake-up during idle for dynamic tick */
1091 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1092 __raw_writel(1 << offset, reg);
1093 }
1094 #endif
1095 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1096 if (bank->method == METHOD_GPIO_24XX) {
1097 /* Disable wake-up during idle for dynamic tick */
1098 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1099 __raw_writel(1 << offset, reg);
1100 }
1101 #endif
1102 #ifdef CONFIG_ARCH_OMAP4
1103 if (bank->method == METHOD_GPIO_44XX) {
1104 /* Disable wake-up during idle for dynamic tick */
1105 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1106 __raw_writel(1 << offset, reg);
1107 }
1108 #endif
1109 if (!cpu_class_is_omap1()) {
1110 bank->mod_usage &= ~(1 << offset);
1111 if (!bank->mod_usage) {
1112 void __iomem *reg = bank->base;
1113 u32 ctrl;
1114
1115 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1116 reg += OMAP24XX_GPIO_CTRL;
1117 else if (cpu_is_omap44xx())
1118 reg += OMAP4_GPIO_CTRL;
1119 ctrl = __raw_readl(reg);
1120 /* Module is disabled, clocks are gated */
1121 ctrl |= 1;
1122 __raw_writel(ctrl, reg);
1123 }
1124 }
1125 _reset_gpio(bank, bank->chip.base + offset);
1126 spin_unlock_irqrestore(&bank->lock, flags);
1127 }
1128
1129 /*
1130 * We need to unmask the GPIO bank interrupt as soon as possible to
1131 * avoid missing GPIO interrupts for other lines in the bank.
1132 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1133 * in the bank to avoid missing nested interrupts for a GPIO line.
1134 * If we wait to unmask individual GPIO lines in the bank after the
1135 * line's interrupt handler has been run, we may miss some nested
1136 * interrupts.
1137 */
1138 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1139 {
1140 void __iomem *isr_reg = NULL;
1141 u32 isr;
1142 unsigned int gpio_irq, gpio_index;
1143 struct gpio_bank *bank;
1144 u32 retrigger = 0;
1145 int unmasked = 0;
1146
1147 desc->irq_data.chip->irq_ack(&desc->irq_data);
1148
1149 bank = get_irq_data(irq);
1150 #ifdef CONFIG_ARCH_OMAP1
1151 if (bank->method == METHOD_MPUIO)
1152 isr_reg = bank->base +
1153 OMAP_MPUIO_GPIO_INT / bank->stride;
1154 #endif
1155 #ifdef CONFIG_ARCH_OMAP15XX
1156 if (bank->method == METHOD_GPIO_1510)
1157 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1158 #endif
1159 #if defined(CONFIG_ARCH_OMAP16XX)
1160 if (bank->method == METHOD_GPIO_1610)
1161 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1162 #endif
1163 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1164 if (bank->method == METHOD_GPIO_7XX)
1165 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1166 #endif
1167 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1168 if (bank->method == METHOD_GPIO_24XX)
1169 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1170 #endif
1171 #if defined(CONFIG_ARCH_OMAP4)
1172 if (bank->method == METHOD_GPIO_44XX)
1173 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1174 #endif
1175
1176 if (WARN_ON(!isr_reg))
1177 goto exit;
1178
1179 while(1) {
1180 u32 isr_saved, level_mask = 0;
1181 u32 enabled;
1182
1183 enabled = _get_gpio_irqbank_mask(bank);
1184 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1185
1186 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1187 isr &= 0x0000ffff;
1188
1189 if (cpu_class_is_omap2()) {
1190 level_mask = bank->level_mask & enabled;
1191 }
1192
1193 /* clear edge sensitive interrupts before handler(s) are
1194 called so that we don't miss any interrupt occurred while
1195 executing them */
1196 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1197 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1198 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1199
1200 /* if there is only edge sensitive GPIO pin interrupts
1201 configured, we could unmask GPIO bank interrupt immediately */
1202 if (!level_mask && !unmasked) {
1203 unmasked = 1;
1204 desc->irq_data.chip->irq_unmask(&desc->irq_data);
1205 }
1206
1207 isr |= retrigger;
1208 retrigger = 0;
1209 if (!isr)
1210 break;
1211
1212 gpio_irq = bank->virtual_irq_start;
1213 for (; isr != 0; isr >>= 1, gpio_irq++) {
1214 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1215
1216 if (!(isr & 1))
1217 continue;
1218
1219 #ifdef CONFIG_ARCH_OMAP1
1220 /*
1221 * Some chips can't respond to both rising and falling
1222 * at the same time. If this irq was requested with
1223 * both flags, we need to flip the ICR data for the IRQ
1224 * to respond to the IRQ for the opposite direction.
1225 * This will be indicated in the bank toggle_mask.
1226 */
1227 if (bank->toggle_mask & (1 << gpio_index))
1228 _toggle_gpio_edge_triggering(bank, gpio_index);
1229 #endif
1230
1231 generic_handle_irq(gpio_irq);
1232 }
1233 }
1234 /* if bank has any level sensitive GPIO pin interrupt
1235 configured, we must unmask the bank interrupt only after
1236 handler(s) are executed in order to avoid spurious bank
1237 interrupt */
1238 exit:
1239 if (!unmasked)
1240 desc->irq_data.chip->irq_unmask(&desc->irq_data);
1241 }
1242
1243 static void gpio_irq_shutdown(struct irq_data *d)
1244 {
1245 unsigned int gpio = d->irq - IH_GPIO_BASE;
1246 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1247
1248 _reset_gpio(bank, gpio);
1249 }
1250
1251 static void gpio_ack_irq(struct irq_data *d)
1252 {
1253 unsigned int gpio = d->irq - IH_GPIO_BASE;
1254 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1255
1256 _clear_gpio_irqstatus(bank, gpio);
1257 }
1258
1259 static void gpio_mask_irq(struct irq_data *d)
1260 {
1261 unsigned int gpio = d->irq - IH_GPIO_BASE;
1262 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1263
1264 _set_gpio_irqenable(bank, gpio, 0);
1265 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1266 }
1267
1268 static void gpio_unmask_irq(struct irq_data *d)
1269 {
1270 unsigned int gpio = d->irq - IH_GPIO_BASE;
1271 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1272 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1273 struct irq_desc *desc = irq_to_desc(d->irq);
1274 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1275
1276 if (trigger)
1277 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1278
1279 /* For level-triggered GPIOs, the clearing must be done after
1280 * the HW source is cleared, thus after the handler has run */
1281 if (bank->level_mask & irq_mask) {
1282 _set_gpio_irqenable(bank, gpio, 0);
1283 _clear_gpio_irqstatus(bank, gpio);
1284 }
1285
1286 _set_gpio_irqenable(bank, gpio, 1);
1287 }
1288
1289 static struct irq_chip gpio_irq_chip = {
1290 .name = "GPIO",
1291 .irq_shutdown = gpio_irq_shutdown,
1292 .irq_ack = gpio_ack_irq,
1293 .irq_mask = gpio_mask_irq,
1294 .irq_unmask = gpio_unmask_irq,
1295 .irq_set_type = gpio_irq_type,
1296 .irq_set_wake = gpio_wake_enable,
1297 };
1298
1299 /*---------------------------------------------------------------------*/
1300
1301 #ifdef CONFIG_ARCH_OMAP1
1302
1303 /* MPUIO uses the always-on 32k clock */
1304
1305 static void mpuio_ack_irq(struct irq_data *d)
1306 {
1307 /* The ISR is reset automatically, so do nothing here. */
1308 }
1309
1310 static void mpuio_mask_irq(struct irq_data *d)
1311 {
1312 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1313 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1314
1315 _set_gpio_irqenable(bank, gpio, 0);
1316 }
1317
1318 static void mpuio_unmask_irq(struct irq_data *d)
1319 {
1320 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1321 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1322
1323 _set_gpio_irqenable(bank, gpio, 1);
1324 }
1325
1326 static struct irq_chip mpuio_irq_chip = {
1327 .name = "MPUIO",
1328 .irq_ack = mpuio_ack_irq,
1329 .irq_mask = mpuio_mask_irq,
1330 .irq_unmask = mpuio_unmask_irq,
1331 .irq_set_type = gpio_irq_type,
1332 #ifdef CONFIG_ARCH_OMAP16XX
1333 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1334 .irq_set_wake = gpio_wake_enable,
1335 #endif
1336 };
1337
1338
1339 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1340
1341
1342 #ifdef CONFIG_ARCH_OMAP16XX
1343
1344 #include <linux/platform_device.h>
1345
1346 static int omap_mpuio_suspend_noirq(struct device *dev)
1347 {
1348 struct platform_device *pdev = to_platform_device(dev);
1349 struct gpio_bank *bank = platform_get_drvdata(pdev);
1350 void __iomem *mask_reg = bank->base +
1351 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1352 unsigned long flags;
1353
1354 spin_lock_irqsave(&bank->lock, flags);
1355 bank->saved_wakeup = __raw_readl(mask_reg);
1356 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1357 spin_unlock_irqrestore(&bank->lock, flags);
1358
1359 return 0;
1360 }
1361
1362 static int omap_mpuio_resume_noirq(struct device *dev)
1363 {
1364 struct platform_device *pdev = to_platform_device(dev);
1365 struct gpio_bank *bank = platform_get_drvdata(pdev);
1366 void __iomem *mask_reg = bank->base +
1367 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1368 unsigned long flags;
1369
1370 spin_lock_irqsave(&bank->lock, flags);
1371 __raw_writel(bank->saved_wakeup, mask_reg);
1372 spin_unlock_irqrestore(&bank->lock, flags);
1373
1374 return 0;
1375 }
1376
1377 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1378 .suspend_noirq = omap_mpuio_suspend_noirq,
1379 .resume_noirq = omap_mpuio_resume_noirq,
1380 };
1381
1382 /* use platform_driver for this, now that there's no longer any
1383 * point to sys_device (other than not disturbing old code).
1384 */
1385 static struct platform_driver omap_mpuio_driver = {
1386 .driver = {
1387 .name = "mpuio",
1388 .pm = &omap_mpuio_dev_pm_ops,
1389 },
1390 };
1391
1392 static struct platform_device omap_mpuio_device = {
1393 .name = "mpuio",
1394 .id = -1,
1395 .dev = {
1396 .driver = &omap_mpuio_driver.driver,
1397 }
1398 /* could list the /proc/iomem resources */
1399 };
1400
1401 static inline void mpuio_init(void)
1402 {
1403 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1404 platform_set_drvdata(&omap_mpuio_device, bank);
1405
1406 if (platform_driver_register(&omap_mpuio_driver) == 0)
1407 (void) platform_device_register(&omap_mpuio_device);
1408 }
1409
1410 #else
1411 static inline void mpuio_init(void) {}
1412 #endif /* 16xx */
1413
1414 #else
1415
1416 extern struct irq_chip mpuio_irq_chip;
1417
1418 #define bank_is_mpuio(bank) 0
1419 static inline void mpuio_init(void) {}
1420
1421 #endif
1422
1423 /*---------------------------------------------------------------------*/
1424
1425 /* REVISIT these are stupid implementations! replace by ones that
1426 * don't switch on METHOD_* and which mostly avoid spinlocks
1427 */
1428
1429 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1430 {
1431 struct gpio_bank *bank;
1432 unsigned long flags;
1433
1434 bank = container_of(chip, struct gpio_bank, chip);
1435 spin_lock_irqsave(&bank->lock, flags);
1436 _set_gpio_direction(bank, offset, 1);
1437 spin_unlock_irqrestore(&bank->lock, flags);
1438 return 0;
1439 }
1440
1441 static int gpio_is_input(struct gpio_bank *bank, int mask)
1442 {
1443 void __iomem *reg = bank->base;
1444
1445 switch (bank->method) {
1446 case METHOD_MPUIO:
1447 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1448 break;
1449 case METHOD_GPIO_1510:
1450 reg += OMAP1510_GPIO_DIR_CONTROL;
1451 break;
1452 case METHOD_GPIO_1610:
1453 reg += OMAP1610_GPIO_DIRECTION;
1454 break;
1455 case METHOD_GPIO_7XX:
1456 reg += OMAP7XX_GPIO_DIR_CONTROL;
1457 break;
1458 case METHOD_GPIO_24XX:
1459 reg += OMAP24XX_GPIO_OE;
1460 break;
1461 case METHOD_GPIO_44XX:
1462 reg += OMAP4_GPIO_OE;
1463 break;
1464 default:
1465 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1466 return -EINVAL;
1467 }
1468 return __raw_readl(reg) & mask;
1469 }
1470
1471 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1472 {
1473 struct gpio_bank *bank;
1474 void __iomem *reg;
1475 int gpio;
1476 u32 mask;
1477
1478 gpio = chip->base + offset;
1479 bank = get_gpio_bank(gpio);
1480 reg = bank->base;
1481 mask = 1 << get_gpio_index(gpio);
1482
1483 if (gpio_is_input(bank, mask))
1484 return _get_gpio_datain(bank, gpio);
1485 else
1486 return _get_gpio_dataout(bank, gpio);
1487 }
1488
1489 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1490 {
1491 struct gpio_bank *bank;
1492 unsigned long flags;
1493
1494 bank = container_of(chip, struct gpio_bank, chip);
1495 spin_lock_irqsave(&bank->lock, flags);
1496 _set_gpio_dataout(bank, offset, value);
1497 _set_gpio_direction(bank, offset, 0);
1498 spin_unlock_irqrestore(&bank->lock, flags);
1499 return 0;
1500 }
1501
1502 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1503 unsigned debounce)
1504 {
1505 struct gpio_bank *bank;
1506 unsigned long flags;
1507
1508 bank = container_of(chip, struct gpio_bank, chip);
1509
1510 if (!bank->dbck) {
1511 bank->dbck = clk_get(bank->dev, "dbclk");
1512 if (IS_ERR(bank->dbck))
1513 dev_err(bank->dev, "Could not get gpio dbck\n");
1514 }
1515
1516 spin_lock_irqsave(&bank->lock, flags);
1517 _set_gpio_debounce(bank, offset, debounce);
1518 spin_unlock_irqrestore(&bank->lock, flags);
1519
1520 return 0;
1521 }
1522
1523 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1524 {
1525 struct gpio_bank *bank;
1526 unsigned long flags;
1527
1528 bank = container_of(chip, struct gpio_bank, chip);
1529 spin_lock_irqsave(&bank->lock, flags);
1530 _set_gpio_dataout(bank, offset, value);
1531 spin_unlock_irqrestore(&bank->lock, flags);
1532 }
1533
1534 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1535 {
1536 struct gpio_bank *bank;
1537
1538 bank = container_of(chip, struct gpio_bank, chip);
1539 return bank->virtual_irq_start + offset;
1540 }
1541
1542 /*---------------------------------------------------------------------*/
1543
1544 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1545 {
1546 u32 rev;
1547
1548 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1549 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1550 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1551 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1552 else if (cpu_is_omap44xx())
1553 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1554 else
1555 return;
1556
1557 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1558 (rev >> 4) & 0x0f, rev & 0x0f);
1559 }
1560
1561 /* This lock class tells lockdep that GPIO irqs are in a different
1562 * category than their parents, so it won't report false recursion.
1563 */
1564 static struct lock_class_key gpio_lock_class;
1565
1566 static inline int init_gpio_info(struct platform_device *pdev)
1567 {
1568 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1569 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1570 GFP_KERNEL);
1571 if (!gpio_bank) {
1572 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1573 return -ENOMEM;
1574 }
1575 return 0;
1576 }
1577
1578 /* TODO: Cleanup cpu_is_* checks */
1579 static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1580 {
1581 if (cpu_class_is_omap2()) {
1582 if (cpu_is_omap44xx()) {
1583 __raw_writel(0xffffffff, bank->base +
1584 OMAP4_GPIO_IRQSTATUSCLR0);
1585 __raw_writel(0x00000000, bank->base +
1586 OMAP4_GPIO_DEBOUNCENABLE);
1587 /* Initialize interface clk ungated, module enabled */
1588 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1589 } else if (cpu_is_omap34xx()) {
1590 __raw_writel(0x00000000, bank->base +
1591 OMAP24XX_GPIO_IRQENABLE1);
1592 __raw_writel(0xffffffff, bank->base +
1593 OMAP24XX_GPIO_IRQSTATUS1);
1594 __raw_writel(0x00000000, bank->base +
1595 OMAP24XX_GPIO_DEBOUNCE_EN);
1596
1597 /* Initialize interface clk ungated, module enabled */
1598 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1599 } else if (cpu_is_omap24xx()) {
1600 static const u32 non_wakeup_gpios[] = {
1601 0xe203ffc0, 0x08700040
1602 };
1603 if (id < ARRAY_SIZE(non_wakeup_gpios))
1604 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1605 }
1606 } else if (cpu_class_is_omap1()) {
1607 if (bank_is_mpuio(bank))
1608 __raw_writew(0xffff, bank->base +
1609 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1610 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1611 __raw_writew(0xffff, bank->base
1612 + OMAP1510_GPIO_INT_MASK);
1613 __raw_writew(0x0000, bank->base
1614 + OMAP1510_GPIO_INT_STATUS);
1615 }
1616 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1617 __raw_writew(0x0000, bank->base
1618 + OMAP1610_GPIO_IRQENABLE1);
1619 __raw_writew(0xffff, bank->base
1620 + OMAP1610_GPIO_IRQSTATUS1);
1621 __raw_writew(0x0014, bank->base
1622 + OMAP1610_GPIO_SYSCONFIG);
1623
1624 /*
1625 * Enable system clock for GPIO module.
1626 * The CAM_CLK_CTRL *is* really the right place.
1627 */
1628 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1629 ULPD_CAM_CLK_CTRL);
1630 }
1631 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1632 __raw_writel(0xffffffff, bank->base
1633 + OMAP7XX_GPIO_INT_MASK);
1634 __raw_writel(0x00000000, bank->base
1635 + OMAP7XX_GPIO_INT_STATUS);
1636 }
1637 }
1638 }
1639
1640 static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1641 {
1642 int j;
1643 static int gpio;
1644
1645 bank->mod_usage = 0;
1646 /*
1647 * REVISIT eventually switch from OMAP-specific gpio structs
1648 * over to the generic ones
1649 */
1650 bank->chip.request = omap_gpio_request;
1651 bank->chip.free = omap_gpio_free;
1652 bank->chip.direction_input = gpio_input;
1653 bank->chip.get = gpio_get;
1654 bank->chip.direction_output = gpio_output;
1655 bank->chip.set_debounce = gpio_debounce;
1656 bank->chip.set = gpio_set;
1657 bank->chip.to_irq = gpio_2irq;
1658 if (bank_is_mpuio(bank)) {
1659 bank->chip.label = "mpuio";
1660 #ifdef CONFIG_ARCH_OMAP16XX
1661 bank->chip.dev = &omap_mpuio_device.dev;
1662 #endif
1663 bank->chip.base = OMAP_MPUIO(0);
1664 } else {
1665 bank->chip.label = "gpio";
1666 bank->chip.base = gpio;
1667 gpio += bank_width;
1668 }
1669 bank->chip.ngpio = bank_width;
1670
1671 gpiochip_add(&bank->chip);
1672
1673 for (j = bank->virtual_irq_start;
1674 j < bank->virtual_irq_start + bank_width; j++) {
1675 struct irq_desc *d = irq_to_desc(j);
1676
1677 lockdep_set_class(&d->lock, &gpio_lock_class);
1678 set_irq_chip_data(j, bank);
1679 if (bank_is_mpuio(bank))
1680 set_irq_chip(j, &mpuio_irq_chip);
1681 else
1682 set_irq_chip(j, &gpio_irq_chip);
1683 set_irq_handler(j, handle_simple_irq);
1684 set_irq_flags(j, IRQF_VALID);
1685 }
1686 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1687 set_irq_data(bank->irq, bank);
1688 }
1689
1690 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1691 {
1692 static int gpio_init_done;
1693 struct omap_gpio_platform_data *pdata;
1694 struct resource *res;
1695 int id;
1696 struct gpio_bank *bank;
1697
1698 if (!pdev->dev.platform_data)
1699 return -EINVAL;
1700
1701 pdata = pdev->dev.platform_data;
1702
1703 if (!gpio_init_done) {
1704 int ret;
1705
1706 ret = init_gpio_info(pdev);
1707 if (ret)
1708 return ret;
1709 }
1710
1711 id = pdev->id;
1712 bank = &gpio_bank[id];
1713
1714 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1715 if (unlikely(!res)) {
1716 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1717 return -ENODEV;
1718 }
1719
1720 bank->irq = res->start;
1721 bank->virtual_irq_start = pdata->virtual_irq_start;
1722 bank->method = pdata->bank_type;
1723 bank->dev = &pdev->dev;
1724 bank->dbck_flag = pdata->dbck_flag;
1725 bank->stride = pdata->bank_stride;
1726 bank_width = pdata->bank_width;
1727
1728 spin_lock_init(&bank->lock);
1729
1730 /* Static mapping, never released */
1731 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1732 if (unlikely(!res)) {
1733 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1734 return -ENODEV;
1735 }
1736
1737 bank->base = ioremap(res->start, resource_size(res));
1738 if (!bank->base) {
1739 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1740 return -ENOMEM;
1741 }
1742
1743 pm_runtime_enable(bank->dev);
1744 pm_runtime_get_sync(bank->dev);
1745
1746 omap_gpio_mod_init(bank, id);
1747 omap_gpio_chip_init(bank);
1748 omap_gpio_show_rev(bank);
1749
1750 if (!gpio_init_done)
1751 gpio_init_done = 1;
1752
1753 return 0;
1754 }
1755
1756 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1757 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1758 {
1759 int i;
1760
1761 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1762 return 0;
1763
1764 for (i = 0; i < gpio_bank_count; i++) {
1765 struct gpio_bank *bank = &gpio_bank[i];
1766 void __iomem *wake_status;
1767 void __iomem *wake_clear;
1768 void __iomem *wake_set;
1769 unsigned long flags;
1770
1771 switch (bank->method) {
1772 #ifdef CONFIG_ARCH_OMAP16XX
1773 case METHOD_GPIO_1610:
1774 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1775 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1776 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1777 break;
1778 #endif
1779 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1780 case METHOD_GPIO_24XX:
1781 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1782 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1783 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1784 break;
1785 #endif
1786 #ifdef CONFIG_ARCH_OMAP4
1787 case METHOD_GPIO_44XX:
1788 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1789 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1790 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1791 break;
1792 #endif
1793 default:
1794 continue;
1795 }
1796
1797 spin_lock_irqsave(&bank->lock, flags);
1798 bank->saved_wakeup = __raw_readl(wake_status);
1799 __raw_writel(0xffffffff, wake_clear);
1800 __raw_writel(bank->suspend_wakeup, wake_set);
1801 spin_unlock_irqrestore(&bank->lock, flags);
1802 }
1803
1804 return 0;
1805 }
1806
1807 static int omap_gpio_resume(struct sys_device *dev)
1808 {
1809 int i;
1810
1811 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1812 return 0;
1813
1814 for (i = 0; i < gpio_bank_count; i++) {
1815 struct gpio_bank *bank = &gpio_bank[i];
1816 void __iomem *wake_clear;
1817 void __iomem *wake_set;
1818 unsigned long flags;
1819
1820 switch (bank->method) {
1821 #ifdef CONFIG_ARCH_OMAP16XX
1822 case METHOD_GPIO_1610:
1823 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1824 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1825 break;
1826 #endif
1827 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1828 case METHOD_GPIO_24XX:
1829 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1830 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1831 break;
1832 #endif
1833 #ifdef CONFIG_ARCH_OMAP4
1834 case METHOD_GPIO_44XX:
1835 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1836 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1837 break;
1838 #endif
1839 default:
1840 continue;
1841 }
1842
1843 spin_lock_irqsave(&bank->lock, flags);
1844 __raw_writel(0xffffffff, wake_clear);
1845 __raw_writel(bank->saved_wakeup, wake_set);
1846 spin_unlock_irqrestore(&bank->lock, flags);
1847 }
1848
1849 return 0;
1850 }
1851
1852 static struct sysdev_class omap_gpio_sysclass = {
1853 .name = "gpio",
1854 .suspend = omap_gpio_suspend,
1855 .resume = omap_gpio_resume,
1856 };
1857
1858 static struct sys_device omap_gpio_device = {
1859 .id = 0,
1860 .cls = &omap_gpio_sysclass,
1861 };
1862
1863 #endif
1864
1865 #ifdef CONFIG_ARCH_OMAP2PLUS
1866
1867 static int workaround_enabled;
1868
1869 void omap2_gpio_prepare_for_idle(int off_mode)
1870 {
1871 int i, c = 0;
1872 int min = 0;
1873
1874 if (cpu_is_omap34xx())
1875 min = 1;
1876
1877 for (i = min; i < gpio_bank_count; i++) {
1878 struct gpio_bank *bank = &gpio_bank[i];
1879 u32 l1 = 0, l2 = 0;
1880 int j;
1881
1882 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1883 clk_disable(bank->dbck);
1884
1885 if (!off_mode)
1886 continue;
1887
1888 /* If going to OFF, remove triggering for all
1889 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1890 * generated. See OMAP2420 Errata item 1.101. */
1891 if (!(bank->enabled_non_wakeup_gpios))
1892 continue;
1893
1894 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1895 bank->saved_datain = __raw_readl(bank->base +
1896 OMAP24XX_GPIO_DATAIN);
1897 l1 = __raw_readl(bank->base +
1898 OMAP24XX_GPIO_FALLINGDETECT);
1899 l2 = __raw_readl(bank->base +
1900 OMAP24XX_GPIO_RISINGDETECT);
1901 }
1902
1903 if (cpu_is_omap44xx()) {
1904 bank->saved_datain = __raw_readl(bank->base +
1905 OMAP4_GPIO_DATAIN);
1906 l1 = __raw_readl(bank->base +
1907 OMAP4_GPIO_FALLINGDETECT);
1908 l2 = __raw_readl(bank->base +
1909 OMAP4_GPIO_RISINGDETECT);
1910 }
1911
1912 bank->saved_fallingdetect = l1;
1913 bank->saved_risingdetect = l2;
1914 l1 &= ~bank->enabled_non_wakeup_gpios;
1915 l2 &= ~bank->enabled_non_wakeup_gpios;
1916
1917 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1918 __raw_writel(l1, bank->base +
1919 OMAP24XX_GPIO_FALLINGDETECT);
1920 __raw_writel(l2, bank->base +
1921 OMAP24XX_GPIO_RISINGDETECT);
1922 }
1923
1924 if (cpu_is_omap44xx()) {
1925 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1926 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1927 }
1928
1929 c++;
1930 }
1931 if (!c) {
1932 workaround_enabled = 0;
1933 return;
1934 }
1935 workaround_enabled = 1;
1936 }
1937
1938 void omap2_gpio_resume_after_idle(void)
1939 {
1940 int i;
1941 int min = 0;
1942
1943 if (cpu_is_omap34xx())
1944 min = 1;
1945 for (i = min; i < gpio_bank_count; i++) {
1946 struct gpio_bank *bank = &gpio_bank[i];
1947 u32 l = 0, gen, gen0, gen1;
1948 int j;
1949
1950 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1951 clk_enable(bank->dbck);
1952
1953 if (!workaround_enabled)
1954 continue;
1955
1956 if (!(bank->enabled_non_wakeup_gpios))
1957 continue;
1958
1959 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1960 __raw_writel(bank->saved_fallingdetect,
1961 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1962 __raw_writel(bank->saved_risingdetect,
1963 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1964 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1965 }
1966
1967 if (cpu_is_omap44xx()) {
1968 __raw_writel(bank->saved_fallingdetect,
1969 bank->base + OMAP4_GPIO_FALLINGDETECT);
1970 __raw_writel(bank->saved_risingdetect,
1971 bank->base + OMAP4_GPIO_RISINGDETECT);
1972 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1973 }
1974
1975 /* Check if any of the non-wakeup interrupt GPIOs have changed
1976 * state. If so, generate an IRQ by software. This is
1977 * horribly racy, but it's the best we can do to work around
1978 * this silicon bug. */
1979 l ^= bank->saved_datain;
1980 l &= bank->enabled_non_wakeup_gpios;
1981
1982 /*
1983 * No need to generate IRQs for the rising edge for gpio IRQs
1984 * configured with falling edge only; and vice versa.
1985 */
1986 gen0 = l & bank->saved_fallingdetect;
1987 gen0 &= bank->saved_datain;
1988
1989 gen1 = l & bank->saved_risingdetect;
1990 gen1 &= ~(bank->saved_datain);
1991
1992 /* FIXME: Consider GPIO IRQs with level detections properly! */
1993 gen = l & (~(bank->saved_fallingdetect) &
1994 ~(bank->saved_risingdetect));
1995 /* Consider all GPIO IRQs needed to be updated */
1996 gen |= gen0 | gen1;
1997
1998 if (gen) {
1999 u32 old0, old1;
2000
2001 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2002 old0 = __raw_readl(bank->base +
2003 OMAP24XX_GPIO_LEVELDETECT0);
2004 old1 = __raw_readl(bank->base +
2005 OMAP24XX_GPIO_LEVELDETECT1);
2006 __raw_writel(old0 | gen, bank->base +
2007 OMAP24XX_GPIO_LEVELDETECT0);
2008 __raw_writel(old1 | gen, bank->base +
2009 OMAP24XX_GPIO_LEVELDETECT1);
2010 __raw_writel(old0, bank->base +
2011 OMAP24XX_GPIO_LEVELDETECT0);
2012 __raw_writel(old1, bank->base +
2013 OMAP24XX_GPIO_LEVELDETECT1);
2014 }
2015
2016 if (cpu_is_omap44xx()) {
2017 old0 = __raw_readl(bank->base +
2018 OMAP4_GPIO_LEVELDETECT0);
2019 old1 = __raw_readl(bank->base +
2020 OMAP4_GPIO_LEVELDETECT1);
2021 __raw_writel(old0 | l, bank->base +
2022 OMAP4_GPIO_LEVELDETECT0);
2023 __raw_writel(old1 | l, bank->base +
2024 OMAP4_GPIO_LEVELDETECT1);
2025 __raw_writel(old0, bank->base +
2026 OMAP4_GPIO_LEVELDETECT0);
2027 __raw_writel(old1, bank->base +
2028 OMAP4_GPIO_LEVELDETECT1);
2029 }
2030 }
2031 }
2032
2033 }
2034
2035 #endif
2036
2037 #ifdef CONFIG_ARCH_OMAP3
2038 /* save the registers of bank 2-6 */
2039 void omap_gpio_save_context(void)
2040 {
2041 int i;
2042
2043 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2044 for (i = 1; i < gpio_bank_count; i++) {
2045 struct gpio_bank *bank = &gpio_bank[i];
2046 gpio_context[i].irqenable1 =
2047 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2048 gpio_context[i].irqenable2 =
2049 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2050 gpio_context[i].wake_en =
2051 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2052 gpio_context[i].ctrl =
2053 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2054 gpio_context[i].oe =
2055 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2056 gpio_context[i].leveldetect0 =
2057 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2058 gpio_context[i].leveldetect1 =
2059 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2060 gpio_context[i].risingdetect =
2061 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2062 gpio_context[i].fallingdetect =
2063 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2064 gpio_context[i].dataout =
2065 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2066 }
2067 }
2068
2069 /* restore the required registers of bank 2-6 */
2070 void omap_gpio_restore_context(void)
2071 {
2072 int i;
2073
2074 for (i = 1; i < gpio_bank_count; i++) {
2075 struct gpio_bank *bank = &gpio_bank[i];
2076 __raw_writel(gpio_context[i].irqenable1,
2077 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2078 __raw_writel(gpio_context[i].irqenable2,
2079 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2080 __raw_writel(gpio_context[i].wake_en,
2081 bank->base + OMAP24XX_GPIO_WAKE_EN);
2082 __raw_writel(gpio_context[i].ctrl,
2083 bank->base + OMAP24XX_GPIO_CTRL);
2084 __raw_writel(gpio_context[i].oe,
2085 bank->base + OMAP24XX_GPIO_OE);
2086 __raw_writel(gpio_context[i].leveldetect0,
2087 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2088 __raw_writel(gpio_context[i].leveldetect1,
2089 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2090 __raw_writel(gpio_context[i].risingdetect,
2091 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2092 __raw_writel(gpio_context[i].fallingdetect,
2093 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2094 __raw_writel(gpio_context[i].dataout,
2095 bank->base + OMAP24XX_GPIO_DATAOUT);
2096 }
2097 }
2098 #endif
2099
2100 static struct platform_driver omap_gpio_driver = {
2101 .probe = omap_gpio_probe,
2102 .driver = {
2103 .name = "omap_gpio",
2104 },
2105 };
2106
2107 /*
2108 * gpio driver register needs to be done before
2109 * machine_init functions access gpio APIs.
2110 * Hence omap_gpio_drv_reg() is a postcore_initcall.
2111 */
2112 static int __init omap_gpio_drv_reg(void)
2113 {
2114 return platform_driver_register(&omap_gpio_driver);
2115 }
2116 postcore_initcall(omap_gpio_drv_reg);
2117
2118 static int __init omap_gpio_sysinit(void)
2119 {
2120 int ret = 0;
2121
2122 mpuio_init();
2123
2124 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2125 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2126 if (ret == 0) {
2127 ret = sysdev_class_register(&omap_gpio_sysclass);
2128 if (ret == 0)
2129 ret = sysdev_register(&omap_gpio_device);
2130 }
2131 }
2132 #endif
2133
2134 return ret;
2135 }
2136
2137 arch_initcall(omap_gpio_sysinit);
Linux with added FPC-III support