2 * x86 instruction analysis
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * Copyright (C) IBM Corporation, 2002, 2004, 2009
22 #include <linux/string.h>
29 /* Verify next sizeof(t) bytes can be on the same instruction */
30 #define validate_next(t, insn, n) \
31 ((insn)->next_byte + sizeof(t) + n <= (insn)->end_kaddr)
33 #define __get_next(t, insn) \
34 ({ t r = *(t*)insn->next_byte; insn->next_byte += sizeof(t); r; })
36 #define __peek_nbyte_next(t, insn, n) \
37 ({ t r = *(t*)((insn)->next_byte + n); r; })
39 #define get_next(t, insn) \
40 ({ if (unlikely(!validate_next(t, insn, 0))) goto err_out; __get_next(t, insn); })
42 #define peek_nbyte_next(t, insn, n) \
43 ({ if (unlikely(!validate_next(t, insn, n))) goto err_out; __peek_nbyte_next(t, insn, n); })
45 #define peek_next(t, insn) peek_nbyte_next(t, insn, 0)
48 * insn_init() - initialize struct insn
49 * @insn: &struct insn to be initialized
50 * @kaddr: address (in kernel memory) of instruction (or copy thereof)
51 * @x86_64: !0 for 64-bit kernel or 64-bit app
53 void insn_init(struct insn
*insn
, const void *kaddr
, int buf_len
, int x86_64
)
56 * Instructions longer than MAX_INSN_SIZE (15 bytes) are invalid
57 * even if the input buffer is long enough to hold them.
59 if (buf_len
> MAX_INSN_SIZE
)
60 buf_len
= MAX_INSN_SIZE
;
62 memset(insn
, 0, sizeof(*insn
));
64 insn
->end_kaddr
= kaddr
+ buf_len
;
65 insn
->next_byte
= kaddr
;
66 insn
->x86_64
= x86_64
? 1 : 0;
75 * insn_get_prefixes - scan x86 instruction prefix bytes
76 * @insn: &struct insn containing instruction
78 * Populates the @insn->prefixes bitmap, and updates @insn->next_byte
79 * to point to the (first) opcode. No effect if @insn->prefixes.got
82 void insn_get_prefixes(struct insn
*insn
)
84 struct insn_field
*prefixes
= &insn
->prefixes
;
94 b
= peek_next(insn_byte_t
, insn
);
95 attr
= inat_get_opcode_attribute(b
);
96 while (inat_is_legacy_prefix(attr
)) {
97 /* Skip if same prefix */
98 for (i
= 0; i
< nb
; i
++)
99 if (prefixes
->bytes
[i
] == b
)
102 /* Invalid instruction */
104 prefixes
->bytes
[nb
++] = b
;
105 if (inat_is_address_size_prefix(attr
)) {
106 /* address size switches 2/4 or 4/8 */
108 insn
->addr_bytes
^= 12;
110 insn
->addr_bytes
^= 6;
111 } else if (inat_is_operand_size_prefix(attr
)) {
112 /* oprand size switches 2/4 */
113 insn
->opnd_bytes
^= 6;
119 b
= peek_next(insn_byte_t
, insn
);
120 attr
= inat_get_opcode_attribute(b
);
122 /* Set the last prefix */
123 if (lb
&& lb
!= insn
->prefixes
.bytes
[3]) {
124 if (unlikely(insn
->prefixes
.bytes
[3])) {
125 /* Swap the last prefix */
126 b
= insn
->prefixes
.bytes
[3];
127 for (i
= 0; i
< nb
; i
++)
128 if (prefixes
->bytes
[i
] == lb
)
129 prefixes
->bytes
[i
] = b
;
131 insn
->prefixes
.bytes
[3] = lb
;
134 /* Decode REX prefix */
136 b
= peek_next(insn_byte_t
, insn
);
137 attr
= inat_get_opcode_attribute(b
);
138 if (inat_is_rex_prefix(attr
)) {
139 insn
->rex_prefix
.value
= b
;
140 insn
->rex_prefix
.nbytes
= 1;
143 /* REX.W overrides opnd_size */
144 insn
->opnd_bytes
= 8;
147 insn
->rex_prefix
.got
= 1;
149 /* Decode VEX prefix */
150 b
= peek_next(insn_byte_t
, insn
);
151 attr
= inat_get_opcode_attribute(b
);
152 if (inat_is_vex_prefix(attr
)) {
153 insn_byte_t b2
= peek_nbyte_next(insn_byte_t
, insn
, 1);
156 * In 32-bits mode, if the [7:6] bits (mod bits of
157 * ModRM) on the second byte are not 11b, it is
160 if (X86_MODRM_MOD(b2
) != 3)
163 insn
->vex_prefix
.bytes
[0] = b
;
164 insn
->vex_prefix
.bytes
[1] = b2
;
165 if (inat_is_vex3_prefix(attr
)) {
166 b2
= peek_nbyte_next(insn_byte_t
, insn
, 2);
167 insn
->vex_prefix
.bytes
[2] = b2
;
168 insn
->vex_prefix
.nbytes
= 3;
169 insn
->next_byte
+= 3;
170 if (insn
->x86_64
&& X86_VEX_W(b2
))
171 /* VEX.W overrides opnd_size */
172 insn
->opnd_bytes
= 8;
175 * For VEX2, fake VEX3-like byte#2.
176 * Makes it easier to decode vex.W, vex.vvvv,
177 * vex.L and vex.pp. Masking with 0x7f sets vex.W == 0.
179 insn
->vex_prefix
.bytes
[2] = b2
& 0x7f;
180 insn
->vex_prefix
.nbytes
= 2;
181 insn
->next_byte
+= 2;
185 insn
->vex_prefix
.got
= 1;
194 * insn_get_opcode - collect opcode(s)
195 * @insn: &struct insn containing instruction
197 * Populates @insn->opcode, updates @insn->next_byte to point past the
198 * opcode byte(s), and set @insn->attr (except for groups).
199 * If necessary, first collects any preceding (prefix) bytes.
200 * Sets @insn->opcode.value = opcode1. No effect if @insn->opcode.got
203 void insn_get_opcode(struct insn
*insn
)
205 struct insn_field
*opcode
= &insn
->opcode
;
210 if (!insn
->prefixes
.got
)
211 insn_get_prefixes(insn
);
213 /* Get first opcode */
214 op
= get_next(insn_byte_t
, insn
);
215 opcode
->bytes
[0] = op
;
218 /* Check if there is VEX prefix or not */
219 if (insn_is_avx(insn
)) {
221 m
= insn_vex_m_bits(insn
);
222 p
= insn_vex_p_bits(insn
);
223 insn
->attr
= inat_get_avx_attribute(op
, m
, p
);
224 if (!inat_accept_vex(insn
->attr
) && !inat_is_group(insn
->attr
))
225 insn
->attr
= 0; /* This instruction is bad */
226 goto end
; /* VEX has only 1 byte for opcode */
229 insn
->attr
= inat_get_opcode_attribute(op
);
230 while (inat_is_escape(insn
->attr
)) {
231 /* Get escaped opcode */
232 op
= get_next(insn_byte_t
, insn
);
233 opcode
->bytes
[opcode
->nbytes
++] = op
;
234 pfx_id
= insn_last_prefix_id(insn
);
235 insn
->attr
= inat_get_escape_attribute(op
, pfx_id
, insn
->attr
);
237 if (inat_must_vex(insn
->attr
))
238 insn
->attr
= 0; /* This instruction is bad */
247 * insn_get_modrm - collect ModRM byte, if any
248 * @insn: &struct insn containing instruction
250 * Populates @insn->modrm and updates @insn->next_byte to point past the
251 * ModRM byte, if any. If necessary, first collects the preceding bytes
252 * (prefixes and opcode(s)). No effect if @insn->modrm.got is already 1.
254 void insn_get_modrm(struct insn
*insn
)
256 struct insn_field
*modrm
= &insn
->modrm
;
257 insn_byte_t pfx_id
, mod
;
260 if (!insn
->opcode
.got
)
261 insn_get_opcode(insn
);
263 if (inat_has_modrm(insn
->attr
)) {
264 mod
= get_next(insn_byte_t
, insn
);
267 if (inat_is_group(insn
->attr
)) {
268 pfx_id
= insn_last_prefix_id(insn
);
269 insn
->attr
= inat_get_group_attribute(mod
, pfx_id
,
271 if (insn_is_avx(insn
) && !inat_accept_vex(insn
->attr
))
272 insn
->attr
= 0; /* This is bad */
276 if (insn
->x86_64
&& inat_is_force64(insn
->attr
))
277 insn
->opnd_bytes
= 8;
286 * insn_rip_relative() - Does instruction use RIP-relative addressing mode?
287 * @insn: &struct insn containing instruction
289 * If necessary, first collects the instruction up to and including the
290 * ModRM byte. No effect if @insn->x86_64 is 0.
292 int insn_rip_relative(struct insn
*insn
)
294 struct insn_field
*modrm
= &insn
->modrm
;
299 insn_get_modrm(insn
);
301 * For rip-relative instructions, the mod field (top 2 bits)
302 * is zero and the r/m field (bottom 3 bits) is 0x5.
304 return (modrm
->nbytes
&& (modrm
->value
& 0xc7) == 0x5);
308 * insn_get_sib() - Get the SIB byte of instruction
309 * @insn: &struct insn containing instruction
311 * If necessary, first collects the instruction up to and including the
314 void insn_get_sib(struct insn
*insn
)
320 if (!insn
->modrm
.got
)
321 insn_get_modrm(insn
);
322 if (insn
->modrm
.nbytes
) {
323 modrm
= (insn_byte_t
)insn
->modrm
.value
;
324 if (insn
->addr_bytes
!= 2 &&
325 X86_MODRM_MOD(modrm
) != 3 && X86_MODRM_RM(modrm
) == 4) {
326 insn
->sib
.value
= get_next(insn_byte_t
, insn
);
327 insn
->sib
.nbytes
= 1;
338 * insn_get_displacement() - Get the displacement of instruction
339 * @insn: &struct insn containing instruction
341 * If necessary, first collects the instruction up to and including the
343 * Displacement value is sign-expanded.
345 void insn_get_displacement(struct insn
*insn
)
347 insn_byte_t mod
, rm
, base
;
349 if (insn
->displacement
.got
)
353 if (insn
->modrm
.nbytes
) {
355 * Interpreting the modrm byte:
356 * mod = 00 - no displacement fields (exceptions below)
357 * mod = 01 - 1-byte displacement field
358 * mod = 10 - displacement field is 4 bytes, or 2 bytes if
359 * address size = 2 (0x67 prefix in 32-bit mode)
360 * mod = 11 - no memory operand
362 * If address size = 2...
363 * mod = 00, r/m = 110 - displacement field is 2 bytes
365 * If address size != 2...
366 * mod != 11, r/m = 100 - SIB byte exists
367 * mod = 00, SIB base = 101 - displacement field is 4 bytes
368 * mod = 00, r/m = 101 - rip-relative addressing, displacement
371 mod
= X86_MODRM_MOD(insn
->modrm
.value
);
372 rm
= X86_MODRM_RM(insn
->modrm
.value
);
373 base
= X86_SIB_BASE(insn
->sib
.value
);
377 insn
->displacement
.value
= get_next(signed char, insn
);
378 insn
->displacement
.nbytes
= 1;
379 } else if (insn
->addr_bytes
== 2) {
380 if ((mod
== 0 && rm
== 6) || mod
== 2) {
381 insn
->displacement
.value
=
382 get_next(short, insn
);
383 insn
->displacement
.nbytes
= 2;
386 if ((mod
== 0 && rm
== 5) || mod
== 2 ||
387 (mod
== 0 && base
== 5)) {
388 insn
->displacement
.value
= get_next(int, insn
);
389 insn
->displacement
.nbytes
= 4;
394 insn
->displacement
.got
= 1;
400 /* Decode moffset16/32/64. Return 0 if failed */
401 static int __get_moffset(struct insn
*insn
)
403 switch (insn
->addr_bytes
) {
405 insn
->moffset1
.value
= get_next(short, insn
);
406 insn
->moffset1
.nbytes
= 2;
409 insn
->moffset1
.value
= get_next(int, insn
);
410 insn
->moffset1
.nbytes
= 4;
413 insn
->moffset1
.value
= get_next(int, insn
);
414 insn
->moffset1
.nbytes
= 4;
415 insn
->moffset2
.value
= get_next(int, insn
);
416 insn
->moffset2
.nbytes
= 4;
418 default: /* opnd_bytes must be modified manually */
421 insn
->moffset1
.got
= insn
->moffset2
.got
= 1;
429 /* Decode imm v32(Iz). Return 0 if failed */
430 static int __get_immv32(struct insn
*insn
)
432 switch (insn
->opnd_bytes
) {
434 insn
->immediate
.value
= get_next(short, insn
);
435 insn
->immediate
.nbytes
= 2;
439 insn
->immediate
.value
= get_next(int, insn
);
440 insn
->immediate
.nbytes
= 4;
442 default: /* opnd_bytes must be modified manually */
452 /* Decode imm v64(Iv/Ov), Return 0 if failed */
453 static int __get_immv(struct insn
*insn
)
455 switch (insn
->opnd_bytes
) {
457 insn
->immediate1
.value
= get_next(short, insn
);
458 insn
->immediate1
.nbytes
= 2;
461 insn
->immediate1
.value
= get_next(int, insn
);
462 insn
->immediate1
.nbytes
= 4;
465 insn
->immediate1
.value
= get_next(int, insn
);
466 insn
->immediate1
.nbytes
= 4;
467 insn
->immediate2
.value
= get_next(int, insn
);
468 insn
->immediate2
.nbytes
= 4;
470 default: /* opnd_bytes must be modified manually */
473 insn
->immediate1
.got
= insn
->immediate2
.got
= 1;
480 /* Decode ptr16:16/32(Ap) */
481 static int __get_immptr(struct insn
*insn
)
483 switch (insn
->opnd_bytes
) {
485 insn
->immediate1
.value
= get_next(short, insn
);
486 insn
->immediate1
.nbytes
= 2;
489 insn
->immediate1
.value
= get_next(int, insn
);
490 insn
->immediate1
.nbytes
= 4;
493 /* ptr16:64 is not exist (no segment) */
495 default: /* opnd_bytes must be modified manually */
498 insn
->immediate2
.value
= get_next(unsigned short, insn
);
499 insn
->immediate2
.nbytes
= 2;
500 insn
->immediate1
.got
= insn
->immediate2
.got
= 1;
508 * insn_get_immediate() - Get the immediates of instruction
509 * @insn: &struct insn containing instruction
511 * If necessary, first collects the instruction up to and including the
512 * displacement bytes.
513 * Basically, most of immediates are sign-expanded. Unsigned-value can be
514 * get by bit masking with ((1 << (nbytes * 8)) - 1)
516 void insn_get_immediate(struct insn
*insn
)
518 if (insn
->immediate
.got
)
520 if (!insn
->displacement
.got
)
521 insn_get_displacement(insn
);
523 if (inat_has_moffset(insn
->attr
)) {
524 if (!__get_moffset(insn
))
529 if (!inat_has_immediate(insn
->attr
))
533 switch (inat_immediate_size(insn
->attr
)) {
535 insn
->immediate
.value
= get_next(signed char, insn
);
536 insn
->immediate
.nbytes
= 1;
539 insn
->immediate
.value
= get_next(short, insn
);
540 insn
->immediate
.nbytes
= 2;
543 insn
->immediate
.value
= get_next(int, insn
);
544 insn
->immediate
.nbytes
= 4;
547 insn
->immediate1
.value
= get_next(int, insn
);
548 insn
->immediate1
.nbytes
= 4;
549 insn
->immediate2
.value
= get_next(int, insn
);
550 insn
->immediate2
.nbytes
= 4;
553 if (!__get_immptr(insn
))
556 case INAT_IMM_VWORD32
:
557 if (!__get_immv32(insn
))
561 if (!__get_immv(insn
))
565 /* Here, insn must have an immediate, but failed */
568 if (inat_has_second_immediate(insn
->attr
)) {
569 insn
->immediate2
.value
= get_next(signed char, insn
);
570 insn
->immediate2
.nbytes
= 1;
573 insn
->immediate
.got
= 1;
580 * insn_get_length() - Get the length of instruction
581 * @insn: &struct insn containing instruction
583 * If necessary, first collects the instruction up to and including the
586 void insn_get_length(struct insn
*insn
)
590 if (!insn
->immediate
.got
)
591 insn_get_immediate(insn
);
592 insn
->length
= (unsigned char)((unsigned long)insn
->next_byte
593 - (unsigned long)insn
->kaddr
);